Stack Gate Structure

Abstract

An embodiment of the invention may include a semiconductor structure and a manufacturing method. The semiconductor structure may include a top channel and a bottom channel, where the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers disposed on each side of the gate. A first spacer includes a dielectric material disposed between the plurality of vertically oriented channels. A second spacer includes a dielectric material disposed between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.

Description

[Technical field]

[0001] The present invention relates to semiconductor device manufacturing, and more particularly to stacked FET gates. [Background technology]

[0002] The stacked nanosheet design offers significant benefits for the structural scaling of both logic and memory devices by stacking FETs on top of each other. Stacked nanosheet devices allow two n-type FETs, two p-type FET devices, or a combination of an n-type FET device and a p-type FET device to be placed in the same footprint of a nanosheet. Summary of the Invention

[0003] An embodiment of the invention may include a semiconductor structure and a method of manufacture. The semiconductor structure may include a top channel and a bottom channel, the top channel including a plurality of vertically oriented channels. The bottom channel including a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include a spacer disposed on each side of the gate. The first spacer includes a dielectric material disposed between the plurality of vertically oriented channels. The second spacer includes a dielectric material disposed between the plurality of horizontally oriented channels. This may allow for spacer formation between the vertical spacers.

[0004] In another embodiment, the semiconductor structure may have a first spacer thickness that is different from a second spacer thickness.

[0005] In another embodiment, the semiconductor structure may comprise a second spacer further comprising a top element, the top element comprising a dielectric material in contact with a bottom surface of the top channel and a top surface of the bottom channel.

[0006] In another embodiment, the semiconductor structure can include a structure interface that exists between a first spacer and a second spacer.

[0007] In another embodiment, the semiconductor structure may include a top element having a top and a bottom, the top including a plurality of fin protrusions, each fin protrusion disposed beneath each of a plurality of vertically oriented channels, and the bottom including a horizontal layer connecting each of the top fin protrusions, which may enable spacer formation between the top and bottom channels.

[0008] In another embodiment, the semiconductor structure may include a top channel that is part of a first transistor and a bottom channel that is part of a second transistor, which may allow the semiconductor device to act as a stacked gate structure.

[0009] In another embodiment, the semiconductor structure may include a first transistor and a second transistor that form a complementary field effect transistor, which may allow the semiconductor device to act as a stacked gate structure.

[0010] An embodiment of the invention may include a semiconductor structure and a method of manufacture. The semiconductor structure may include a gate structure. The semiconductor structure may include a top channel. The top channel includes at least one vertically oriented channel. A bottom surface of the at least one vertically oriented channel contacts an insulator layer. A top surface and a vertical surface of the at least one vertically oriented channel contact a gate structure. The semiconductor structure may include a bottom channel, the bottom channel including a plurality of horizontally oriented channels, and a gate surrounding the bottom channel. This may provide structural support to the top channel.

[0011] In another embodiment, the semiconductor structure may include a gate dielectric disposed on each surface of the bottom channel, the gate dielectric disposed on the top surface, a vertical surface of the at least one vertically oriented channel contacting the gate structure, and a gate dielectric disposed on a surface of the insulator layer not contacting the at least one vertically oriented channel.

[0012] In another embodiment, the semiconductor structure may include a top channel that is part of a first transistor and a bottom channel that is part of a second transistor, which may allow the semiconductor device to act as a stacked gate structure.

[0013] In another embodiment, the semiconductor structure may include a first transistor and a second transistor that form a complementary field effect transistor, which may allow the semiconductor device to act as a stacked gate structure. [Brief description of the drawings]

[0014] [Figure 1] 1 illustrates a top view of a fin region and a gate region, showing a cross section of each region, according to a first exemplary embodiment.

[0015] [Diagram 2] 2 shows a cross-sectional view along line x in the gate region of the layered structure according to a first exemplary embodiment.

[0016] [Diagram 3] 1A shows a cross-sectional view along line x in the gate region after patterning of the vertical channel in the top FET of each CFET structure according to a first exemplary embodiment.

[0017] [Figure 4] 4 shows a cross-sectional view along line x in the gate region after forming a sacrificial liner between the vertical channels of each top FET according to a first exemplary embodiment.

[0018] [Diagram 5] 4 shows a cross-sectional view along line x in the gate region after forming sacrificial spacers around each top FET in accordance with a first exemplary embodiment.

[0019] [Figure 6] 1A-1C show cross-sectional views along line x in the gate region after patterning of the bottom FET of each CFET structure according to a first exemplary embodiment.

[0020] [Figure 7] 1 shows a cross-sectional view along line x in the gate region after removal of the sacrificial spacer according to a first exemplary embodiment.

[0021] [Figure 8A] 2 shows a cross-sectional view along line x in the gate region of a CFET device after dummy gate formation according to a first exemplary embodiment.

[0022] [Figure 8B] 4 illustrates a cross-sectional view along line y in the fin region of a CFET device after dummy gate formation according to a first exemplary embodiment.

[0023] [Figure 9A] 2 shows a cross-sectional view along line x in the gate region of a CFET device after spacer formation and patterning of the channel region according to a first exemplary embodiment.

[0024] [Figure 9B] 4 illustrates a cross-sectional view along line y in the fin region of a CFET device following spacer formation and patterning of the channel region according to a first exemplary embodiment.

[0025] [Figure 9C] 4 shows a cross-sectional view along line z in the spacer region of a CFET device after spacer formation and patterning of the channel region according to a first exemplary embodiment.

[0026] [Figure 9D] 1A shows a top view illustrating a cross-sectional view after spacer formation and patterning of the channel region according to a first exemplary embodiment.

[0027] [Figure 10A]1 shows a cross-sectional view along line x in the gate region of a CFET device after removing the sacrificial liner under the gate spacer according to a first exemplary embodiment.

[0028] [Figure 10B] 4 illustrates a cross-sectional view along line y in the fin region of a CFET device after removing the sacrificial liner under the gate spacer according to a first exemplary embodiment.

[0029] [Figure 10C] 1 shows a cross-sectional view along line z in the spacer region of a CFET device after removing the sacrificial liner under the gate spacer according to a first exemplary embodiment.

[0030] [Figure 10D] FIG. 1 illustrates a top view showing a cross-sectional view after removing the sacrificial liner under the gate spacer according to a first exemplary embodiment.

[0031] [Figure 11A] 4 shows a cross-sectional view along line x in the gate region of a CFET device after forming an inner spacer of the top FET of the CFET according to a first exemplary embodiment.

[0032] [Figure 11B] 4 illustrates a cross-sectional view along line y in the fin region of a CFET device after forming an inner spacer of the top FET of the CFET according to a first exemplary embodiment.

[0033] [Figure 11C] 4 illustrates a cross-sectional view along line z in the spacer region of a CFET device after forming an inner spacer of a top FET of the CFET according to a first exemplary embodiment.

[0034] [Figure 11D] 1 shows a top view illustrating a cross-sectional view after forming an inner spacer of a top FET of a CFET according to a first exemplary embodiment.

[0035] [Figure 12A] 1 illustrates a cross-sectional view along line x in the gate region of a CFET device after pulling back the sacrificial layer of the bottom FET of the CFET according to a first exemplary embodiment.

[0036] [Figure 12B] 1 illustrates a cross-sectional view along line y in the fin region of a CFET device after pulling back the sacrificial layer of the bottom FET of the CFET in accordance with a first exemplary embodiment.

[0037] [Figure 12C] 1 illustrates a cross-sectional view along line z in a spacer region of a CFET device after pulling back a sacrificial layer of a bottom FET of the CFET according to a first exemplary embodiment.

[0038] [Figure 12D] FIG. 1 illustrates a top view showing a cross-sectional view after pulling back the sacrificial layer of the bottom FET of the CFET according to a first exemplary embodiment.

[0039] [Figure 13A] 2 illustrates a cross-sectional view along line x in the gate region of a CFET device after forming an inner spacer of the bottom FET of the CFET according to a first exemplary embodiment.

[0040] [Figure 13B] 4 illustrates a cross-sectional view along line y in the fin region of a CFET device after forming an inner spacer of the bottom FET of the CFET in accordance with a first exemplary embodiment.

[0041] [Figure 13C] 4 illustrates a cross-sectional view along line z in a spacer region of a CFET device after forming an inner spacer of a bottom FET of the CFET according to a first exemplary embodiment.

[0042] [Figure 13D]1 shows a top view illustrating a cross-sectional view after forming an inner spacer of a bottom FET of a CFET according to a first exemplary embodiment.

[0043] [Figure 14A] 2 illustrates a cross-sectional view along line x in the gate region of a CFET device after forming a bottom source / drain of the bottom FET, a source / drain isolation layer, and a top source / drain of the top FET according to a first exemplary embodiment.

[0044] [Figure 14B] 1 illustrates a cross-sectional view along line y in the fin region of a CFET device after forming a bottom source / drain of the bottom FET, a source / drain isolation layer, and a top source / drain of the top FET according to a first exemplary embodiment.

[0045] [Figure 14C] 2 illustrates a cross-sectional view along line z in a spacer region of a CFET device after forming a bottom source / drain of a bottom FET, a source / drain isolation layer, and a top source / drain of a top FET according to a first exemplary embodiment.

[0046] [Figure 14D] 2A shows a top view illustrating a cross-sectional view after forming a bottom source / drain of a bottom FET, a source / drain isolation layer, and a top source / drain of a top FET according to a first exemplary embodiment.

[0047] [Figure 15A] FIG. 2 illustrates a cross-sectional view along line x in the gate region of a CFET device after CMP to remove ILD fill and dummy gate hardmask in the source / drain regions in accordance with a first exemplary embodiment.

[0048] [Figure 15B]FIG. 2 illustrates a cross-sectional view along line y in the fin region of a CFET device after CMP to remove ILD fill and dummy gate hardmask in the source / drain regions in accordance with a first exemplary embodiment.

[0049] [Figure 15C] FIG. 1 illustrates a cross-sectional view along line z in a spacer region of a CFET device after CMP to remove ILD fill and dummy gate hardmask in source / drain regions according to a first exemplary embodiment.

[0050] [Figure 15D] 1A shows a top view illustrating a cross-sectional view after CMP to remove ILD fill and dummy gate hardmask in the source / drain regions according to a first exemplary embodiment.

[0051] [Figure 16A] 1 shows a cross-sectional view along line x in the gate region of a CFET device after dummy gate removal and sacrificial layer release according to a first exemplary embodiment.

[0052] [Figure 16B] 1 illustrates a cross-sectional view along line y in the fin region of a CFET device after dummy gate removal and sacrificial layer release according to a first exemplary embodiment.

[0053] [Figure 16C] 1 shows a cross-sectional view along line z in the spacer region of a CFET device after dummy gate removal and sacrificial layer release according to a first exemplary embodiment.

[0054] [Figure 16D] 1A shows a top view illustrating a cross-sectional view after dummy gate removal and sacrificial layer release according to a first exemplary embodiment.

[0055] [Figure 17A]FIG. 2 illustrates a cross-sectional view along line x in the gate region of a CFET device after RMG (replacement metal gate) and contact formation according to a first exemplary embodiment.

[0056] [Figure 17B] 1 illustrates a cross-sectional view along line y in the fin region of a CFET device after RMG and contact formation in accordance with a first exemplary embodiment.

[0057] [Figure 17C] 1 illustrates a cross-sectional view along line z in a spacer region of a CFET device after RMG and contact formation according to a first exemplary embodiment.

[0058] [Figure 17D] 1 illustrates a top view showing a cross-sectional view after RMG and contact formation according to a first exemplary embodiment.

[0059] [Figure 17E] 1 illustrates a cross-sectional view along line z in a source / drain region of a CFET device after RMG and contact formation according to a first exemplary embodiment.

[0060] [Figure 18] FIG. 13 illustrates a top view of the fin and gate regions showing cross sections of each region according to a second exemplary embodiment.

[0061] [Figure 19] 4 illustrates a layered structure according to a second exemplary embodiment.

[0062] [Figure 20A] 13 shows a cross-sectional view along line x in the fin region of a CFET device after patterning a vertical channel in the top FET of a CFET structure according to a second exemplary embodiment.

[0063] [Figure 20B]13 shows a cross-sectional view along line y in the gate region of a CFET device after patterning a vertical channel in the top FET of a CFET structure according to a second exemplary embodiment.

[0064] [Figure 21A] FIG. 13 illustrates a cross-sectional view along line x in the fin region of a CFET device after patterning self-aligned spacers, patterning the bottom FET of a CFET structure using the self-aligned spacers, and forming STI according to a second exemplary embodiment.

[0065] [Figure 21B] FIG. 13 illustrates a cross-sectional view along line y in the gate region of a CFET device after patterning self-aligned spacers, patterning the bottom FET of a CFET structure using the self-aligned spacers, and forming STI according to a second exemplary embodiment.

[0066] [Figure 22A] 13 illustrates a cross-sectional view along line x in the fin region of a CFET device after removing the self-aligned spacers, the bottom sacrificial layer, and depositing a bottom dielectric layer in accordance with a second exemplary embodiment.

[0067] [Figure 22B] 13 shows a cross-sectional view along line y in the gate region of a CFET device after removing the self-aligned spacers, the bottom sacrificial layer, and depositing a bottom dielectric layer according to a second exemplary embodiment.

[0068] [Figure 23A] 13 illustrates a cross-sectional view along line x in the fin region of a CFET device after dummy gate formation, channel formation of the upper FET of the CFET and protective spacers according to a second exemplary embodiment.

[0069] [Figure 23B]13 shows a cross-sectional view along line y in the gate region of a CFET device after dummy gate formation, channel formation of the upper FET of the CFET and protective spacers according to a second exemplary embodiment.

[0070] [Figure 24A] 1 illustrates a cross-sectional view along line x in a fin region of a CFET device after channel formation of the bottom FET of the CFET in accordance with a second exemplary embodiment.

[0071] [Figure 24B] 13 illustrates a cross-sectional view along line y in the gate region of a CFET device after channel formation of the bottom FET of the CFET according to a second exemplary embodiment.

[0072] [Figure 25A] 1 illustrates a cross-sectional view along line x in the fin region of a CFET device after source / drain formation on the bottom FET and isolation layer of the CFET according to a second exemplary embodiment.

[0073] [Figure 25B] 13 illustrates a cross-sectional view along line y in the gate region of a CFET device after source / drain formation on the bottom FET and isolation layer of the CFET according to a second exemplary embodiment.

[0074] [Figure 26A] 1 illustrates a cross-sectional view along line x in the fin region of a CFET device after forming source / drains on the top FET of the CFET according to a second exemplary embodiment.

[0075] [Figure 26B] 13 shows a cross-sectional view along line y in the gate region of a CFET device after forming source / drains on the top FET of the CFET according to a second exemplary embodiment.

[0076] [Figure 27A]13 illustrates a cross-sectional view along line x in the fin region of a CFET device after ILD formation, dummy gate removal, and sacrificial layer release in accordance with a second exemplary embodiment.

[0077] [Figure 27B] 13 illustrates a cross-sectional view along line y in the gate region of a CFET device after ILD formation, dummy gate removal, and sacrificial layer release in accordance with a second exemplary embodiment.

[0078] [Figure 28A] 4 shows a cross-sectional view along line x in the fin region of a CFET device after depositing a gate dielectric according to a second exemplary embodiment.

[0079] [Figure 28B] 4 shows a cross-sectional view along line y in the gate region of a CFET device after depositing a gate dielectric according to a second exemplary embodiment.

[0080] [Figure 29A] 13 shows a cross-sectional view along line x in the fin region of a CFET device after depositing a workfunction metal according to a second exemplary embodiment.

[0081] [Figure 29B] 4 shows a cross-sectional view along line y in the gate region of a CFET device after depositing a workfunction metal according to a second exemplary embodiment.

[0082] [Figure 30A] 13 illustrates a cross-sectional view along line x in the fin region of a CFET device after gate contact formation according to a second exemplary embodiment.

[0083] [Figure 30B] 13 shows a cross-sectional view along line y in the gate region of a CFET device after gate contact formation according to a second exemplary embodiment.

[0084] Elements in the figures are not necessarily to scale and are not intended to depict specific parameters of the invention. Dimensions of elements may be exaggerated for clarity and ease of illustration. For exact dimensions, please refer to the detailed description. The drawings are intended to depict only typical embodiments of the invention and therefore should not be considered as limiting the scope of the invention. In the drawings, like reference numbers represent like elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0085] Exemplary embodiments will now be described more fully with reference to the accompanying drawings in which exemplary embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be considered as limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the specification, details of well-known features and techniques may be omitted so as to avoid unnecessarily obscuring the depicted embodiments.

[0086] For purposes of the following description, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top" and "bottom" and their derivations relate to the disclosed structures and methods as oriented in the drawing figures. Terms such as "on", "overlying", "above", "on top of", "located on top of" or "located on top of" refer to a first element, such as a first structure, being present on a second element, such as a second structure, where an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating or semiconducting layers at the interface of the two elements.

[0087] In the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and explanation, and in some cases may not be described in detail, so as not to obscure the presentation of the embodiments of the present invention. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses heavily on the distinctive features or elements of various embodiments of the present invention.

[0088] The trend towards miniaturization of devices requires new structures that allow more transistors to be placed in a smaller footprint. Using stacked devices, such as complementary field effect transistors (CFETs), can allow two transistors to occupy a similar footprint and also reduce the number of contacts (and wiring between them) of such devices. However, there are construction challenges resulting from miniaturization due to the limited size of components, and also difficulties in maintaining the desired spacing between components. By using vertically oriented channels for the top gates of stacked devices and horizontally oriented channels for the bottom gates of stacked devices, such construction limitations can be reduced.

[0089] In a first embodiment depicted in Figures 1 to 17E, methods and structures are introduced that allow spacers to be effectively formed in three stages, thereby enabling adequate filling of the space between semiconductor channels when the distance between the channels and the thickness of the spacer are minimized.

[0090] In a second embodiment depicted in Figures 18 to 30B, a method and structure are introduced in which a vertical channel is formed directly on the insulator layer, thereby isolating the top gate from the bottom gate and also providing additional structural support for the vertically oriented channel on the top gate.

[0091] Referring to FIG. 1, a top view of the gate region 10 and the fin region 20 is depicted and used as a reference for the semiconductor structures on a substrate depicted in FIG. 2 through FIG. 17E. The straight line x of the cross section of the gate region 10 may be used to indicate the structures disposed in the gate region 10 during each stage. The straight line y of the cross section of the fin region 20 may be used to indicate the structures disposed along each transistor device during each stage. The straight line z of the cross section shown in FIG. 9D of the spacer disposed next to the gate region 10 may be used to indicate the structures disposed adjacent to the gate region 10 during each stage.

[0092] Referring to FIG. 2, a structure having a layered structure having a substrate 100, a buried oxide layer 110, a sacrificial nanosheet 130, a nanosheet material 120, an intermediate buffer layer 140, a top semiconductor layer 150, and a hard mask 160 is depicted.

[0093] According to an exemplary embodiment, the substrate 100 is a semiconductor wafer of a semiconductor such as silicon (Si), germanium (Ge), or III-V or a combination thereof, having a buried oxide layer 110 to create a semiconductor-on-insulator (SOI) wafer. Alternatively, the substrate 100 can be a bulk semiconductor wafer without the buried oxide layer 110. The SOI wafer includes a sacrificial nanosheet 130 separated from the underlying substrate 100 by the buried oxide layer 110. When the buried insulator is an oxide, it is referred to herein as a buried oxide or BOX. On the substrate 100, structures (not shown) such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc. can be pre-built.

[0094] The term "nanosheet" as used herein refers to a sheet or layer having nanoscale dimensions. Furthermore, the term "nanosheet" is meant to encompass other nanoscale structures such as nanowires. For example, a "nanosheet" may refer to a nanowire having a larger width, or a "nanowire" may refer to a nanosheet having a smaller width, or vice versa.

[0095] In general, the material stack disposed on the buried oxide layer 110 includes a nanosheet material 120 separated by a sacrificial nanosheet 130, and an upper semiconductor layer 150 separated from a lower nanosheet by an intermediate buffer layer 140. By "sacrificial" it is meant that the layer or a portion thereof is removed during fabrication of the device. By way of example only, each of the nanosheets 120, 130, 140 and 150 in the material stack are deposited on top of each other on the substrate 100 using an epitaxial growth process. According to an exemplary embodiment, each of the nanosheets 120 and 130 in the material stack has a thickness ranging from about 10 nanometers (nm) to about 25 nm and therebetween. According to an exemplary embodiment, each of the intermediate buffer layers 140 in the material stack has a thickness ranging from about 20 nanometers (nm) to about 60 nm and therebetween. According to an exemplary embodiment, each of the intermediate buffer layers 140 in the material stack has a thickness ranging from about 25 nanometers (nm) to about 100 nm and therebetween.

[0096] The material stack includes alternating layers of nanosheet material 120 and sacrificial nanosheet 130. For example, according to an exemplary embodiment, nanosheet material 120 is Si and sacrificial nanosheet 130 is SiGe. However, this is merely an example and other configurations are contemplated herein. Additionally, while there are two nanosheets in first nanosheet material 120, additional nanosheets are contemplated. For example, in an alternative embodiment, the first nanosheet material is SiGe while the second nanosheet material is Si. As will be explained in detail below, these nanosheet materials are used to form the channels of the existing stack nanosheet device and the sacrificial material between the channels. Removal of the sacrificial material releases the channel from the stack, allowing for the formation of a gate that completely surrounds the channel in a gate-all-around configuration. It is therefore preferred that the first and second nanosheet materials have etch selectivity with respect to each other. Thus, when one serves as the channel, the other sacrificial material can be selectively removed to release the channel from the stack. By way of example only, Si and SiGe provide such etch selectivity.

[0097] Similarly, the upper semiconductor layer 150 and the intermediate buffer layer 140 may be selected for selectivity. For example, when the upper semiconductor layer 150 is Si, the intermediate buffer layer 140 is SiGe. Similarly, this is merely an example, and other configurations are possible. For example, the first nanosheet material may alternatively be SiGe, while the second nanosheet material is Si. Additionally, while there are two nanosheets for the intermediate buffer layer 140, additional nanosheets are envisioned. Furthermore, the size of the material stack 105 shown is merely an example, and embodiments are envisioned herein in which the number of lower or upper nanosheets, or a combination thereof, differs from that shown in the figures.

[0098] According to an exemplary embodiment, both sacrificial nanosheets 130 and 140 are formed from SiGe having a high germanium (Ge) content. For example, in one exemplary embodiment, the high Ge content ranges from about 50% Ge to about 100% Ge (i.e., pure Ge) and therebetween. For example, in one non-limiting example, sacrificial nanosheets 130 and 140 are formed from SiGe60 (having a Ge content of about 60%). The use of a higher Ge content allows the SiGe to etch the sacrificial nanosheets 130 and 140 selectively relative to the nanosheet material 120, and the upper semiconductor layer 150 provided above can be formed from Si or SiGe or a combination thereof. However, it should be noted that the SiGe used as the lower / upper nanosheet material has a low Ge content. For example, in one exemplary embodiment, the low Ge content ranges from about 20% Ge to about 50% Ge and therebetween. For example, in one non-limiting example, the nanosheet material 120 and the top semiconductor layer 150 are formed from SiGe 30 (having a Ge content of about 30%).

[0099] A patterned nanosheet hard mask 160 is then formed on the material stack. Suitable materials for the nanosheet hard mask 160 include, but are not limited to, nitride materials such as silicon nitride (SixNy), silicon oxynitride (SiON), or silicon carbonitride (SiCN), or combinations thereof, or oxide materials such as silicon oxide (SiOx), or combinations thereof.

[0100] (X-cut) Referring to FIG. 3, it is depicted that fins 155 covered by FIN hard mask 165 are formed from top semiconductor layer 150, and intermediate buffer layer 140 is etched to form etched intermediate buffer layer 145. Fins 155 are formed having a width W1 between each fin of about 8 to about 20 nm. Additionally, an etch to intermediate buffer layer 140 is performed to a depth D1 of about 5 to about 55 nm while forming fins 155. This leaves an intermediate buffer layer having a first portion (i.e., non-etched portion) having a thickness T1 of about 5 to about 20 nm and a second portion under each fin having a thickness equal to the etch depth D1. Each of the etch dimensions W1, T1, and D1 can be selected such that the conformal deposition can replace any material removed in a subsequent stage. For example, W1, T1, and D1 can be selected to be smaller than the thickness of a subsequent conformal deposition stage, thereby allowing the conformal deposition to completely fill voids left by removing a portion of the layer. The fins 155 may be formed using sidewall image transfer techniques, formed on a hard mask 160 and etched into the intermediate buffer layer 140 .

[0101] Referring to FIG. 4, the deposition of a sacrificial liner 170 between the fins 155 is depicted. The sacrificial liner may be conformally deposited along the exposed surfaces and isotropically etched, leaving only the sacrificial liner 170 between the fins 155. The sacrificial liner 170 may be a material that can be removed with respect to the intermediate buffer layer 145 and the fins 155. In an exemplary embodiment, when the fins 155 are Si and the intermediate buffer layer 145 is SiGe30, the high Ge content of the sacrificial liner 170 may be from about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween. For example, in one non-limiting example, the sacrificial liner 170 is formed of SiGe60 (having a Ge content of about 60%).

[0102] 5, a sacrificial spacer liner 180 is depicted being formed adjacent to the fin 155. The sacrificial spacer liner 180 may be any material that can be selectively etched with respect to the intermediate buffer layer 145 and the sacrificial nanosheets 130 and 140. The sacrificial spacer liner 180 may be formed by conformal deposition followed by reactive ion etching (RIE).

[0103] 6, patterning of the bottom nanosheet is depicted to form the sacrificial layer 135, the bottom semiconductor layer 125, and the intermediate buffer layer 147. The patterning can be done by performing RIE using the sacrificial spacer liner 180 as a mask.

[0104] 7, removal of the sacrificial spacer liner 180 is depicted. Removal of the sacrificial spacer liner 180 and the FIN hard mask 165 may be performed using any etching process capable of selectively removing the sacrificial spacer liner 180 from the sacrificial layer 135, the bottom semiconductor layer 125, the intermediate buffer layer 147, the fins 155, and the sacrificial liner 170.

[0105] Referring to FIG. 8A (X-cut) and FIG. 8B (Y-cut), the formation of a dummy gate 200 and a dummy gate hard mask 210 is depicted. Next, the dummy gate 200 is formed on the nanosheet device stack 105 above the channel region of the stacked nanosheet device. To form the dummy gate 200, a sacrificial gate material is first blanket deposited on the structure of FIG. 7. Suitable sacrificial gate materials include, but are not limited to, a thin layer of SiO2 followed by polysilicon (poly-Si) or amorphous silicon (a-Si) or a combination thereof. Processes such as CVD, ALD or PVD may be utilized to deposit the sacrificial gate material.

[0106] The dummy gate 200 serves as a placeholder for the final gate of the stacked nanosheet device. That is, the dummy gate 200 is removed later in the process and replaced with a metal gate stack that serves as the final gate of the stacked nanosheet device. Thus, these final gates of the stacked nanosheet device are also referred to herein as "replacement metal gates" or simply "RMG". The use of the RMG process is advantageous because it prevents exposure of the metal gate stack materials to potentially harmful conditions during subsequent processing steps. For example, high-K dielectrics used in RMG gate stacks can be damaged by exposure to high temperatures. Thus, these gate stack materials are placed only near the end of the process.

[0107] Next, a dummy gate hard mask 210 is formed on the sacrificial gate material to mark the footprint and location of each of the dummy gates 200. Suitable materials for the dummy gate hard mask 210 include, but are not limited to, nitride hard mask materials such as SiN, SiON, or SiCN or combinations thereof, or oxide hard mask materials such as SiOx or combinations thereof. Then, an etch using the dummy gate hard mask 210 is used to pattern the sacrificial gate material into the individual dummy gates 200 shown in Figures 8A and 8B. A directional (anisotropic) etch process such as RIE may be utilized for the sacrificial gate etch.

[0108] 9A-9D, forming spacers 220 and patterning the bottom nanosheet to form the sacrificial layer 138, the lower nanosheet 128, the middle buffer layer 148, and the fins 157 are depicted. The spacers 220 may be formed by conformal deposition followed by reactive ion etching (RIE). RIE may be performed on the buried oxide layer 110 to form the channel regions for each of the devices. FIG. 9C depicts a cross section along the Z axis through the spacers. The spacers 220 encase the FIN / nanosheet stack.

[0109] 10A-10D, removal of a portion of a sacrificial liner 170 (e.g., SiGe 60) in the gate spacer region is depicted to form a void 172 depicted in FIG 10C while leaving a sacrificial liner 175 in the gate region of the device. The depth of removal of the sacrificial liner 170 should be about 5 to about 10 nm, allowing conformal deposition of spacer material to fill the void in a subsequent step.

[0110] 11A-11D, the deposition of top spacers 230 between fins 157 is depicted. The thickness of the conformal deposition of material to form top spacers 230 should be sufficient to fill the gaps 172 created in the previous step. Suitable materials for dielectric spacers 230 include, but are not limited to, SiOx, SiC, or SiCO, or combinations thereof. A process such as CVD, ALD, or PVD may be utilized to deposit top spacers 230 in gaps 172, followed by isotropic etching to remove all of the conformal deposition layer except the pinch-off region in the previous gap 172. Top spacers 230 may have a structural interface that distinguishes them from previously formed spacers 220. Such an interface may be the result of deposition of the spacers in a separate step. Additionally, top spacers 230 may have a different thickness than spacers 220, which may be the result of inaccuracies in the isotropic etching process to create gaps 172. Such a process may result in an interface of the spacer with the gate region that is not substantially coplanar with the gate region (a result of conformal deposition of a previously patterned anisotropically etched gate region).

[0111] 12A-12D, a pullback of the sacrificial layer 138 (e.g., SiGe 30) and buffer layer 148 (e.g., SiGe 30) of the bottom FET of the CFET is performed to create sacrificial layer 139 and buffer layer 149. A selective etch is performed to recess the exposed lower nanosheets 128 along the sidewalls of the nanosheet stack. This recess etch forms pockets along the sidewalls that are then filled with spacer material. In embodiments where the sacrificial layer 138 and buffer layer 148 are SiGe, a SiGe selective non-directional (isotropic) etch process can be used for the recess etch.

[0112] 13A-13D, formation of bottom spacer 240 for the bottom FET of the CFET is performed. Suitable materials for bottom spacer 240 include, but are not limited to, SiOx, SiC, or SiCO, or combinations thereof. A process such as CVD, ALD, or PVD may be utilized to deposit dielectric spacer 230 along sacrificial layer 139, followed by an isotropic etch to remove all spacer liner 240 except for the pinched-off areas in regions 149 and 139. Bottom spacer 240 may have a structural interface that distinguishes it from previously formed spacer 220 and top spacer 230. Such an interface may be the result of deposition of the spacers in separate stages. Additionally, bottom spacer 240 may have a different thickness than spacer 220 and top spacer 230, which may be the result of inaccuracies in the selective etching process of sacrificial layer 138 and buffer layer 148. Such a process may result in an interface of the spacer with the gate region that is not substantially coplanar with the gate region (a result of conformal deposition of a previously patterned anisotropically etched gate region).

[0113] 14A-14D, formation and patterning of bottom source / drain 250, source / drain isolation layer 255, and top source / drain 260 is performed. Bottom source / drain 250 is then formed in a trench on the opposite side of lower nanosheet 128. See, for example, U.S. Patent No. 10,418,449, issued to Paul et al., entitled "Circuits Based on Complementary Field Effect Transistors," the contents of which are incorporated by reference as if fully set forth herein.

[0114] According to an exemplary embodiment, the lower source / drains are each formed from an epitaxial material, such as epitaxial Si, epitaxial SiGe, etc., that is in-situ doped (i.e., during growth) or ex-situ doped (e.g., via ion implantation). Suitable n-type dopants include, but are not limited to, phosphorus (P) or arsenic (As) or combinations thereof. Suitable p-type dopants include, but are not limited to, boron (B). With internal spacers 240 disposed along the sidewalls, the epitaxial growth of the bottom source / drain 250 and the top source / drain 260 is templated by the (exposed) edges of the lower nanosheet 128 and the fin 155, respectively. As provided above, the lower nanosheet may form a device of a first polarity, i.e., a PFET or an NFET, and if the lower device is a PFET, the upper nanosheet in the stack may form a device of a second / opposite polarity, i.e., an NFET, or vice versa. For example, in one exemplary non-limiting embodiment, the lower nanosheet forms a PFET, whereby the bottom source / drain 250 includes a p-type dopant, and the upper nanosheet forms an NFET, whereby the top source / drain 260 includes an n-type dopant.

[0115] That is, according to an exemplary embodiment, a first (n or p type) doped epitaxial material is grown in the trench on the opposite side of the channel and then recessed to form the bottom source / drain 250. A directional (anisotropic) etching process, such as RIE, may be used to recess the bottom source / drain 250.

[0116] A spacer material may be deposited in the trench above the bottom source / drain 250 and then recessed to form the source / drain isolation layer 255. Suitable materials for the source / drain isolation layer 255 include, but are not limited to, SiN, SiOx, SiC, or SiCO, or combinations thereof. Processes such as CVD, ALD, or PVD may be utilized to deposit the spacer material.

[0117] A second (n or p type) doped epitaxial material is grown in the trenches on the opposite side of the nanosheet stack 30 and on one side of the nanosheet stack 31 above the source / drain isolation layer 255, which then forms the recessed top source / drain 260. A directional (anisotropic) etching process such as RIE may be used to recess the top source / drain 260.

[0118] 15A-15D, following the formation of the ILD 270, the dummy gate hard mask 210 is removed by CMP to expose the dummy gate 200. Suitable ILD materials include, but are not limited to, oxide low-K materials, such as silicon oxide (SiOx), or oxide ultra-low-K interlayer dielectrics (ULK-ILDs), or combinations thereof, having a dielectric constant K value of less than 2.7. In comparison, silicon dioxide (SiO2) has a dielectric constant K value of 3.9. Suitable ultra-low-K dielectric materials include, but are not limited to, porous organo-silica glass (pSiCOH). A process such as CVD, ALD, or PVD may be utilized to deposit the ILD 270 around the sacrificial gate 200. Following deposition, the ILD 270 may be planarized using a process such as chemical mechanical polishing (CMP) to a height below the dummy gate hard mask 210, thereby exposing the dummy gate 200.

[0119] 16A-16D, removal of the dummy gate 200, the buffer layer 149, and the sacrificial layer 139 may occur. The dummy gate 200 may be removed by any suitable etching process known in the art that allows for selective removal of the dummy gate 200 without substantially removing material from the surrounding structure. In an exemplary embodiment, the dummy gate 200 may be removed by a wet etching process that is capable of selectively removing, for example, a-Si. The buffer layer 149 and the sacrificial layer 139 that are now accessible through the gate trench are then selectively removed. Removal of these nanosheets frees the lower nanosheet 128 and the fin 157. That is, there is now a gap between the lower nanosheet 128 and the fin 157 in the channel region of the device. In this example, the lower nanosheet 128 and the fin 157 are used to form the channel of the stack device. The gate trenches and gaps in the lower nanosheet 128 and fin 157 enable a substitutional metal gate (RMG), i.e., one comprising a gate dielectric and at least one work function metal, to be formed to fully surround a portion of each of the nanosheet channels in a gate-all-around configuration.

[0120] With reference to FIGS. 17A-17D, formation of the RMG 300 and contacts 310 may occur. The RMG 300 may include a gate dielectric, a work function metal, and a metal contact. A conformal gate dielectric may be deposited into and lining each of the gate trenches and gaps in the channel region of the device. According to an exemplary embodiment, the gate dielectric is a high-K material. As used herein, the term "high-K" refers to a material that has a relative dielectric constant K much higher than silicon dioxide (e.g., dielectric constant K=25 for hafnium oxide (HfO2) and 4 for SiO2). Suitable high-K gate dielectrics include, but are not limited to, HfO2 or lanthanum oxide (La2O3), or combinations thereof. To deposit the gate dielectric, processes such as CVD, ALD, or PVD may be utilized. According to an exemplary embodiment, the gate dielectric is about 1 nanometer (nm) to about 5 nm thick and in the range therebetween. Following deposition of the gate dielectric, a high reliability anneal may be performed. In one embodiment, the high reliability anneal is performed for a period ranging from about 1 nanosecond to about 30 seconds and at a temperature ranging from about 500° C. to about 1200° C. and therebetween. Preferably, the high reliability anneal is performed in the presence of an inert gas, such as nitrogen-containing air.

[0121] 17A-17D, a first work function metal may be deposited in the gate trench and gap on the gate dielectric. The first work function metal may conform to the selected polarity of the gate. At this point in the process, the first work function metal is disposed on the lower nanosheet 128 and the fin 157. However, as described in detail below, this first work function metal is later removed from the fin 157 and replaced with a second work function metal of the opposite polarity. That is, if the first work function metal is a p-type metal, the second work function metal may be an n-type metal, or vice versa. In yet another embodiment, the first work function metal and the second work function metal may be of the same polarity (both n-type or both p-type).

[0122] Suitable n-type work function metals include, but are not limited to, alloys containing titanium nitride (TiN), tantalum nitride (TaN), or aluminum (Al), or combinations thereof, such as titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), or tantalum aluminum carbide (TaAlC), or combinations thereof. Suitable p-type work function metals include, but are not limited to, TiN, TaN, or tungsten (W), or combinations thereof. TiN and TaN are relatively thick (e.g., greater than about 2 nm) when used as p-type work function metals. However, very thin TiN or TaN layers (e.g., less than about 2 nm) may also be used under Al-containing alloys in n-type work function stacks to improve electrical properties such as gate leakage current. Thus, there is some overlap in the exemplary n-type and p-type work function metals given above.

[0123] To deposit the first work function metal, a process such as CVD, ALD, or PVD may be utilized. After deposition, a process such as CMP may be used to remove the metal overburden. Additionally, it should be noted that although this example shows a first work function metal pinching off the gap between the lower nanosheets 131 and 133, other work function metal configurations are also contemplated herein, such as a first work function metal or a second work function metal or combinations thereof comprised of multiple metals or multiple layers of metals or combinations thereof.

[0124] To remove the first work function metal from the fin 157, the first work function metal and the gate dielectric are first recessed in the gate trench. To do so, a planarizing material such as an OPL material is deposited over the device structure and in the gate trench and then recessed. To deposit the planarizing material, a casting process such as spin coating or spray casting can be utilized. A directional (anisotropic) etching process such as RIE can be used to recess the planarizing material. The first work function metal and the gate dielectric are then recessed (e.g., using an anisotropic etching process such as RIE) down to the (recessed) planarizing material. The planarizing material is removed. By way of example only, a process such as ashing can be used to remove the OPL planarizing material.

[0125] The first work function metal is then removed from the fin 157. A recess etch is used to remove the first work function metal from the fin 157. A block mask is used to cover / mask the first work function metal disposed on the lower nanosheet 128.

[0126] According to an exemplary embodiment, the recess etch of the first work function metal is performed using a non-directional (isotropic) metal selective etch process. For example, a SC1 wet clean (e.g., hydrofluoric acid (HF) and hydrogen peroxide (H2O2); ammonium hydroxide (NH4OH) mixture) may be utilized to recess the work function metal selectively to the gate dielectric.

[0127] Removing the first work function metal from the fin 157 reopens the gate trench and gap in the fin 157. A second work function metal may be deposited in the gate trench and gap on the gate dielectric. The second work function metal may be selected as a suitable n-type or p-type material based on the desired device characteristics. Suitable n-type and p-type work function metals are provided above.

[0128] To deposit the second work function metal, a process such as CVD, ALD or PVD may be utilized. After deposition, a process such as CMP may be used to remove the metal overburden. Additionally, while this example shows the second work function metal pinching off the gap between the fins 157, it should be noted that other work function metal configurations are also contemplated herein, such as a first work function metal or a second work function metal or combinations thereof comprised of multiple metals or multiple layers of metals or combinations thereof. As shown in Figures 26A and 26B, after deposition, the second work function metal is recessed in the gate trench. A process for recessing the work function metal in this manner, i.e., using a planarizing material such as OPL, has been described above.

[0129] A low resistivity gate fill metal may be deposited and recessed into the gate trench above the second work function metal. Suitable low resistivity gate fill metals include, but are not limited to, TiN or W or combinations thereof. Processes such as CVD, ALD or PVD may be utilized to deposit the low resistivity gate fill metal into the gate trench.

[0130] A damascene process, a sidewall image process, or any other process capable of precisely forming a trench over the desired contact may be used to form the contact 310. Following trench formation, the trench may be filled with a conductive material such as copper and any seed material or liner that may aid in adhesion / conduction, thereby forming the contact 310.

[0131] Referring to Figure 18, a top view of the fin region 1001 and gate region 1002 is depicted, with x and y cross sections of each region shown in Figures 19-30B. The straight line x in the cross section of the gate region 10 may be used to indicate structures disposed in the gate region 10 during each stage. The straight line y in the cross section of the fin region 20 may be used to indicate structures disposed along each transistor device during each stage.

[0132] 19, a layered structure according to a second exemplary embodiment is depicted. The layered structure includes a substrate 1100, a first sacrificial layer 1110, a bottom semiconductor nanosheet 1120, a sacrificial nanosheet 1130, an oxide layer 1140, and a top semiconductor layer 1150. The layered structure may be formed by bonding an SOI structure having an oxide box layer 1140 and a top semiconductor layer 1150 to the layered structure including the base substrate 1100, the first sacrificial layer 1110, the bottom semiconductor nanosheet 1120, and the sacrificial nanosheet 1130.

[0133] According to an exemplary embodiment, the base substrate 1100 of the first substrate 1010 may be a bulk semiconductor wafer, such as a silicon (Si), germanium (Ge) or III-V semiconductor wafer or a combination thereof. The first sacrificial layer 1110, the bottom semiconductor nanosheet 1120 and the sacrificial nanosheet 1130 may be epitaxially deposited to form the first substrate 1010 according to the steps described below.

[0134] According to an exemplary embodiment, the substrate 1020 is a semiconductor, such as a silicon (Si), germanium (Ge), or III-V or combination semiconductor wafer, having an oxide layer 1140 formed by oxidizing a Si substrate 1150.

[0135] The term "nanosheet" as used herein refers to a sheet or layer having nanoscale dimensions. Furthermore, the term "nanosheet" is meant to encompass other nanoscale structures such as nanowires. For example, a "nanosheet" can refer to a nanowire having a larger width, or a "nanowire" can refer to a nanosheet having a smaller width, or a combination thereof, or vice versa.

[0136] In general, the material stack disposed on the base substrate includes a bottom semiconductor nanosheet 1120 separated by a sacrificial nanosheet 1130 disposed on a first sacrificial nanosheet 1110. By "sacrificial" it is meant that the layer or a portion thereof is removed during the fabrication of the device. By way of example only, each of the nanosheets 1110, 1120 and 1130 in the material stack is deposited on top of the other on the base substrate 1100 using an epitaxial growth process. According to an exemplary embodiment, each of the nanosheets 1110, 1120 and 1130 in the material stack has a thickness ranging from about 10 nanometers (nm) to about 25 nm and therebetween. After depositing the material stack to form the first substrate 1010, the first substrate 1010 is bonded to the second substrate 1020 and the top portion of 1150 is split and removed.

[0137] The lower nanosheet comprises alternating layers of bottom semiconductor nanosheet 1120 and sacrificial nanosheet 1130. For example, according to an exemplary embodiment, bottom semiconductor nanosheet 1120 is Si and sacrificial nanosheet 1130 is SiGe. However, this is merely an example and other configurations are contemplated herein. Additionally, while there are two nanosheets in bottom semiconductor nanosheet 1120, additional nanosheets are contemplated. For example, in an alternative embodiment, the first nanosheet material is SiGe while the second nanosheet material is Si. As will be explained in detail below, these nanosheet materials are used to form the channels of the existing stack nanosheet device and the sacrificial material between the channels. Removal of the sacrificial material releases the channel from the stack and allows for the formation of a gate that completely surrounds the channel in a gate-all-around configuration. It is therefore preferred that the first and second nanosheet materials have etch selectivity with respect to each other. Thus, when one serves as the channel, the other sacrificial material can be selectively removed to release the channel from the stack. By way of example only, Si and SiGe provide such etch selectivity. Additionally, the first sacrificial nanosheet 1110 may be selected for selectivity with respect to the bottom semiconductor nanosheet 1120 and the sacrificial nanosheet 1130.

[0138] According to an exemplary embodiment, the sacrificial nanosheet 1110 is formed from SiGe having a high germanium (Ge) content. For example, in one exemplary embodiment, the high Ge content ranges from about 50% Ge to about 100% Ge (i.e., pure Ge) and in between. For example, in one non-limiting example, the sacrificial nanosheet 1110 is SiGe60 (having a Ge content of about 60%). The use of a higher Ge content allows the SiGe to be etched selectively relative to the nanosheet 1120, and as provided above, the sacrificial layer 1130 can be formed from Si or SiGe60 or a combination thereof. However, it should be noted that the SiGe used as the sacrificial material 1130 has a low Ge content. For example, in one exemplary embodiment, the low Ge content ranges from about 20% Ge to about 50% Ge and in between. For example, in one non-limiting example, the bottom semiconductor nanosheet 1120 and the top semiconductor layer 1150 are formed from Si.

[0139] Referring to (X-cut) FIG. 20A and (Y-cut) FIG. 20B, formation of a hard mask 1170 on the surface of the top semiconductor layer 1150 and the vertical channel 1152 from the top semiconductor layer 1150 may occur. Next, the hard mask 1170 is formed on the material stack. Suitable materials for the hard mask 1170 include, but are not limited to, nitride materials such as silicon nitride (SixNy), silicon oxynitride (SiON), or silicon carbonitride (SiCN) or combinations thereof, or oxide materials such as silicon oxide (SiOx), or combinations thereof. The vertical channel 1152 may be patterned using a sidewall image transfer technique, formed on the hard mask 1170, and etched into the oxide layer 1140.

[0140] 21A and 21B, the formation of a hard mask pattern 1160 and the removal of non-patterned materials may result in the creation of the footprint of the nanosheet device and the formation of the STI 1105. Following the removal of the non-patterned materials, the first sacrificial layer 1115, the bottom semiconductor nanosheet 1125, the second sacrificial layer 1135, and the oxide layer 1145 may remain. A hard mask pattern 1160 is then formed on the material stack. Suitable materials for the hard mask pattern 1160 include, but are not limited to, nitride materials such as silicon nitride (SixNy), silicon oxynitride (SiON), or silicon carbonitride (SiCN) or combinations thereof, or oxide materials such as silicon oxide (SiOx), or combinations thereof. The hard mask pattern may define the width of the device, and the pattern may be transferred to the base substrate 1100.

[0141] Next, shallow trench isolation (STI) regions 1105 are formed in the base substrate 1000. According to an exemplary embodiment, the STI regions 1105 may be formed from an oxide material (also referred to herein as "STI oxide") such as silicon oxide (SiOx). Although not explicitly shown in the figures, a liner (e.g., thermal oxide or silicon nitride (SiN)) may be deposited before the STI oxide.

[0142] 22A and 22B, the hard mask patterns 1160 and 1170 may be removed and a dummy gate 1180, a hard mask 1190 and a top spacer 1200 may be formed. Additionally, the first sacrificial layer 1115 may be removed and replaced with an isolation layer 1195. To form the dummy gate 1180, a sacrificial gate material is first blanket deposited onto the structure of FIGS. 21A and 21B. Suitable sacrificial gate materials include, but are not limited to, a thin layer of SiO2 followed by polysilicon (poly-Si) or amorphous silicon (a-Si) or a combination thereof. Processes such as CVD, ALD or PVD may be utilized to deposit the sacrificial gate material.

[0143] The dummy gate 1180 serves as a placeholder for the final gate of the stacked nanosheet device. That is, the dummy gate 1180 is removed later in the process and replaced with a metal gate stack that serves as the final gate of the stacked nanosheet device. Thus, these final gates of the stacked nanosheet device are also referred to herein as "replacement metal gates" or simply "RMG". The use of the RMG process is advantageous because it prevents exposure of the metal gate stack materials to potentially harmful conditions during subsequent processing steps. For example, the high-K dielectrics used in the RMG gate stacks can be damaged by exposure to high temperatures. Thus, these gate stack materials are placed only near the end of the process.

[0144] A hard mask 1190 is then formed on the sacrificial gate material to mark the footprint and location of each of the dummy gates 1180. Suitable materials for the hard mask 1190 include, but are not limited to, nitride hard mask materials such as SiN, SiON, or SiCN or combinations thereof, or oxide hard mask materials such as SiOx or combinations thereof. An etch using the hard mask 1190 is then used to pattern the sacrificial gate material into the individual dummy gates 1180 shown in Figures 22A and 22B. A directional (anisotropic) etch process such as RIE may be utilized for the sacrificial gate etch. After the gate etch, the first sacrificial layer 1115 is removed by any suitable isotropic etch that removes the first sacrificial layer 1115 selective to the surrounding layers, forming a cavity under the stack 1010.

[0145] The top spacer 1200 may be formed by conformal deposition followed by reactive ion etching (RIE). The top spacer 1200 may be formed from any suitable dielectric material. The conformal deposition of the top spacer also fills the cavity created by removing the first sacrificial layer 1115, forming the bottom dielectric isolation 1195.

[0146] 23A and 23B, the vertical channel 1152 may be formed into the top channel 1155 (FIGS. 22A and 22B) and a sacrificial top spacer 1210 may be formed. The top spacer 1200 may be used to define the footprint of the top device 1152. The formation of the vertical channel 1152 may be performed using an anisotropic etch such as RIE, with the top spacer 1200 acting as a mask for the etch. Following the formation of the vertical channel 1152, the sacrificial top spacer 1210 may be formed by conformal deposition of a material followed by an RIE etch. The sacrificial top spacer 1210 may be formed from any material that can be selectively removed from the structure.

[0147] 24A and 24B, the channel region of the bottom FET may be formed based on the pattern of the sacrificial top spacer 1210. Following the formation of the channel region of the bottom FET, the bottom channel 1127, the second sacrificial layer 1137, and the oxide layer 1147 may be formed. The sacrificial top spacer 1210 may be used to define the footprint of the bottom semiconductor nanosheet 1125.

[0148] 25A and 25B, the second sacrificial layer 1137 may be pulled back to form the second sacrificial layer 1138, and the bottom spacer 1220 may be formed. Additionally, the bottom source / drain 1230 and the source / drain isolation layer 1240 may be formed. A selective etch is performed to recess the exposed second sacrificial layer 1137 along the sidewalls of the nanosheet stack. This recess etch forms pockets along the sidewalls that are then filled with spacer material. In an embodiment where the second sacrificial layer 1138 is SiGe 30, a SiGe selective non-directional (isotropic) etch process may be used for the recess etch. The formation of the bottom spacer 1220 for the bottom FET of the CFET is performed. Suitable materials for the bottom spacer 1220 include, but are not limited to, SiOx, SiC, or SiCO, or combinations thereof. A process such as CVD, ALD or PVD may be utilized to deposit the bottom spacer 1220 along the second sacrificial layer 1138, followed by an isotropic etch of all of the bottom spacer 1220 except for the area that is pinched off in the recess.

[0149] According to an exemplary embodiment, the lower source / drain are each formed from an epitaxial material, such as epitaxial Si, epitaxial SiGe, etc., that is in-situ doped (i.e., during growth) or ex-situ doped (e.g., via ion implantation). Suitable n-type dopants include, but are not limited to, phosphorus (P) or arsenic (As) or combinations thereof. Suitable p-type dopants include, but are not limited to, boron (B). The epitaxial growth of the bottom source / drain 1230 is templated by the (exposed) end of the bottom channel 1127, due to the sacrificial spacer 1210 disposed along the sidewall of the vertical channel 1152. As provided above, the lower nanosheet may form a device of a first polarity, i.e., a PFET or an NFET, and if the lower device is a PFET, the upper nanosheet in the stack may form a device of a second / opposite polarity, i.e., an NFET, or vice versa. For example, in one exemplary non-limiting embodiment, the lower nanosheet forms a PFET, whereby the bottom source / drain 1230 comprises a p-type dopant, and the upper nanosheet forms an NFET, whereby the top source / drain 1250 comprises an n-type dopant.

[0150] That is, according to an exemplary embodiment, a first (n or p type) doped epitaxial material is grown in the trench on the opposite side of the channel and then recessed to form the bottom source / drain 1230. A directional (anisotropic) etching process such as RIE may be used to recess the bottom source / drain 1230.

[0151] A spacer material may be deposited into the trench above the bottom source / drain 1230 and then recessed to form the bottom spacer 1220. Suitable materials for the bottom spacer 1220 include, but are not limited to, SiN, SiOx, SiC, or SiCO, or combinations thereof. Processes such as CVD, ALD, or PVD may be utilized to deposit the spacer material.

[0152] 26A and 26B, the sacrificial spacer 1210 may be removed and the top source / drain 1250 may be formed. The sacrificial spacer 1210 may be removed using any process capable of selectively removing material with respect to other materials of the structure, thereby exposing the vertical channel 1152. A second (n- or p-type) doped epitaxial material is grown in the trench opposite the vertical channel on the source / drain isolation layer 255 and then recessed to form the top source / drain 260. A directional (anisotropic) etching process such as RIE may be used to recess the top source / drain 260.

[0153] 27A and 27B, formation of the ILD 1260 and removal of the hard mask 1190, the dummy gate 1180, and the second sacrificial layer 1138 may occur. Suitable ILD materials include, but are not limited to, oxide low-K materials, such as silicon oxide (SiOx), or oxide ultra-low-K interlayer dielectric (ULK-ILD) materials, or combinations thereof, having a dielectric constant K of less than 2.7. In comparison, silicon dioxide (SiO2) has a dielectric constant K value of 3.9. Suitable ultra-low-K dielectric materials include, but are not limited to, porous organo-silica glass (pSiCOH). A process such as CVD, ALD, or PVD may be utilized to deposit the ILD 1260 around the sacrificial gate 200. Following deposition, the ILD 1260 may be planarized using a process such as chemical mechanical polishing (CMP) to a height below the hard mask 1190, thereby exposing the dummy gate 1180.

[0154] Removal of the dummy gate 1180 and the sacrificial layer 1138 may occur. The dummy gate 1180 may be removed by any suitable etching process known in the art that allows for selective removal of the dummy gate 1180 without substantially removing material from the surrounding structure. In an exemplary embodiment, the dummy gate 1180 may be removed by, for example, an isotropic wet etching process that can selectively remove silicon. The sacrificial layer 1138, now accessible through the gate trenches, is then selectively removed. Removal of these nanosheets frees the bottom channels 1127; that is, there is now a gap between the bottom channels 1127 in the channel region of the device. In this example, the bottom channels 1127 are used to form the channels of the stacked device. The gate trenches and gaps in the bottom channels 1127 allow a replacement metal gate (RMG), i.e., one that includes a gate dielectric and at least one work function metal, to be formed to fully surround a portion of each of the nanosheet channels in a gate-all-around configuration.

[0155] With reference to FIG. 28A and FIG. 28B, deposition of the gate dielectric 1270 may occur. A conformal gate dielectric 1270 may be deposited into and lining each of the gate trenches and gaps in the channel region of the device. According to an exemplary embodiment, the gate dielectric 1270 is a high-K material. As used herein, the term "high-K" refers to a material having a relative dielectric constant K much higher than silicon dioxide (e.g., dielectric constant K=25 for hafnium oxide (HfO2) and 4 for SiO2). Suitable high-K gate dielectrics include, but are not limited to, HfO2 or lanthanum oxide (La2O3), or combinations thereof. To deposit the gate dielectric, processes such as CVD, ALD, or PVD may be utilized. According to an exemplary embodiment, the gate dielectric 1270 is about 1 nanometer (nm) to about 5 nm thick and in the range therebetween. Following deposition of the gate dielectric 1270, a high reliability anneal may be performed. In one embodiment, the high reliability anneal is performed for a period ranging from about 1 nanosecond to about 30 seconds and at a temperature ranging from about 500° C. to about 1200° C. and therebetween. Preferably, the high reliability anneal is performed in the presence of an inert gas, such as nitrogen-containing air.

[0156] 29A and 29B, deposition and reduction of work function metal 1280 may occur. Reduction of work function metal 1280 may occur only in the work function metal surrounding the bottom channel 1127. Work function metal 1280 may be deposited into the gate trench and gap on the gate dielectric. The work function metal 1280 may follow the selected polarity of the gate. At this point in the process, the work function metal 1280 is disposed on the bottom channel 1127 and the vertical channel 1152. However, this work function metal 1280 will later be removed from the vertical channel 1152, as will be described in more detail below.

[0157] Suitable n-type work function metals include, but are not limited to, alloys containing titanium nitride (TiN), tantalum nitride (TaN), or aluminum (Al), or combinations thereof, such as titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), or tantalum aluminum carbide (TaAlC), or combinations thereof. Suitable p-type work function metals include, but are not limited to, TiN, TaN, or tungsten (W), or combinations thereof. TiN and TaN are relatively thick (e.g., greater than about 2 nm) when used as p-type work function metals. However, very thin TiN or TaN layers (e.g., less than about 2 nm) may also be used under Al-containing alloys in n-type work function stacks to improve electrical properties such as gate leakage current. Thus, there is some overlap in the exemplary n-type and p-type work function metals given above.

[0158] To deposit the work function metal 1280, a process such as CVD, ALD or PVD may be utilized. Following deposition, a process such as CMP may be used to remove the metal overburden. Additionally, while this example shows work function metal 1280 pinching off the gap between the lower nanosheets 131 and 133, it is noted that other work function metal configurations are also contemplated herein, such as a first work function metal or a second work function metal or combinations thereof comprised of multiple metals or multiple layers of metals or combinations thereof.

[0159] To remove the work function metal 1280 from the vertical channel 1152, the work function metal 1280 and the gate dielectric are first recessed in the gate trench. To do so, a planarizing material such as an OPL material is deposited over the device structure and into the gate trench and then recessed. To deposit the planarizing material, a casting process such as spin coating or spray casting can be utilized. A directional (anisotropic) etching process such as RIE can be used to recess the planarizing material. The work function metal 1280 and the gate dielectric are then recessed (e.g., using an anisotropic etching process such as RIE) down to the (recessed) planarizing material. The planarizing material is removed. By way of example only, a process such as ashing can be used to remove the OPL planarizing material.

[0160] The work function metal 1280 is then removed from the vertical channels 1152. A recess etch is used to remove the work function metal 1280 from the vertical channels 1152. A block mask is used to cover / mask the work function metal 1280 disposed on the lower nanosheet 128.

[0161] According to an exemplary embodiment, the recess etch of the work function metal 1280 is performed using a non-directional (isotropic) metal selective etch process. For example, a SC1 wet clean (e.g., hydrofluoric acid (HF) and hydrogen peroxide (H2O2); ammonium hydroxide (NH4OH) mixture) may be utilized to recess the work function metal selectively to the gate dielectric.

[0162] Referring to FIG. 30A and FIG. 30B, a second WFM metal (1290 is a combination of the second WFM and the gate fill metal) followed by a low resistivity gate fill metal can be deposited on the gate. The low resistivity gate fill metal can be deposited in the gate trench. Suitable low resistivity gate fill metals include, but are not limited to, W, Co, Al. Processes such as CVD, ALD or PVD can be utilized to deposit the low resistivity gate fill metal in the gate trench. The second WFM can be TiN, TiC, TiAl, TiAlC, TaN, etc.

[0163] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. Therefore, it is intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a top channel and a bottom channel, the top channel including a plurality of vertically oriented channels and the bottom channel including a plurality of horizontally oriented channels; a gate surrounding the top channel and the bottom channel; a spacer disposed on each side of the gate, a first spacer including a dielectric material disposed between the vertically oriented channels and a second spacer including a dielectric material disposed between the horizontally oriented channels; Equipped with The second spacer further comprises a top element, the top element comprising a dielectric material contacting a bottom surface of the top channel and a top surface of the bottom channel.

2. 2. The semiconductor structure of claim 1, wherein a structure interface exists between the first spacer and the second spacer.

3. 2. The semiconductor structure of claim 1, wherein the top element has a top and a bottom, the top including a plurality of fin protrusions, each fin protrusion being disposed below each of the plurality of vertically oriented channels, and the bottom including a horizontal layer connecting each of the plurality of fin protrusions of the top.

4. A gate structure; a top channel, the top channel including at least one vertically oriented channel, an entire bottom surface of the at least one vertically oriented channel contacting an insulator layer, and a top surface and a vertical surface of the at least one vertically oriented channel contacting the gate structure; a bottom channel, the bottom channel including a plurality of horizontally oriented channels, the gate structure surrounding the bottom channel; A semiconductor structure comprising:

5. 5. The semiconductor structure of claim 4, wherein a dielectric of the gate structure is disposed on each surface of the bottom channel, the dielectric of the gate structure is disposed on the top surface, the vertical surface of the at least one vertically oriented channel contacts the gate structure, and the dielectric of the gate structure is disposed on a surface of the insulator layer that is not contacting the at least one vertically oriented channel.

6. A gate structure; a top channel, the top channel including at least one vertically oriented channel, a bottom surface of the at least one vertically oriented channel contacting an insulator layer, and a top surface and a vertical surface of the at least one vertically oriented channel contacting the gate structure; a bottom channel, the bottom channel including a plurality of horizontally oriented channels, the gate structure surrounding the bottom channel; Equipped with 1. A semiconductor structure, comprising: a gate structure dielectric disposed on each surface of the bottom channel; a gate structure dielectric disposed on the top surface; a vertical surface of the at least one vertically oriented channel contacting the gate structure; and a gate structure dielectric disposed on a surface of the insulator layer that is not contacting the at least one vertically oriented channel.

7. 7. The semiconductor structure of claim 1, wherein the top channel is part of a first transistor and the bottom channel is part of a second transistor.

8. 8. The semiconductor structure of claim 7, wherein said first transistor and said second transistor form complementary field effect transistors.

9. 1. A method of forming a semiconductor structure, comprising: forming a top channel in a semiconductor layer disposed over the layered nanosheet stack, the top channel comprising a plurality of vertically oriented channels; depositing a sacrificial liner between said vertically oriented channels; forming a dummy gate over the top channel; forming gate spacers on vertically opposing surfaces of the dummy gate; removing a portion of the sacrificial liner disposed under the gate spacer to create a spacer gap; depositing a top spacer in the spacer gap; A method for providing the above.

10. 10. The method of claim 9, further comprising forming a bottom spacer, the bottom spacer including a dielectric material disposed between a plurality of horizontally oriented channels and a top element including a dielectric material contacting a bottom surface of the top channel and a top surface of the bottom channel.

11. The method of claim 10 , wherein a structure interface exists between the top spacer and the gate spacer.

12. 11. The method of claim 10, wherein the top element has a top and a bottom, the top including a plurality of fin protrusions, each fin protrusion being disposed beneath each of a plurality of vertically oriented channels, and the bottom including a horizontal layer connecting each of the plurality of fin protrusions of the top.

13. 1. A method of forming a semiconductor structure, comprising: forming a top channel in a semiconductor layer disposed on the layered nanosheet stack, the top channel comprising a plurality of vertically oriented channels, a bottom surface of the plurality of vertically oriented channels contacting an insulator layer, the layered nanosheet stack comprising a plurality of sacrificial nanosheets disposed between a plurality of semiconductor nanosheets; forming a dummy gate over the top channel; forming gate spacers on vertically opposing surfaces of the dummy gate; removing the dummy gate and the sacrificial nanosheet to form a gate gap; depositing a dielectric in the gate gap, the dielectric surrounding the plurality of semiconductor nanosheets, and the dielectric disposed on top and vertical surfaces of the plurality of vertically oriented channels by depositing the dielectric. A method for providing the above.

14. 14. The method of claim 13, wherein the dielectric of the gate gap is disposed on each surface of a bottom channel, the dielectric of the gate gap is disposed on the top surface, the vertical surface of at least one of the vertically oriented channels contacts a gate structure, and the dielectric of the gate gap is disposed on a surface of an insulator layer that is not in contact with the at least one vertically oriented channel.

15. 15. The method of claim 9, wherein the top channel is part of a first transistor and the bottom channel is part of a second transistor.

16. 16. The method of claim 15, wherein the first transistor and the second transistor form complementary field effect transistors.

17. The method of claim 1, further comprising: a bottom source-drain region adjacent to an opposing side of the bottom channel; 7. The semiconductor structure of claim 4, further comprising:

18. A semiconductor structure as described in any one of claims 4 to 6, wherein a top surface of the insulator layer contacts a bottom surface of the top source-drain region.

19. A semiconductor structure as described in claim 5 or 6, wherein the dielectric of the gate structure is in direct contact with a bottom surface and an opposing sidewall of the insulator layer.

20. A semiconductor structure as described in any one of claims 4 to 6, wherein the width of the insulator layer measured parallel to the gate structure is substantially equal to the width of the bottom channel measured parallel to the gate structure.

21. A semiconductor structure as described in any one of claims 4 to 6, wherein the width of the top channel measured perpendicular to the gate structure is less than the width of the insulator layer measured perpendicular to the gate structure.

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