Inkjet head and inkjet recording device

Abstract

To provide an inkjet head that can be stopped when sensing an error, and an inkjet recording device.SOLUTION: An inkjet head according to an embodiment comprises a driving circuit, an interface, a determining circuit, and a switch. The driving circuit supplies a driving voltage to an ejecting part that ejects ink. The interface obtains a state parameter showing a state of the ejecting part. The determining circuit determines whether an error condition is satisfied, on the basis of the state parameter. The switch, when the determining circuit determines that the error condition is satisfied, turns off the driving circuit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] An embodiment of the present invention relates to an inkjet head and an inkjet recording apparatus. [Background technology]

[0002] Some inkjet heads apply ejection pulses to actuators that contract and expand pressure chambers, thereby ejecting ink droplets from nozzles connected to the pressure chambers onto a medium such as paper. Such inkjet heads send parameters such as the pressure of the pressure chambers, the temperature of the ink, and the drive voltage to a host controller.

[0003] The host controller detects an error in the inkjet head based on the parameters, and when the host controller detects an error, it stops the inkjet head.

[0004] Conventionally, inkjet heads have the problem of being unable to autonomously detect errors and stop operation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-220544 Summary of the Invention [Problem to be solved by the invention]

[0006] In order to solve the above problem, an inkjet head and an inkjet recording device are provided that can detect an error and stop the operation. [Means for solving the problem]

[0007] According to an embodiment, an inkjet head includes a drive circuit, an interface, a determination circuit, and a switch. The drive circuit supplies a drive voltage to an ejection unit that ejects ink. The interface acquires a status parameter indicating the status of the ejection unit. The determination circuit determines whether an error condition is satisfied based on the status parameter. The switch turns off the drive circuit when the determination circuit determines that the error condition is satisfied. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram schematically illustrating an example of the configuration of an inkjet recording apparatus according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a control system of the inkjet printing apparatus according to this embodiment. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a head driving circuit according to the embodiment. [Figure 4] FIG. 4 is a flowchart showing an example of the operation of the inkjet head according to the embodiment. [Figure 5] FIG. 5 is a flowchart showing an example of the operation of the inkjet head according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] An inkjet recording apparatus according to an embodiment will be described below with reference to the drawings. An inkjet recording device according to an embodiment forms an image on a medium such as paper using an inkjet head. The inkjet recording device ejects ink droplets from pressure chambers in the inkjet head onto the medium to print an image on the medium. Examples of inkjet recording devices include office inkjet recording devices, barcode inkjet recording devices, POS inkjet recording devices, industrial inkjet recording devices, and 3D inkjet recording devices. Note that the medium on which the inkjet recording device forms an image is not limited to a specific configuration. The inkjet head included in the printer according to an embodiment is an example of a liquid ejection head, and ink is an example of a liquid.

[0010] FIG. 1 is a schematic diagram showing an example of the configuration of an inkjet recording apparatus 1 according to an embodiment. The inkjet recording apparatus 1 forms an image on an image forming medium S or the like using a recording material such as ink. The inkjet recording apparatus 1 includes, for example, a plurality of liquid ejection units 2, a head support mechanism 3 that movably supports the liquid ejection units 2, and a medium support mechanism 4 (support unit) that movably supports the image forming medium S. The image forming medium S is, for example, a sheet made of paper, cloth, resin, or the like.

[0011] As shown in Figure 1, a plurality of liquid ejection units 2 are arranged in parallel in a predetermined direction and supported by a head support mechanism 3. The head support mechanism 3 is attached to an endless belt 3b that is wound around a roller 3a. The inkjet recording device 1 can move the head support mechanism 3 in a main scanning direction A that is perpendicular to the transport direction of the image forming medium S by rotating the roller 3a.

[0012] The liquid ejection unit 2 integrally includes an inkjet head 10 and a circulation device 20 . The inkjet head 10 ejects ink droplets made of ink I onto an image forming medium S. The circulation device 20 also supplies the ink I to the inkjet head 10 and collects the ink I from the inkjet head 10.

[0013] The liquid ejection unit 2 performs an ejection operation to eject, as a liquid, for example, ink I from the inkjet head 10. As an example, the inkjet recording device 1 is a scan type that performs an ink ejection operation while moving the head support mechanism 3 back and forth in the main scanning direction A, thereby forming a desired image on an image forming medium S that is arranged opposite it. Alternatively, the inkjet recording device 1 may be a single-pass type that performs an ink ejection operation without moving the head support mechanism 3. In this case, the roller 3a and endless belt 3b may not be provided. In this case, the head support mechanism 3 is fixed to, for example, the housing of the inkjet recording device 1.

[0014] The liquid ejection units 2 eject, for example, four colors of ink corresponding to CMYK (cyan, magenta, yellow, and key (black)), that is, cyan ink, magenta ink, yellow ink, and black ink, respectively.

[0015] Next, the control system of the inkjet recording apparatus 1 will be described. FIG. 2 is a block diagram showing an example of the configuration of a control system of the inkjet recording apparatus 1. As shown in FIG. 2, the inkjet recording apparatus 1 includes a processor 201, a ROM 202, a RAM 203, an operation panel 204, a communication interface 205, a conveying motor 206, a motor driving circuit 207, a pump 208, a pump driving circuit 209, and an inkjet head 10. The inkjet head 10 includes a head driving circuit 11 and an ejection unit 12 that ejects ink.

[0016] The inkjet recording apparatus 1 also includes bus lines 211 such as an address bus and a data bus. The processor 201 is connected to a ROM 202, a RAM 203, an operation panel 204, a communication interface 205, a motor drive circuit 207, a pump drive circuit 209, and a head drive circuit 11 via the bus line 211, either directly or via an input / output circuit. The motor drive circuit 207 is connected to a transport motor 206. The pump drive circuit 209 is connected to a pump 208. The head drive circuit 11 is connected to a discharge unit 12.

[0017] The processor 201 has the function of controlling the overall operation of the inkjet recording apparatus 1. The processor 201 may also include an internal cache and various interfaces. The processor 201 performs various processes by executing programs stored in advance in the internal cache or ROM 202. The processor 201 performs various functions of the inkjet recording apparatus 1 in accordance with the operating system, application programs, etc.

[0018] Note that some of the various functions realized by the processor 201 executing the programs may be realized by hardware circuits. In this case, the processor 201 controls the functions executed by the hardware circuits. The processor 201 also functions as a host controller for the inkjet head 10 .

[0019] The ROM 202 is a non-volatile memory in which control programs, control data, etc. are stored in advance. The control programs and control data stored in the ROM 202 are pre-installed in accordance with the specifications of the inkjet recording apparatus 1. For example, the ROM 202 stores an operating system, application programs, etc.

[0020] The RAM 203 is a volatile memory. The RAM 203 temporarily stores data being processed by the processor 201. The RAM 203 stores various application programs based on instructions from the processor 201. The RAM 203 may also store data necessary for executing application programs and execution results of the application programs. The RAM 203 may also function as an image memory into which print data is expanded.

[0021] The operation panel 204 is an interface that accepts input of instructions from an operator and displays various information to the operator. The operation panel 204 is composed of an operation unit that accepts input of instructions and a display unit that displays information.

[0022] The operation panel 204 transmits a signal indicating an operation received from an operator as an operation of the operation unit to the processor 201. For example, the operation unit has function keys such as a power key, a paper feed key, and an error reset key.

[0023] The operation panel 204, as a display unit, displays various information under the control of the processor 201. For example, the operation panel 204 displays the status of the inkjet recording apparatus 1. For example, the display unit is configured by a liquid crystal monitor. The operation unit may be configured as a touch panel. In this case, the display unit may be formed integrally with the touch panel serving as the operation unit.

[0024] The communication interface 205 is an interface for transmitting and receiving data to and from an external device via a network such as a local area network (LAN). For example, the communication interface 205 is an interface that supports LAN connections. For example, the communication interface 205 receives print data from a client terminal via the network. For example, when an error occurs in the inkjet recording apparatus 1, the communication interface 205 transmits a signal notifying the client terminal of the error.

[0025] The motor drive circuit 207 controls the driving of the carry motor 206 in accordance with a signal from the processor 201. For example, the motor drive circuit 207 transmits power or a control signal to the carry motor 206.

[0026] The carry motor 206 is driven under the control of a motor drive circuit 207. The carry motor 206 functions as a drive source for the head support mechanism 3, the medium support mechanism 4, etc. For example, when the carry motor 206 is driven, the medium support mechanism 4 carries the medium. Also, when the carry motor 206 is driven, the head support mechanism 3 carries the inkjet head 10.

[0027] The pump drive circuit 209 controls the operation of the pump 208 according to a signal from the processor 201. For example, the pump drive circuit 209 transmits power or a control signal to the pump 208.

[0028] The pump 208 is driven under the control of a pump drive circuit 209. The pump 208 is a pump for circulating the ink I in the circulation device 20. When the pump 208 is driven, the ink I is supplied from the circulation device 20 to the inkjet head 10 and the ink I is collected from the inkjet head 10.

[0029] The inkjet head 10 includes a head drive circuit 11 and a discharge unit 12. The head drive circuit 11 supplies a drive voltage and the like to the ejection unit 12. For example, the head drive circuit 11 supplies an ejection pulse that causes the ejection unit 12 to eject ink droplets. The head drive circuit 11 also acquires parameters (state parameters) that indicate the state of the ejection unit 12. The head drive circuit 11 will be described in detail later.

[0030] The ejection unit 12 ejects ink droplets under control of the head drive circuit 11. The ejection unit 12 is composed of multiple channels including pressure chambers, actuators, electrodes, nozzles, etc. Based on control signals from the head drive circuit 11, the ejection unit 12 expands and contracts the actuators to eject ink droplets from each pressure chamber.

[0031] The ejection unit 12 also includes a sensor for measuring state parameters. For example, the sensor measures the state parameters such as the pressure in the pressure chamber and the temperature of the ink I. The ejection unit 12 transmits the measured state parameters (analog signals) to the head drive circuit 11.

[0032] The inkjet recording apparatus 1 may further include components as necessary in addition to the components shown in FIGS. 1 and 2, or certain components may be excluded from the inkjet recording apparatus 1.

[0033] Next, an example of the configuration of the head drive circuit 11 will be described. Fig. 3 is a block diagram showing an example configuration of the head drive circuit 11. As shown in Fig. 3, the head drive circuit 11 includes an ADC-integrated FPGA 100, a driver IC 120, and an FET 130. The ADC-integrated FPGA 100 is connected to the ejection unit 12, the driver IC 120, and the FET 130. The driver IC 120 is connected to the ejection unit 12 and the FET 130.

[0034] The FPGA 100 with built-in ADC outputs setting data to the driver IC 120 and outputs ejection pulses and the like to the ejection unit 12 under the control of the processor 201. The FPGA 100 with built-in ADC also acquires state parameters. The FPGA 100 with built-in ADC detects errors based on the state parameters. The ADC-integrated FPGA 100 will be described in detail later.

[0035] The driver IC 120 (drive circuit) outputs ejection pulses and the like to the ejection units 12 under the control of the ADC built-in FPGA 100. The driver IC 120 also receives a drive voltage and the like from a power source through the FET .

[0036] Before the setting of the discharge unit 12 is completed, the driver IC 120 inputs a signal (Low) indicating that the setting is incomplete to the AND circuit unit 111 (described later). Furthermore, when the setting is completed, the driver IC 120 inputs a signal (High, CNF_DONE) indicating that the setting is completed to the AND circuit unit 111.

[0037] The FET 130 (Field Effect Transistor) supplies a drive voltage from a power supply or the like to the driver IC 120. The FET 130 turns on or off the supply of the drive voltage or the like based on a control signal from the ADC built-in FPGA 100. In other words, the FET 130 functions as a switch that controls the driver IC 120 to turn on or off.

[0038] Next, the ADC-integrated FPGA 100 will be described. As shown in FIG. 3, the ADC-embedded FPGA 100 includes a data receiving circuit unit 101, a data processing unit 102, a data transfer circuit unit 103, an ADC 104, a moving average circuit unit 105, a FIFO 106, a non-volatile memory 107, a memory processing unit 108, a comparison unit 109, a serial communication unit 110, and an AND circuit unit 111.

[0039] The data receiving circuit unit 101 is connected to the data processing unit 102 and the comparison unit 109. The data processing unit 102 is connected to the data transfer circuit unit 103. The data transfer circuit unit 103 is connected to the driver IC 120.

[0040] The ADC 104 is connected to the output unit 12, the moving average circuit unit 105, the FIFO 106, the comparison unit 109, and the FET 130. The moving average circuit unit 105 is connected to the comparison unit 109. The comparison unit 109 is connected to the data transfer circuit unit 103, the memory processing unit 108, and the FET 130. The memory processing unit 108 is connected to the FIFO 106, the non-volatile memory 107, the serial communication unit 110, and the AND circuit unit 111. The AND circuit unit 111 is connected to the driver IC 120.

[0041] The data receiving circuit unit 101 receives preconfiguration data from the processor 201 etc. The preconfiguration data includes supervisory control parameters used for error detection etc. The supervisory control parameters will be described later.

[0042] The data receiving circuit unit 101 transmits the monitoring control parameters and the like to the comparison unit 109 .

[0043] The data receiving circuit unit 101 also receives data (print data) for outputting ejection pulses from the processor 201 or the like. The data receiving circuit unit 101 transmits the preconfiguration (or part of the configuration data), print data, and the like to the data processing unit 102.

[0044] The data processing unit 102 processes the configuration data, print data, etc. from the data receiving circuit unit 101. The data processing unit 102 transmits the processed configuration data, print data, etc. to the data transfer circuit unit 103.

[0045] The data transfer circuit unit 103 receives the configuration data and print data from the data processing unit 102 and transmits them to the driver IC 120 . The data transfer circuit unit 103 also receives a stop request to stop the driver IC 120 from the comparison unit 109. The data transfer circuit unit 103 transmits the received stop request to the driver IC 120.

[0046] The ADC 104 (Analog to Digital Converter) is an interface that acquires state parameters. The ADC 104 acquires the temperature of the ink I, the pressure of the pressure chamber, and the like from the ejection unit 12 as state parameters. The ADC 104 also acquires the drive voltage to the driver IC 120, and the like from the FET 130 as state parameters. The ADC 104 converts the acquired state parameters into digital signals.

[0047] The ADC 104 transmits the state parameters converted into digital signals to the moving average circuit unit 105 , the FIFO 106 and the comparison unit 109 .

[0048] The moving average circuit unit 105 receives the state parameters. The moving average circuit unit 105 calculates a moving average of the state parameters over a predetermined range. The moving average circuit unit 105 transmits the calculated moving average to the comparison unit 109.

[0049] The FIFO 106 (First in First out) is a volatile memory that temporarily stores the state parameters from the ADC 104. The FIFO 106 continues to store the state parameters from the ADC 104. When the capacity of the FIFO 106 for storing the state parameters reaches an upper limit, the FIFO 106 overwrites the oldest state parameters with new state parameters. In other words, the FIFO 106 temporarily stores the state parameters in a FIFO manner.

[0050] The non-volatile memory 107 non-temporarily stores the state parameters under the control of the memory processing unit 108. The non-volatile memory 107 is a memory to which data can be written and rewritten. For example, the non-volatile memory 107 is configured by a hard disk drive (HDD), a solid state drive (SSD), a flash memory, or the like.

[0051] The comparison unit 109 (determination circuit) determines whether the condition (write condition) for writing the state parameter to the nonvolatile memory is satisfied based on the state parameter (or the moving average of the state parameter) and the supervisory control parameter.

[0052] For example, the supervisory control parameters include threshold values ​​for comparing with the state parameters with respect to the writing conditions, such as a threshold value (such as 20° C.) for comparing with the temperature of the ink I. The monitoring control parameters may also include threshold values ​​that are compared with the length of a period (warning period) during which the state parameter is equal to or greater than a predetermined threshold value (or less than or equal to a predetermined threshold value). For example, the monitoring control parameters may include a threshold value (e.g., 10 seconds) that is compared with the length of a period during which the temperature of the ink I is equal to or greater than a predetermined threshold value (e.g., 20°C).

[0053] Additionally, the supervisory control parameters may include thresholds for multiple state parameters.

[0054] The comparison unit 109 compares the threshold value included in the monitoring control parameters with the state parameters. The comparison unit 109 determines whether the write condition is satisfied based on the comparison result. For example, the comparison unit 109 may determine that the write condition is satisfied when one of the state parameters is equal to or greater than (or equal to or less than) the threshold value (or when the length of the warning zone is equal to or greater than the threshold value). The comparison unit 109 may also determine that the write condition is satisfied when each state parameter is equal to or greater than (or equal to or less than) the threshold value (or when the length of each warning zone is equal to or greater than the threshold value). The comparison unit 109 may also determine that the write condition is satisfied when a predetermined number or more of the state parameters are equal to or greater than (or equal to or less than) the threshold value (or when the length of the warning zone is equal to or greater than the threshold value). The contents of the writing conditions are not limited to a specific configuration.

[0055] If it is determined that the write condition is met, the comparison unit 109 transmits a control signal (write signal) to the memory processing unit 108 to write the state parameter into the nonvolatile memory 107.

[0056] Furthermore, the comparison unit 109 determines whether the condition for detecting an error (error condition) is met based on the state parameter (or the moving average of the state parameter) and the supervisory control parameter.

[0057] For example, the monitoring control parameters include thresholds for comparing with the status parameters with respect to error conditions. That is, the monitoring control parameters include thresholds for writing conditions and thresholds for error conditions. The monitoring control parameters also store a threshold for the error condition that indicates that the status of the discharge unit 12 has deteriorated compared to the threshold for the writing condition.

[0058] For example, the supervisory control parameters include a threshold value (such as 30° C.) to which the temperature of ink I is compared. The monitoring control parameters may also include threshold values ​​that are compared with the length of a period (warning period) during which the state parameter is equal to or greater than a predetermined threshold value (or less than or equal to a predetermined threshold value). For example, the monitoring control parameters may include a threshold value (e.g., 20 seconds) that is compared with the period during which the temperature of the ink I is equal to or greater than a predetermined threshold value (e.g., 30°C).

[0059] Additionally, the supervisory control parameters may include thresholds for multiple state parameters.

[0060] The comparison unit 109 compares the state parameters with thresholds included in the monitoring and control parameters. The comparison unit 109 determines whether the error condition is satisfied based on the comparison result. For example, the comparison unit 109 may determine that the error condition is satisfied when one of the state parameters is equal to or greater than (or less than) the threshold (or when the length of the warning zone is equal to or greater than the threshold). The comparison unit 109 may also determine that the error condition is satisfied when each state parameter is equal to or greater than (or less than) the threshold (or when the length of each warning zone is equal to or greater than the threshold). The comparison unit 109 may also determine that the error condition is satisfied when a predetermined number or more of the state parameters are equal to or greater than (or less than) the threshold (or when the length of the warning zone is equal to or greater than the threshold). The nature of the error condition is not limited to any particular configuration.

[0061] If it is determined that the error condition is satisfied, the comparison unit 109 stops the ejection operation of the ejection unit 12. For example, the comparison unit 109 sends a stop request to the driver IC 120 through the data transfer circuit unit 103. The comparison unit 109 also turns off the FET 130. That is, the comparison unit 109 stops the supply of the drive voltage to the driver IC 120.

[0062] The memory processing unit 108 (memory processing circuit) stores the state parameters stored in the FIFO 106 in the non-volatile memory 107 under the control of the comparison unit 109. For example, when the memory processing unit 108 receives a write signal from the comparison unit 109, it retrieves the state parameters from the FIFO 106 going back a predetermined period. After retrieving the state parameters for the predetermined period, the memory processing unit 108 stores the retrieved state parameters for the predetermined period in the non-volatile memory 107.

[0063] Furthermore, the memory processing unit 108 may store the state parameters newly stored in the FIFO 106 in the non-volatile memory 107 until a predetermined period has elapsed since the reception of the write signal. That is, the memory processing unit 108 may store the state parameters in the non-volatile memory 107 for a predetermined period extending before and after the timing of receiving the write signal.

[0064] Furthermore, when the state parameters can be written to the nonvolatile memory 107 (when there is sufficient capacity in the nonvolatile memory 107), the memory processing unit 108 inputs a signal (High) indicating that writing is possible to the AND circuit unit 111. When the state parameters cannot be written to the nonvolatile memory 107 (when the capacity of the nonvolatile memory 107 has reached its upper limit), the memory processing unit 108 sets a FULL status bit indicating that the nonvolatile memory 107 is full. Furthermore, the memory processing unit 108 inputs a signal (Low) indicating that writing is not possible to the AND circuit unit 111.

[0065] When the error condition is satisfied, the memory processing unit 108 may store the state parameters in the nonvolatile memory 107 even if the capacity of the nonvolatile memory 107 has reached its upper limit. That is, the memory processing unit 108 overwrites the state parameters stored in the nonvolatile memory 107 (for example, the oldest state parameters) with new state parameters.

[0066] Furthermore, when the error condition is satisfied, the memory processing unit 108 inputs a signal (Low) indicating that an error has occurred to the AND circuit unit 111.

[0067] The AND circuit unit 111 transmits a control signal obtained by ANDing the signal from the memory processing unit 108 and the signal from the driver IC 120 to the processor 201. For example, when the AND circuit unit 111 receives a High signal from the memory processing unit 108 and a High (CNF_DONE) signal from the driver IC 120, it transmits a signal (High, CFG_DONE) indicating that the inkjet head 10 is operable to the processor 201. Furthermore, when either signal is Low, the AND circuit unit 111 transmits a signal (Low) indicating that the inkjet head 10 is inoperable to the processor 201.

[0068] The serial communication unit 110 is an interface for transmitting and receiving data to and from the processor 201. For example, the serial communication unit 110 transmits state parameters stored in the non-volatile memory 107 to the processor 201 under control of the processor 201. The serial communication unit 110 also receives from the processor 201 a release signal for releasing an error state, a reset signal for resetting a FULL status bit, and the like.

[0069] Next, an example of the operation of the FPGA 100 with built-in ADC will be described. 4 and 5 are flowcharts for explaining an example of the operation of the FPGA 100 with built-in ADC.

[0070] First, the FPGA with built-in ADC 100 causes the data receiving circuit unit 101 to receive pre-configuration data (ACT11). Upon receiving the pre-configuration data, the FPGA with built-in ADC 100 sets the monitoring and control parameters included in the pre-configuration data in the comparator unit 109 (ACT12). Upon receiving the configuration data, the FPGA with built-in ADC 100 transmits the setting data to the driver IC 120.

[0071] After setting the monitoring control parameters in the comparison unit 109, the FPGA with built-in ADC 100 determines whether the driver IC 120 has output CNF_DONE (ACT13). If it determines that the driver IC 120 has not output CNF_DONE (ACT13, NO), the FPGA with built-in ADC 100 returns to ACT13.

[0072] When it is determined that the driver IC 120 has output CNF_DONE (ACT13, YES), the ADC built-in FPGA 100 starts the ADC 104, the comparison unit 109, etc. (ACT14).

[0073] When the data receiving circuit unit 101 receives print data, the print data is transferred to the driver IC 120, and the driver IC 120 supplies a discharge pulse or the like to the discharge unit 12, causing the discharge unit 12 to start discharging ink droplets.

[0074] When the ADC 104 and the comparing unit 109 are started, the FPGA 100 with built-in ADC stores the state parameters from the ADC 104 in the FIFO 106 (ACT 15). After storing the state parameters, the FPGA 100 with built-in ADC causes the comparing unit 109 to determine whether the write condition is met (ACT 17).

[0075] If the comparing section 109 determines that the write condition is not met (ACT17, NO), the FPGA with built-in ADC 100 returns to ACT15.

[0076] When the comparison unit 109 determines that the write condition is satisfied (ACT17, YES), the ADC built-in FPGA 100 causes the comparison unit 109 to determine whether the error condition is satisfied (ACT18). When the comparison unit 109 determines that the error condition is satisfied (ACT18, YES), the ADC built-in FPGA 100 causes the comparison unit 109 to stop the ejection operation (ACT19).

[0077] When the discharge operation is stopped, the ADC built-in FPGA 100 causes the memory processing unit 108 to send a signal indicating that an error has occurred to the processor 201 (ACT20). When the processor 201 is caused to send a signal indicating that an error has occurred, the ADC built-in FPGA 100 causes the memory processing unit 108 to store the state parameters stored in the FIFO 106 in the non-volatile memory 107 (ACT21).

[0078] After storing the state parameters in the non-volatile memory 107, the FPGA with built-in ADC 100 determines whether the error state has been released (ACT 22). For example, the FPGA with built-in ADC 100 determines whether a release signal has been received from the processor 201 or the like.

[0079] If it is determined that the error state has not been resolved (ACT22, NO), the FPGA with built-in ADC 100 returns to ACT22. If it is determined that the error state has been resolved (ACT22, YES), the FPGA with built-in ADC 100 returns to ACT13.

[0080] When the comparing unit 109 determines that the error condition is not satisfied (ACT18, NO), the FPGA with built-in ADC 100 causes the memory processing unit 108 to store the state parameters stored in the FIFO 106 in the non-volatile memory 107 (ACT23).

[0081] After storing the state parameters in the non-volatile memory 107, the ADC integrated FPGA 100 manages the capacity of the non-volatile memory 107 (ACT 24), and causes the memory processing unit 108 to determine whether the capacity of the non-volatile memory 107 has reached its upper limit (ACT 25).

[0082] If the memory processing unit 108 determines that the capacity of the nonvolatile memory 107 has not reached the upper limit (ACT25, NO), the FPGA with built-in ADC 100 returns to ACT15.

[0083] When the memory processing unit 108 determines that the capacity of the non-volatile memory 107 has reached its upper limit (ACT25, YES), the ADC-integrated FPGA 100 causes the memory processing unit 108 to set a FULL status bit and send a signal indicating that writing is not possible to the processor 201 (ACT26).

[0084] When the processor 201 transmits a signal indicating that writing is not possible, the FPGA 100 with built-in ADC stops the ADC 104 (ACT 27). When the ADC 104 is stopped, the FPGA 100 with built-in ADC determines whether the FULL status bit has been reset (ACT 28). For example, the FPGA 100 with built-in ADC determines whether a reset signal has been received from the processor 201 or the like.

[0085] If it is determined that the FULL status bit is not reset (ACT28, NO), the FPGA with built-in ADC 100 returns to ACT28. If it is determined that the FULL status bit has been reset (ACT28, YES), the FPGA with built-in ADC 100 returns to ACT14.

[0086] After ACT25, YES, the FPGA with built-in ADC 100 may stop or continue the ejection operation.

[0087] Furthermore, the memory processing unit 108 may continue to store the state parameters stored in the FIFO 106 in the non-volatile memory 107 for a predetermined period after ACT21 and ACT23.

[0088] Furthermore, the FPGA with built-in ADC 100 may transmit the state parameters stored in the non-volatile memory 107 to the processor 201 under the control of the processor 201. Furthermore, the FPGA with built-in ADC 100 may delete the data stored in the non-volatile memory 107 under the control of the processor 201.

[0089] Furthermore, the FPGA with built-in ADC 100 may notify the processor 201 or the like of the reason why CFG_DONE has become Low (satisfaction of an error condition or setting of the FULL status bit) via the serial communication unit 110 or the like.

[0090] The inkjet head configured as described above acquires status parameters relating to the status of the ejection section. The inkjet head detects an error based on the status parameters. When the inkjet head detects an error, it stops the ejection operation. Therefore, the inkjet head can autonomously detect an error and stop the operation.

[0091] Furthermore, when an error is detected, the inkjet head stores the status parameters before and after the error was detected in nonvolatile memory. Therefore, the inkjet head can store necessary data in nonvolatile memory while saving the capacity of the nonvolatile memory.

[0092] Furthermore, when the inkjet head detects a state in which an error is likely to occur but is not an error, the inkjet head stores the state parameters before and after the detection of the state in which an error is likely to occur in the nonvolatile memory. Therefore, the inkjet head can store the state parameters in the state in which an error is likely to occur in the nonvolatile memory.

[0093] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0094] 1...inkjet recording device, 2...liquid ejection unit, 3...head support mechanism, 3a...roller, 3b...endless belt, 4...medium support mechanism, 10...inkjet head, 11...head drive circuit, 12...ejection unit, 20...circulation device, 101...data receiving circuit unit, 102...data processing unit, 103...data transfer circuit unit, 104...ADC, 105...moving average circuit unit, 106...FIFO, 107...non-volatile memory, 108...memory processing unit, 109...comparison unit, 110...serial communication unit, 111...AND circuit unit, 120...driver IC, 130...FET, 201...processor, 202...ROM, 203...RAM, 204...operation panel, 205...communication interface, 206...conveyor motor, 207...motor drive circuit, 208...pump, 209...pump drive circuit, 211...bus line

Claims

1. A drive circuit that supplies a drive voltage to an ejection unit that ejects ink; an interface for acquiring a status parameter indicating a status of the ejection unit; a decision circuit that decides whether an error condition is met based on the state parameters; a switch that turns off the drive circuit when the determination circuit determines that the error condition is satisfied; An inkjet head comprising:

2. The determination circuit determines whether a write condition is satisfied based on the state parameter; a volatile memory for temporarily storing the state parameters acquired by the interface; A non-volatile memory for storing data; a memory processing circuit that stores the state parameters stored in the volatile memory in the non-volatile memory when the determination circuit determines whether a write condition is satisfied; Equipped with 2. The ink-jet head according to claim 1.

3. when it is determined that the write condition is satisfied, the determination circuit determines whether the error condition is satisfied.

3. The ink-jet head according to claim 2.

4. a receiving circuit for receiving a supervisory control parameter; the determination circuit determines whether the error condition is satisfied based on the supervisory control parameters; The ink-jet head according to claim 1 .

5. An inkjet recording apparatus that ejects ink droplets onto a medium, A support portion that supports the medium; An inkjet head according to any one of claims 1 to 4; An inkjet recording apparatus comprising:

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