Semiconductor Device

Abstract

To reduce parasitic capacitance in a semiconductor device having a transistor which has an oxide semiconductor.SOLUTION: A transistor has: a first gate electrode; a first gate insulation film on the first gate electrode; an oxide semiconductor film on the first gate insulation film; a source electrode electrically connected to the oxide semiconductor film; and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film has a first oxide semiconductor film on a first gate electrode side and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has ratio of the number of In atoms larger than ratio of the number of M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atoms. The second oxide semiconductor film has ratio of the number of In atoms smaller than that of the first oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device for performing the same and a method for driving the same.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials such as silicon are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] The present invention provides a highly reliable semiconductor by imparting stable electrical characteristics to a transistor using an oxide semiconductor. To obtain the device, oxide semiconductor films with different compositions were stacked to place more In on the channel side. An oxide semiconductor film containing a large amount of stabilizer such as Ga is used on the back channel side. A semiconductor device using a compound semiconductor film has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2013-175715 A Summary of the Invention [Problem to be solved by the invention]

[0007] A transistor using an oxide semiconductor film as an active layer is A transistor with a structure in which the gate electrode and drain electrode partially overlap each other (referred to as "Lov" in this specification). On the other hand, a gate electrode and a source electrode are often fabricated. Or a transistor in which the gate electrode and drain electrode do not overlap (referred to as "Loff" in this specification). In the case of a gate electrode and a source electrode of an oxide semiconductor film, It is difficult to reduce the electrical resistance in the area where the gate electrode and drain electrode do not overlap. This may result in a decrease in the field effect mobility of the transistor.

[0008] However, when Lov type transistors are used as pixel transistors in liquid crystal displays, Therefore, parasitic capacitance occurs between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. Due to the presence of parasitic capacitance, the time constant during operation becomes large, so the rise time of the pulse voltage As a result, the time it takes to fall becomes longer. It is difficult to ensure that the voltage applied to the liquid crystal element and the capacitance element reaches the required value within the time limit. As the panel size of display devices such as LCDs and OLEDs increases, As the resolution of a display screen having pixels increases, the above problems become more pronounced. Therefore, in the case of Lov type transistors with large parasitic capacitance, the screen is high definition and large. This makes it difficult to create panels with large display screen sizes.

[0009] In addition, there are variations in transistor characteristics and deterioration of organic EL elements in the pixels of organic EL displays. It is effective to provide a circuit to correct the parasitic capacitance, but it is difficult to provide a correction circuit if the parasitic capacitance is large. The calculation becomes complicated.

[0010] In view of the above problems, one aspect of the present invention provides a semiconductor device having a small parasitic capacitance. In one embodiment of the present invention, a display having a large panel size and high resolution is provided. Another object of the present invention is to provide a display device. Another object of the present invention is to provide a display device having a high image quality. Another object of the present invention is to provide a novel semiconductor device. In this regard, one of the objects is to provide a novel display device.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor. a gate electrode, a first gate insulating film on the first gate electrode, and an oxide film on the first gate insulating film. a source electrode electrically connected to the oxide semiconductor film; and a drain electrode electrically connected to the first transistor.

[0013] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has an atomic ratio of In of 1 to 100. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atom The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0014] The oxide semiconductor film has a first region overlapping with the first gate electrode, a second region overlapping with the source electrode, The second region and the third region overlapping the drain electrode. The first region is The second region does not include the first region and the third region.

[0015] Another embodiment of the present invention is a semiconductor device including a transistor. a first gate electrode, a first gate insulating film on the first gate electrode, and a second gate insulating film on the first gate insulating film. a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; and a second gate electrode on the second gate insulating film.

[0016] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the second gate electrode. a fourth region overlapping the source electrode, a second region overlapping the drain electrode, and a third region overlapping the drain electrode. The first region does not include the second region and the third region. does not include the second region and the third region.

[0017] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has an atomic ratio of In of 1 to 100. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atom The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0018] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the second gate electrode. a fourth region overlapping the source electrode, a second region overlapping the drain electrode, and a third region overlapping the drain electrode. In addition, the first region or the fourth region does not include the second region and the third region.

[0019] Another embodiment of the present invention is a semiconductor device including a transistor. a source electrode electrically connected to the oxide semiconductor film; A drain electrode electrically connected to the first gate insulating film on the oxide semiconductor film, and a first and a first gate electrode on the gate insulating film.

[0020] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has an atomic ratio of In of 1 to 100. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atom The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0021] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the source electrode. The first region is a first region, and the second region is a third region overlapping the drain electrode. and does not include a third region.

[0022] Another embodiment of the present invention is a semiconductor device including a transistor. a first gate electrode, a first gate insulating film on the first gate electrode, and a second gate insulating film on the first gate insulating film. a source electrode electrically connected to the oxide semiconductor film; and a drain electrode electrically connected to the film.

[0023] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has an atomic ratio of In of 1 to 100. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atom The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0024] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the source electrode. The first region is a first region, and the second region is a third region overlapping the drain electrode. Or does not include the third region.

[0025] Another embodiment of the present invention is a semiconductor device including a transistor. a first gate electrode, a first gate insulating film on the first gate electrode, and a second gate insulating film on the first gate insulating film. a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; and a second gate electrode on the second gate insulating film.

[0026] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has an atomic ratio of In of 1 to 100. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atom The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0027] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the second gate electrode. The semiconductor device further includes a fourth region overlapping the source electrode, a second region overlapping the drain electrode, and a third region overlapping the drain electrode. Additionally, the first region or the fourth region does not include the second region or the third region.

[0028] Another embodiment of the present invention is a semiconductor device including a transistor. a source electrode electrically connected to the oxide semiconductor film; A drain electrode electrically connected to the first gate insulating film on the oxide semiconductor film, and a first and a first gate electrode on the gate insulating film.

[0029] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has an atomic ratio of In of 1 to 100. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atom The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0030] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the source electrode. The first region is a first region, and the second region is a third region overlapping the drain electrode. Or does not include the third region.

[0031] In each of the above configurations, the semiconductor device has a scanning line and a data line, and the first gate electrode The source electrodes are electrically connected to the scan lines, and the source electrodes are electrically connected to the data lines. In the region where the gate insulating film is formed, an insulating film having a thickness larger than that of the first gate insulating film is formed between the scanning line and the data line. It is preferable to have a membrane.

[0032] In each of the above structures, the oxide semiconductor film contains In, M, and Zn. In each of the above structures, the oxide semiconductor film preferably has a crystal part. The crystal part is a part in which the c-axis of the crystal part is parallel to the normal vector of the surface on which the oxide semiconductor film is formed. It is preferable that the compound has the following structure:

[0033] In each of the above configurations, the first region has a higher proportion of crystal portions than the second region. In each of the above structures, the first region preferably has a larger diameter than the second region. It is preferable that the hydrogen concentration is low in the hydrogen-containing layer.

[0034] Another embodiment of the present invention is a semiconductor device and a display element according to any one of the above structures. Another embodiment of the present invention is a display device including the display device and a touch sensor. Another embodiment of the present invention is a display module having any one of the above structures. The semiconductor device according to any one of claims 1 to 5, the display device, or the display module, and an operation key or and a battery. Effect of the Invention

[0035] According to one embodiment of the present invention, a semiconductor device with low parasitic capacitance can be provided. According to one embodiment of the present invention, a display device having a large panel size and high resolution can be provided. According to one embodiment of the present invention, a display device with high display quality can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided.

[0036] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0037] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] 1A and 1B are a top view and a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Diagram 5]1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 19] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 20] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 21] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 22] Electron diffraction pattern of CAAC-OS. [Figure 23] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 24] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Diagram 25]A diagram explaining InGaZnO4 crystals and pellets. [Figure 26] Schematic diagram explaining a film formation model of CAAC-OS. [Figure 27] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 28] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 29] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 30] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Diagram 31] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 32] 1 is a block diagram of a display unit, an equivalent circuit diagram of a pixel circuit provided in a pixel of the display unit, and a schematic diagram of the transmittance-voltage characteristics of polarized light passing through a liquid crystal element. [Diagram 33] 3A and 3B are a timing chart and a schematic diagram illustrating the operation of a pixel circuit included in a pixel portion of a display device. [Diagram 34] FIG. 2 is a diagram illustrating a display module. [Diagram 35] 1A to 1C are diagrams illustrating electronic devices. [Diagram 36] 1A to 1C are diagrams illustrating electronic devices. [Figure 37] 1 is a top view illustrating a structure of a semiconductor device according to an embodiment; [Figure 38] FIG. 13 is a graph showing Id-Vg characteristics of a transistor in the embodiment. [Figure 39] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 40] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Diagram 41] 3 shows a configuration example of an RF device tag according to the embodiment. [Diagram 42] 3 shows an example of the configuration of a CPU according to the embodiment. [Diagram 43] 1 is a circuit diagram of a memory element according to an embodiment. [Diagram 44] FIG. 1 is a top view illustrating an apparatus according to one embodiment of the present invention. [Diagram 45] FIG. 1 is a block diagram illustrating an apparatus according to one embodiment of the present invention. [Figure 46] FIG. 1 is a cross-sectional view of an apparatus according to one embodiment of the present invention. [Figure 47] FIG. 1 is a cross-sectional view of an apparatus according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the present invention in various forms without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0039] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0040] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0041] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain can be used interchangeably. Let us assume that.

[0042] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0043] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content of.

[0044] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, The reference numerals are used commonly among different drawings.

[0045] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0046] In this specification and the like, the terms "film" and "layer" may be used interchangeably. For example, the term "conductive layer" may be used interchangeably. In some cases, the term "conductive film" may be changed to "conductive film". For example, the term "insulating film" may be changed to the term "insulating layer." .

[0047] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention and a method for manufacturing the semiconductor device will be described. The method will now be described with reference to Figures 1 to 7 and 10 to 18.

[0048] <Structure Example 1 of Semiconductor Device> FIG. 1A shows a transistor which is a semiconductor device of one embodiment of the present invention. FIG. 1B is a top view of the rotor 100, and FIG. 1B is a top view of the rotor 100 between the dashed line X1-X2 shown in FIG. FIG. 1C is a cross-sectional view of the cross section of the dashed line Y1-Y2 shown in FIG. 1A. In FIG. 1(A), in order to avoid complication, Therefore, some of the components of the transistor 100 (such as an insulating film that functions as a gate insulating film) can be omitted. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1- The Y2 direction may be referred to as the channel width direction. In the subsequent drawings, as in FIG. 1(A), some of the components may be omitted. There is.

[0049] The transistor 100 includes a conductive film 104 that functions as a first gate electrode on a substrate 102. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. The oxide semiconductor film 108 over the insulating film 107 and the insulating film 108 electrically connected to the oxide semiconductor film 108 The conductive film 112a serving as a source electrode and the oxide semiconductor film 108 are electrically connected to and a conductive film 112b serving as a drain electrode connected to the gate of the transistor 10. More specifically, an insulating film is formed on the conductive films 112a and 112b and the oxide semiconductor film 108. 114, 116, and an insulating film 118 are provided. It functions as a protective insulating film for the transistor 100 .

[0050] A conductive film 104 functioning as a first gate electrode and a conductive film 112 functioning as a source electrode. a, a conductive film 104 functioning as a first gate electrode, and a conductive film 105 functioning as a drain electrode. The conductive films 112b are arranged so as not to overlap each other. A transistor in which the source electrode or gate electrode and the drain electrode do not overlap each other is called a "Loff type transistor." In this specification, when there are multiple gate electrodes, the source If there is even one gate electrode that does not overlap with the electrode or drain electrode, A transistor having the structure will be referred to as a "Loff type transistor" or the like. is that all gate electrodes and source electrodes, and all gate electrodes and drain electrodes are mutually A structure having an overlapping region is referred to as a "Lov type transistor" or the like.

[0051] The oxide semiconductor film 108 includes a first region overlapping with the conductive film 104 and a second region overlapping with the conductive film 112a. The first region includes a second region overlapping the conductive film 112b, and the third region overlapping the conductive film 112b. In other words, the first region is arranged so as not to include the second region and the third region. The first region and the third region are disposed so as to not overlap.

[0052] The oxide semiconductor film 108 does not overlap with the conductive film 104, the conductive film 112a, and the conductive film 112b. The conductive film 104, the conductive film 112a, and the conductive film 112b do not overlap with each other. The area corresponds to area 122.

[0053] By forming a Loff type transistor, the first gate electrode and the source electrode and the first The parasitic capacitance between the gate electrode and the drain electrode of the MOSFET can be reduced. By using transistors in the display panel, the time constant can be reduced, It is possible to provide a display device with a large pixel size and high resolution. By using such transistors in liquid crystal displays, feedthrough and other problems can be suppressed. Therefore, a display device with high display quality can be provided.

[0054] In addition, the oxide semiconductor film 108 is a first gate electrode on the conductive film 104 side. A first oxide semiconductor film 108a and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a. The insulating film 106 and the insulating film 107 are formed in the transistor 100. It functions as the first gate insulating film.

[0055] The oxide semiconductor film 108 is In-M (wherein M is Ti, Ga, Sn, Y, Zr, La , Ce, Nd, or Hf) oxide, In-M-Zn oxide can be used. In particular, it is preferable to use In-M-Zn oxide for the oxide semiconductor film 108.

[0056] The first oxide semiconductor film 108a has a first oxide semiconductor layer in which the atomic ratio of In is larger than the atomic ratio of M. The second oxide semiconductor film 108b has a region similar to that of the first oxide semiconductor film 108. The second region has a lower atomic ratio of In than the first region a. It has a thinner portion than

[0057] A first region in which the atomic ratio of In is larger than the atomic ratio of M is formed in the first oxide semiconductor film 108a. By having such a structure, the field effect mobility (simply called mobility, or μFE) of the transistor 100 can be improved. In some cases, the amount of heat generated can be increased.

[0058] The Loff type transistor has a first gate electrode and a source or a first gate electrode and a drain. The oxide semiconductor region where the gates do not overlap acts as a series resistor, so compared to Lov-type transistors, Therefore, the current (on-current) when the transistor is turned on tends to decrease. The atomic ratio of In in the first oxide semiconductor film 108a is made larger than the atomic ratio of M. an oxide semiconductor region in which the first gate electrode and the source or the first gate electrode and the drain do not overlap with each other; This can reduce the resistance of the transistor, thereby suppressing the decrease in the on-state current. As a result, even Loff type transistors can be applied to various semiconductor devices and display devices. This makes it possible.

[0059] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. A driver (especially a demux connected to the output terminal of a shift register of a gate driver) By using it in a semiconductor device or display device with a narrow frame (also called a narrow frame), Locations can be provided.

[0060] On the other hand, a first oxide semiconductor having a first region in which the atomic ratio of In is greater than the atomic ratio of M is By using the solid film 108a, the electrical characteristics of the transistor 100 are less likely to change when irradiated with light. However, in the semiconductor device according to one embodiment of the present invention, the first oxide semiconductor film 10 A second oxide semiconductor film 108b is formed on the second oxide semiconductor film 8a. The thickness of the first oxide semiconductor film 108b in the vicinity of the channel region is smaller than the thickness of the first oxide semiconductor film 108a. .

[0061] The second oxide semiconductor film 108b has a higher In content than the first oxide semiconductor film 108a. Since the second region has a smaller atomic ratio, Eg is smaller than that of the first oxide semiconductor film 108a. Therefore, the first oxide semiconductor film 108a and the second oxide semiconductor film 10 The oxide semiconductor film 108 having a stacked structure with 8b has a resistance to a negative bias stress test using light irradiation. will become higher.

[0062] By using the oxide semiconductor film having the above structure, the oxide semiconductor film 108 can be prevented from being damaged by light irradiation. Therefore, the amount of absorption of the transistor 100 during light irradiation can be reduced. Fluctuations in electrical characteristics can be suppressed. Since the insulating film 114 or the insulating film 116 contains excess oxygen, the insulating film 114 or the insulating film 116 is not irradiated with light. This can further suppress the fluctuation in the electrical characteristics of the transistor 100.

[0063] Here, the oxide semiconductor film 108 will be described in detail with reference to FIG.

[0064] FIG. 2 is an enlarged view of the oxide semiconductor film 108 and its surroundings in the transistor 100 shown in FIG. FIG.

[0065] In FIG. 2, the thickness of the first oxide semiconductor film 108a is t1, and the thickness of the second oxide semiconductor film 108b is t2. The thicknesses of the oxide film 108b are indicated as t2-1 and t2-2, respectively. Since the second oxide semiconductor film 108b is provided on the oxide semiconductor film 108a, When the films 112a and 112b are formed, the first oxide semiconductor film 108a is etched by the etching gas. Therefore, the first oxide semiconductor film 1 is not exposed to gas, etching solution, or the like. In the case of 08a, the film thickness is not reduced or is very small. In the case of 108b, when the conductive films 112a and 112b are formed, the second oxide semiconductor The portions of the film 108b that do not overlap the conductive films 112a and 112b are etched to form recesses. That is, the second oxide semiconductor film 108b overlaps with the conductive films 112a and 112b. The thickness of the region is t2-1, and the conductive films 112a and 112b of the second oxide semiconductor film 108b are The thickness of the region not overlapping with b is t2-2.

[0066] The relationship between the thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b is as follows: It is preferable that -1>t1>t2-2. By making such a film thickness relationship, high A transistor having high field effect mobility and small fluctuation in threshold voltage when irradiated with light. It is possible to make it a gyroscope.

[0067] In addition, when oxygen vacancies are formed in the oxide semiconductor film 108 of the transistor 100, This generates electrons as carriers, and the device is prone to normally-on characteristics. By reducing oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a, This is also important in obtaining stable transistor characteristics. In the configuration of the transistor, an insulating film on the oxide semiconductor film 108, By introducing excess oxygen into the insulating film 114 and / or the insulating film 116 on the insulating film 108, Oxygen is transferred from the insulating film 114 and / or the insulating film 116 into the oxide semiconductor film 108, and the oxide semiconductor film 108 is oxidized. To compensate for oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a. is characterized by.

[0068] Note that as the insulating films 114 and 116, it is more preferable to have a region (oxygen-excess region) containing oxygen in excess of the stoichiometric composition. In other words, the insulating films 114 and 116 are insulating films capable of releasing oxygen. To provide an oxygen-excess region in the insulating films 114 and 116, for example, oxygen is introduced into the insulating films 114 and 116 after film formation to form an oxygen-excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used. region (oxygen-excess region). Moreover, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less. In addition, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is more preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, it is sufficient to satisfy the relationship of t2-2 < t1. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less. region. Moreover, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less.

[0069] Moreover, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less. Moreover, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less. Moreover, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less. Moreover, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less. m or more and 10 nm or less.

[0070] Hereinafter, other components included in the semiconductor device of the present embodiment will be described in detail. will be described in detail.

[0071] <Substrate> There is no great limitation on the material of the substrate 102, etc., but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 102. Also, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied, and semiconductor elements are provided on these substrates. substrate. substrate. substrate. substrate, an SOI substrate, etc. can be applied, and semiconductor elements are provided on these substrates. The substrate 102 may be a glass substrate. When used, 6th generation (1500mm x 1850mm), 7th generation (1870mm x 22 00mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 28 By using large area substrates such as 1000mm and 10th generation (2950mm x 3400mm), Therefore, a large display device can be manufactured.

[0072] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0073] <Conductive film functioning as first gate electrode, source electrode, and drain electrode> A conductive film 104 functions as a ground electrode, a conductive film 112a functions as a source electrode, and The conductive film 112b functioning as the drain electrode may be made of chromium (Cr), copper (Cu), Aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), Tantalum (Ta), Titanium (Ti), Tungsten (W), Manganese (Mn), Nickel (Ni), iron (Fe), cobalt (Co), or the above-mentioned metallic elements The alloys are formed by using alloys containing the above-mentioned metal elements or alloys combining the above-mentioned metal elements. It is possible.

[0074] The conductive films 104, 112a, and 112b may have a single-layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, titanium on an aluminum film, A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a titanium nitride film A two-layer structure in which a tungsten film is laminated on top of a tantalum nitride film or a tungsten nitride film A two-layer structure in which a tungsten film is laminated, a titanium film, and an aluminum film is laminated on the titanium film. There are three-layer structures, such as a titanium film on top of an aluminum film. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of these may be used.

[0075] The conductive films 104, 112a, and 112b are made of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. It is also possible.

[0076] The conductive films 104, 112a, and 112b are made of a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. This allows processing using a wet etching process, which reduces manufacturing costs. It becomes possible.

[0077] <Insulating film functioning as first gate insulating film> First gate insulating film of transistor 100 The insulating films 106 and 107 functioning as the insulating film are formed by plasma enhanced chemical vapor deposition (PECVD). Plasma Enhanced Chemical Vapor Depositio n)) method, sputtering method, etc., to form a silicon oxide film, a silicon oxynitride film, a nitride oxide film, Silicon film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, The insulating layer includes one or more of a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film, It is to be noted that the insulating films 106 and 107 may be formed of the above-mentioned materials instead of the laminated structure. A selected single layer insulating film or a three or more layer insulating film may be used.

[0078] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain an excess of acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0079] Note that the oxide semiconductor film 108 functioning as a channel region of the transistor 100 The insulating film 107 is preferably an oxide insulating film, and has an oxide content in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen excess region). The insulating film 107 is capable of releasing oxygen. In order to provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Oxygen may be introduced into the insulating film 107 to form an oxygen excess region. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Zuma processing or the like can be used.

[0080] When hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Since the thickness of the insulating film 107 can be made larger than that of the case where silicon oxide is used, the tunnel current In other words, it is possible to reduce the leakage current caused by the current flowing through the transistor. Furthermore, hafnium oxide, which has a crystalline structure, can be used to realize an amorphous structure. It has a higher dielectric constant than hafnium oxide, which has a smaller off-state current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic. are not limited to these.

[0081] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 is The silicon oxide film is formed as a result of the above. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so it is suitable for transistors. The first gate insulating film of the transistor 100 includes a silicon nitride film, which makes the insulating film physically Therefore, the decrease in the dielectric strength of the transistor 100 can be suppressed, and In addition, the dielectric strength can be improved, and electrostatic breakdown of the transistor 100 can be suppressed.

[0082] <Oxide Semiconductor Film> The oxide semiconductor film 108 can be made of the above-mentioned materials. In the case where the oxide semiconductor film 108 is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose is In≧M, Zn≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target and In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1 are preferred. In addition, when the oxide semiconductor film 108 is an In-M-Zn oxide, It is preferable to use a target containing polycrystalline In-M-Zn oxide as the target. By using a target containing crystalline In-M-Zn oxide, it is possible to obtain a crystalline oxide semiconductor. The oxide semiconductor film 108 to be formed has an atomic ratio of The error is the atomic ratio of the metal elements contained in the sputtering target. Including a fluctuation of plus or minus 40%. For example, as a sputtering target, the number of atoms When the ratio of In:Ga:Zn=4:2:4.1 is used, the oxide semiconductor film 108 is deposited. The atomic ratio of In:Ga:Zn may be approximately In:Ga:Zn=4:2:3.

[0083] For example, the first oxide semiconductor film 108a may be formed using the above-mentioned In:M:Zn=2:1:3 , In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, etc. The second oxide semiconductor film 108b may be formed using the above-described oxide semiconductor film 108b. If the material is formed using In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, etc. Note that the metal element of the sputtering target used for the second oxide semiconductor film 108b is The atomic ratio of elements does not necessarily have to satisfy In≧M, Zn≧M, but In≧M, Zn <Mを Specifically, the composition may be In:M:Zn=3:2:1.

[0084] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In particular, the first oxide semiconductor film 108a is preferably made of a material having an energy gap of 2 eV or more. The second oxide semiconductor film 108b is an oxide semiconductor film having a conductivity of 2 eV to 3.0 eV. When an oxide semiconductor film having an energy gap of 2.5 eV or more and 3.5 eV or less is used, In addition, the second oxide semiconductor film 108b is more preferable than the first oxide semiconductor film 108a. It is preferable that the energy gap is large.

[0085] The thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are Each of them is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably Preferably, the thickness is 3 nm or more and 50 nm or less. It is preferable that the thickness relationship described above is satisfied. .

[0086] The second oxide semiconductor film 108b is an oxide semiconductor film with low carrier density. For example, the second oxide semiconductor film 108b has a carrier density of 1×10 17 pcs / c m 3 Less than or equal to 1×10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following applies.

[0087] However, the present invention is not limited to these, and the semiconductor properties and electrical properties required (field effect mobility, etc.) The appropriate atomic ratio can be used according to the required transistor characteristics (e.g., threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, and atomic number of the conductive film 108b are It is preferable to set the inter-element distance, density, etc. appropriately.

[0088] Note that the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are By using an oxide semiconductor film having a low impurity concentration and a low density of defect states, This is preferable because it allows the fabrication of a transistor with excellent electrical characteristics. The term "high purity intrinsic or substantially intrinsic" refers to a material with a low oxygen concentration and a low defect level density (low oxygen vacancies). A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film is called a highly pure intrinsic oxide semiconductor film. Since the number of rear generation sources is small, the carrier density can be reduced. The transistor in which the channel region is formed in the semiconductor film has a negative threshold voltage. It is also rare for the material to become normally on. A highly pure intrinsic oxide semiconductor film has a low density of defect states and therefore a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film may be formed by The off-state current is extremely small, and the channel width is 1×10 6 μm and channel length L is 10 μm However, the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V. In the range, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×1 0 -13 It is possible to obtain a characteristic of A or less.

[0089] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small variations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are dissipated. It takes a long time for the charge to reach a certain level, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has a high current density. Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0090] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. In this case, oxygen vacancies are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can combine with oxygen, which combines with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, in the oxide semiconductor film 108, a hydrogen concentration obtained by SIMS analysis is Degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×1, more preferably 0 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 below Let us assume that.

[0091] The first oxide semiconductor film 108a has a higher hydrogen concentration than the second oxide semiconductor film 108b. It is preferable that the first oxide semiconductor film 108a has a portion where the degree of oxidation is small compared to that of the second oxide semiconductor film 108b. By having a portion with a lower hydrogen concentration than the semiconductor film 108b, a highly reliable semiconductor The device may be a body device.

[0092] In addition, the first oxide semiconductor film 108a contains silicon, which is a Group 14 element, When carbon is contained, oxygen vacancies are increased in the first oxide semiconductor film 108a, and the first oxide semiconductor film 108a becomes n-type. As a result, the concentrations of silicon and carbon in the first oxide semiconductor film 108a and The concentrations of silicon and carbon in the vicinity of the interface with the first oxide semiconductor film 108a (measured by SIMS analysis) The concentration that can be obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0093] In addition, in the first oxide semiconductor film 108a, the alkali metal oxide film The concentration of metal or alkaline earth metal is 1×10 18 atoms / cm 3 The following is preferably is 2 × 10 16 atoms / cm 3 The following are the alkali metals and alkaline earth metals: When a compound is bonded to an oxide semiconductor, carriers may be generated, increasing the off-state current of a transistor. For this reason, the alkali metal or It is preferable to reduce the concentration of alkaline earth metals.

[0094] When the first oxide semiconductor film 108a contains nitrogen, electrons serving as carriers This increases the carrier density and makes it easier to become n-type. A transistor using a conductor film tends to have a normally-on characteristic. In the solid film, it is preferable that nitrogen is reduced as much as possible. For example, SIMS analysis The nitrogen concentration obtained is 5×10 18 atoms / cm 3 It is preferable to do the following: .

[0095] The first oxide semiconductor film 108a and the second oxide semiconductor film 108b are The non-single crystal structure may be, for example, CAAC-OS (CAx is Aligned Crystalline Oxide Semiconductor or), polycrystalline, microcrystalline, or amorphous structures. The crystalline structure has the highest density of defect states, while the CAAC-OS has the lowest density of defect states.

[0096] <Insulating Film Functioning as a Protective Insulating Film for Transistors> The insulating films 114 and 116 are made of an oxide semiconductor. The insulating film 118 has a function of supplying oxygen to the conductive film 108. The insulating films 114 and 116 each serve as a protective insulating film for the semiconductor device 100. The insulating films 114 and 116 contain oxygen. The insulating film 114 is an insulating film that can transmit oxygen. The insulating film 116 is formed later to reduce damage to the oxide semiconductor film 108. It also functions as a membrane.

[0097] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0098] In addition, it is preferable that the insulating film 114 has a small amount of defects. Typically, the insulating film 114 has a small amount of defects as determined by ESR measurement. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3×10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects is high, oxygen enters the defects, and the oxygen in the insulating film 114 The amount of transmission decreases.

[0099] In the insulating film 114, all of the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, In some cases, oxygen may move through the film 114. When the oxide insulating film capable of forming the insulating film 116 is formed over the insulating film 114, The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0100] The insulating film 114 is formed using an oxide insulating film having a low density of states caused by nitrogen oxides. Note that the density of states due to the nitrogen oxides can be determined by the valence The energy of the top of the electron band (E v_os ) and the energy of the conduction band minimum of the oxide semiconductor film (E c_os) may be formed between the insulating film and the insulating layer. Silicon oxynitride film with low emission or aluminum oxynitride film with low emission of nitrogen oxide For example, a tungsten film or the like can be used.

[0101] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, is This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of emission is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 55°C or lower. This is the amount released by heating at 0℃ or below.

[0102] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO or NO forms a level in the insulating film 114 or the like. The oxides of nitrogen are located within the energy gap of the insulating film 114 and the When the oxide semiconductor film 108 diffuses to the interface between the insulating film 114 and the oxide semiconductor film 108, the level transfers electrons to the insulating film 114 side. As a result, the trapped electrons may penetrate into the insulating film 114 and the oxide semiconductor. Since it remains near the interface of the conductor film 108, the threshold voltage of the transistor is shifted in the positive direction. This causes them to do so.

[0103] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with ammonia contained in the insulating film 116 during the heat treatment. Therefore, the amount of nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0104] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor can be reduced. It is possible to reduce the shift and the variation in the electrical characteristics of the transistor. Cut.

[0105] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less: The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.001 to 2.002. A second signal with a g value of .003 or less and a third signal with a g value between 1.964 and 1.966, inclusive. A null is observed. Note that the split width of the first signal and the second signal, The split width of the second and third signals is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The total spin density of the third signal is 1×10 18 spins / cm 3 is less than Typically 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Less than be.

[0106] In addition, the g value in the ESR spectrum below 100K is 2.037 to 2.039. The first signal has a g value of 2.001 to 2.003, and the second signal has a g value of 1 The third signal, between .964 and 1.966, is nitrogen oxide (NOx , x is greater than 0 Representative examples of nitrogen oxides are: Examples include nitrogen monoxide and nitrogen dioxide. That is, the g value is between 2.037 and 2.039. a first signal having a g value of 2.001 to 2.003, and a second signal having a g value of The lower the sum of the spin densities of the third signals between 1.964 and 1.966, the more acidic the signal is. This means that the nitride insulating film contains a small amount of nitrogen oxide.

[0107] The nitrogen concentration of the oxide insulating film measured by SIMS is 6×10 20 atoms / cm 3 The following is the result.

[0108] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film by the VD method, a dense and hard film can be obtained. It can be formed.

[0109] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric composition. The oxide insulating film had a loss of oxygen of 1.0×10 in terms of oxygen atoms as determined by TDS analysis. 1 8 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 That's all. The oxide insulating film is a thin film. The surface temperature of the film during the TDS analysis was 100°C or less. The temperature range is preferably from 100° C. to 500° C. or from 100° C. to 700° C.

[0110] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or less can be used.

[0111] In addition, it is preferable that the insulating film 116 has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the insulating film 116 is preferably an oxide semiconductor compared to the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0112] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating films In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a dashed line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single-layer structure without being limited thereto.

[0113] The insulating film 118 contains nitrogen. The insulating film 118 also contains nitrogen and silicon. The insulating film 118 is also resistant to blockages such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. By providing the insulating film 118, the oxide semiconductor film 108 can prevent the oxidation of the oxide semiconductor film 108. The diffusion of oxygen contained in the insulating films 114 and 116 to the outside, and the diffusion of oxygen from the outside This can prevent hydrogen, water, and the like from entering the oxide semiconductor film 108. For example, a nitride insulating film can be used. Silicon nitride oxide, aluminum nitride, aluminum oxide nitride, etc. A nitride insulator that has a blocking effect against nitrogen, hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of the insulating film, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. As an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like, aluminum oxide is used. nium, aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, Examples include yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

[0114] Note that the various films described above, such as the conductive film, the insulating film, and the oxide semiconductor film, are formed by sputtering. It can be formed by the CVD method or PECVD method, but other methods such as thermal CVD (Ch Alternatively, the insulating layer may be formed by thermal CVD. As an example of the method, MOCVD (Metal Organic Chemical Vapor Deposition) Deposition method and ALD (Atomic Layer Deposition) method n) method may also be used.

[0115] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0116] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0117] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until a thin film of the desired thickness is formed. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film depends on the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin FETs.

[0118] Thermal CVD methods such as MOCVD and ALD can be used to form the conductive film, insulating film, and oxide film of the above-mentioned embodiment. It is possible to form various films such as semiconductor films and metal oxide films. For example, In-Ga-Zn When forming a -O film, trimethylindium, trimethylgallium, and dimethyl Zinc is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is The formula is Zn(CH3)2. In addition, the combination is not limited to these, and trimethyl gas is also available. Triethylgallium (chemical formula Ga(C2H5)3) can be used instead of lithium. Diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. .

[0119] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is made by vaporizing hafnium amide (such as TDMAH) and acid. Two types of gases are used: tetrakisdimethylamide (TDA) and ozone (O3). The chemical formula for fluorine is Hf[N(CH3)2]4. Other liquid materials include tetrahydrofuran. Examples include rakis(ethylmethylamido)hafnium.

[0120] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( Dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0121] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, the chlorine contained in the adsorbed matter is removed, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0122] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by repeatedly introducing B2H6 gas and WF The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. Alternatively, SiH4 gas may be used instead of gas.

[0123] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a Ga After forming an O layer, Zn(CH3)2 gas and O3 gas were repeatedly introduced in sequence to form a Zn The order of these layers is not limited to this example. By mixing these layers, mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers are formed. Alternatively, H2 obtained by bubbling an inert gas such as Ar instead of O3 gas may be used. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of the gas In(C2H5)3, the gas Ga(CH3) Instead of the Zn(CH3)2 gas, Ga(C2H5)3 gas may be used. may also be used.

[0124] Another example of the transistor having the above structure is shown in FIG. 39. This structure is the transistor shown in FIG. It may also have a structure having a top view like that of the transistor 153. 9(A-1) is a cross-sectional view taken along the dashed line X1-X2-X3.

[0125] In addition, the oxide semiconductor film 108b in the transistor 100 illustrated in FIG. However, there is no or very little film loss as in the transistor 154 shown in FIG. Also, as shown in FIG. 39(C), a transistor 155 having a channel The structure may have a protective layer 125.

[0126] <Configuration Example 2 of Semiconductor Device> Next, a transistor different from the transistor 100 shown in FIGS. A configuration example of the above will be described with reference to Figs. 3(A), (B), and (C). In cases where the function is the same as that of the function, the hatch pattern shall be the same and no special code shall be attached. There is.

[0127] FIG. 3A is a top view of a transistor 170 which is a semiconductor device of one embodiment of the present invention. 3B corresponds to a cross-sectional view taken along dashed line X1-X2 in FIG. 3A. FIG. 3(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 3(A). Correct.

[0128] The transistor 170 includes a conductive film 104 over a substrate 102, the conductive film 104 serving as a first gate electrode. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. an oxide semiconductor film 108 on the insulating film 107; and an insulating film 114 on the oxide semiconductor film 108. The insulating film 116 on the insulating film 114 and the source electrode 114 electrically connected to the oxide semiconductor film 108 are The conductive film 112a serving as a gate electrode and the gate electrode electrically connected to the oxide semiconductor film 108 The conductive film 112b functions as a drain electrode, and the conductive film 112a, the conductive film 112b and the acid An insulating film 114 on the compound semiconductor film 108, an insulating film 116 on the insulating film 114, and an insulating film 11 6, an insulating film 118 on the insulating film 118, a conductive film 120a on the insulating film 118, and a conductive film 1 The insulating films 114, 116, and 118 form a second gate of the transistor 170. The conductive film 120a functions as a gate insulating film. 18, the conductive film 112b is electrically connected to the conductive film 112b through an opening 142c provided in the conductive film 112b. In the transistor 170, the conductive film 120a is, for example, a pixel electrode used in a display device. In the transistor 170, the conductive film 120b functions as a second It functions as a gate electrode (also called a backgate electrode).

[0129] The conductive film 120b functions as a second gate electrode and the conductive film 11 functions as a source electrode. 2a, a conductive film 120b functioning as a second gate electrode, and a conductive film 120c functioning as a drain electrode. The conductive films 112b are arranged so as not to overlap each other.

[0130] In this configuration example, the oxide semiconductor film 108 includes a first region that overlaps with the conductive film 104. a second region overlapping the conductive film 112a; a third region overlapping the conductive film 112b; The first region includes the second region and the third region. The fourth region is arranged so as not to include the second region and the third region. In other words, the first region is arranged so that the second region and the third region do not overlap. The fourth region is disposed so as not to overlap the second region and the third region. .

[0131] In FIG. 3B, the conductive film 104 and the conductive film 120b are depicted with the same width. may be the same for the conductive film 120b and the conductive film 104, or may be different.

[0132] As shown in FIG. 3C, the conductive film 120b is formed by insulating films 106, 107, 114, and 1 In the openings 142a and 142b provided in the gate electrodes 16 and 118, Therefore, the conductive film 120b and the conductive film 104 are the same. A potential is applied.

[0133] In this embodiment, openings 142a and 142b are provided, and the conductive film 120b and Although the configuration in which the conductive film 104 is connected has been illustrated, the present invention is not limited to this. Only one of the openings 142a and 142b is formed, and the conductive film 120b and The conductive film 104 is connected, or the openings 142a and 142b are not provided, and the conductive film 104 is not connected. The conductive film 120b and the conductive film 104 may not be connected to each other. In the case where the conductive film 104 is not connected, the conductive film 120b and the conductive film 104 are each provided with different It is possible to apply a voltage to the

[0134] As shown in FIG. 3B, the oxide semiconductor film 108 functions as a first gate electrode. The conductive film 104 functions as a second gate electrode, and the conductive film 120b functions as a second gate electrode. The second gate electrode is sandwiched between two conductive films that function as gate electrodes. The length of the conductive film 120b functioning as a gate electrode in the channel width direction is The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 114. The gate electrode is covered with a conductive film 120b via the gate electrodes 116 and 118. The conductive film 120b functioning as the first gate electrode and the conductive film 104 functioning as the first gate electrode are formed by insulating film 1. At the openings 142a and 142b provided in the In order to connect the oxide semiconductor film 108, the side surfaces of the oxide semiconductor film 108 in the channel width direction are 6 and 118, it faces the conductive film 120b which functions as the second gate electrode.

[0135] In other words, in the channel width direction of the transistor 170, The conductive film 104 functioning as the second gate electrode and the conductive film 120b functioning as the first gate electrode are The insulating films 106 and 107 functioning as a first gate insulating film and the insulating film 108 functioning as a second gate insulating film The insulating films 114, 116, and 118 are connected through openings, and the first gate The insulating films 106 and 107 function as first gate insulating films, and the insulating film 108 functions as a second gate insulating film. The insulating films 114, 116, and 118 surround the oxide semiconductor film 108.

[0136] With such a structure, the oxide semiconductor film 108 included in the transistor 170 The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. It can be electrically surrounded by the electric field of the conductive film 120b. The electric field of the first gate electrode and the second gate electrode causes an oxide film in which a channel region is formed. The device structure of the transistor that electrically surrounds the nitride semiconductor film is called surrounded ch This can be called an annel (s-channel) structure.

[0137] Since the transistor 170 has an s-channel structure, The conductive film 104 functions as a gate insulating film, and the electric field for inducing the channel is effectively applied to the oxide semiconductor. This allows the current drive capability of the transistor 170 to be improved. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 170. The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. Since the transistor 170 has a structure surrounded by the conductive film 120b, the mechanical strength of the transistor 170 is increased. It can be done.

[0138] The other configuration of the transistor 170 is the same as that of the transistor 100 shown above. Yes, and it has the same effect.

[0139] In addition, the transistor according to the present embodiment can be freely combined with each of the above structures. For example, the transistor 100 shown in FIG. 3 is used as a transistor for the gate driver of the display device. It can be used for data.

[0140] <Configuration Example 3 of Semiconductor Device> In Configuration Example 2, a first gate electrode, a source electrode, and a first gate a first gate electrode, a second source electrode, and a second gate electrode; The first gate electrode and the source electrode or the first drain electrode are configured not to overlap. The gate electrode and the drain electrode may not overlap each other.

[0141] In addition, when a function similar to that described above is provided, the hatch pattern is the same, and may not be signed.

[0142] FIG. 8A is a top view of a transistor 171 which is a semiconductor device of one embodiment of the present invention. FIG. 8B corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 8(C) corresponds to a cross-sectional view taken along dashed line Y1-Y2 in FIG. 8(A). do.

[0143] FIG. 8B shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a serving as the first gate electrode and the conductive film 104 serving as the drain electrode are The conductive film 112b functioning as the second gate electrode does not overlap with the conductive film 112b. 120b, a conductive film 112a functioning as a source electrode, and a conductive film 112b functioning as a second gate electrode. The conductive film 120b functioning as the drain electrode and the conductive film 112b functioning as the drain electrode have an overlapping region. The device is arranged to have

[0144] By adopting the above-mentioned configuration, the first gate electrode and the source electrode or the first gate electrode and The parasitic capacitance between the drain electrodes can be reduced.

[0145] FIG. 9A is a top view of a transistor 172 which is a semiconductor device of one embodiment of the present invention. FIG. 9B corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 9(C) corresponds to a cross-sectional view taken along dashed line Y1-Y2 in FIG. 9(A). do.

[0146] FIG. 9B shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a serving as the first gate electrode and the conductive film 104 serving as the drain electrode are The conductive film 112b, which functions as a second gate electrode, has an overlapping region. a conductive film 120b serving as a source electrode, a conductive film 112a serving as a second gate electrode, The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode are overlapped with each other. are positioned so that

[0147] In this configuration example, the oxide semiconductor film 108 includes a first region that overlaps with the conductive film 104. a second region overlapping the conductive film 112a; a third region overlapping the conductive film 112b; The first region or the fourth region is a region that overlaps the second region and the fourth region. In other words, the first region or the fourth region is not included. is disposed so as not to overlap with the second region and the third region.

[0148] By adopting the above-mentioned configuration, the second gate electrode and the source electrode or the second gate electrode and The parasitic capacitance between the drain electrodes can be reduced.

[0149] The other configurations of the transistors 171 and 172 are the same as those of the transistor 1 shown above. It is the same as 00 and has the same effect.

[0150] <Configuration Example 4 of Semiconductor Device> Note that in Configuration Example 1, the first gate electrode is disposed under the oxide semiconductor film. The present invention describes a bottom-gate transistor located at the top of the A top-gate transistor may be used, in which the gate is located above the semiconductor film. The transistor 160 will be described with reference to FIGS. In the case where the function is the same as that described above, the hatch pattern is the same and the symbol is In some cases, the number may not be added.

[0151] FIG. 10A is a top view of a transistor 160 which is a semiconductor device of one embodiment of the present invention. FIG. 10B is a cross-sectional view taken along the dashed line X1-X2 in FIG. FIG. 10C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. This corresponds to a surface view.

[0152] The transistor 160 includes an oxide semiconductor film 108 over a substrate 102 and a a conductive film 112a serving as a source electrode electrically connected to the oxide semiconductor film 10 A conductive film 112b serving as a drain electrode electrically connected to the drain electrode 8 and a conductive film 112a The insulating film 107 on the conductive film 112b and the oxide semiconductor film 108 and the insulating film 107 The insulating film 106 is provided on the substrate 100, and the conductive film 104 is provided on the insulating film 106 and functions as a first gate electrode. In addition, on the transistor 160, more specifically, the insulating film 106, the conductive film 112a, On the conductive film 104, insulating films 114, 116, and 118 are provided. The insulating films 114, 116, and 118 function as protective insulating films for the transistor 160. do.

[0153] A conductive film 104 functioning as a first gate electrode and a conductive film 112 functioning as a source electrode. a, a conductive film 104 functioning as a first gate electrode, and a conductive film 105 functioning as a drain electrode. The conductive films 112b are arranged so as not to overlap each other.

[0154] In this configuration example, the oxide semiconductor film 108 includes a first region that overlaps with the conductive film 104. The conductive film 112a has a second region overlapping the conductive film 112b, and the conductive film 112b has a third region overlapping the conductive film 112b. The first region is disposed so as not to include the second region and the third region. The first region is disposed so as not to overlap with the second region and the third region.

[0155] By adopting the above-mentioned configuration, the first gate electrode and the source electrode and the first gate electrode The parasitic capacitance between the drain electrodes can be reduced.

[0156] The other configuration of the transistor 160 is similar to that of the transistor 100 shown above. Yes, and it has the same effect.

[0157] <Configuration Example 5 of Semiconductor Device> In the first configuration example, the first gate electrode and the source electrode, and the first gate electrode and the drain electrode Although the first gate electrode and the source electrode or the first gate electrode and the drain electrode are not overlapped, The inner electrodes may not overlap each other.

[0158] The above configuration example will be described with reference to FIG. 11. FIG. 11 (A-1) and (B-1) show the present 11(A) and 11(B) are top views of transistors 151 and 152 which are semiconductor devices of one embodiment of the present invention. A-2) corresponds to a cross-sectional view of the cut surface between the dashed line X1-X2 shown in FIG. 11(A-1). FIG. 11(B-2) is a cross-section taken along dashed line X1-X2 in FIG. 11(B-1). The cross-sectional view of the cut surface between the dashed line Y1-Y2 corresponds to the cross-sectional view of FIG. ) is omitted because it has the same shape as the above-mentioned function. In some cases, the hatch patterns are the same and no particular reference numbers are assigned.

[0159] FIG. 11(A-2) shows a conductive film 104 functioning as a first gate electrode and a The functioning conductive film 112a has an overlapping region and functions as a first gate electrode. The conductive film 104 and the conductive film 112b functioning as the drain electrode are arranged so as not to overlap each other. It has been done.

[0160] FIG. 11B-2 shows a conductive film 104 functioning as a first gate electrode and a The conductive films 112a that function do not overlap each other, and the conductive film 10 that functions as the first gate electrode 4 and the conductive film 112b functioning as a drain electrode are arranged so as to have an overlapping area with each other. It has been done.

[0161] In this configuration example, the oxide semiconductor film 108 includes a first region that overlaps with the conductive film 104. The conductive film 112a has a second region overlapping the conductive film 112b, and the conductive film 112b has a third region overlapping the conductive film 112b. The first region is disposed so as not to include the second region or the third region. The first region is disposed so as not to overlap with the second region or the third region.

[0162] By adopting the above-mentioned configuration, the first gate electrode and the source electrode or the first gate electrode and The parasitic capacitance between the drain electrodes can be reduced.

[0163] The other configurations of the transistors 151 and 152 are the same as those of the transistor 1 shown above. It is the same as 00 and has the same effect.

[0164] <Configuration Example 6 of Semiconductor Device> In the configuration example 2, the first gate electrode and the source electrode and the first gate a first gate electrode, a second drain electrode, a second source electrode, and a second gate electrode The first gate electrode and the source electrode, and the first gate a first gate electrode and a drain electrode, a second gate electrode and a source electrode, or a second gate electrode and a drain electrode. The rain electrodes may be configured not to overlap.

[0165] The above configuration example will be described with reference to Figs. 12 to 17. 1) and (B-1) are transistors 173 to 174 which are semiconductor devices according to one embodiment of the present invention. 12 to 17 are top views of the 84, and (A-2) and (B-2) of FIG. 12 to FIG. Cross-sectional views of the cut surface between dashed lines X1-X2 shown in (A-1) and (B-1) of 17. The cross-sectional view taken along the dashed line Y1-Y2 corresponds to FIG. 3(C). In addition, if the function is the same as that described above, In some cases, the patterns are the same and no particular symbols are attached.

[0166] FIG. 12(A-2) shows a conductive film 104 functioning as a first gate electrode and a The conductive film 112a that functions as a first gate electrode and the conductive film 104 that functions as a drain electrode the conductive film 112b functioning as a second gate electrode, and the conductive film 120b functioning as a second gate electrode. The conductive film 112a functioning as the second gate electrode and the conductive film 112b functioning as the source electrode do not overlap each other. The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode overlap each other in an area. The electrodes are arranged to have a region.

[0167] FIG. 12B-2 shows a conductive film 104 functioning as a first gate electrode and a The conductive film 112a that functions as a first gate electrode and the conductive film 104 that functions as a drain electrode the conductive film 112b functioning as a second gate electrode, and the conductive film 120b functioning as a second gate electrode. The conductive film 112b functioning as the second gate electrode and the conductive film 112b functioning as the drain electrode do not overlap with each other. The conductive film 120b functioning as a source electrode and the conductive film 112a functioning as a source electrode overlap each other in an area. The electrodes are arranged to have a region.

[0168] FIG. 13(A-2) shows a conductive film 104 functioning as a first gate electrode and a drain electrode. a conductive film 112b functioning as a second gate electrode; a conductive film 120b functioning as a source electrode; A conductive film 112a functions as a first gate electrode, and a conductive film 120 functions as a second gate electrode. b and the conductive film 112b functioning as the drain electrode do not overlap each other, and the first gate electrode The conductive film 104 functioning as a source electrode and the conductive film 112a functioning as a source electrode overlap each other. The electrodes are arranged to have a region.

[0169] FIG. 13B-2 shows a conductive film 104 functioning as a first gate electrode and a A conductive film 112a that functions as a second gate electrode, a conductive film 120b that functions as a source electrode, a conductive film 112a functioning as a second gate electrode, and a conductive film 120b functioning as a second gate electrode. The conductive film 112b functioning as the first gate electrode and the conductive film 112b functioning as the drain electrode do not overlap with each other. The conductive film 104 functioning as a drain electrode and the conductive film 112b functioning as a drain electrode overlap each other. The electrodes are arranged to have a region.

[0170] FIG. 14(A-2) shows a conductive film 104 functioning as a first gate electrode and a The conductive films 112a and 112b functioning as the first gate electrode do not overlap each other. 04, a conductive film 112b functioning as a drain electrode, and a conductive film 112c functioning as a second gate electrode. The conductive film 120b functions as a source electrode, the conductive film 112a functions as a second gate electrode, and The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode are overlapped with each other. The electrodes are arranged to have a region where the electrodes are spaced apart from each other.

[0171] FIG. 14B-2 shows a conductive film 104 functioning as a first gate electrode and a drain electrode. The conductive film 112b functioning as the first gate electrode does not overlap with the conductive film 112a. 104, a conductive film 112a functioning as a source electrode, and a conductive film 112b functioning as a second gate electrode. The conductive film 120b functions as a source electrode, the conductive film 112a functions as a second gate electrode, and The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode are overlapped with each other. The electrodes are arranged to have a region where the electrodes are spaced apart.

[0172] FIG. 15(A-2) shows a conductive film 120b functioning as a second gate electrode and a drain electrode. The conductive film 112b functioning as the first gate electrode does not overlap with the conductive film 112a. The conductive film 112a functions as a first gate electrode. The conductive film 104, the conductive film 112b functioning as a drain electrode, and the second gate electrode The conductive film 120b functioning as the source electrode and the conductive film 112a functioning as the source electrode are overlapped with each other. The electrodes are arranged to have a region.

[0173] FIG. 15B-2 shows a conductive film 120b functioning as a second gate electrode and a conductive film 120c functioning as a source electrode. The conductive film 112a functioning as the first gate electrode does not overlap with the conductive film 112b. 104, a conductive film 112a functioning as a source electrode, and a conductive film 112b functioning as a first gate electrode. a conductive film 104, a conductive film 112b functioning as a drain electrode, and a second gate electrode The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode are overlapped with each other. The electrodes are arranged to have a region.

[0174] FIG. 16(A-2) shows a conductive film 104 functioning as a first gate electrode and a drain electrode. and a conductive film 120b functioning as a second gate electrode. The conductive film 112b, which functions as a drain electrode, does not overlap with each other and serves as a first gate electrode. The conductive film 104 functioning as a source electrode, the conductive film 112a functioning as a second gate electrode, The conductive film 120b functioning as an electrode and the conductive film 112a functioning as a source electrode are are arranged to have an overlapping area.

[0175] FIG. 16B-2 shows a conductive film 104 functioning as a first gate electrode and a The conductive film 112a functions as a second gate electrode, and the conductive film 120b functions as a second gate electrode. The conductive film 112a, which functions as a first gate electrode, does not overlap with the conductive film 112a. The conductive film 104 functions as a drain electrode, the conductive film 112b functions as a second gate electrode, and the conductive film 112c functions as a second gate electrode. The conductive film 120b functioning as the electrode and the conductive film 112b functioning as the drain electrode are are arranged to have an overlapping area.

[0176] FIG. 17(A-2) shows a conductive film 104 functioning as a first gate electrode and a drain electrode. a conductive film 112b functioning as a second gate electrode, and a conductive film 120b functioning as a second gate electrode. The conductive film 112a, which functions as a source electrode, does not overlap with each other and serves as a first gate electrode. The conductive film 104 functions as a source electrode, the conductive film 112a functions as a second gate electrode, and the conductive film 112b functions as a source electrode. The conductive film 120b functions as a source electrode and the conductive film 112b functions as a drain electrode. They are arranged so as to have an overlapping area with each other.

[0177] FIG. 17B-2 shows a conductive film 104 functioning as a first gate electrode and a The conductive film 112a functions as a gate electrode, and the conductive film 120b functions as a second gate electrode. The conductive film 112b, which functions as a drain electrode, does not overlap with each other and serves as a first gate electrode. The conductive film 104 that functions as a drain electrode, the conductive film 112b that functions as a second gate electrode, and the conductive film 112b that functions as a drain electrode are The conductive film 120b serving as a gate electrode and the conductive film 112a serving as a source electrode are They are arranged so as to have an overlapping area with each other.

[0178] In this configuration example, the oxide semiconductor film 108 includes a first region that overlaps with the conductive film 104. a second region overlapping the conductive film 112a; a third region overlapping the conductive film 112b; The first region or the fourth region is a region overlapping the second region or the fourth region. In other words, the first region or the fourth region is not included. is disposed so as not to overlap with the second region or the third region.

[0179] By adopting the above-mentioned configuration, the first gate electrode and the source electrode, the first gate electrode and the drain electrode between the in-electrode, the second gate electrode and the source electrode or between the second gate electrode and the drain electrode The parasitic capacitance can be reduced.

[0180] The other configurations of the transistors 173 to 184 are the same as those of the transistor 10 shown above. It is the same as 0 and has the same effect.

[0181] <Configuration Example 7 of Semiconductor Device> In the configuration example 4, the first gate The first gate electrode and the source electrode, and the first gate electrode and the drain electrode are not overlapped. The first gate electrode and the source electrode or the first gate electrode and the drain electrode do not overlap each other. It may also be composed of.

[0182] The above configuration example will be described with reference to FIG. 18. FIG. 18(A-1) and (B-1) show the configuration of this 18(A) and 18(B) are top views of transistors 161 and 162 which are semiconductor devices of one embodiment of the invention. A-2) corresponds to a cross-sectional view of the cut surface between the dashed line X1-X2 shown in FIG. 18(A-1). FIG. 18(B-2) is a cross-section taken along the dashed line X1-X2 shown in FIG. 18(B-1). The cross-sectional view of the cut surface between the dashed line Y1-Y2 is shown in FIG. Since it has the same shape as C), it will be omitted. In such cases, the hatch patterns may be the same and no particular reference numbers may be used.

[0183] FIG. 18(A-1) shows a conductive film 104 functioning as a first gate electrode and a The functioning conductive film 112a has an overlapping region and functions as a first gate electrode. The conductive film 104 and the conductive film 112b functioning as the drain electrode are arranged so as not to overlap each other. It has been done.

[0184] FIG. 18B-2 shows a conductive film 104 functioning as a first gate electrode and a The conductive films 112a that function do not overlap each other, and the conductive film 10 that functions as the first gate electrode 4 and the conductive film 112b functioning as a drain electrode are arranged so as to have an overlapping area with each other. It has been done.

[0185] In this configuration example, the oxide semiconductor film 108 includes a first region that overlaps with the conductive film 104. The conductive film 112a has a second region overlapping the conductive film 112b, and the conductive film 112b has a third region overlapping the conductive film 112b. The first region is disposed so as not to include the second region or the third region. The first region is disposed so as not to overlap with the second region or the third region.

[0186] By adopting the above-mentioned configuration, the first gate electrode and the source electrode or the first gate electrode and The parasitic capacitance between the drain electrodes can be reduced.

[0187] The other configurations of the transistors 161 and 162 are the same as those of the transistor 1 It is the same as 00 and has the same effect.

[0188] <Method 1 for manufacturing semiconductor device> Next, a transistor 10 which is a semiconductor device of one embodiment of the present invention will be described. A method for manufacturing the semiconductor device 10 will be described in detail below with reference to FIGS. 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device.

[0189] Note that the films constituting the transistor 100 (the insulating film, the oxide semiconductor film, the conductive film, and the like) are Sputtering, Chemical Vapor Deposition (CVD), Vacuum Evaporation, Pulsed Laser Deposition (PLD) Alternatively, the insulating layer 14 can be formed by a coating method or a printing method. The most common deposition methods are sputtering and plasma enhanced chemical vapor deposition (PECVD). However, a thermal CVD method may also be used. An example of a thermal CVD method is MOCVD (metal organic chemical vapor deposition) ) method or ALD (atomic layer deposition) method may also be used.

[0190] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0191] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating the gas introduction sequence. For example, By switching each switching valve (also called high-speed valve), two or more types of raw materials can be The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so that multiple source gases do not mix. Simultaneously with or after the second gas, an inert gas (such as argon or nitrogen) is introduced. Introduce the raw material gas. If an inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monoatomic layer is formed by reacting with the second source gas introduced later. Layer upon layer is laminated to form a thin film.

[0192] This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. This allows precise film thickness control, making it possible to fabricate minute transistors. It is suitable for fabrication.

[0193] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive film 104 that functions as a first gate electrode is formed. On the conductive film 104, insulating films 106 and 107 that function as a first gate insulating film are formed (see FIG. 4(A)).

[0194] The conductive film 104 functioning as the first gate electrode is formed by a method such as sputtering or chemical vapor deposition ( It can be formed using the CVD method, the vacuum evaporation method, the pulsed laser deposition (PLD) method, etc. Alternatively, it can be formed by a coating method or a printing method. The most representative methods are the plasma enhanced chemical vapor deposition (PECVD) method, but the previously explained organic metal Thermal CVD methods such as MOCVD or atomic layer deposition (ALD) can also be used. good.

[0195] In this embodiment, a glass substrate is used as the substrate 102, which functions as the first gate electrode. A tungsten film having a thickness of 100 nm is formed as the conductive film 104 by sputtering. .

[0196] The insulating films 106 and 107 functioning as the first gate insulating film are formed by sputtering, PE The film can be formed by using a CVD method, a thermal CVD method, a vacuum deposition method, a PLD method, or the like. In this embodiment, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 by the PECVD method. Then, a silicon oxynitride film is formed as the insulating film 107 to a thickness of 50 nm.

[0197] The insulating film 106 may have a stacked structure of a silicon nitride film. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminate structure with a silicon film can be formed. An example of the three-layer laminate structure is as follows: It can be formed as follows:

[0198] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PECVD was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gas. The pressure in the reaction chamber was controlled at 100 Pa, and a high-frequency wave of 27.12 MHz was generated. A power of 2000 W may be supplied using a microwave power source to form the film to a thickness of 50 nm. stomach.

[0199] For the second silicon nitride film, silane at a flow rate of 200 sccm, The nitrogen gas and the ammonia gas with a flow rate of 2000sccm were used as the source gases in the PECVD equipment. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply was used. A power of 2000 W may be supplied using the above method to form a film having a thickness of 300 nm.

[0200] The third silicon nitride film was prepared by using silane at a flow rate of 200 sccm and 5000 sccm. The pressure in the reaction chamber was kept at 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power source. It is sufficient to form it so that the thickness is 50 nm.

[0201] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during formation can be 350°C.

[0202] By forming the insulating film 106 in a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper (Cu) is used for 4, the following effects are achieved.

[0203] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and can be used as the first gate insulating film. The third silicon nitride film can improve the breakdown voltage of the insulating film that functions as a third nitride film. The hydrogen release from the first silicon nitride film is small, and the hydrogen release from the second silicon nitride film is small. The diffusion of the substance can be suppressed.

[0204] The insulating film 107 is an oxide semiconductor film 108 (more specifically, a first In order to improve the interface characteristics with the oxide semiconductor film 108a), It would be preferable if this could be done.

[0205] Next, a first oxide semiconductor film 108a is formed over the insulating film 107. A second oxide semiconductor film 108b is formed over the oxide semiconductor film 108a (see FIG. 4B). (see).

[0206] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: A first oxide semiconductor film was formed by sputtering using a SiO2 / SiO2 (atomic ratio: 2:4.1). Then, in vacuum, the In-Ga-Zn metal oxide target (In:Ga: The second oxide semiconductor was deposited by sputtering using Zn (atomic ratio: 1:1:1.2). A conductive film is formed to form a stacked oxide semiconductor film. A mask is formed on the oxide semiconductor film by a lithography process, and the oxide semiconductor film of the stack is formed in a desired region. By processing the oxide semiconductor film 108 into an island shape, the oxide semiconductor film 108 is formed.

[0207] When the oxide semiconductor film 108 is formed by a sputtering method, a sputtering gas In the case of the above, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used. In the case of a mixed gas, it is preferable to increase the ratio of oxygen to rare gas. It is also necessary to increase the purity of the sputtering gas. For example, oxygen used as a sputtering gas The gas or argon gas has a dew point of -40°C or less, preferably -80°C or less, and more preferably By using gas that has been highly purified to temperatures below -100℃, and more preferably below -120℃, This can prevent moisture and the like from being absorbed into the oxide semiconductor film 108 as much as possible.

[0208] In addition, when the oxide semiconductor film 108 is formed by a sputtering method, a sputtering apparatus The chamber is designed to remove water and other impurities that may be contained in the oxide semiconductor film 108 as much as possible. In order to remove the gas, a high vacuum pump (5×10 -7 Pa to 1×10 -4 It is preferable to use a turbo molecular pump. A combination of a filter and a cold trap is used to extract gas, especially carbon or water, from the exhaust system into the chamber. It is preferable to prevent backflow of oxygen-containing gas.

[0209] Next, a source electrode and a drain electrode are formed on the insulating film 107 and the second oxide semiconductor film 108b. A conductive film 112 that functions as an electrode is formed (see FIG. 4C).

[0210] In this embodiment, the conductive film 112 is a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 40 A laminated film with a 0 nm aluminum film is formed by sputtering. In the embodiment, the conductive film 112 has a stacked structure of two layers, but is not limited to this. The conductive film 112 is a tungsten film having a thickness of 50 nm and an aluminum film having a thickness of 400 nm. Alternatively, the insulating layer may have a three-layer structure consisting of a 100 nm thick titanium film and a 100 nm thick titanium film.

[0211] Next, masks 140a and 140b are formed in desired regions on the conductive film 112 (FIG. 4(D) )reference).

[0212] In this embodiment, the masks 140a and 140b are formed by applying a photosensitive resin film. The photosensitive resin film is then patterned by a lithography process to form the insulating film.

[0213] Next, etching gas 138 is used to remove the conductive film 112 and the masks 140a and 140b. Then, the conductive film 112 and the second oxide semiconductor film 108b are processed (see FIG. 5A).

[0214] In this embodiment, the conductive film 112 and the second acid are removed by using a dry etching apparatus. However, the method for forming the conductive film 112 is not limited to this. For example, a chemical solution may be used as the etching gas 138 to perform wet etching. The conductive film 112 and the second oxide semiconductor film 108b may be processed by using a processing device. Then, the conductive film 112 and the second oxide semiconductor film 108 are etched using a wet etching apparatus. Rather than processing step b, the conductive film 112 and the second oxide semiconductor film 113 are processed by using a dry etching apparatus. Processing the conductive film 108b is preferable because it allows for the formation of finer patterns. It is.

[0215] Next, the masks 140a and 140b are removed, so that the second oxide semiconductor film 108b is left The conductive film 112a serving as a source electrode of the second oxide semiconductor film 108b and the drain electrode of the second oxide semiconductor film 108b are A conductive film 112b functioning as an in-electrode is formed. The first oxide semiconductor film 108a and the second oxide semiconductor film 108b having a recess are (See FIG. 5(B)).

[0216] In addition, a chemical solution was sprayed onto the second oxide semiconductor film 108b and the conductive films 112a and 112b. The surface (back channel side) of the second oxide semiconductor film 108b may be cleaned by applying the solution. The cleaning method may be, for example, cleaning with a chemical solution such as phosphoric acid. By cleaning with a chemical solution, impurities attached to the surface of the second oxide semiconductor film 108b are removed. (For example, elements contained in the conductive films 112a and 112b) can be removed. However, the washing is not necessarily required, and in some cases, washing may not be performed.

[0217] In addition, during the formation of the conductive films 112a and 112b and / or during the above-mentioned cleaning process, The oxide semiconductor film 108b has a second region having a smaller thickness than the first oxide semiconductor film 108a. A region is formed.

[0218] Next, the insulating films 114 and 112 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. Form 6 (see FIG. 5(C)).

[0219] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposing it to the air. After the insulating film 114 is formed, it is preferable to adjust the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the air. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. At the same time, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0220] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, etc. Examples of oxidizing gases include nitrous oxide, nitrous oxide, and trisilane. In addition, the flow rate of the oxidizing gas is set to 20 times or more the flow rate of the deposition gas. The pressure in the treatment chamber is set to less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the treatment chamber is set to less than 100 Pa. By using the PECVD method at a pressure of 50 Pa or less, preferably 50 Pa or less, the insulating film 114 is The insulating film contains the above and has a small amount of defects.

[0221] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220° C. The source gases were silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm. The pressure in the treatment chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6×10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using this.

[0222] The insulating film 116 is formed by depositing a substrate in a vacuum-evacuated processing chamber of a PECVD apparatus. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the treatment chamber to increase the pressure in the treatment chamber. is set to 100 Pa or more and 250 Pa or less, and more preferably set to 100 Pa or more and 200 Pa or less. 0.17 W / cm2 at the electrode installed in the treatment chamber 2 More than 0.5W / cm 2 Below are some more Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0223] The conditions for forming the insulating film 116 are as follows: high frequency power density in a reaction chamber with the above pressure; By supplying power, the efficiency of decomposition of the source gas in the plasma increases, and the number of oxygen radicals increases. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes lower than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is Since the oxygen in the film is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. An oxide that contains more oxygen than satisfies the theoretical composition and loses some of the oxygen when heated. An insulating film can be formed.

[0224] The process of forming the insulating film 116 is carried out in a PECVD apparatus at a temperature of 180° C. to 350° C. The insulating film 116 is formed during the manufacturing process of the transistor 100. It is preferable that the temperature in the process is the highest. For example, the temperature at which the insulating film 116 is formed is set to 350° C. By carrying out the above steps, it is possible to form the transistor 100 directly on a flexible substrate, etc. .

[0225] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0226] In the deposition conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the amount of defects in the insulating film 116. In the first place, ESR measurements revealed that the g value was 2.001, which is due to the dangling bonds of silicon. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5×10 17 spins / cm 3 The following is a missing It is possible to form an oxide insulating layer with few defects. As a result, the reliability of the transistor is improved. It can be done.

[0227] After the insulating films 114 and 116 are formed, heat treatment may be performed. This can reduce the amount of nitrogen oxide contained in the insulating films 114 and 116. By the heat treatment, part of oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. By this, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0228] The temperature for the heat treatment of the insulating films 114 and 116 is typically 150° C. or higher and 350° C. or lower. Heat treatment is carried out in an atmosphere of nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably air at less than 1 ppm, preferably less than 10 ppb), or rare gases (argon, helium The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas may be added to the water atmosphere. It is preferable that the mixture does not contain hydrogen, water, etc. The heat treatment is carried out using an electric furnace, an RTA device, etc. It is possible.

[0229] In this embodiment, heat treatment is performed in a nitrogen atmosphere at 350° C. for 1 hour. In the step of forming the transistor 100, the temperature at which the insulating film 116 is formed should be the highest. Alternatively, heat treatment at a temperature similar to that for forming the insulating film 116 may be performed in a different step.

[0230] Next, an oxide conductive film 131 is formed over the insulating film 116 (see FIG. 5D).

[0231] The oxide conductive film 131 is a film made of oxygen and a metal (indium, zinc, titanium, aluminum, tantalum, etc.). At least one selected from the group consisting of tin, tantalum, and molybdenum. do.

[0232] Examples of the oxide conductive film 131 include a tantalum oxynitride film, a titanium oxide film, and an indium Tin oxide (ITO) film, aluminum oxide film, oxide semiconductor film (e.g., I A GZO film (In:Ga:Zn=1:4:5 (atomic ratio)) can be used. The oxide conductive film 131 can be formed by a sputtering method. The thickness of the oxide conductive film 131 is 1 nm or more and 20 nm or less, or 2 nm or more and 10 nm or less. In this embodiment, the oxide conductive film 131 has a thickness of 50 nm or less. Indium tin oxide doped with silicon oxide (hereinafter referred to as ITSO) is used.

[0233] Next, the insulating films 114 and 116 and the oxide semiconductor film 108 are In the figure, oxygen 139 is added to the insulating film 114 and the insulating film 116. The oxygen that is released is represented diagrammatically as oxygen-139 (see FIG. 6(A)).

[0234] The insulating films 114 and 116 and the oxide semiconductor film 108 are filled with oxygen through the oxide conductive film 131. Methods for adding 39 include ion doping, ion implantation, plasma treatment, etc. In addition, when oxygen 139 is added, applying a bias to the substrate side effectively increases the amount of oxygen. The element 139 can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. The bias may be, for example, a power density of 1 W / cm 2 More than 5W / cm 2 Let's say the following: By providing the oxide conductive film 131 over the insulating film 116 and adding oxygen, the oxide conductive film The insulating film 131 functions as a protective film that suppresses oxygen from being released from the insulating film 116. Therefore, more oxygen can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. can.

[0235] Next, the oxide conductive film 131 is removed by an etchant 142 (see FIG. 6B). .

[0236] The oxide conductive film 131 can be removed by dry etching or wet etching. or a combination of dry etching and wet etching. In the case of the dry etching method, the etchant 142 is an etching gas. In the case of wet etching, the etchant 142 is a chemical liquid. In the second step, the oxide conductive film 131 is removed by wet etching.

[0237] Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 6C).

[0238] Note that a heat treatment is performed before or after the insulating film 118 is formed to obtain an insulating film. Excess oxygen contained in the films 114 and 116 is diffused into the oxide semiconductor film 108, and the oxide semiconductor Alternatively, the insulating film 118 can be formed by heating and filling the oxygen vacancies in the insulating film 108. By this, excess oxygen contained in the insulating films 114 and 116 is diffused into the oxide semiconductor film 108. Thus, oxygen vacancies in the oxide semiconductor film 108 can be filled.

[0239] When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to 180° C. or higher and 350° C. or lower. This is preferable because it allows a dense film to be formed.

[0240] For example, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma and becomes active. The active species are generated by reacting with silicon and hydrogen contained in the deposition gas containing silicon. This breaks the triple bond between silicon and nitrogen, promoting the bonding of silicon and nitrogen. To form a dense silicon nitride film with few bonds between silicon and hydrogen and few defects. On the other hand, if the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and Nitrogen decomposition does not progress, silicon and hydrogen bonds remain, defects increase, and roughness is generated. For these reasons, the source gas should be ammonia-free. The flow rate ratio of nitrogen to oxygen is preferably 5 or more and 50 or less, and more preferably 10 or more and 50 or less.

[0241] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, etc., using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 100 for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the flow rate was 27.12 MWh. A high-frequency power supply of 1000 W is supplied to the parallel plate electrodes. The device has an electrode surface area of ​​6000 cm 2 The parallel plate type PECVD equipment is The force can be converted to power per unit area (power density) of 1.7 x 10 -1 W / cm 2 is .

[0242] Through the above steps, the transistor 100 shown in FIG. 1 can be formed.

[0243] In addition, the Loff type transistor and the Lov type transistor have a first gate electrode, an oxide semiconductor By changing the pattern of the conductor film, source electrode, or drain electrode, Since this is possible, they can be formed on the same substrate at the same time by the same manufacturing method.

[0244] In addition, in the present manufacturing method, the first gate electrode and the source electrode, and the first gate electrode and the drain electrode are The above description is given assuming that the first gate electrode and the source electrode do not overlap. The same manufacturing method can also be applied to a configuration in which the first gate electrode and the drain electrode do not overlap.

[0245] <Method for manufacturing semiconductor device 2> Next, a method for manufacturing the transistor 170 of one embodiment of the present invention This will be described in detail below with reference to FIG. 7. FIG. 7 illustrates a method for manufacturing a semiconductor device. 7(A), (C), (E), and (G) are cross-sectional views showing the fabrication of a transistor 170. 7(B), (D), (F), and (H) are cross-sectional views in the channel length direction during fabrication of a transistor. 13 is a cross-sectional view of the substrate 170 in the channel width direction during fabrication. FIG.

[0246] First, the same steps as in the method for manufacturing the transistor 100 described above (the steps shown in FIGS. 4 to 6) are performed. ) is performed, and a conductive film 104, insulating films 106 and 107, and an oxide semiconductor film 108 are formed on the substrate 102. , conductive films 112a and 112b, and insulating films 114, 116, and 118 are formed (FIG. 7(A) )(see B)).

[0247] Next, a mask is formed on the insulating film 118 by a lithography process, and the insulating films 114 and 11 An opening 142c is formed in a desired region of the insulating film 118. A mask is formed by a photolithography process, and the desired insulating films 106, 107, 114, 116, and 118 are formed. In this region, openings 142a and 142b are formed. The openings 142a and 142b are formed so as to reach the conductive film 10 4 (see Figures 7(C) and (D)).

[0248] The openings 142a, 142b and the opening 142c may be formed in the same process or in different processes. The openings 142a, 142b and the opening 142c may be formed in the same process. When forming the insulating film, for example, a gray-tone mask or a half-tone mask may be used. The openings 142a and 142b may be formed in a plurality of steps. For example, First, the insulating films 106 and 107 are processed, and then the insulating films 114, 116 and 118 are processed.

[0249] Next, a conductive film 12 is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. 0 (see Figures 7(E) and (F)).

[0250] The conductive film 120 may be made of, for example, indium (In), zinc (Zn), or tin (Sn). In particular, the conductive film 120 may be made of a material containing one selected from the group consisting of an acid, Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide (ITO), indium zinc oxide, indium stannate with silicon oxide A conductive material having light transmitting properties, such as an ITSO film, can be used. The film 120 can be formed by using, for example, a sputtering method. In this embodiment, an ITSO film having a thickness of 110 nm is formed by sputtering.

[0251] Next, a mask is formed on the conductive film 120 by a lithography process, and the conductive film 112 is By processing the conductive film 120a and the conductive film 120b into the shape shown in FIG. ).

[0252] The conductive films 120a and 120b can be formed by dry etching, wet etching, or the like. Examples of the method include a combination of dry etching and wet etching. In this embodiment, the conductive film 120 is formed by wet etching. The conductive films 120a and 120b are then processed.

[0253] Through the above steps, the transistor 170 illustrated in FIG. 3 can be manufactured.

[0254] In addition, the Loff type transistor and the Lov type transistor have a first gate electrode and a second gate electrode. By changing the patterns of the gate electrode, the oxide semiconductor film, the source electrode, or the drain electrode, Since it is possible to fabricate them separately, they can be formed simultaneously on the same substrate using the same fabrication method. It is possible.

[0255] In addition, in the present fabrication method, the first gate electrode and the source electrode, the first gate electrode and the drain electrode the second gate electrode and the source electrode, and the second gate electrode and the drain electrode are connected to each other. Although the above description is given by taking an example of a non-overlapping configuration, the first gate electrode, the source electrode, and the first A gate electrode and a drain electrode, or a second gate electrode and a source electrode and a second gate The same manufacturing method can be applied to a configuration in which the first electrode and the drain electrode do not overlap each other. a first gate electrode and a source electrode, a first gate electrode and a drain electrode, a second gate electrode and a source electrode, The same method was used to fabricate a structure in which the first gate electrode and the drain electrode do not overlap each other. The method can be applied.

[0256] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0257] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor included in a semiconductor device of one embodiment of the present invention will be described. A detailed explanation will be given below.

[0258] <Structure of oxide semiconductor> Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As non-single crystal oxide semiconductors, CAAC-OS (C Ax is Aligned Crystalline Oxide Semiconductor or), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide e Semiconductor, pseudo-amorphous oxide semiconductor (a-like OS:a morphous like oxide semiconductor, amorphous oxide semiconductors, etc.

[0259] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0260] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0261] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor, which is not amorphous (for example, has a periodic structure in a microscopic region), is transformed into a completely amorphous oxide. However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. In terms of physical properties, it can be said that the semiconductor is close to an amorphous oxide semiconductor.

[0262] <caac-os>First, let me explain about CAAC-OS.

[0263] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0264] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0265] The following describes the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0266] A Cs-corrected high-resolution TEM image of the enlarged area (1) in Figure 19(A) is shown in Figure 19(B). From FIG. 19(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0267] As shown in FIG. 19(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of a single pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the inclination between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used as a C-Axis Aligned Nanoclip The semiconductor may also be referred to as an oxide semiconductor having metal ions.

[0268] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 19(D)). Between the pellets observed in FIG. 19(C), The portion where the inclination occurs corresponds to an area 5161 shown in FIG.

[0269] FIG. 20(A) shows the C 20(A) shows the s-corrected high-resolution TEM images of regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 20(B), (C) and (D), respectively. As shown in Figure 20(D), Figure 20(B), Figure 20(C) and Figure 20(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0270] Next, C was analyzed by X-ray diffraction (XRD). We will explain AAC-OS. For example, CAAC-O with InGaZnO4 crystals When the structure of S is analyzed using the out-of-plane method, the result is as shown in Figure 21(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal has a c-axis orientation. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0271] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0272] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I It is attributed to the (110) plane of the crystal of nGaZnO4. In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in FIG. On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in FIG. 21(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0273] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 2(B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 22(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0274] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0275] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0276] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0277] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Such an oxide semiconductor is a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. CAAC-OS has low impurity concentration and low defect level density. In other words, it has stable characteristics. It can be said that the oxide semiconductor has the above structure.

[0278] <nc-os>Next, we will explain nc-OS.

[0279] In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or greater than 1 nm. The oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor. For example, in high-resolution TEM images, the grain boundaries of the nc-OS are clearly identified. In addition, the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is sometimes called a pellet. be.

[0280] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0281] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0282] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0283] <a-like OS> The a-like OS is a cross between the nc-OS and an amorphous oxide semiconductor. The oxide semiconductor has the following structure.

[0284] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen, and areas where crystals can be seen. and areas where it is not possible to

[0285] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0286] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0287] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0288] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the crystals is 0.28 nm to 0.30 nm are considered to be crystal parts of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0289] Figure 23 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in FIG. 23, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 23, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0290] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0291] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0292] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0293] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0294] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0295] <Film formation model> Below, we will explain an example of the film formation model of CAAC-OS and nc-OS. explain.

[0296] FIG. 24A shows a process of forming a CAAC-OS film by a sputtering method. FIG. 1 is a schematic diagram of the inside of a membrane chamber.

[0297] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The arrangement and configuration of the magnets are described above. Please refer to the description of the film formation chamber mentioned above. The ring method is called magnetron sputtering.

[0298] The target 5130 has a polycrystalline structure, with each grain including a cleavage plane.

[0299] As an example, the cleavage surface of target 5130 having In-Ga-Zn oxide is described. FIG. 25(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In FIG. 25(A), the c-axis is oriented upward, and the InGaZn This is the structure of an O4 crystal.

[0300] As shown in FIG. 25(A), in two adjacent Ga-Zn-O layers, It can be seen that the oxygen atoms are arranged close to each other. And the oxygen atoms have a negative charge. By this, the two adjacent Ga-Zn-O layers repel each other. A ZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0301] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The deposition chamber is mostly filled with deposition gas (e.g., oxygen, argon, or a mixture containing 5% or more by volume of oxygen) and The pressure is controlled to be 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, a discharge starts and a plasma is generated. It is confirmed that a high density plasma region is generated near the target 5130 by the magnetic field. In the high-density plasma region, the deposition gas is ionized, and ions 5101 The ion 5101 is, for example, an oxygen cation (O + ) and argon cations ( Ar + ) etc.

[0302] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually At this time, flat or pellet-shaped sputtered particles are ejected from the cleavage plane. The pellets 5100a and 5100b are peeled off and knocked out. The pellet 5100a and the pellet 5100b are deformed by the impact of the ion 5101. Distortion may occur.

[0303] The pellet 5100a is a flat plate or pellet having a triangular, for example equilateral, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles having a plate-like or pellet-like shape. The term pellets refers to flat or pellet-shaped sputter particles such as pellet 5100b. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, but may be any shape, e.g. For example, a shape may be formed by combining multiple triangles. In some cases, the shape may be a quadrilateral (for example, a rhombus) made up of two joined sides.

[0304] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. A pellet shape with no lumps is preferable to a thick cube shape. The thickness of the 5100 is 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. For example, the pellet 5100 has a width of 1 nm or more. 100 corresponds to the initial nucleus described in (1) of FIG. 23 above. For example, In-Ga- When ions 5101 are collided with a target 5130 having Zn oxide, as shown in FIG. As shown in Fig. 1, the ZnO layer has three layers: a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer. The pellet 5100 pops out. Note that in FIG. 25(C), the pellet 5100 is aligned along the c-axis. This is the structure when viewed from a parallel direction. Therefore, the pellet 5100 has two G A nano-sized sandwich structure with a-Zn-O layer (bread) and In-O layer (stuffing) It can also be called construction.

[0305] The pellet 5100 receives a charge as it passes through the plasma, causing the sides to become negative or The pellet 5100 has oxygen atoms on the side, and the oxygen atoms In this way, the sides can be charged with the same polarity, The loads repel each other, allowing the flat shape to be maintained. When S is an In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. Or, it may be possible that the indium, gallium or zinc atoms are bonded to The oxygen atoms may become negatively charged. Also, as the pellet 5100 passes through the plasma, When this happens, the atoms bond with indium, gallium, zinc, and oxygen, etc., and grow. This corresponds to the difference in size between (2) and (1) in FIG. 23 above. Here, when the substrate 5120 is at room temperature, the pellet 5100 does not grow any more. As a result, it becomes nc-OS (see FIG. 24(B)). Since the temperature at which the film can be formed is about room temperature, Even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow 5100 in plasma, the deposition power in the sputtering method must be increased. It is effective to increase the deposition power to stabilize the structure of the pellet 5100. It is possible.

[0306] As shown in FIG. 24(A) and FIG. 24(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to the area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, a vertical magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is on the upper surface of the substrate 5120. Due to the action of the magnetic field and the electric current, a force (Lorentz force) is exerted on the object. This can be understood using Greg's left-hand rule.

[0307] The pellet 5100 has a large mass compared to a single atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It is possible that the force is generated by the action of a magnetic field and an electric current. In order to increase the force, the upper surface of the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably Alternatively, a region having a resistance of 50 G or more may be provided on the upper surface of the substrate 5120. A magnetic field oriented parallel to the top surface of the plate 5120 is 1. 5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is advisable to provide an area where

[0308] At this time, the magnet unit and / or the substrate 5120 move relatively. By rotating the substrate 5120, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Therefore, on the upper surface of the substrate 5120, the pellet 5100 is subjected to forces in various directions. can be received and moved in various directions.

[0309] Also, when the substrate 5120 is heated as shown in FIG. 24(A), the pellet 510 0 and the substrate 5120, the resistance due to friction is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches its side surface, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 00 is removed. The removed oxygen atom causes the Since oxygen vacancies may be filled, the CAAC-OS has a low density of defect states. The temperature of the upper surface of the plate 5120 is, for example, 100° C. or more and less than 500° C., 150° C. or more and 450° C. The temperature may be less than 170°C, 170°C or more and less than 400°C, or 170°C or more and 350°C or less. Even if the substrate 5120 has a large area, the CAAC-OS film can be formed.

[0310] In addition, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relieved. The pellet 51 with the distortion relieved is shown in FIG. Pellet 5100 is almost a single crystal. Pellet 5100 is almost a single crystal. Even if the 5100 pellets are heated after bonding, the 5100 pellets themselves hardly expand or contract. Therefore, the gaps between the pellets 5100 are widened, and the grain boundaries and other No defects or crevasses will form.

[0311] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The pellets are made of nano-crystals, and the aggregates resemble bricks or blocks stacked together. In addition, there are no grain boundaries between them. Even if CAAC-OS shrinks or deforms due to subsequent heating or bending, local stress is not a problem. It is therefore possible to reduce forces or release strain. The structure is suitable for semiconductor devices. nc-OS is a collection of pellets 5100 (nanocrystals). The resulting arrangement resembles a chaotic pile of elements.

[0312] When the target is sputtered with ions, not only pellets but also zinc oxide and other substances fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And it reaches 0.1nm to 10nm, 0.2nm to 5nm, or 0. A zinc oxide layer 5102 having a thickness of 5 nm or more and 2 nm or less is formed. A schematic cross-sectional view is shown in FIG.

[0313] As shown in FIG. 26(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c and 5105c are arranged so that their sides are in contact with each other. After being deposited on the pellet 5105b, the pellet 510 slides on the pellet 5105b. In another aspect of FIG. 05a, a plurality of particles 51 ejected from the target along with zinc oxide. The substrate 5120 is heated to crystallize the SiO 2 film 5103, forming a region 5105a1. Particles 5103 may include oxygen, zinc, indium, gallium, and the like.

[0314] Then, as shown in FIG. 26(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a2. It is arranged so as to be in contact with another side surface of 105b.

[0315] Next, as shown in FIG. 26(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the pellet 5105b. It also slides toward the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0316] As shown in FIG. 26(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105e is placed so that its side is in contact with the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. At the surface, a plurality of particles 5103 that have come out of the target together with zinc oxide are deposited on the substrate 51 By heating at 20, it is crystallized and a region 5105d1 is formed.

[0317] As described above, the piled pellets are arranged so that they come into contact with each other, and the pellets are Crystal growth occurs, forming a CAAC-OS on the substrate 5120. CAAC-OS has larger individual pellets than nc-OS. This is because This corresponds to the difference in size between (3) and (2) in Figure 23.

[0318] In addition, the gaps between the pellets 5100 are extremely small, so it feels like one large pellet. Large pellets may form. Large pellets have a single crystal structure. For example, large The pellet size, as viewed from above, is between 10 nm and 200 nm, and between 15 nm and 100 nm. m or less, or from 20 nm to 50 nm. If the channel formation area of ​​the pellet is smaller than that of the large pellet, the single crystal is considered as the channel formation area. In addition, the pellets can be enlarged to allow for the formation of a tran-crystalline structure. A region having a single crystal structure as a channel forming region, a source region, and a drain region of a transistor. In some cases, a region can be used.

[0319] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0320] Based on the above model, it is considered that the pellet 5100 is deposited on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is formed does not have a crystal structure, For example, the CAAC-OS film can be formed even in the case of a substrate 5120. Even if the structure of the top surface (the surface on which the material is formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a film of AC-OS.

[0321] In addition, even if the upper surface of the substrate 5120 on which the CAAC-OS is to be formed is uneven, It can be seen that the pellets 5100 are arranged along the shape of the substrate 5120. If the surface is atomically flat, the pellet 5100 will face down on a flat surface that is parallel to the ab plane. Since the layers are aligned toward each other, a layer with uniform thickness, flatness, and high crystallinity is formed. By stacking these layers n times (n is a natural number), we can obtain CAAC-OS. Cut.

[0322] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 51 The structure is made up of n layers (n is a natural number) of 00 arranged side by side along the convex surface. Since the surface of the pellet 5100 is uneven, gaps tend to form between the pellets 5100 in the CAAC-OS. However, intermolecular forces act between the pellets 5100, so even if there are uneven surfaces, the pellets Therefore, even if there are irregularities, high crystallinity is achieved. The CAAC-OS may have the following features:

[0323] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if the thickness is small, a uniform film can be formed.

[0324] Since the CAAC-OS film is formed by such a model, the sputtered particles are distributed evenly throughout the film. It is preferable that the sputtered particles are in the form of thick pellets. In this case, the surface facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. There is.

[0325] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface having an amorphous structure. Thus, a CAAC-OS having the above properties can be obtained.

[0326] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0327] (Embodiment 3) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described below with reference to FIGS.

[0328] 27 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed opposite to the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 27, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0329] The display device 700 is surrounded by a sealant 712 on the first substrate 701. A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 705 are arranged in a region different from the region. and an FPC terminal portion 708 (FPC: Flexible Printed Circuit portion 706) electrically connected to the In addition, the FPC terminal portion 708 is provided with The FPC 716 is connected to the pixel section 702 and the source driver circuit Various signals are supplied to the pixel section 704 and the gate driver circuit section 706. 02, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section 7 08 are connected to signal lines 710. Various signals are supplied by the FPC 716. 7, are connected to a pixel section 702, a source driver circuit section 704, a gate driver circuit section 705, and the like via a signal line 710. The wiring is provided to a driver circuit portion 706 and an FPC terminal portion 708.

[0330] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0331] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0332] The display device 700 can also include various elements, such as liquid crystal. Elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) etc.), transistors (transistors that emit light according to current), electron emitters, electron insulators , electrophoretic element, grating light valve (GLV), plasma display (P Display elements using DP, MEMS (Micro-Electro-Mechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter ), MIRASOL (registered trademark), IMOD (Interference Modulation ) element, shutter type MEMS display element, optical interference type MEMS display element, elect Rougheting element, piezoelectric ceramic display, carbon nanotube display In addition to these, the contrast, brightness, reflection The display device may have a display medium whose reflectance, transmittance, etc. change. An example of a display device using electron-emitting devices is an EL display. is a field emission display (FED) or SED type flat panel display (SED:Surface-conduction Electron-emitter An example of a display device using liquid crystal elements is a liquid crystal display. Play (transmissive LCD, semi-transmissive LCD, reflective LCD) , direct-view LCD, projection LCD, etc. Electronic ink or electro An example of a display device using electrophoretic elements is electronic paper. In order to realize a reflective liquid crystal display, a part of the pixel electrode or , all of the pixel electrodes may function as reflective electrodes. Alternatively, the entire material may be aluminum, silver, etc. It is also possible to provide a memory circuit such as an SRAM under the reflective electrode. Furthermore, power consumption can be reduced.

[0333] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB compose one color element, and two different colors are created by the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be selected for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used with monochrome displays. The present invention can also be applied to display devices such as those shown in FIG.

[0334] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light ( In order to display full color on a display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) , yellow (Y), etc. can be used in appropriate combination. The color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the amount of light emitted by organic EL elements and inorganic EL elements by about 30%. When using elements to display full color, R, G, B, Y, and white (W) are It is also possible to emit light from an element having a luminescent color. By using a self-luminous element, it is possible to use a colored layer. In some cases, power consumption can be reduced even further than when the

[0335] In this embodiment, a liquid crystal element and an EL element are used as display elements. 28 and 29. Note that FIG. 28 shows the area indicated by the dashed line QR in FIG. FIG. 29 is a cross-sectional view of the liquid crystal display device, which uses a liquid crystal element as a display element. 27, which is a cross-sectional view taken along the dashed line QR, and shows a configuration in which an EL element is used as a display element. It is.

[0336] First, the common parts shown in FIG. 28 and FIG. 29 will be explained, and then the different parts will be explained. This will be explained below.

[0337] <Description of Common Parts of the Display Device> The display device 700 shown in FIG. 28 and FIG. The wiring section 711, the pixel section 702, the source driver circuit section 704, and the FPC terminal section 70 8. The wiring portion 711 has a signal line 710. The source driver circuit 702 includes a transistor 750 and a capacitor 790. The unit 704 includes a transistor 752 .

[0338] The transistors 750 and 752 may be the transistors shown above. can.

[0339] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The transistor has a low current value in an off state (off-state current value). Therefore, the retention time of electric signals such as image signals can be extended, and the power supply When the write interval is on, it is possible to set it longer. This reduces the frequency of refresh operations. This has the effect of reducing power consumption.

[0340] In addition, the transistor described in Embodiment 1 can be used as a transistor in a pixel portion. On the other hand, the transistors used in the driver circuit section are Lo It is preferable to use a V-type transistor in the driver circuit section. For example, a transistor having a Lov type transistor and the transistor described in embodiment 1 may be used. The transistor includes a first gate electrode, a second gate electrode, an oxide semiconductor film, a source electrode, By changing the pattern of the drain electrode, The switching transistors in the main circuit and the driver transistors in the drive circuit are made on the same substrate. In addition, the transistor in the pixel portion may be formed on a substrate. By using transistors, it is possible to reduce parasitic capacitance, so the switching This allows the time constant during switching operation to be reduced. This reduces the panel size. It is possible to manufacture a large, high-definition display device. Since there is no need to use semiconductor devices formed from silicon wafers, etc., The number of points can be reduced.

[0341] The capacitor 790 has a structure having a dielectric between a pair of electrodes. One electrode of the transistor 790 functions as a first gate electrode of the transistor 750. The other electrode of the capacitor 790 is formed using a conductive film formed in the same process as the conductive film. A conductive film is used to function as a source electrode and a drain electrode of the transistor 750. The dielectric sandwiched between the pair of electrodes functions as a gate insulating film of the transistor 750. A functional insulating film is used.

[0342] 28 and 29, a transistor 750, a transistor 752, and a capacitor Over the quantum dot element 790, insulating films 764, 766, and 768, an oxide semiconductor film 767, and a planarizing An insulating film 770 is provided.

[0343] The insulating films 764, 766, and 768 are the same as the insulating film 114 shown in the previous embodiment. , 116, 118 can be formed by the same material and manufacturing method. The oxide semiconductor film 767 may be formed of the same material as the oxide semiconductor film 117 described in the above embodiment. The planarization insulating film 770 can be formed by the above-mentioned method. resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin Heat-resistant organic materials such as grease and epoxy resin can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films made of the same material. Further, the planarization insulating film 770 does not necessarily have to be provided.

[0344] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 75. 0, 752 source electrode and drain electrode, a conductive film formed in a different process, for example, The signal line 710 may be a conductive film that functions as a gate electrode of the When materials containing this material are used, signal delays caused by wiring resistance are minimal, making it possible to display images on a large screen. It becomes Noh.

[0345] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the drain electrode. The terminal of the PC 716 is electrically connected via an anisotropic conductive film 780 .

[0346] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0347] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778. In this embodiment, the structure 778 is provided on the first substrate 701 side. However, the present invention is not limited to this. For example, a structure 778 may be provided on the second substrate 705 side. Alternatively, the structures 778 may be provided on both the first substrate 701 and the second substrate 705. .

[0348] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0349] <Example of the configuration of a display device using a liquid crystal element as a display element> A display device 700 shown in FIG. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. In the display device 700 shown in FIG. The orientation state of the liquid crystal layer 776 is changed by the voltage, thereby controlling the transmission or non-transmission of light. The image can be displayed.

[0350] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. The liquid crystal display device 730 is a so-called reflective color liquid crystal display device, which reflects the light and displays it through the colored film 736.

[0351] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0352] In addition, when a conductive film that is reflective to visible light is used as the conductive film 772, the conductive film The film may have a laminated structure. For example, an aluminum film having a thickness of 100 nm is formed on the lower layer, A 30 nm thick silver alloy film (e.g., an alloy film containing silver, palladium, and copper) is formed on the upper layer. The above-mentioned structure provides the following excellent effects.

[0353] (1) The adhesion between the base film and the conductive film 772 can be improved. It is possible to etch the aluminum film and the silver alloy film at the same time. The cross-sectional shape of the conductive film 772 can be made to be a good shape (for example, a tapered shape). The reason for this is that the aluminum film is etched slower by chemicals than the silver alloy film. Or, after etching the upper silver alloy film, the lower aluminum film is exposed. The electrons are taken from aluminum, which is a metal with a lower ionization tendency than gold. Because of this, etching of the silver alloy film is suppressed and etching of the underlying aluminum film is suppressed. This is because the progression is faster.

[0354] In the display device 700 shown in FIG. 28, the planarization insulating film 770 of the pixel section 702 The unevenness is formed in a part of the insulating film 770 by, for example, forming an organic resin film or the like. The reflecting current can be formed by forming a reflecting current on the surface of the organic resin film and providing the reflecting current on the surface of the organic resin film. The conductive film 772, which functions as an electrode, is formed along the above-mentioned unevenness. When light enters the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772. This makes it possible to improve visibility.

[0355] The display device 700 shown in FIG. 28 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above-mentioned. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0356] Although not shown in FIG. 28, the conductive films 772 and 774 on the side in contact with the liquid crystal layer 776 In addition, although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Crites, sidelights, etc. may also be used.

[0357] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0358] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in the liquid crystal layer. It has a short response time, is optically isotropic so no alignment treatment is required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. It is possible to prevent electrostatic damage caused by electrostatic discharge, and thus to prevent defects in liquid crystal display devices during the manufacturing process. Damage can be reduced.

[0359] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0360] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0361] In display devices using liquid crystal elements, image data is usually rewritten at 60 Hz or the like. However, since the off-state current of a transistor using an oxide semiconductor is extremely low, the write frequency For example, it is possible to reduce the write frequency to 15Hz or even 1H z. By reducing the write frequency, the power consumption can be reduced, for example. This has the effect of reducing

[0362] <Display device using light-emitting elements as display elements> A display device 700 shown in FIG. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. In the display device 700 shown in FIG. 29, the EL layer 786 of the light emitting element 782 emits light. By doing so, an image can be displayed.

[0363] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one of the electrodes of the display element. In the above, a conductive film that transmits light or a conductive film that reflects visible light can be used. Examples of conductive films that are transparent to visible light include indium (In), zinc (Zn), and ZnO. It is recommended to use a material containing one of the following elements: Zn (Zn) or tin (Sn). The reflective conductive film may be made of a material containing aluminum or silver. stomach.

[0364] In addition, in the display device 700 shown in FIG. 29, an insulating film is provided over the planarization insulating film 770 and the conductive film 784. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0365] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0366] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0367] (Embodiment 4) <Examples of problems that can be solved by one embodiment of the present invention> The problem that can be solved will be described with reference to FIG. 32 and FIG. 33. Specifically, When the liquid crystal element is driven with an AC voltage to prevent deterioration of the liquid crystal, This will explain the problem of eye fatigue that occurs when viewing a display device.

[0368] <<Configuration of display unit and pixel>> Block diagram of a display unit provided in a display device, FIG. 1 shows an equivalent circuit diagram of a pixel circuit and a schematic diagram of the transmittance-voltage characteristics of polarized light passing through a liquid crystal element. Shown in Figure 32.

[0369] FIG. 33 is a timing chart illustrating the operation of a pixel circuit included in a pixel portion of a display device. FIG.

[0370] Regarding the display device: The display unit 930 is a part of the display device. 31 (see FIG. 32(A)).

[0371] The pixel section 931 includes a plurality of pixels 931p, and a first drive signal (also called an S signal) is applied to each column of the pixels 931p. A plurality of signal lines S (S1 to Sx) that can supply a second The liquid crystal display has a plurality of scanning lines G (G1 to Gy) that can supply driving signals (also called G signals).

[0372] Each pixel 931p is connected to at least one of the scanning lines G and at least one of the signal lines S. It is being done.

[0373] In addition, a signal for selecting the pixel 931p for each row may be used as the G signal. An S signal including image gradation information or the like may be supplied to the pixel 931p.

[0374] The G driving circuit 932 can control the input of a G signal to the scanning line G. The S driving circuit 933 can control the input of a G signal to the scanning line G. You can control the input of S signals to S.

[0375] The pixel 931p illustrated here includes a liquid crystal element 935LC and the liquid crystal element 935LC. It has a pixel circuit 934 (see FIG. 32(B)).

[0376] The pixel circuit 934 is a transistor that can control the supply of an S signal to the liquid crystal element 935LC. It has a dial 934t.

[0377] The gate of the transistor 934t is electrically connected to one of the scan lines G. The first electrode (either the source or the drain) of the transistor 934t is connected to one of the signal lines S. The second electrode (the other of the source and drain) of the transistor 934t is electrically connected to ) is electrically connected to the first electrode of the liquid crystal element 935LC. The electrode 2 is electrically connected to a common line C.

[0378] The transistor 934t has a parasitic capacitance 934tc. The capacitance between the gate electrode and the source or drain and the capacitance between the gate electrode and the channel Includes the capacity to

[0379] In addition, the pixel circuit 934 holds a voltage between the first electrode and the second electrode of the liquid crystal element 935LC. The capacitor 934c may include a capacitor element 934c.

[0380] The transistor 934t receives a G signal at its gate electrode, and the liquid crystal element 935LC The input to the inverter can be controlled as a single switching element.

[0381] The liquid crystal element 935LC includes a first electrode, a second electrode, and a liquid crystal layer between the first electrode and the second electrode. The liquid crystal layer includes a liquid crystal material to which a voltage of

[0382] The transmittance of polarized light passing through the liquid crystal element 935LC depends on the alignment state of the liquid crystal molecules contained in the liquid crystal layer. The alignment state of the liquid crystal layer depends on the voltage applied between the first electrode and the second electrode of the liquid crystal element 935LC. Therefore, the voltage corresponding to the S signal, which contains the gradation information of the image, is applied to the liquid crystal. When provided between the first and second electrodes of the liquid crystal element 935LC, the liquid crystal element 935LC is transparent. The transmittance of the polarized light can be set according to the grayscale information.

[0383] <Characteristics of Liquid Crystal Elements> The transmittance of polarized light passing through a normally white type liquid crystal element and The relationship between the voltage applied to the liquid crystal element and the polarization is shown in FIG. The horizontal axis corresponds to the ratio of the electrical potential of the first electrode relative to the second electrode.

[0384] The transmittance of polarized light passing through a normally white liquid crystal element is determined by the ratio of the first electrode to the second electrode. When the voltage between them is zero, the transmittance is high, and when the voltage is increased, the transmittance decreases. When this element is used in a transmissive liquid crystal display device, when the voltage of the S signal is close to 0, the display will be white, and when it is large, the display will be white. Can display black.

[0385] It is known that applying a DC voltage to the liquid crystal layer of a liquid crystal element for a long period of time causes the liquid crystal element to deteriorate. To avoid this, the liquid crystal element must be driven with an AC voltage.

[0386] In order to maintain the transmittance of polarized light passing through the liquid crystal element at the transmittance Ta, the first voltage Vp of the second electrode must be The polarity of the pole can be switched to positive (potential +Va) or negative (potential -Va). In other words, the liquid crystal element may be driven using an AC voltage whose amplitude is kept constant.

[0387] <<How to drive the liquid crystal element>> The liquid crystal element 935LC of the pixel circuit 934 is driven by an AC voltage. This section explains how to drive the device.

[0388] The potential Vg of the G signal input to the gate electrode of the transistor 934t of the pixel circuit 934 and FIG. 33A shows a timing chart of the potential Vsa of the S signal input to the first electrode. FIG. 33B shows a timing chart of the potential Vs output from the second electrode. Note that the potential Vs is also a potential input to the first electrode of the liquid crystal element 935LC.

[0389] The S drive circuit 933 receives the secondary image signal and outputs the S signal. The secondary image signal may have the same amplitude as the primary image signal. The difference between the potential of the image signal and the reference potential Vsc can be set as the amplitude of the secondary image signal. The secondary image signal is a signal whose polarity is inverted for each successive frame.

[0390] The period from when one scanning line G provided in the pixel portion 931 is selected until when it is selected again is defined as 1 Therefore, the G signal is input to the gate electrode of the transistor 934t every frame. When the G signal is high, the potential Vg is VgH. When the signal is low, the potential Vg is VgL.

[0391] <<Feedthrough Occurrence>> The potential Vs of the second electrode of the transistor 934t is As a result, the voltage Vg input to the first electrode of the transistor 934t is This potential is different from the potential Vsa of the S signal (same as the potential of the secondary image signal). A period in which the potential is higher than the sub-potential Vsc by Vsa1 and a period in which the potential is lower by Vsa2. The secondary image signal is input to the S drive circuit, which generates an S signal with the same potential as the secondary image signal. This will be explained using an example where

[0392] In the first frame F1, the difference between the potential Vg of the gate electrode and the potential Vsa of the S signal is When the threshold voltage Vth of the transistor 934t is exceeded, the transistor 934t is turned on. The potential Vs rises to the potential Vsa.

[0393] After that, when the difference between the gate electrode potential Vg and the S signal potential Vsa becomes less than the threshold voltage Vth, , the transistor 934t is turned off, and the potential V The potential of the second electrode of the transistor 934t drops by ΔV1 from the potential Vsa of the S signal. The amount by which the potential Vs drops from the potential Vsa of the S signal is defined as a first feedthrough ΔV1. .

[0394] In the second frame F2, the secondary image signal with the polarity inverted is input to the S driver circuit 933. The difference between the potential Vg and the potential Vsa of the S signal is the threshold voltage Vth of the transistor 934t. When the voltage Vcc exceeds the threshold voltage Vcc, the transistor 934t is turned on and the second electrode of the transistor 934t is The potential Vs of the S signal drops to the potential Vsa of the S signal.

[0395] After that, when the difference between the gate electrode potential Vg and the S signal potential Vsa becomes less than the threshold voltage Vth, , the transistor 934t is turned off, and the potential V The potential Vs of the second electrode of the transistor 934t drops by ΔV2 from the potential Vsa. The amount of drop from the potential Vsa is the second feedthrough ΔV2.

[0396] <About the size of the feedthrough> The feedthrough is the parasitic capacitance of the transistor 934t. This occurs due to capacitive coupling caused by quantity 934tc (see FIG. 32(B)). The magnitude ΔV of the current can be predicted using the following formula (3). LH is the gate voltage The amplitude of the potential of the electrodes (the difference between VgH and VgL), CL is the capacitance of the liquid crystal element 935LC, and Cs is the capacitance The capacitance, Cdg, of element 934c is the parasitic capacitance 934tc of transistor 934t.

[0397]

number

[0398] <<Asymmetry of the feedthrough size>> The gate electrode of transistor 934t is The G signal input is not a perfect square wave. For example, the G signal is a square wave with a shorter upper base than the lower base. When the potential Vs of the input S signal is low, the potential Vs of the S signal is high. The time that the transistor 934t is in the on state is increased. This causes the value of Cdg to increase. Since the second feedthrough ΔV2 varies depending on the effect of the capacitance of the V1, and the size of the first feedthrough ΔV1 and the second feedthrough ΔV2 The size becomes asymmetric.

[0399] By keeping the waveform of the G signal constant, the first feedthrough ΔV1 and the second feedthrough The feedthrough value is input even if the magnitude of the feedthrough ΔV2 becomes asymmetric. This can be predicted for each potential of the S signal.

[0400] 《Effect of feedthrough on the transmittance of polarized light passing through a liquid crystal element》 Amplitude is constant When a liquid crystal element is driven using an AC voltage maintained at is kept constant.

[0401] However, when feedthrough occurs in the pixel circuit, the transmission of polarized light passing through the liquid crystal element The rate does not remain constant.

[0402] The first feedthrough ΔV1 is a difference between the potential Vs of the second electrode of the transistor 934t and the reference potential Vs. The second feedthrough also acts to reduce the difference |Vs-Vsc| between the power supply voltages Vsc and Vs-Vsc. ΔV2 is the difference between the potential Vs of the second electrode of the transistor 934t and the reference potential Vsc |Vs- Vsc| increases (see FIG. 33(C)).

[0403] As a result, when the liquid crystal element 935LC is a normally white type, the liquid crystal element 935L The transmittance of polarized light passing through C is higher than the transmittance Ta in the first frame F1 by ΔT1. In the second frame F2, the transmittance becomes lower than Ta by ΔT2 (see FIG. 3). 3(D)). The common potential Vcom is a common potential input to the second electrode of the liquid crystal element 935LC. This potential is equal to the reference potential Vsc.

[0404] As a result, the transmittance of polarized light passing through the liquid crystal element 935LC of the display unit of the display device changes (specifically, In practical terms, this change is equivalent to the sum of ΔT1 and ΔT2, and flicker is observed.

[0405] Normally, this effect is made invisible by adjusting the common potential. If the capacitor is turned on, flicker may be observed. However, this would affect the aperture ratio, so we decided to use a larger If the impact of the feed-through itself is kept small, the impact itself is less likely to be noticeable.

[0406] <<About eye fatigue>> There is nervous system eye fatigue.

[0407] Nervous system fatigue can be caused by staring at the light emitted by the display or a flashing screen for a long period of time, and the brightness of the screen can also be a cause of fatigue. It stimulates the retina, nerves, or brain, causing fatigue. The phenomenon in which the display part blinks rapidly is called flicker, and this type of flicker is a symptom of nervous system fatigue. causes labor.

[0408] As described above, when an AC voltage is applied to the liquid crystal element to prevent deterioration of the liquid crystal element, This causes flicker due to the loop, which causes eye fatigue for the user of the display device. .

[0409] The transistor described in the first embodiment has a small parasitic capacitance and a high field-effect mobility. By using this high-performance transistor with low parasitic capacitance, As described in the embodiment, various defects caused by feedthroughs can be reduced. It is possible to do this.

[0410] (Embodiment 5) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0411] The display device shown in FIG. 30A has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0412] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0413] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0414] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0415] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0416] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0417] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0418] The protection circuit 506 shown in FIG. 30(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0419] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0420] As shown in FIG. 30A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge or the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be done like this.

[0421] In FIG. 30A, the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0422] In addition, the pixel circuits 501 shown in FIG. 30(A) may be, for example, a configuration shown in FIG. It can be said that:

[0423] The pixel circuit 501 shown in FIG. 30B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0424] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0425] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0426] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G L_m. The transistor 550 can be turned on or off. Thus, the write control circuit 100 has a function of controlling the writing of data of the data signal.

[0427] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0428] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0429] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0430] In addition, the pixel circuits 501 shown in FIG. 30(A) may have a configuration shown in FIG. It can be said that:

[0431] The pixel circuit 501 shown in FIG. 30C includes transistors 552 and 554 and a capacitance element. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0432] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 5 is electrically connected to a wiring (hereinafter, referred to as a data line DL_n). The gate electrode 52 is connected to a wiring (hereinafter, referred to as a scanning line GL_m) to which a gate signal is applied. are electrically connected.

[0433] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0434] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0435] The capacitor 562 functions as a storage capacitor for storing written data.

[0436] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0437] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0438] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0439] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0440] In a display device having the pixel circuit 501 shown in FIG. 30C, for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0441] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0442] In the region 580 where the GL_m line and the DL_n line overlap each other as shown in FIG. Capacity C GD Similar to the parasitic capacitance of a transistor, the parasitic capacitance C GD If it is large, Since the rise time is slow, it becomes difficult to increase the panel size of the display device. Therefore, it is preferable to reduce the capacitance between the GL_m line and the DL_n line.

[0443] Usually, an insulating layer is formed between the GL_m line and the DL_n line in the same process as the first gate insulating layer. There are a film 106 and an insulating film 107. Therefore, an insulating film is formed between the GL_m line and the DL_n line. 106 and insulating film 107 are inserted to further increase the thickness of the insulating film. is preferable because it is possible to reduce the parasitic capacitance of the transistor.

[0444] FIG. 31(A) shows a top view of the vicinity of region 580 in FIG. 30(B) and (C). A cross-sectional view of Z1-Z2 of A) is shown in FIG. 31(B). For example, as shown in FIG. 31(A) and (B), As shown in FIG. 1, the insulating film 106, the insulating film 107, and the insulating film 121 are formed between the GL_m line and the DL_n line. In this laminated structure, the insulating film 106 and the insulating film 107 are between the GL_m line and the DL_n line. The thickness of the insulating film between the GL_m line and the DL_n line is thicker than that in the case of only one line. Parasitic capacitance C between DL_n lines GD Also, the parasitic capacitance C GD To reduce For this reason, it is preferable to use a material with a low dielectric constant for the insulating film 121 .

[0445] The insulating film 121 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or an aluminum oxide film. Aluminum film, aluminum oxide nitride film, aluminum nitride oxide film, aluminum nitride film, etc. etc. can be used.

[0446] The insulating film 121 is formed by a sputtering method, a CVD method (thermal CVD method, MOCVD method, PECVD method, etc. The method may be, for example, an MBE method, an ALD method, or a PLD method. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, the insulating film has excellent coating properties. In addition, in order to reduce damage caused by plasma, The CVD method, the MOCVD method or the ALD method is preferred.

[0447] Also, a silicon carbonitride film (SiCN film) can be used as the insulating film 121. USG (Undoped Silicate Glass), BPSG (Boron Phosphorus Silicate Glass), BSG (Borosili USG, BPSG, etc. can be used by the atmospheric pressure CVD method. For example, HSQ (hydrogen silsesquioxane) or the like may be used as the coating material. It may be formed using

[0448] The insulating film 121 may be a laminate of two or more layers. Alternatively, a USG may be laminated on the insulating film.

[0449] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0450] (Embodiment 6) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be described with reference to Figs. 34, 35 and 36.

[0451] The display module 8000 shown in FIG. 34 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, A display panel 8006, a backlight 8007, a frame 8009, and a printed circuit board 801 0, has battery 8011.

[0452] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0453] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 8006.

[0454] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0455] The backlight 8007 has a light source 8008. In FIG. In the above embodiment, the light source 8008 is disposed on the light source 8007, but the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 8007 need not be provided.

[0456] The frame 8009 protects the display panel 8006 and also supports the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 8009 may also function as a heat sink.

[0457] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. , this can be omitted when using a commercial power source.

[0458] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0459] 35(A) to 35(G) are diagrams showing electronic devices. These electronic devices are housed in a housing. A body 9000, a display unit 9001, a speaker 9003, and operation keys 9005 (power switch, etc.) includes an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed, Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electricity Measures field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays The device may have a built-in microphone 9008, etc.

[0460] The electronic devices illustrated in FIGS. 35A to 35G can have various functions. For example, the function to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software ( A function to control processing by a program, wireless communication function, and various functions using wireless communication function Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and displaying the program or data. The function of displaying the information on the display unit can be provided. The functions that the electronic device shown in the figure can have are not limited to these, and the electronic device may have a variety of functions. Although not shown in Figs. 35(A) to 35(G), the electronic device may include The electronic device may have a plurality of display units. The function to take pictures, record videos, and store the images on a recording medium (external or built-in to the camera) ) and a function for displaying the captured image on a display unit.

[0461] The electronic devices shown in FIGS. 35A to 35G will be described in detail below.

[0462] FIG. 35A is a perspective view showing a portable information terminal 9100. The display unit 9001 has flexibility. The display unit 9001 can be incorporated along the screen. The device is equipped with a touch sensor, and can be operated by touching the screen with a finger or a stylus. By touching the icon displayed on the display 9001, the application can be started. can.

[0463] FIG. 35B is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, the mobile information terminal 9101 can be used as a smartphone. Although the speaker 9003, the connection terminal 9006, the sensor 9007, etc. are omitted in the figure, It can be installed in the same position as the mobile information terminal 9100 shown in FIG. The information terminal 9101 can display text and image information on multiple surfaces. For example, Three operation buttons 9050 (also called operation icons or simply icons) are displayed on the display unit 900. The information 9051 shown in the dashed rectangle can be displayed on one side of the display unit 90. 01. An example of the information 9051 is an e-mail Displays to notify you of incoming calls, SNS (social networking services), etc. , subject of email or SNS, sender name of email or SNS, date and time, time, Battery level, antenna reception strength, etc. Or, information 9051 is displayed. Instead of the information 9051, an operation button 9050 or the like may be displayed at that position.

[0464] FIG. 35C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 holds the portable information terminal 9102 in the breast pocket of the clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed on the mobile information terminal 9102 so that it can be observed from above. The user can read the display without taking the mobile information terminal 9102 out of his pocket. You can check the number and decide whether to answer the call or not.

[0465] 35(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is used for mobile phone calls, e-mail, document browsing and writing, music playback, and Internet communications. It is possible to execute various applications such as computer games. The display unit 9001 has a curved display surface, and displays information along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. Power may also be supplied wirelessly without going through 6.

[0466] 35(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 35(E) is a perspective view of the portable information terminal 9201 in an unfolded state. (F) shows the mobile information terminal 9201 being changed from one of the unfolded and folded states to the other. FIG. 35(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded and is unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. The portable information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0467] 36(A) to 36(G) are diagrams showing electronic devices. These electronic devices are housed in a housing. A body 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, and an operation key 50 05 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 ( Force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances , sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, 5008, etc.) can.

[0468] FIG. 36(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc. FIG. 36(B) shows a mobile phone equipped with a recording medium. A portable image reproducing device (e.g., a DVD reproducing device) and, in addition to the above, the following devices are also included: The display unit 5002, the recording medium reading unit 5011, etc. In addition to the above, the display includes a second display unit 5002 and a support unit 5012. , earphones 5013, etc. FIG. 36(D) shows a portable game machine. In addition to the above, the recording medium reading unit 5011 and the like can be included. This is a digital camera with a television receiving function, and in addition to the above, it also has an antenna 5014, The mobile phone may have a shutter button 5015, an image receiving unit 5016, etc. This is a slot machine, and in addition to the above, it has a second display unit 5002, a recording medium reading unit 5011, , etc. FIG. 36(G) shows a portable television receiver, In addition to the above, it may have a charger 5017 capable of transmitting and receiving signals, etc.

[0469] The electronic devices shown in Figures 36(A) to 36(G) can have various functions. For example, the function to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software (platform A function to control processing by a program, a wireless communication function, and a function to control various Functions for connecting to computer networks, wireless communication functions for transmitting various data, The function of receiving, reading out the program or data recorded on the recording medium and displaying it on the display Furthermore, in an electronic device having multiple display units, In this case, one display section is used mainly to display image information, and the other display section is used mainly to display text information. A function to display images with parallax taken into account on multiple displays to create a stereoscopic effect. Furthermore, in electronic devices having an image receiving unit, These include functions for taking still images, taking videos, and automatically or manually correcting the images. The camera has a function to correct the captured image, a function to save the captured image on a recording medium (external or built-in to the camera), The image displayed on the display unit can have a function of displaying the image. The functions that the electronic device shown in 6(G) can have are not limited to these, and various functions may be included. It is possible to have.

[0470] The electronic device described in this embodiment has a display unit for displaying some information. The display device described in the embodiment 5 can be used for the display portion. do.

[0471] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. This can also be applied to vessels.

[0472] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0473] (Embodiment 7) <Memory Device> A memory device in which power is supplied using a transistor according to one embodiment of the present invention. A semiconductor device that can retain memory contents even when data is not written to it and that has no limit on the number of times it can be written to. An example of the device (memory device) is shown in FIG. 40. Note that FIG. 40(B) is a circuit diagram of FIG. 40(A). This is what was done.

[0474] The semiconductor device shown in FIGS. 40A and 40B includes a transistor 3 using a first semiconductor material. 200, a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that the transistor described in Embodiment 1 is used as the transistor 3300. It can be used.

[0475] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-state current of the transistor 3300 is small, This means that the memory contents can be retained for a long period of time without requiring a refresh operation. Alternatively, the frequency of refresh operations can be extremely low. This makes it possible to sufficiently reduce power consumption.

[0476] In FIG. 40B, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode and the drain electrode of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is connected to a capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0477] In the semiconductor device shown in FIG. 40A, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0478] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is provided with A given charge is applied (write). Here, the charge is applied to two different potential levels. (hereinafter referred to as low-level charge and high-level charge) After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 is turned on. The charge applied to the port electrode is retained (retained).

[0479] Since the off-state current of the transistor 3300 is extremely small, the gate voltage of the transistor 3200 The charge on the pole is retained for a long period of time.

[0480] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the transistor According to the amount of charge held in the gate electrode of transistor 3200, the second wiring 3002 assumes different potentials. Generally, if transistor 3200 is an n-channel type, the apparent threshold value Vth_H when a high-level charge is applied to the gate electrode of transistor 3200 is lower than the apparent threshold value Vth_L when a low-level charge is applied to the gate electrode of transistor 3200. Here, the apparent threshold voltage is defined as the potential of the fifth wiring 3005 required to turn transistor 3200 into the "on state". Therefore, by setting the potential of the fifth wiring 3005 to a potential V0 between Vth_H and Vth_L, the charge applied to the gate electrode of transistor 3200 can be discriminated. For example, in writing, if a high-level charge was applied, when the potential of the fifth wiring 3005 becomes V0 (> Vth_H), transistor 3200 enters the "on state". If a low-level charge was applied, even when the potential of the fifth wiring 3005 becomes V0 (< Vth_L), transistor 3200 remains in the "off state". Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out. When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. For example, in a memory cell where information is not read, a potential such that transistor 3200 enters the "off state" regardless of the gate state, that is, a potential lower than Vth_H, is applied to the fifth wiring 3005 so that only the information of the desired memory cell can be read. Or, in a memory cell where information is not read, the gate Regardless of the state, a configuration may be adopted in which a potential that causes transistor 3200 to be in the "off state", that is, a potential lower than Vth_H, is applied to the fifth wiring 3005 so that only the information of the desired memory cell can be read. Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out. When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell.

[0481] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. For example, in a memory cell where information is not read, a potential such that transistor 3200 is in the "off state" regardless of the gate state, that is, a potential lower than Vth_H, is applied to the fifth wiring 3005 so that only the information of the desired memory cell can be read. Or, in a memory cell where information is not read, a potential such that transistor 3200 is in the "off state" regardless of the gate state, that is, a potential lower than Vth_H, is applied to the fifth wiring 3005 so that only the information of the desired memory cell can be read. Regardless of the state, a potential such that transistor 3200 is in the "off state", that is, a potential lower than Vth_H, is applied to the fifth wiring 3005 so that only the information of the desired memory cell can be read. By applying a potential lower than Vth_H to the fifth wiring 3005, only the information of the desired memory cell can be read. Or, in a memory cell where information is not read, a potential such that transistor 3200 is in the "off state" regardless of the gate state, that is, a potential lower than Vth_H, is applied to the fifth wiring 3005 so that only the information of the desired memory cell can be read. The potential at which transistor 3200 is “on” regardless of the state of the gate, i.e. By applying a potential higher than Vth_L to the fifth wiring 3005, the information of the desired memory cell is It is sufficient to have a configuration in which only the information can be read out.

[0482] The semiconductor device shown in FIG. 40(C) is different from the semiconductor device shown in FIG. 40(A) in that the transistor 3200 is not provided. In this case, the writing and holding of information is performed in the same manner as above. It is possible.

[0483] Next, reading of data from the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor element 3400, which are in a floating state, becomes conductive, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, The amount of change in the potential of the third wiring 3003 is determined by the capacitance element. The potential of one of the electrodes of the capacitor 3400 (or the charge stored in the capacitor 3400) It takes different values.

[0484] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of the memory cell 250 is If the potential of one of the electrodes of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0485] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0486] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be laminated on the driver circuit.

[0487] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0488] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0489] The storage device shown in this embodiment is, for example, a CPU (Central Processing g Unit), DSP (Digital Signal Processor), LSI, PLD (Programmable Logic Device) etc. I, RF-ID (Radio Frequency Identification) can also be applied.

[0490] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0491] (Embodiment 8) In this embodiment, an RF device including the transistor or memory device described in the above embodiment will be The device tag will be explained with reference to FIG.

[0492] The RF device tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. The sensor stores information about the sensor and transmits and receives information to and from the outside using a non-contact means, such as wireless communication. Due to these characteristics, RF device tags can identify objects by reading their individual information. It can be used for individual authentication systems to identify products. Extremely high reliability is required for this use.

[0493] The configuration of the RF device tag will be described with reference to FIG. 41. FIG. 41 shows the configuration of the RF device tag. FIG. 2 is a block diagram showing a configuration example of the

[0494] As shown in FIG. 41, an RF device tag 800 includes a communicator 801 (an interrogator, a reader / writer, 803 is received from an antenna 802 connected to The RF device tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, demodulation circuit 807, modulation circuit 808, logic circuit 809, memory circuit 810, ROM8 11. Note that the transistor having a rectifying effect included in the demodulation circuit 807 has a reverse polarity. A material capable of sufficiently suppressing the inverse current, for example, an oxide semiconductor, is used. This can suppress the deterioration of the rectification caused by the reverse current, and the output of the demodulation circuit can be In other words, the output of the demodulation circuit is linearly proportional to the input of the demodulation circuit. The data transmission format is a pair of coils arranged facing each other and mutual induction is performed. The electromagnetic coupling method uses induction to communicate, the electromagnetic induction method uses an induced electromagnetic field to communicate, and the The RF device tag 8 shown in this embodiment is 00 can be used in either method.

[0495] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side of the rectifier circuit 805. A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent a certain amount of power from being input to the downstream circuit. This is a circuit for controlling the

[0496] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0497] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit that performs modulation based on the

[0498] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0499] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0500] Here, the memory cell described in the above embodiment can be used for the memory circuit 810. Memory cells using oxide semiconductors can retain data even when the power supply is cut off. Therefore, it can be suitably used for RF device tags. The power (voltage) required to write data to a memory cell is significantly higher than that of conventional non-volatile memory. Since the size is so small, there is no difference in the maximum communication distance when reading and writing data. Furthermore, when writing data, there may be a shortage of power, which may cause malfunction or erroneous writing. This can prevent the occurrence of such problems.

[0501] In addition, a memory cell using an oxide semiconductor can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data to the memory, so that users cannot freely rewrite it. It is preferable to have the manufacturer write the unique number on the product before shipping it. By doing so, instead of assigning a unique number to each RF device tag produced, This allows the allocation of unique numbers only to good products, and prevents the unique numbers of products from becoming inaccurate after shipment. This avoids continuity and facilitates customer management of products after shipment.

[0502] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0503] (Embodiment 9) In this embodiment, at least the transistors described in the embodiment can be used. A CPU including the storage device described in the above embodiment will be described.

[0504] FIG. 42 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 1 is a block diagram showing a configuration of an example.

[0505] The CPU shown in FIG. 42 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, etc. A glass substrate or the like is used. The ROM 1199 and the ROM interface 1189 are Of course, the CPU shown in FIG. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, The configuration including the CPU or arithmetic circuit shown in FIG. 42 is regarded as one core, and includes multiple such cores, The cores may be configured to operate in parallel. The number of bits that can be handled by the data bus is, for example, 8 bits, 16 bits, 32 bits, and 64 bits. It can be, for example,

[0506] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0507] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0508] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by the internal clock generator 100. Supply to the seed circuit.

[0509] In the CPU shown in FIG. 42, a register 1196 is provided with a memory cell. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0510] In the CPU shown in FIG. 42, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0511] FIG. 43 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. The semiconductor device may further include other elements such as a capacitor.

[0512] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the gate of the transistor 1209 is connected through a load such as a resistor. The configuration will be based on the above.

[0513] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., traction) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0514] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection portion is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply potential. The other is electrically connected to a wiring (e.g., a GND line) that can supply a 203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) The first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ) is electrically connected to the second terminal of the switch 1204 (the source of the transistor 1214). The other of the source and drain is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214). The input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207 are The connection point is referred to as a node M1. The other of the electrodes may be configured to have a constant potential input thereto. For example, A potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1207 is a wiring that can supply a low power supply potential. (for example, a GND line) is electrically connected to the other of the pair of electrodes of the capacitor 1208. For example, a low power supply potential (GND, etc.) can be input to the Alternatively, a high power supply potential (such as VDD) can be input. The other of the pair of electrodes is a wiring that can supply a low power supply potential (for example, a GND line ) is electrically connected to

[0515] The capacitors 1207 and 1208 are formed by accumulating parasitic capacitances of transistors and wirings. It is possible to omit it by using it in an extreme manner.

[0516] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD that is different from the control signal WE. Thus, a conductive state or a non-conductive state between the first terminal and the second terminal is selected, and one of the switches When the first and second terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a conductive state. There is no continuity between the terminals.

[0517] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 43, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0518] In FIG. 43, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is fed to the logic element 1206 and the circuit 1220. 1201 is shown as an example, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted in logic value. For example, the input may be input to the circuit 1201 without being If there is a node that holds a signal with the logic value of the signal input from the input terminal inverted, , the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0519] In addition, in FIG. 43, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. 0. For example, a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed of oxide semiconductor films. Alternatively, the memory element 1200 may include any other element other than the transistor 1209. The other transistors may include a transistor in which a channel is formed using an oxide semiconductor film. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor that is connected to the gate of the transistor.

[0520] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0521] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0522] Further, a transistor in which a channel is formed in an oxide semiconductor film has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 1 Even when the power supply voltage is not supplied to 200, the signal held in the capacitance element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0523] In addition, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above, the circuit 1201 is restored to its original state after the power supply voltage is resumed. This can shorten the time it takes to re-store the data.

[0524] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal can be read out accurately.

[0525] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0526] In this embodiment, the memory element 1200 is used as a CPU. The 200 is equipped with a DSP (Digital Signal Processor), custom L SI, PLD (Programmable Logic Device) and other LSIs, R Also applied to F-ID (Radio Frequency Identification) It is possible.

[0527] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0528] (Embodiment 10) <Imaging Apparatus> Hereinafter, an imaging apparatus according to one aspect of the present invention will be described.

[0529] 44(A) is a plan view showing an example of an imaging device 2000 according to one embodiment of the present invention. The device 2000 includes a pixel section 2010 and a peripheral circuit 2060 for driving the pixel section 2010. 20, a peripheral circuit 2070, a peripheral circuit 2080, and a peripheral circuit 2090. 010 is a set of multiple pixels arranged in a matrix of p rows and q columns (p and q are integers of 2 or greater). The peripheral circuit 2060, the peripheral circuit 2070, the peripheral circuit 2080, and the peripheral The side circuits 2090 are connected to the plurality of pixels 2011, respectively, and drive the plurality of pixels 2011. In this specification, the peripheral circuit 2060 has a function of supplying a signal to the peripheral circuit 2060. The peripheral circuits 2070, 2080, and 2090 are all referred to as "peripheral circuits." For example, the peripheral circuit 2060 may be one of the peripheral circuits. It can be said to be a department.

[0530] The imaging device 2000 preferably includes a light source 2091. It is possible to emit an outgoing light P1.

[0531] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the same substrate as the pixel portion 2010. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits are the peripheral circuit 2060, the peripheral circuit 2070, the peripheral circuit 2080, and the peripheral circuit One or more of the paths 2090 may be omitted.

[0532] As shown in FIG. 44B, in a pixel unit 2010 of the imaging device 2000, The pixel 2011 may be arranged at an angle. This allows the pixel interval (pitch) in the vertical and column directions to be shortened. This can improve the quality of the image captured at 000.

[0533] <Example of pixel configuration> One pixel 2011 of the imaging device 2000 is divided into a plurality of sub-pixels 2012 Each subpixel 2012 is provided with a filter (color By combining these filters, it is possible to obtain information necessary to realize a color image display. can be done.

[0534] FIG. 45(A) is a plan view showing an example of a pixel 2011 for acquiring a color image. The pixel 2011 shown in FIG. 45(A) is a color filter that transmits light in the red (R) wavelength band. A subpixel 2012 (hereinafter also referred to as "subpixel 2012R") having a green (G) wavelength A subpixel 2012 (hereinafter, “subpixel 201”) is provided with a color filter that transmits light in the The color filters transmit light in the blue (B) and red (C) wavelength bands. The subpixel 2012 (hereinafter also referred to as "subpixel 2012B") is It can function as a photosensor.

[0535] The subpixels 2012 (subpixel 2012R, subpixel 2012G, and subpixel 2012B) are Electrically connected to the wiring 2031, the wiring 2047, the wiring 2048, the wiring 2049, and the wiring 2050 In addition, the subpixels 2012R, 2012G, and 2012B are connected to each other. Each of them is connected to an independent wiring 2053. The wiring 2048 and the wiring 2049 connected to the eye pixel 2011 are respectively connected to the wiring 204 8[n] and wiring 2049[n]. The connected wiring 2053 is described as wiring 2053[m]. , a wiring 2053 connected to a sub-pixel 2012R of the pixel 2011 in the mth column is connected to a wiring 205 3[m]R, the wiring 2053 connected to the subpixel 2012G is the wiring 2053[m]G, and The wiring 2053 connected to the subpixel 2012B is indicated as wiring 2053[m]B. The element 2012 is electrically connected to the peripheral circuits via the wiring.

[0536] In addition, the imaging device 2000 has color filters 2011 that transmit light of the same wavelength band. The sub-pixels 2012 provided with filters are electrically connected to each other via switches. FIG. 45(B) shows a matrix with n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). The pixel 2011 has a sub-pixel 2012 arranged in the pixel 2011 (n number of pixels) and the sub-pixel 2012 adjacent to the pixel 2011 An example of a connection of the sub-pixel 2012 of the pixel 2011 arranged in the +1 row and the m column is shown in FIG. In B), the subpixel 2012R arranged in the nth row and the mth column and the subpixel 2012R arranged in the n+1th row and the mth column are A pixel 2012R is connected via a switch 2001. The subpixel 2012G arranged in the n+1th row and the mth column is connected to the switch 2002. In addition, the sub-pixel 2012B arranged in the nth row and the mth column is connected via The sub-pixels 2012B arranged in a column are connected via switches 2003.

[0537] The color filters used for the subpixel 2012 are limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A filter may be used. A single pixel 2011 may have three sub-pixels for detecting light of different wavelength bands. By providing the pixels 2012, a full color image can be obtained.

[0538] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the subpixel 2012, a color filter that transmits yellow (Y) light is provided. Alternatively, a pixel 2011 having a subpixel 2012 may be used. A subpixel 201 provided with a color filter that transmits yellow (Y) and magenta (M) light. In addition to the pixel 2, the pixel 2012 has a color filter that transmits blue (B) light. A pixel 2011 that detects light of four different wavelength bands may be used. By providing a sub-pixel 2012 that outputs a different color, it is possible to further improve the color reproducibility of the captured image. can.

[0539] Also, for example, in FIG. 45A, a subpixel 2012 for detecting the red wavelength band and a subpixel 2013 for detecting the green wavelength band are A subpixel 2012 for detecting the long wavelength band and a subpixel 2012 for detecting the blue wavelength band The ratio of the number of pixels (or the ratio of the light receiving areas) does not have to be 1:1:1. The area ratio may be a Bayer array with red:green:blue=1:2:1. The ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0540] The number of sub-pixels 2012 provided in the pixel 2011 may be one, but it is preferable that the number is two or more. For example, by providing two or more sub-pixels 2012 that detect the same wavelength band, redundancy can be increased. The reliability of the imaging device 2000 can be improved.

[0541] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 2000 that detects infrared light.

[0542] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0543] In addition to the above-mentioned filters, a lens may be provided in the pixel 2011. An example of the arrangement of the pixel 2011, the filter 2054, and the lens 2055 will be described with reference to the cross-sectional view of FIG. By providing the lens 2055, the photoelectric conversion element can efficiently receive the incident light. Specifically, as shown in FIG. 46(A), a lens 2055 formed in a pixel 2011 , filter 2054 (filter 2054R, filter 2054G and filter 2054 B), and light 2056 is incident on the photoelectric conversion element 2020 through the pixel circuit 2030, etc. The structure can be such that

[0544] However, as shown in the area surrounded by the dashed line, a part of the light 2056 indicated by the arrow is connected to the wiring 205 7 may block the light. Therefore, as shown in FIG. A lens 2055 and a filter 2054 are arranged on the photoelectric conversion element 2020 side. The element 2020 is preferably configured to efficiently receive the light 2056. By making light 2056 incident on the photoelectric conversion element 2020 from the side, an imaging device with high detection sensitivity is obtained. 2000 can be provided.

[0545] As the photoelectric conversion element 2020 shown in FIG. 46, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0546] The photoelectric conversion element 2020 is made of a material that absorbs radiation and generates electric charges. The material having the function of absorbing radiation and generating electric charges may be, for example, Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy There is gold etc.

[0547] For example, if selenium is used in the photoelectric conversion element 2020, in addition to visible light, ultraviolet light, and infrared light, A photoelectric conversion element that has an optical absorption coefficient over a wide wavelength range, including X-rays and gamma rays. 2020 can be achieved.

[0548] Here, one pixel 2011 included in the imaging device 2000 is a sub-pixel 2012 shown in FIG. In addition, it may have a subpixel 2012 having a first filter.

[0549] <Structural example of an imaging device> Fig. 47 is a cross-sectional view of an element constituting an imaging device. The imaging device includes a layer 621, a layer 620 provided on the layer 621, and a The layer 621 includes the transistor 491 disposed on the substrate 400, and a photodiode 2360 disposed on the substrate 400. The transistor 490 and the transistor 490b are The transistor described in Embodiment 1 can be used as the transistor 490b.

[0550] The photodiode 2360 of the imaging device has two electrodes 2361 and 2362. The electrode 2362 has a conductive layer 312 in the layer 621 and a semiconductor layer sandwiched between the conductive layer 312 in the layer 621. The conductive layer 313b is connected to the conductive layer 343b of the layer 620 through the conductive layer 313b. The conductive layer 313b is in contact with at least a part of the top and side surfaces of the protrusions of the conductive layer 313b. 622 and the conductive layer 416b of the transistor 490 through the conductive layer 344b, etc. In addition, a part of the conductive layer 313b is preferably in contact with the upper surface of the insulating film 371. .

[0551] The electrode 2361 includes a conductive layer 341c provided on the upper portion of the low resistance layer 2363, and a layer Through other wiring layers such as the conductive layer 312c of the layer 621, the conductive layer 343e of the layer 620 The conductive layer 313e is connected to at least the top and side surfaces of the protrusion of the conductive layer 343e. The conductive layer 313e is in contact with a part of the layer 622 through the conductive layer 344c and the like. The conductive layer 313e is connected to another wiring layer of the insulating film 322. It is preferable that it contacts the upper surface of 71.

[0552] The conductive layers 313b and 313e are the conductive layer 313, and the conductive layers 343b and 343e are the conductive layers 343b and 343e. For details, the description of the conductive layer 343 can be referred to.

[0553] In the example of the cross-sectional view shown in FIG. 47, a transistor 491 is formed on a substrate 400. The light receiving surface of the photodiode 2360 is disposed on the opposite side to the surface that is exposed. This makes it possible to ensure an optical path without being affected by various transistors and wiring. Therefore, it is possible to form a pixel with a high aperture ratio. Alternatively, the light receiving surface of the transistor 491 may be the same as the surface on which the transistor 491 is formed.

[0554] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. EXAMPLES

[0555] In this embodiment, the transistor 100 shown in FIG. 1 and the transistor 100 shown in FIG. A transistor equivalent to 71 was fabricated and its Id-Vg characteristics were evaluated. Ta.

[0556] In this example, the following samples A1 and A2 were prepared and evaluated. Samples A1 and A2 are samples according to one embodiment of the present invention. Sample A1 is The sample A1 is a transistor having one gate electrode, and the sample A2 is a transistor having two gate electrodes. It is a ninja.

[0557] The structure of the transistor shown in this embodiment will be described with reference to FIG. 37. FIG. 37(A) shows 37A is a top view of the transistor 100, and FIG. 37B is a top view of the transistor 171. The length 123 of the gate electrode of A1 and A2 was set to 6 μm. The distance 122a ( In this specification, the offset length of the source electrode is sometimes referred to as the "offset length of the source electrode." The distance 12 between the conductive film 112b functioning as the first gate electrode and the conductive film 104 functioning as the second gate electrode is 2b (sometimes referred to as the "drain offset length" in this specification) is set to 1.5 μm. The width 124 of the oxide semiconductor film 108 was set to 10 μm.

[0558] The samples A1 and A2 prepared in this example will be described below. In the above, the transistor 100 shown in FIG. 1 and the transistor 171 shown in FIG. In the fabrication process, the sample A1 was not fabricated, and the sample A2 was fabricated. There is a process that is performed only on the above.

[0559] <Method of Manufacturing Samples A1 and A2> First, a conductive film 104 was formed on a substrate 102. A glass substrate was used as 102. The size of the glass substrate was 600 mm. The conductive film 104 was 100 nm thick. The tungsten film was formed using a sputtering device.

[0560] Next, insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the substrate 6, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. In addition, as the insulating film 107, a silicon oxynitride film having a thickness of 50 nm was formed by using a PECVD apparatus. It was formed by

[0561] The conditions for forming the insulating film 106 were a substrate temperature of 350° C. and a flow rate of 200 sccm. Run gas, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm The pressure was set to 100 Pa, and the parallel flat plate installed in the PECVD device was A 2000W RF power was supplied between the electrodes of the plate to form a silicon nitride film with a thickness of 50nm. Next, the flow rate of ammonia gas was changed to 2000sccm, and a nitride silicon layer with a thickness of 300nm was formed. Then, the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 50 A silicon nitride film with a thickness of nm was formed.

[0562] The conditions for forming the insulating film 107 are a substrate temperature of 350° C. and a flow rate of 20 sccm. Silane gas at a flow rate of 3000 sccm and nitrous oxide gas at a flow rate of 3000 sccm were introduced into the chamber, and the pressure The pressure was set to 40 Pa, and an RF power of 100 W was applied between the parallel plate electrodes installed in the PECVD device. A force was applied to deposit the film.

[0563] Next, the oxide semiconductor film 108 was formed over the insulating film 107. A first oxide semiconductor film 108a on the conductive film 104 side functioning as a first gate electrode and a second oxide semiconductor film 108b on the conductive film 104 side functioning as a first gate electrode The first oxide semiconductor film 108a and the second oxide semiconductor film 108b were stacked on each other. In addition, an IGZO film having a thickness of 10 nm is formed as the first oxide semiconductor film 108a. As the second oxide semiconductor film 108b, an IGZO film having a thickness of 15 nm was formed.

[0564] Note that the first oxide semiconductor film 108a was formed under the following conditions: the substrate temperature was 170° C. Argon gas with a flow rate of 140 sccm and oxygen gas with a flow rate of 60 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:G The film was formed by applying 2500 W of AC power to a mixture of Zn and Fe (a:Zn=4:2:4.1 [atomic ratio]).

[0565] The second oxide semiconductor film 108b was formed under the following conditions: the substrate temperature was 170° C. Argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were poured into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn film (atomic ratio: 1:1:1.2). .

[0566] Next, a first heat treatment was performed at 450° C. in a nitrogen gas atmosphere. The heating was continued for 1 hour at 450° C. in a nitrogen gas and oxygen gas atmosphere.

[0567] Next, the conductive films 112a and 112b are formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b were a tungsten film having a thickness of 50 nm and a SiO2 film having a thickness of 400 nm. A 100 nm thick aluminum film and a 100 nm thick titanium film were deposited on the substrate using a sputtering device. A tungsten film, an aluminum film, and a titanium film were successively formed in this order in a vacuum.

[0568] Next, an insulating film was formed over the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. The insulating film 114 and the insulating film 116 were formed. The insulating film 114 was a 50 nm thick oxynitride film. The silicon film was formed using a PECVD apparatus. A silicon oxynitride film having a thickness of 100 nm was formed using a PECVD apparatus. The insulating film 4 and the insulating film 116 were formed successively in a vacuum using a PECVD apparatus.

[0569] The conditions for forming the insulating film 114 were a substrate temperature of 220° C. and a silica gel flow rate of 50 sccm. Nitrous oxide gas at a flow rate of 2000 sccm was introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 116 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 μm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was placed between the parallel plate electrodes in the PECVD device. An RF power of 1500 W was supplied to the substrate to form the film.

[0570] Next, a second heat treatment was performed at 350° C. in a nitrogen gas atmosphere. It was set to one hour.

[0571] An ITSO film having a thickness of 5 nm was formed on the insulating film 116 by using a sputtering apparatus. The conditions for forming the ITSO film were: substrate temperature at room temperature, argon gas at a flow rate of 72 sccm. Gas and oxygen gas at a flow rate of 5 sccm were introduced into the chamber, and the pressure was set to 0.15 Pa. A metal oxide target (In2O3:SnO2:Si The film was formed by supplying 1000 W of DC power to a mixture of 1000 μm and 100 μm of ZnO (O2 = 85:10:5 [wt %]).

[0572] Next, an oxygen addition process was performed on the insulating film 116 through the ITSO film. The ashing equipment was used, the substrate temperature was set to 40° C., and oxygen gas was used at a flow rate of 250 sccm. was introduced into the chamber, the pressure was set to 15 Pa, and a bias was applied to the substrate side. RF power of 4500 W was applied between the parallel plate electrodes installed in the ashing device for 120 sec. I supplied it.

[0573] Next, the ITSO film was removed to expose the insulating film 116. A wet etching device was used, and a 5% oxalic acid solution was used for etching. After etching for 15 seconds, the specimen was etched with 0.5% hydrofluoric acid for 15 seconds. We performed the switching.

[0574] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 100 mm. A silicon nitride film having a thickness of nm was formed using a PECVD apparatus. The conditions were a substrate temperature of 350° C., a silane gas flow rate of 50 sccm, and a Nitrogen gas at a flow rate of 0 sccm and ammonia gas at a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 100 Pa, and a 1000 W current was applied between the parallel plate electrodes installed in the PECVD device. The film was formed by supplying RF power of 1000 .mu.m.

[0575] Next, for only the sample A2, the opening 142c reaching the conductive film 112b and the The openings 142a, 142b, and 142c are formed. was formed using a dry etching apparatus.

[0576] Next, only the sample A2 is provided with an insulating film 118 so as to cover the openings 142a, 142b, and 142c. A conductive film was formed on the insulating film 120 and processed to form conductive films 120a and 120b. The conductive films 120a and 120b are ITSO films having a thickness of 100 nm, which are deposited by sputtering. The composition of the target used for the ITSO film was the same as that of the ITSO film shown above. The composition was the same as that of the membrane.

[0577] Next, for sample A1, a conductive layer was formed on the insulating film 118, and for sample A2, a conductive layer was formed on the insulating film 118. A photosensitive acrylic film having a thickness of 1.5 μm is spin-coated on the film 120a and the conductive film 120b. After forming the film by a coating method, exposure was performed.

[0578] Next, a third heat treatment was performed at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0579] Next, a fourth heat treatment was performed at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0580] Through the above steps, samples A1 and A2 of this example were fabricated.

[0581] <Id-Vg characteristics of transistor> Next, the Id- The Id-Vg characteristics of the samples A1 and A2 are shown in FIG. In FIG. 38(A) and (B), the first vertical axis represents Id(A) and the second vertical axis represents μFE(cm 2 / Vs) and the horizontal axis represents Vg (V).

[0582] In addition, it functions as a first gate electrode in the Id-Vg measurement of the transistor of sample A1. The voltage applied to the conductive film 104 (hereinafter also referred to as gate voltage (Vg)) is The voltage was applied from -15 V to +15 V in steps of 0.25 V. In the Id-Vg measurement of the photodiode, the voltage applied to the conductive film 104 functioning as the first gate electrode was The voltage (Vg) applied to the conductive film 120b functioning as the second gate electrode (Vbg) was applied in steps of 0.25V from -15V to +15V. In the samples A1 and A2, the voltage applied to the conductive film 112a functioning as the source electrode is The voltage applied to the drain electrode (hereinafter referred to as the source voltage (Vs)) is set to 0V (comm). The voltage applied to the conductive film 112b functioning as a drain voltage (hereinafter also referred to as drain voltage (Vd)) is ) was set to 0.1 V or 10 V. The field effect mobility (μFE) was calculated as Vd = Results for 10V are shown.

[0583] The field effect mobility is calculated by dividing the length 123 of the gate electrode in FIG. 37(A) and (B) by the channel length L (L=6 μm), the width 124 of the oxide semiconductor film 108 is the channel width W (W=10 μm), The field effect mobility in the saturated region was calculated using the formula for the saturation mobility. The maximum saturation mobility obtained by calculation is the saturation region (gate voltage The current driving force when the drain voltage (Vg) is less than the drain voltage (Vd) + threshold voltage (Vth) The capacitance of the insulating film is different from the approximate mobility as a physical property value of the oxide semiconductor film. In the case of the sample A2, the insulating film 106 functioning as the first gate insulating film and the insulating film 1 Calculations were performed using the volume of 07.

[0584] From the results shown in FIG. 38(A), in the transistor of sample A1, When the offset length of the junction is 1.5 μm, the maximum field effect mobility is 2 cm. 2 / Vs or later It was confirmed that the result shown in FIG. 38(B) was higher than that of sample A2. In a transistor, the field effect is Maximum mobility is 5cm 2 It was confirmed ...

Claims

1. A first conductive layer; and a first insulating layer having a region disposed on the first conductive layer; an oxide semiconductor layer having a region disposed on the first insulating layer; a second conductive layer having a region disposed on the oxide semiconductor layer; a third conductive layer having a region disposed on the oxide semiconductor layer; a second insulating layer having a region disposed on the oxide semiconductor layer; a fourth conductive layer having a region disposed on the second insulating layer; a pixel electrode of an EL element electrically connected to the third conductive layer; the first conductive layer functions as a first gate electrode of a transistor; the oxide semiconductor layer includes a channel formation region of the transistor, the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the fourth conductive layer functions as a second gate electrode of the transistor; the oxide semiconductor layer has a first region, a second region, a third region, a fourth region, and a fifth region; the first region does not overlap the first conductive layer, overlaps the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the second region does not overlap the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the third region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and overlaps the fourth conductive layer; the fourth region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the fifth region overlaps the first conductive layer, does not overlap the second conductive layer, overlaps the third conductive layer, and does not overlap the fourth conductive layer; the first conductive layer overlaps with an entire region of the fourth conductive layer that overlaps with the oxide semiconductor layer in a plan view; the first conductive layer overlaps with the entire third region, the entire fourth region, and the entire fifth region in a plan view; a region of the oxide semiconductor layer that overlaps with the fourth conductive layer does not overlap with the second conductive layer or the third conductive layer in a plan view; Semiconductor device.

2. A first conductive layer; and a first insulating layer on the first conductive layer; an oxide semiconductor layer on the first insulating layer; a second conductive layer on the oxide semiconductor layer; a third conductive layer on the oxide semiconductor layer; a second insulating layer on the oxide semiconductor layer; a fourth conductive layer on the second insulating layer; and a pixel electrode of an EL element electrically connected to the third conductive layer; the first conductive layer functions as a first gate electrode of a transistor; the oxide semiconductor layer includes a channel formation region of the transistor, the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the fourth conductive layer functions as a second gate electrode of the transistor; the oxide semiconductor layer has a first region, a second region, a third region, a fourth region, and a fifth region; the first region does not overlap the first conductive layer, overlaps the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the second region does not overlap the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the third region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and overlaps the fourth conductive layer; the fourth region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the fifth region overlaps the first conductive layer, does not overlap the second conductive layer, overlaps the third conductive layer, and does not overlap the fourth conductive layer; the first conductive layer overlaps with an entire region of the fourth conductive layer that overlaps with the oxide semiconductor layer in a plan view; the first conductive layer overlaps with the entire third region, the entire fourth region, and the entire fifth region in a plan view; a region of the oxide semiconductor layer that overlaps with the fourth conductive layer does not overlap with the second conductive layer or the third conductive layer in a plan view; The first conductive layer and the fourth conductive layer can be applied with different potentials. Semiconductor device.

3. In claim 1 or 2, the second region has a region having a thickness smaller than that of the first region, The fourth region has a region having a smaller thickness than the fifth region. Semiconductor device.

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