Digital signal processing device and coherent digital signal processing device

Abstract

This digital signal processing device comprises: a waveform shaping filter unit that executes a digital filtering process for a reception symbol generated by performing an equalization process on a reception signal and that outputs the execution result; a candidate symbol generation unit that generates a candidate symbol assumed as a transmission symbol before modulation of the reception signal; a transmission line simulation filter unit that executes a digital filtering process for the candidate symbol and a determination symbol determined to be a transmission symbol in the past and outputs the execution result; a symbol likelihood calculation unit that calculates, on the basis of the output from the waveform shaping filter unit and the output from the transmission line simulation filter unit, the likelihood of a symbol value represented by the reception symbol; and a symbol determination unit that determines the transmission symbol on the basis of the likelihood of the symbol value calculated by the symbol likelihood calculation unit.

Description

[Technical field]

[0001] The present invention relates to a digital signal processing device and a coherent digital signal processing device. [Background technology]

[0002] With the increase in demand for data communication, optical transmission networks using optical signal modulation technology and optical signal multiplexing technology that enable the transmission of large volumes of traffic are becoming widespread. In particular, digital coherent technology, which combines coherent detection and digital signal processing technology, has become widely used in ultra-high-speed optical transmission systems with a transmission speed of 200 Gb / s or more per wave. On the other hand, with the spread of large-volume data communication by mobile terminals, such as LTE (Long Term Evolution), there is a demand for realizing ultra-high-speed optical transmission of 200 Gb / s class at a lower cost, i.e., with a simpler transceiver configuration.

[0003] Direct detection, which demodulates data signals based on optical signal intensity information, is one method for achieving ultra-high-speed optical transmission of 200 Gb / s with a simple transceiver configuration. In particular, research is underway into ultra-high-speed optical transmission using 4-level intensity modulation (PAM4: 4-level Pulse Amplitude Modulation), which has higher frequency utilization efficiency than the 2-level intensity modulation NRZ (Non Return-to-Zero) method.

[0004] In 200Gb / s-class optical transmission using digital coherent technology, which has been put to practical use as a long-distance transmission technology, polarization multiplexed QPSK modulation (PDM-QPSK) is generally used, with a modulation speed of about 50Gbaud. On the other hand, when implementing 200Gb / s-class ultra-high-speed optical transmission using PAM4, which can be realized with the above-mentioned simple transceiver configuration, the modulation speed is about 100Gbaud, so the signal spectrum occupies a wider frequency range than the PDM-QPSK method. This means that the 200Gb / s-class PAM4 method is more susceptible to waveform degradation caused by filtering due to the band of electro-optical devices than the PDM-QPSK method.

[0005] To solve this problem, a technology has been proposed that improves the tolerance to waveform degradation caused by the band limitation of electro-optical devices by performing symbol decisions using maximum likelihood sequence estimation (MLSE) when performing digital signal processing on the receiving side (Non-Patent Document 1). In this method, all candidate symbol sequences assumed as transmission symbol sequences are input to a transmission path simulation filter that performs the same processing on the candidate symbol sequences as in the transmission path, and the likelihood of each candidate symbol sequence is calculated by comparing the output of the transmission path simulation filter with the received symbol sequence. By estimating the sequence with the maximum likelihood as the transmission symbol sequence, signal demodulation with high demodulation performance is achieved even in a severely band-limited environment. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] DD Falconer, et al., 'Adaptive channel memory truncation for maximum likelihood sequence estimation,' The Bell System Technical Journal, vol. 52, no. 9, pp. 1541 - 1562 (1973) Summary of the Invention [Problem to be solved by the invention]

[0007] However, in MLSE, in principle, all candidate symbol sequences assumed as transmission symbol sequences must be input to the transmission channel simulation filter and the likelihood of each candidate symbol sequence must be calculated. The length of the candidate symbol sequence is determined by the number of multi-levels of the symbol and the number of taps of the transmission channel simulation filter. If the length of the candidate symbol sequence is L, the number of multi-levels of the symbol is M, and the number of taps of the transmission channel simulation filter is D, then L can be expressed using M and D as follows:

[0008]

number

[0009] Therefore, when the number of taps D of the transmission line simulation filter is large, the number of candidate symbol sequences becomes very large. For example, in the case of a PAM4 signal with M=4, in order to use a 15-tap (D=15) transmission line simulation filter, L=4 is required. 16 ≒4×10 9 It is necessary to calculate the likelihood of each candidate symbol sequence, which results in a huge amount of calculation. An object of the present invention is to provide a digital signal processing device capable of reducing the amount of calculation in MLSE. [Means for solving the problem]

[0010] One aspect of the present invention is a digital signal processing device comprising: a waveform shaping filter unit that performs digital filter processing on received symbols generated by equalizing a received signal and outputs the result of the processing; a candidate symbol generation unit that generates candidate symbols that are assumed to be transmitted symbols before modulation of the received signal; a transmission path simulation filter unit that performs digital filter processing on the candidate symbols and determined symbols that have been determined to be transmitted symbols in the past and outputs the result of the processing; a symbol likelihood calculation unit that calculates the likelihood of a symbol value represented by the received symbol based on the output of the waveform shaping filter unit and the output of the transmission path simulation filter unit; and a symbol determination unit that determines a transmitted symbol based on the likelihood of the symbol value calculated by the symbol likelihood calculation unit.

[0011] One aspect of the present invention is a digital signal processing device comprising: a waveform shaping filter unit that performs digital filter processing on a received symbol and outputs the result of the processing; a transmission path simulation filter unit that performs digital filter processing on a decision symbol that is an estimate of a past received symbol and outputs the result of the processing; and a symbol decision unit that decides a transmission symbol by making a hard decision based on a threshold decision on a received symbol estimate value calculated based on the output of the waveform shaping filter unit and the output of the transmission path simulation filter unit. Effect of the Invention

[0012] According to the present invention, the amount of calculations required in MLSE can be reduced. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 illustrates a configuration of an optical signal demodulator 1. [Diagram 2] 1 is a diagram showing a configuration of a digital signal processing device 4 according to a first embodiment. [Diagram 3] FIG. 2 is a diagram illustrating an example of the configuration of a digital equalization unit 10. [Figure 4] 2 is a diagram illustrating an example of the configuration of a waveform shaping filter unit 12. FIG. [Diagram 5]2 is a diagram illustrating an example of the configuration of a transmission path simulation filter unit 16 according to the first embodiment. FIG. [Figure 6] 13 shows experimental results of the digital signal processing device 4 according to the first embodiment. [Figure 7] 13 shows experimental results of the digital signal processing device 4 according to the first embodiment. [Figure 8] 13 shows experimental results of the digital signal processing device 4 according to the first embodiment. [Figure 9] 13 shows experimental results of the digital signal processing device 4 according to the first embodiment. [Figure 10] FIG. 11 is a diagram illustrating a transmission path simulation filter unit 16 according to a second embodiment. [Figure 11] FIG. 11 is a diagram showing a configuration of a digital signal processing device 4 according to a third embodiment. [Figure 12] FIG. 11 is a diagram showing a configuration of a digital signal processing device 4 according to a fourth embodiment. [Figure 13] FIG. 2 is a diagram showing a configuration of a coherent digital signal processing device 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] [Overall configuration] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 is a diagram showing the configuration of an optical signal demodulator 1. The optical signal demodulator 1 receives an optical signal from an optical signal modulator (not shown). The optical signal demodulator 1 demodulates the transmitted optical signal to determine the transmitted symbol before being modulated by the optical signal modulator. The optical signal demodulator 1 includes an optical receiver 2 , an AD converter 3 and a digital signal processing device 4 .

[0015] The optical receiver 2 receives an optical signal and converts the received optical signal into an electrical signal. In a direct detection system, the optical receiver 2 is an optical intensity receiver. The AD converter 3 converts the electrical signal input from the optical receiver 2 into a digital signal. The digital signal processing device 4 performs symbol decision based on the digital signal input from the AD converter 3.

[0016] <First embodiment> FIG. 2 is a diagram showing the configuration of a digital signal processing device 4 according to the first embodiment. The digital signal processing device 4 includes a digital equalizer 10 , a waveform shaping filter unit 12 , a candidate symbol generator 14 , a transmission path simulation filter unit 16 , a transition likelihood calculator 18 , a symbol likelihood calculator 20 , and a decision symbol determiner 22 .

[0017] The digital equalizer 10 performs digital equalization processing on the digital signal. The digital equalizer 10 is, for example, a feed forward equalizer (FFE). FIG. 3 is a diagram showing an example of the configuration of the digital equalizer 10. The number of taps of the digital equalizer 10 shown in FIG. 3 is two, but is not limited to this. The digital equalizer 10 includes a delayer 102, a multiplier 104, and an adder 106. The delayer 102 stores an input signal and outputs the stored input signal after a certain period of time. The multiplier 104 multiplies the input signal by a predetermined value. The multiplier 124-i (i is an integer between 1 and 3) multiplies the input signal t n-i Tap coefficient b i The adder 106 adds the two input signals.

[0018] At time n, signal t n is input to the digital equalizer 10. At time n, the delay device 102-1 receives a signal t n-1 However, the delay device 102-2 receives the signal t n-2 The multiplier 104-1 multiplies the input t n 2 0 Multiply by t n ×b 0 The multiplier 104-2 outputs the input t n-1 2 1 Multiply by t n-1 ×b 1 The multiplier 104-3 outputs the input t n-2 2 2 Multiply by t n-2 ×b 2 The adder 106-1 outputs the input t n×b 0 and n-1 ×b 1 Add t n ×b 0 +t n-1 ×b 1 The adder 106-2 outputs the input t n ×b 0 +t n-1 ×b 1 and n-2 ×b 2 Add t n ×b 0 +t n-1 ×b 1 +t n-2 ×b 2 Therefore, the received symbol s n s n =t n ×b 0 +t n-1 ×b 1 +t n-2 ×b 2 This is expressed as:

[0019] The waveform shaping filter unit 12 receives the symbol s i The filtered value y n The waveform shaping filter unit 12 is, for example, a finite impulse response (FIR) filter. FIG. 4 is a diagram showing an example of the configuration of the waveform shaping filter unit 12. The number of taps of the waveform shaping filter unit 12 shown in FIG. 4 is three, but is not limited to this. The waveform shaping filter unit 12 includes a delay unit 122, a multiplier 124, and an adder 126. The delay unit 122, the multiplier 124, and the adder 126 have the same functions as the delay unit 102, the multiplier 104, and the adder 106 included in the digital equalization unit 10, respectively. The multiplier 124-i (i is an integer between 1 and 4) multiplies the received symbol s n-i Tap coefficient c i Multiply by.

[0020] The waveform shaping filter unit 12 receives the i The digital equalizer 10 performs the process for t iTherefore, the filtered value y n Yes n =s n ×c 0 +s n-1 ×c 1 +s n-2 ×c 2 +s n-3 ×c 3 This is expressed as: If the number of taps is C, then y n is expressed by the following formula:

[0021]

number

[0022] The candidate symbol generator 14 generates the candidate symbol r n Generate candidate symbol r n is a symbol assumed to be a transmission symbol. For example, in the case of the PAM4 system, the candidate symbol generator 14 generates the candidate symbol r n 4 pieces (r n =0, 1, 2, 3).

[0023] The transmission path simulation filter unit 16 detects the candidate symbol r n and the decision symbol x n The digital filter processing is performed by convolution operation on the simulated filtered value z n The decision symbol used by the transmission channel simulation filter unit 16 is a symbol that has been previously decided to be a transmission symbol. Details of the decision symbol will be described later. The transmission channel simulation filter unit 16 is, for example, a finite impulse response (FIR) filter, similar to the waveform shaping filter unit 12. FIG. 5 is a diagram showing an example of the configuration of the transmission channel simulation filter unit 16 according to the first embodiment. In the transmission channel simulation filter unit 16 shown in FIG. 5, a candidate symbol r n The number of taps related to the decision symbol x nThe number of taps related to is two, but is not limited to this. The transmission path simulation filter unit 16 includes a delay unit 162, a multiplier 164, and an adder 166. The delay unit 162, the multiplier 164, and the adder 166 have the same functions as the delay unit 102, the multiplier 104, and the adder 106 included in the digital equalization unit 10, respectively, except for the following points.

[0024] When delayers 162-1 and 162-3 store input symbols and output the stored input signals after 1 second, delayer 162-2 stores input symbols and outputs the stored input signals after 2 seconds. In other words, delayer 162-2 delays the signal twice as much as delayers 162-1 and 162-3. Also, multiplier 164-i (i is an integer between 1 and 4) applies a tap coefficient d i Multiply by.

[0025] At time n, candidate symbol r n is input to the delay unit 162-1, and the symbol decision value x n is input to the delay unit 162-2. Also, at time n, the multiplier 164-1 receives r n is input to the multiplier 164-2, and r n-1 is input, and the multiplier 164-3 receives x n-2 is input, and the multiplier 164-4 receives x n-3 Here, the simulated filter processing value z n Z n =r n ×d 0 +r n-1 ×d 1 +x n-2 ×d 2 +x n-3 ×d 3 This is expressed as:

[0026] Here, the number of taps is D, and the candidate symbol r n Let the number of taps related to n The number of taps related to the filter is generalized as DR, and the simulated filter processing value z n is expressed by the following formula:

[0027]

number

[0028] Candidate symbol r n The number of taps and decision symbol x n Since the number of taps related to the simulated filter processed value z n The candidate symbol r used to calculate n The decision symbol is not limited to this. For example, n only) or three (r n , r n-1 , r n-2 ) to z n Also, the candidate symbols used do not have to be consecutive symbols. For example, z n To calculate the candidate symbols, n and r n-2 Two symbols are used: n-1 may not be used.

[0029] The transition likelihood calculation unit 18 calculates the likelihood for each candidate symbol sequence (hereinafter, symbol sequence likelihood) based on the filtered value and the simulated filtered value. Here, the candidate symbol sequence is a combination of the candidate symbols used to calculate the simulated filtered value, and (r n , r n-1 ) The symbol sequence likelihood l is calculated, for example, by the following formula:

[0030]

number

[0031] The symbol sequence likelihood l calculated by the above formula corresponds to the logarithm of the inverse of the likelihood, so the smaller the value, the higher the likelihood. n-1 and r n Each has four values, and r n-1 and r nThere are 16 combinations (=4 2 ) there are 16 possible values ​​for l.

[0032] The symbol likelihood calculation unit 20 calculates the likelihood (symbol value likelihood) for each candidate symbol based on the symbol sequence likelihood. The symbol value likelihood is calculated, for example, by the following formula.

[0033]

number

[0034] In the above equation, the right side is r n-1 is the minimum value that the formula in the parentheses can take when r is changed. The symbol value likelihood calculated by the above formula corresponds to the logarithm of the inverse of the likelihood, so the smaller the value, the higher the likelihood. The symbol likelihood calculation unit 20 calculates r n Fix r n-1 When changing, the sum of l calculated by the transition likelihood calculation unit 18 and the symbol value likelihood m calculated by the symbol likelihood calculation unit at time n-1 is calculated as the symbol value likelihood m at time n. Therefore, the symbol value likelihood is r n There are four types, the same as the number of possible values.

[0035] The decision symbol determination unit 22 determines the decision symbol x n Determine the symbol decision value x n is determined, for example, by the following formula:

[0036]

number

[0037] In the above equation, the right side is r n When the equation in brackets takes the minimum value when n That is, the decision symbol determination unit 22 determines the candidate symbol r nis determined as the decision symbol. n The x determined by the decision symbol determination unit 22 is n is input to the transmission line simulation filter unit 16, and z n In addition, the x determined by the decision symbol determination unit 22 is used to calculate n is outputted to the outside as a demodulation result of the optical signal received by the optical signal demodulator 1. In other words, the decision symbol determination unit 22 is an example of a symbol decision unit that decides a transmission symbol based on the symbol value likelihood.

[0038] <Experimental Results> 6 and 7 show experimental results of the digital signal processing device 4 according to the first embodiment. The graph shown in FIG. 6 shows the relationship between the received optical power and the bit error rate (BER) under four different conditions. The four different conditions are roughly divided into a "comparative example" and an "embodiment". In the "comparative example", the digital signal processing device 4 includes only the digital equalizer 10, and outputs a signal that has been digitally equalized by the digital equalizer 10 as a demodulation result of the optical signal. In the "embodiment", it is the same as the digital signal processing device 4 according to the first embodiment. In the "embodiment", the number of taps C of the waveform shaping filter 12 and the number of taps D of the transmission line simulation filter 16 were both changed to 3, 9, and 16, and an experiment was performed. In the transmission line simulation filter 16 in the "embodiment", the number of taps related to the candidate symbol is 1. In the experiment, the transmission speed per wave is 186 Gb / s, and the PAM4 method is used.

[0039] As shown in FIG. 6, it can be seen that the BER is reduced by applying the digital signal processing device 4 according to the first embodiment.

[0040] The graph shown in Fig. 7 shows the relationship between the number of taps C of the waveform shaping filter unit 12 and the BER. Here, the number of taps D of the transmission path simulation filter unit 16 is 9. As shown in Fig. 7, it can be seen that the BER increases when C is set to a value less than D (=9). From the above, it can be seen that in order to reduce the BER, it is desirable to set the number of taps of the waveform shaping filter unit 12 to be equal to or greater than the number of taps of the transmission path simulation filter unit 16.

[0041] 8 and 9 show experimental results of the digital signal processing device 4 according to the first embodiment. 8 and 9 are different from the experimental results shown in Fig. 6 and 7 in that the number of taps related to the candidate symbol in the transmission channel simulation filter unit 16 is 0. That is, in the transmission channel simulation filter unit 16, the candidate symbol is n Only the x symbol is used. n-1 x n-D+1 Except for the above conditions, there is no difference between the experiment shown in Figures 8 and 9 and the experiment shown in Figures 6 and 7.

[0042] From the experimental results shown in FIG. 8 and FIG. 9, it can be seen that, similarly to the experimental results shown in FIG. 6 and FIG. 7, even when only one candidate symbol is used, the BER is reduced and it is desirable to set the number of taps of the waveform shaping filter section 12 to be equal to or greater than the number of taps of the transmission path simulation filter section 16.

[0043] Actions and Effects As described above, according to this embodiment, in MLSE, the number of candidate symbols is reduced by using decision symbols, thereby making it possible to reduce the amount of calculations.

[0044] The digital equalization unit 10 may update the number of taps. For example, the digital equalization unit 10 updates the number of taps so as to minimize the difference between the sequence of received symbols and the signal obtained by hard decision of the sequence of received symbols. Also, for example, the digital equalization unit 10 updates the number of taps so as to minimize the difference between the sequence of received symbols and the sequence of known pilot symbols.

[0045] In addition, the tap coefficient c of the waveform shaping filter unit 12 i and the tap coefficient d of the transmission path simulation filter unit 16 i may be updated. i and d i is updated so that the value of l is minimized. That is, c i and d i is updated to maximize the likelihood. The value of l is r n-1 x n-1 , r n x n Since the minimum value is reached when , the value of l at this time is set to be smaller, so c i and d i is updated. For example, c i and d i are updated to the values ​​in the following equations using the LMS (Least Mean Square) algorithm:

[0046]

number

[0047] That is, c i From μ, E and s n-1 The product of is subtracted, and d i μ and E and x n-1 By adding the product of c i and d i will be updated.

[0048] Here, μ is a step size parameter set in the LMS algorithm, and E is a value expressed by the following equation.

[0049]

number

[0050] Furthermore, the decision symbols input to the transmission path simulation filter unit 16 may be pilot symbols.

[0051] Although the four symbol values, 0, 1, 2, and 3, have been described as an example, the present invention is not limited to this. For example, the four symbol values ​​may be -1, -1 / 3, 1 / 3, and 1. The symbol values ​​are not limited to four values. For example, in the NRZ system, the symbol values ​​can only have two values.

[0052] Second embodiment In addition to the functions of the decision symbol determination unit 22 according to the first embodiment, the decision symbol determination unit 22 according to the second embodiment determines the rank of the symbol values ​​based on the likelihood of the symbol values. The symbol values ​​are ranked higher when the probability that the symbol value is a received symbol is higher. The decision symbol determination unit 22 according to the second embodiment determines the first-ranked symbol value x n (1) is determined.

[0053]

number

[0054] Here, the first symbol value x n (1) is the same as the decision symbol in the first embodiment. Furthermore, the decision symbol determination unit 22 according to the second embodiment determines the second-order symbol value x n (2) is determined.

[0055]

number

[0056] That is, the second symbol value x n (2) is x n This is the most likely symbol value except for (1). x n (1) and x n A symbol that can take one of the two values ​​in (2) is called a ranked symbol, and r' n This is expressed as:

[0057] 10 is a diagram showing a transmission path simulation filter unit 16 according to the second embodiment. In the transmission path simulation filter unit 16 according to the second embodiment, a delay device 162-1 receives a ranked symbol r' n At this time, the simulated filter processing value z n Z n =r n ×d 0 +r' n-1 ×d 1 +x n-2 ×d 2 +x n-3 ×d 3 This is expressed as:

[0058] Here, the number of taps is D, and the ranked symbol r' n If the number of taps related to is 1, z n is expressed by the following formula:

[0059]

number

[0060] The transition likelihood calculation unit 18 calculates the likelihood l for each candidate symbol sequence by the following formula.

[0061]

number

[0062] In the first embodiment, r n-1 takes four values ​​{0, 1, 2, 3}, whereas in the second embodiment, r' n-1 is {x n (1), x n (2)}. As a result, while the symbol sequence likelihood l in the first embodiment was 16, the symbol sequence likelihood l in the second embodiment is reduced to 8. This makes it possible to reduce the amount of calculations compared to the first embodiment.

[0063] The symbol likelihood calculation unit 20 calculates the likelihood for each candidate symbol using the following formula.

[0064]

number

[0065] r' n-1 Since takes two values, m takes four values. Hereinafter, the method of determining the symbol decision value by the decided symbol decision unit 22 in the second embodiment is the same as the method in the first embodiment.

[0066] The ranking of the symbol value determined by the decision symbol determination unit 22 is not limited to the first and second rankings. For example, the rankings may be determined from the first ranking to the third ranking. In this case, the ranked symbol r' n can have three values.

[0067] Third embodiment FIG. 11 is a diagram showing a configuration of a digital signal processing device 4 according to the third embodiment. In the digital signal processing device 4 according to the third embodiment, the candidate symbol generating unit 14 generates the received symbol s n Based on the symbol candidate value r n ' to determine.

[0068] The candidate symbol generator 14 according to the third embodiment selects s n The difference between the two values ​​is small. n For example, the possible symbol values ​​are 0, 1, 2, and 3, and s n is 1.6, the candidate symbol generator 14 assigns 2 and 1 to r n ' is decided.

[0069] r n s n It takes two values ​​based on r n-1 s n-1 Therefore, the symbol sequence likelihood calculated by the transition likelihood calculation unit 18 takes four values. This makes it possible to reduce the amount of calculation compared to the first embodiment.

[0070] Fourth embodiment FIG. 12 is a diagram showing a configuration of a digital signal processing device 4 according to the fourth embodiment. The digital signal processing device 4 according to the fourth embodiment includes a digital equalizer 10, a waveform shaping filter unit 12, a transmission channel simulation filter unit 16, a transition likelihood calculation unit 18, and a decision symbol determination unit 22. Unlike the digital signal processing device 4 according to the first embodiment, the digital signal processing device 4 according to the fourth embodiment does not include the candidate symbol generation unit 14 and the symbol likelihood calculation unit 20.

[0071] In the fourth embodiment, the transmission path simulation filter unit 16 uses only past decision symbols to calculate a simulated filter processing value z n Calculate the simulated filter processing value z n is calculated by the transmission path simulation filter unit 16 using the following formula:

[0072]

number

[0073] z n is the decision symbol x n The transition likelihood calculation unit 18 calculates the received symbol estimate p. The method of calculating the received symbol estimate p is the same as the method of calculating the symbol sequence likelihood l, but the received symbol estimate p takes only one value. Ideally, the received symbol estimate p is calculated based on only the received symbol s 0 The decision symbol determination unit 22 performs hard decision on the received symbol estimate p based on a threshold decision to obtain a decision symbol x n The decision symbol determination unit 22 determines for each bit of the received symbol estimate p whether it is equal to or greater than a predetermined threshold, as 1, or whether it is smaller than the predetermined threshold, as 0, and determines a value corresponding to the decision result for each bit as a decision symbol.

[0074] This reduces the amount of calculations compared to the first embodiment.

[0075] Fifth embodiment The digital signal processing device 4 according to the fifth embodiment includes an LLR calculation unit 24 in addition to the digital signal processing device 4 according to the first embodiment. The LLR calculation unit 24 calculates a log-likelihood ratio (bit LLR) of each bit corresponding to a decision symbol. The calculated bit LLR is used, for example, for decoding of forward error correction (FEC). For example, assume that two bits 00, 01, 11, and 10 are assigned to the four values ​​0, 1, 2, and 3 in the PAM4 format. If the left bit of the two bits is the Most Significant Bit (MSB) and the right bit is the Least Significant Bit (LSB), the bit LLR values ​​for the MSB and LSB are calculated using the following formulas.

[0076]

number

[0077] Here, P 0 From P 3 The value of is the likelihood at each symbol value and is expressed by the following formula:

[0078]

number

[0079] Here, σ is the noise power. The bit LLR values ​​for the MSB and LSB can also be calculated simply by the following formula:

[0080]

number

[0081] Furthermore, in the fourth embodiment, when there is only one candidate filtered value l, the likelihood for each symbol value is calculated by the following formula.

[0082]

number

[0083] In this case, the bit LLR value can be easily calculated by the following formula.

[0084]

number

[0085] <Embodiment for Coherent Detection> FIG. 13 is a diagram showing a configuration of a coherent digital signal processing device 5. The coherent digital signal processing device 5 includes four digital signal processing devices 4. The coherent digital signal processing device 5 is used in coherent detection. At this time, the optical receiver 2 is a coherent receiver. The digital signal processing device 4 receives four digital signals corresponding to the in-phase component (I component) and the quadrature component (Q component) of the X-polarized wave and the Y-polarized wave, respectively. The digital equalization unit 10 performs waveform equalization processing on the input digital signal. The waveform equalization processing is, for example, chromatic dispersion compensation, MIMO adaptive equalization, frequency offset compensation, and carrier phase estimation. After the waveform equalization processing is performed by the digital equalization unit 10, four reception symbols are output from the digital equalization unit 10. The four reception symbols are input to the digital signal processing device 4, and processed in the same manner as in the first embodiment, and a decision symbol is determined.

[0086] The digital signal processing device 4 included in the coherent digital signal processing device 5 is not limited to the digital signal processing device 4 according to the first embodiment. For example, the coherent digital signal processing device 5 may include the digital signal processing device 4 according to the second to fifth embodiments described above.

[0087] Although one embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to the above, and various design changes, etc. are possible within the scope that does not deviate from the gist of the present invention. [Explanation of symbols]

[0088] 1...optical signal demodulator, 2...optical receiver, 3...AD converter, 4...digital signal processing device, 5...coherent digital signal processing device, 10...digital equalization section, 12...wave shaping filter section, 14...candidate symbol generation section, 16...transmission path simulation filter section, 18...transition likelihood calculation section, 20...symbol likelihood calculation section, 22...decision symbol determination section, 102, 122, 162...delay device, 104, 124, 164...multiplier, 106, 126, 166...adder

Claims

1. a waveform shaping filter unit that performs digital filtering on received symbols generated by equalizing a received signal and outputs the filtering result; a candidate symbol generation unit that generates candidate symbols assumed as transmission symbols before modulation of the received signal; a transmission path simulation filter unit that performs digital filtering on the candidate symbols and decision symbols that have been previously determined to be transmission symbols, and outputs the results of the filtering; a symbol likelihood calculation unit that calculates a likelihood of a symbol value represented by the received symbol based on an output of the waveform shaping filter unit and an output of the transmission path simulation filter unit; a symbol determination unit that determines a transmission symbol based on the likelihood of the symbol value calculated by the symbol likelihood calculation unit; Equipped with Digital signal processing device.

2. the symbol decision unit determines a symbol rank indicating which symbol value is a received symbol based on the likelihood of the symbol value; the candidate symbol generation unit generates the candidate symbols based on the symbol rankings.

2. The digital signal processing device according to claim 1.

3. a symbol soft decision unit for determining a symbol candidate value based on the received symbol; Further equipped with the candidate symbol generation unit generates the candidate symbols using the symbol candidate values.

2. The digital signal processing device according to claim 1.

4. the waveform shaping filter unit and the transmission path simulation filter unit change tap coefficients so that the likelihood of the symbol value calculated by the symbol likelihood calculation unit increases. A digital signal processing device according to any one of claims 1 to 3.

5. 2. The digital signal processing device according to claim 1, wherein the number of taps of said waveform shaping filter section is equal to or greater than the number of taps of said transmission path simulation filter section.

6. an LLR calculation unit that calculates a log likelihood ratio for each bit corresponding to the decision symbol; 2. The digital signal processing device according to claim 1.

7. A digital signal processing apparatus comprising: A coherent digital signal processing device, wherein the four digital signal processing devices receive received symbols corresponding to an X-polarized I-channel component, an X-polarized Q-channel component, a Y-polarized I-channel component, and a Y-polarized Q-channel component of a received signal, respectively.

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