Solid-state imaging device and electronic device

Abstract

A solid-state imaging device with improved characteristics such as reduced optical color mixing is provided. [Solution] A solid-state imaging device is configured comprising: a substrate, a first n-type semiconductor region provided in the substrate, a second n-type semiconductor region adjacent to the first n-type semiconductor region and provided in the substrate, a wiring layer provided on the surface of the substrate opposite to the light incident surface, a first element isolation portion provided between the first n-type semiconductor region and the second n-type semiconductor region, a first insulating film having a fixed charge provided above the light incident surfaces of the first n-type semiconductor region and the second n-type semiconductor region, and a light-shielding film provided above the first element isolation portion. In the solid-state imaging device, the first element isolation portion includes a conductor, and the conductor is connected to the light-shielding film provided on the substrate.

Description

[Technical field]

[0001] The present disclosure relates to a back-illuminated solid-state imaging device and an electronic device. [Background technology]

[0002] In recent years, a back-illuminated solid-state imaging device has been proposed, which irradiates light from the side opposite to the side on which a wiring layer is formed on a substrate (see Patent Document 1 below). In a back-illuminated solid-state imaging device, since no wiring layer or circuit elements are formed on the light irradiation side, the aperture ratio of the light receiving section formed on the substrate can be increased, and since incident light is incident on the light receiving section without being reflected by the wiring layer, etc., the sensitivity can be improved. The solid-state imaging device of Patent Document 1 has a light-shielding film provided at pixel boundaries in order to reduce optical color mixing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-186818 A Summary of the Invention [Problem to be solved by the invention]

[0004] In such solid-state imaging devices, there is a demand for further improvement in characteristics, such as reduction in optical mixing.

[0005] The present disclosure provides a solid-state imaging device with improved characteristics such as reduced optical mixing, and also provides an electronic device using the solid-state imaging device. [Means for solving the problem]

[0006] The solid-state imaging device of the present disclosure includes a substrate, a first n-type semiconductor region provided on the substrate, a second n-type semiconductor region adjacent to the first n-type semiconductor region and provided on the substrate, a wiring layer provided on the surface of the substrate opposite to the light incident surface, a first element isolation section provided between the first n-type semiconductor region and the second n-type semiconductor region, a first insulating film having a fixed charge provided above the light incident surfaces of the first n-type semiconductor region and the second n-type semiconductor region, and a light shielding film provided above the first element isolation section. The first element isolation section includes a conductor, and the conductor is connected to the light shielding film provided on the substrate.

[0007] An electronic device according to the present disclosure includes an optical lens, the above-described solid-state imaging device, and a signal processing circuit that processes an output signal output from the solid-state imaging device. Effect of the Invention

[0008] According to the present disclosure, it is possible to further improve the characteristics of a solid-state imaging device, such as reducing color mixing, and it is also possible to obtain an electronic device with improved image quality by using the solid-state imaging device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram showing an overall configuration of a solid-state imaging device according to a first embodiment of the present disclosure. [Diagram 2] 1 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a first embodiment of the present disclosure. [Diagram 3] 1 is a planar layout of a solid-state imaging device according to a first embodiment of the present disclosure. [Figure 4] 4A and 4B are diagrams illustrating a manufacturing method of a solid-state imaging device according to the first embodiment of the present disclosure. [Diagram 5] 4C and 4D are diagrams illustrating a manufacturing method of the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 6] 2A to 2C are potential distribution diagrams of main parts of the solid-state imaging device according to the first embodiment of the present disclosure and a conventional solid-state imaging device. [Figure 7]1 is a planar layout of a solid-state imaging device according to a first modified example of the first embodiment. [Figure 8] 13 is a planar layout of a solid-state imaging device according to Modification 2 of the first embodiment. [Figure 9] 6 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 10] 10A to 10C are diagrams illustrating a method for manufacturing a solid-state imaging device according to the second embodiment of the present disclosure. [Figure 11] 13 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a third embodiment of the present disclosure. FIG. [Figure 12] 13 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a fourth embodiment of the present disclosure. FIG. [Figure 13] 13A and 13B are diagrams illustrating a manufacturing method of a solid-state imaging device according to the fourth embodiment of the present disclosure. [Figure 14] FIG. 14C is a diagram showing a manufacturing method of a solid-state imaging device according to the fourth embodiment of the present disclosure. [Figure 15] 13 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a fifth embodiment of the present disclosure. FIG. [Figure 16] 13 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a sixth embodiment of the present disclosure. FIG. [Figure 17] 13 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a seventh embodiment of the present disclosure. FIG. [Figure 18] 18A and 18B are diagrams illustrating a manufacturing method of a solid-state imaging device according to the seventh embodiment of the present disclosure. [Figure 19] 13 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to an eighth embodiment of the present disclosure. FIG. [Figure 20] 20A and 20B are diagrams illustrating a manufacturing method of a solid-state imaging device according to the eighth embodiment of the present disclosure. [Figure 21] 13 is a diagram showing a cross-sectional configuration of a main part of a solid-state imaging device according to a modified example. [Figure 22] FIG. 13 is a schematic configuration diagram of an electronic device according to a ninth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present inventors have discovered the following problem in the solid-state imaging device of Patent Document 1.

[0011] In a back-illuminated solid-state imaging device, the semiconductor layer in which the photodiode is formed is formed thinner than in a front-illuminated solid-state imaging device. Therefore, in a conventional front-illuminated solid-state imaging device, the signal charge overflowing from the photodiode is configured to overflow in the depth direction (vertical direction) of the semiconductor layer, but in a back-illuminated solid-state imaging device, the signal charge cannot overflow in the depth direction of the semiconductor layer. Therefore, in a back-illuminated solid-state imaging device, the electrons overflowing from the photodiode are configured to flow to the floating diffusion (so-called lateral overflow).

[0012] When a lateral overflow structure is adopted, whether electrons overflowing from a photodiode flow to the floating diffusion side or to the adjacent photodiode side is determined by the potential in the substrate. Therefore, by setting the potential between the photodiode and the floating diffusion higher than the potential between the adjacent photodiodes during charge accumulation, the overflowing electrons can be transferred to the floating diffusion at any time. For this reason, when a configuration is adopted that allows overflowing electrons to be transferred to the floating diffusion, a reduction in the saturation charge (Qs) becomes a major issue. On the other hand, when the saturation charge is increased, the signal charge overflowing from a white dot pixel during long-term accumulation leaks into adjacent pixels, causing blooming, which is one of the causes of resolution degradation and image quality degradation. Furthermore, in a structure in which a light-shielding film is provided on pixel boundaries, it is not possible to completely suppress color mixing that occurs under the light-shielding film when oblique light enters. In an embodiment of the present disclosure, a solid-state imaging device capable of reducing color mixing, suppressing blooming, and improving saturation characteristics will be described.

[0013] Hereinafter, an example of a solid-state imaging device, a manufacturing method thereof, and an electronic device according to an embodiment of the present disclosure will be described with reference to Fig. 1 to Fig. 22. The embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. 1. First embodiment: Solid-state imaging device (example in which four pixels share one floating diffusion section) 1-1 Overall configuration of solid-state imaging device 1-2 Main components 1-3 Manufacturing method of solid-state imaging device 1-4 Variation 1 1-5 Variation 2 2. Second embodiment: Solid-state imaging device (example in which a light-shielding film is formed in an element isolation portion) 3. Third embodiment: Solid-state imaging device (example in which only the end of the element isolation portion on the back side of the substrate is in contact with the p-type semiconductor region) 4. Fourth embodiment: Solid-state imaging device (example in which element isolation portion penetrates substrate) 5. Fifth embodiment: Solid-state imaging device (example in which a light-shielding layer formed in an element isolation portion is connected to a wiring layer) 6. Sixth embodiment: Solid-state imaging device (example in which a two-layer fixed charge film is formed in an element isolation section) 7. Seventh embodiment: Solid-state imaging device (example in which element isolation section has hollow structure) 8. Eighth embodiment: Solid-state imaging device (example in which element isolation section has hollow structure) 8-1 Variations 9. Ninth embodiment: Electronic device

[0014] 1. First embodiment: solid-state imaging device [1-1 Overall configuration of solid-state imaging device] FIG. 1 is a schematic configuration diagram showing the entirety of a CMOS type solid-state imaging device according to a first embodiment of the present disclosure. The solid-state imaging device 1 of this embodiment is configured to include a pixel region 3 having a plurality of pixels 2 arranged on a substrate 11 made of silicon, a vertical driving circuit 4, a column signal processing circuit 5, a horizontal driving circuit 6, an output circuit 7, a control circuit 8, etc.

[0015] The pixel 2 is composed of a photoelectric conversion unit made of a photodiode and a plurality of pixel transistors, and is regularly arranged in a two-dimensional array on the substrate 11. The pixel transistor constituting the pixel 2 may be four MOS transistors composed of a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor, or may be three transistors excluding the selection transistor.

[0016] The pixel region 3 has a plurality of pixels 2 regularly arranged in a two-dimensional array. The pixel region 3 is composed of an effective pixel region that actually receives light, amplifies the signal charge generated by photoelectric conversion, and reads it out to a column signal processing circuit 5, and a black reference pixel region (not shown) for outputting optical black that serves as a reference for the black level. The black reference pixel region is usually formed on the outer periphery of the effective pixel region.

[0017] The control circuit 8 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. The clock signals and control signals generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0018] The vertical drive circuit 4 is configured with, for example, a shift register, and sequentially selects and scans each pixel 2 in the pixel area 3 in the vertical direction on a row-by-row basis. Then, a pixel signal based on a signal charge generated in the photodiode of each pixel 2 according to the amount of received light is supplied to a column signal processing circuit 5 through a vertical signal line.

[0019] The column signal processing circuit 5 is arranged, for example, for each column of pixels 2, and performs signal processing such as noise removal and signal amplification on signals output from one row of pixels 2 for each pixel column using signals from a black reference pixel area (not shown, but formed around the effective pixel area). A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

[0020] The horizontal drive circuit 6 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, and cause each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 10.

[0021] The output circuit 7 processes signals sequentially supplied from each of the column signal processing circuits 5 through a horizontal signal line 10 and outputs the processed signals.

[0022] [1-2 Main components] Fig. 2 shows a cross-sectional configuration of a pixel region 3 of the solid-state imaging device 1 of this embodiment, and Fig. 3 shows a planar layout of the pixel region 3 of the solid-state imaging device 1 of this embodiment. The solid-state imaging device 1 of this embodiment is an example of a back-illuminated CMOS type solid-state imaging device, in which a required pixel transistor is shared by four photoelectric conversion units, so-called four-pixel sharing is one unit. In the following description, the first conductivity type is p-type, and the second conductivity type is n-type.

[0023] 2, the solid-state imaging device 1 of the present embodiment includes a substrate 12 having a plurality of pixels, a wiring layer 13 formed on the front side of the substrate 12, and a support substrate 31. The solid-state imaging device 1 further includes an insulating film having a fixed charge (hereinafter, fixed charge film) 20, an insulating film 21, a light-shielding film 25, a planarizing film 26, a color filter layer 27, and an on-chip lens 28, which are formed in this order on the rear side of the substrate 12.

[0024] The substrate 12 is a semiconductor substrate made of silicon, and is formed to have a thickness of, for example, 1 μm to 6 μm. In the pixel region 3 of the substrate 12, a plurality of pixels, each of which is made up of a photoelectric conversion unit 40 made up of a photodiode and a plurality of pixel transistors (Tr1 to Tr4) constituting a pixel circuit unit, are formed in a two-dimensional matrix. Adjacent photoelectric conversion units 40 are electrically isolated by an element isolation unit 19. Although not shown in FIG. 2, a peripheral circuit unit is formed in the peripheral region of the pixel region formed on the substrate 12.

[0025] The photoelectric conversion section 40 is composed of first conductive type (hereinafter, p-type) semiconductor regions 23, 24 formed on the front and back sides of the substrate 12, and a second conductive type (hereinafter, n-type) semiconductor region 22 formed therebetween. In the photoelectric conversion section 40, a main photodiode is composed of a pn junction between the p-type semiconductor regions 23, 24 and the n-type semiconductor region 22. In the photoelectric conversion section 40, a signal charge according to the amount of incident light is generated and accumulated in the n-type semiconductor region 22. In addition, electrons that cause a dark current generated at the interface of the substrate 12 are absorbed by holes, which are majority carriers in the p-type semiconductor regions 23, 24 formed on the front and back sides of the substrate 12, thereby suppressing the dark current. Moreover, each photoelectric conversion section 40 is electrically isolated by a pixel isolation layer 18 made of a p-type semiconductor region and an element isolation section 19 formed in the pixel isolation layer 18 .

[0026] In this embodiment, as shown in FIG. 3, the pixel transistor is composed of four transistors: a transfer transistor Tr1, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4.

[0027] As shown in Fig. 3, the transfer transistor Tr1 is composed of a floating diffusion section 30 formed in the center of four photoelectric conversion sections 40 formed in two rows and two columns, and a transfer gate electrode 16. As shown in Fig. 2, the floating diffusion section 30 is composed of an n-type semiconductor region formed by ion-implanting n-type impurities at a high concentration into a p-well layer 29 formed on the surface side of the substrate 12. The transfer gate electrode 16 is formed on the surface side of the substrate 12 between the photoelectric conversion section 40 and the floating diffusion section 30, with a gate insulating film 17 interposed therebetween.

[0028] Among the pixel transistors, the reset transistor Tr2, the amplification transistor Tr3, and the selection transistor Tr4 are formed for each of the four photoelectric conversion units 40 that share the floating diffusion unit 30. These pixel transistors are arranged on one side of a group formed of the four photoelectric conversion units 40 as shown in FIG.

[0029] The reset transistor Tr2 is composed of a pair of source-drain regions 35 and 36 and a reset gate electrode 32 formed between the source-drain regions 35, 36. The amplifier transistor Tr3 is composed of a pair of source-drain regions 36 and 37 and an amplifier gate electrode 33 formed between the source-drain regions 36, 37. The select transistor Tr4 is composed of a pair of source-drain regions 37 and 38 and a select gate electrode 34 formed between the source-drain regions 37, 38.

[0030] Although the cross-sectional configurations of the reset transistor Tr2, the amplification transistor Tr3, and the selection transistor Tr4 are not shown, these pixel transistors have the same configuration as the transfer transistor Tr1. That is, like the floating diffusion section 30, the source-drain regions 35-38 are composed of n-type high-concentration impurity regions formed in the p-well layer 29 on the surface of the substrate 12. The reset gate electrode 32, the amplification gate electrode 33, and the selection gate electrode 34 are formed on the surface side of the substrate 12 via the gate insulating film 17.

[0031] The element isolation section 19 is composed of a fixed charge film 20 and an insulating film 21, which are formed by sequentially embedding them in a groove 39 formed in the depth direction from the rear surface side of the substrate 12, and is formed by carving into a pixel isolation layer 18 formed in the substrate 12. That is, the element isolation section 19 is formed in a lattice shape so as to surround the pixels as shown in the figure. Furthermore, when a pixel transistor is formed between adjacent photoelectric conversion sections 40, the element isolation section 19 is arranged so as to overlap the floating diffusion section 30 and the source-drain region.

[0032] Moreover, the element isolation section 19 is formed to a depth that reaches the p-well layer 29 in which the pixel transistor is formed, but is formed to a depth that does not reach the floating diffusion section 30 or the source-drain region. If the depth of the floating diffusion section 30 or the source-drain region is less than 1 μm, the element isolation section 19 can be formed to a depth of about 0.25 to 5.0 μm from the surface of the substrate 12. In this embodiment, the element isolation section 19 is formed to a depth that reaches the p-well layer 29 of the pixel transistor, but it is not necessarily required that the depth reach the p-well layer 29 as long as the end of the element isolation section 19 on the back side of the substrate 12 is formed to be in contact with the p-type semiconductor layer. When the element isolation section 19 is formed in the pixel isolation layer 18 made of a p-type semiconductor layer as in this embodiment, the effect of insulation isolation can be obtained even if the structure does not reach the p-well layer 29.

[0033] The fixed charge film 20 formed in the groove 39 is formed on the inner peripheral surface and bottom surface of the groove 39, and is also formed on the entire back surface of the substrate 12. In the following description, the inner peripheral surface and bottom surface of the groove 39 are collectively referred to as the "inner wall surface". As the fixed charge film 20, it is preferable to use a material that can generate fixed charges and strengthen pinning by depositing on a substrate such as silicon, and a high refractive index material film or a high dielectric film having a negative charge can be used. As a specific material, for example, an oxide or nitride containing at least one element of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti) can be applied. As a film formation method, for example, a chemical vapor deposition method (hereinafter, CVD (Chemical Vapor Deposition) method), a sputtering method, an atomic layer deposition method (hereinafter, ALD (Atomic Layer Deposition) method), etc. can be mentioned. If the ALD method is used, a SiO2 film that reduces the interface state during film formation can be simultaneously formed to a thickness of about 1 nm. Other materials include oxides or nitrides containing at least one element selected from the group consisting of lanthanum (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y). Furthermore, the fixed charge film may be formed of a hafnium oxynitride film or an aluminum oxynitride film.

[0034] The material of the fixed charge film 20 may contain silicon (Si) or nitrogen (N) as long as the insulating properties are not impaired. The concentration is appropriately determined as long as the insulating properties of the film are not impaired. By adding silicon (Si) or nitrogen (N) in this way, it is possible to increase the heat resistance of the film and the blocking ability of ion implantation during the process.

[0035] In this embodiment, the fixed charge film 20 having a negative charge is formed on the inner wall surface of the groove 39 and the back surface of the substrate 12, and therefore an inversion layer is formed on the surface in contact with the fixed charge film 20. As a result, the silicon interface is pinned by the inversion layer, and the generation of dark current is suppressed. Furthermore, when the groove 39 is formed in the substrate 12, physical damage may occur on the sidewall and bottom surface of the groove 39, and depinning may occur around the groove 39. To address this problem, in this embodiment, the fixed charge film 20 having a large amount of fixed charge is formed on the sidewall and bottom surface of the groove 39, thereby preventing depinning.

[0036] The insulating film 21 is embedded in the groove 39 in which the fixed charge film 20 is formed, and is formed on the entire back surface of the substrate 12. The insulating film 21 is preferably formed from a material having a refractive index different from that of the fixed charge film 20, and examples of the material that can be used for the insulating film 21 include silicon oxide, silicon nitride, silicon oxynitride, and resin. The insulating film 21 can be made of a material that has no positive fixed charge or has a small amount of positive fixed charge.

[0037] Moreover, by embedding the grooves 39 in the insulating film 21, the photoelectric conversion units 40 constituting each pixel are separated via the insulating film 21. This makes it difficult for signal charges to leak into adjacent pixels, so that when signal charges exceeding the saturation charge amount (Qs) are generated, it is possible to reduce leakage of the overflowing signal charges into adjacent photoelectric conversion units 40. This makes it possible to suppress electronic color mixing.

[0038] In addition, the two-layer structure of the fixed charge film 20 and the insulating film 21 formed on the back side, which is the incident surface side of the substrate 12, acts as an anti-reflection film due to the difference in refractive index. This prevents the reflection of light incident from the back side of the substrate 12 at the back side of the substrate 12.

[0039] The light-shielding film 25 is formed in a desired region on the insulating film 21 formed on the back surface of the substrate 12, and in the pixel region, is formed in a lattice shape so as to open the photoelectric conversion section 40. That is, the light-shielding film 25 is formed in a position corresponding to the element isolation section 19. The material constituting the light-shielding film 25 may be any material that blocks light, and may be, for example, tungsten (W), aluminum (Al), or copper (Cu). The planarization film 26 is formed on the entire surface of the insulating film 21 including the light-shielding film 25, thereby flattening the surface on the back side of the substrate 12. The planarization film 26 may be made of an organic material such as a resin.

[0040] The color filter layer 27 is formed on the upper surface of the planarization film 26, and is formed to correspond to, for example, R (red), G (green), and B (blue) for each pixel. The color filter layer 27 transmits light of a desired wavelength, and the transmitted light is incident on the photoelectric conversion unit 40 in the substrate 12.

[0041] The on-chip lenses 28 are formed on the upper surface of the color filter layer 27. The on-chip lenses 28 condense the irradiated light, and the condensed light passes through the color filter layer 27 and efficiently enters each photoelectric conversion unit 40.

[0042] The wiring layer 13 is formed on the front surface side of the substrate 12, and is configured to have wiring 15 laminated in multiple layers (three layers in this embodiment) via an interlayer insulating film 14. The pixel transistor Tr constituting the pixel 2 is driven via the wiring 15 formed in the wiring layer 13.

[0043] The support substrate 31 is formed on the surface of the wiring layer 13 opposite to the surface facing the substrate 12. The support substrate 31 is configured to ensure the strength of the substrate 12 during the manufacturing stage, and is configured, for example, from a silicon substrate.

[0044] In the solid-state imaging device 1 having the above configuration, light is irradiated from the back surface side of the substrate 12, and the light transmitted through the on-chip lenses 28 and the color filter layer 27 is photoelectrically converted in the photoelectric conversion unit 40 to generate signal charges. The signal charges generated in the photoelectric conversion unit 40 are output as pixel signals by vertical signal lines formed of desired wiring 15 of the wiring layer 13 via pixel transistors formed on the front surface side of the substrate 12.

[0045] [1-3 Manufacturing method of solid-state imaging device] Next, a method for manufacturing the solid-state imaging device of this embodiment will be described below. Figures 4 and 5 are cross-sectional views showing the manufacturing process of the solid-state imaging device of this embodiment.

[0046] 4A, photoelectric conversion units 40, pixel transistors, and pixel separation layers 18 are formed on substrate 12, and then interlayer insulating films 14 and wiring 15 are alternately formed on the surface of substrate 12 to form wiring layer 13. Impurity regions such as photoelectric conversion units 40 formed on substrate 12 are formed by ion-implanting desired impurities from the surface side of substrate 12.

[0047] Next, a support substrate 31 (see FIG. 4B) made of a silicon substrate is bonded to the top layer of the wiring layer 13 and then inverted. The manufacturing process up to this point is the same as that of a normal back-illuminated solid-state imaging device. Although not shown in the drawings, generally, after inverting the substrate 12, the substrate 12 is polished from the back side to be thinned to a desired thickness.

[0048] Next, as shown in FIG. 4B, at the boundaries of each pixel of substrate 12, i.e., at the portions where pixel separation layers 18 are formed, groove portions 39 of a desired depth are formed by selectively etching from the rear surface side of substrate 12 in the depth direction.

[0049] In the step of forming the grooves 39, a hard mask (not shown) having desired openings is formed on the rear surface of the substrate 12, and the substrate is etched through the hard mask to form the grooves. In consideration of the spectroscopic characteristics, the depth of the grooves 39 is preferably 0.2 μm or more from the rear surface of the substrate 12, and more preferably 1.0 μm or more. In addition, the width of the grooves 39 is preferably 0.02 μm or more, depending on the spectroscopic characteristics. By setting the width of the grooves 39 to be wide, processing of the grooves 39 becomes easier, but the wider the width of the grooves 39, the lower the spectroscopic characteristics and the amount of saturated charge become, so it is more preferable that the width of the grooves 39 is about 0.02 μm.

[0050] In this embodiment, as shown in Fig. 4B, a groove 39 is formed to a depth that reaches the p-well layer 29 of the pixel transistor but does not reach the floating diffusion portion 30 or the source / drain region. Note that the process of forming the groove 39 can be performed in common with other substrate penetration processes, and in this case, the number of processes can be reduced.

[0051] Next, the hard mask used for processing the groove 39 is removed, and the fixed charge film 20 is formed by using a CVD method, a sputtering method, an ALD method, or the like so as to cover the sidewall and bottom surface of the groove 39 and the rear surface of the substrate 12, as shown in Fig. 5C. Thereafter, the insulating film 21 is formed by embedding the insulating film 21 in the groove 39 by using a CVD method, or the like, and the insulating film 21 is also formed on the upper surface of the fixed charge film 20 on the rear surface of the substrate 12.

[0052] Next, a light-shielding material layer is formed on the entire upper surface of the insulating film 21, and then the light-shielding material layer is patterned into a desired shape, thereby opening the photoelectric conversion unit 40 as shown in Fig. 5D, and forming a light-shielding film 25 that provides light shielding between adjacent pixels. Thereafter, the color filter layer 27 and the on-chip lens 28 are formed by a normal method, thereby completing the solid-state imaging device 1 shown in FIG.

[0053] As a result of the above, the solid-state imaging device 1 is formed in which pixels are separated by the element isolation portion 19 formed by embedding the insulating film 21 in the substrate 12. In the solid-state imaging device 1 of this embodiment, the photoelectric conversion section 40 of each pixel is separated by an element separation section 19 formed by embedding an insulating film 21 in a groove section 39. Therefore, leakage of signal charges accumulated in the photoelectric conversion section 40 to the adjacent photoelectric conversion section 40 can be reduced more than in the case of separation by only an impurity region. As a result, when signal charges equal to or greater than the saturation charge amount are generated in the photoelectric conversion section 40, the signal charges can be swept out more efficiently to the floating diffusion section 30. This suppresses the occurrence of blooming.

[0054] FIG. 6 shows the potential distribution during charge accumulation, and is a diagram for explaining a lateral overflow structure. FIG. 6 shows a potential distribution diagram of the substrate 12 in a portion where two adjacent photoelectric conversion units 40 and the transfer transistor Tr1 of the solid-state imaging device 1 of this embodiment are formed. Furthermore, FIG. 6 also shows, as a comparative example, a potential distribution diagram of the substrate in a portion where the photoelectric conversion units and the transfer transistor of a conventional solid-state imaging device are formed, in which adjacent photoelectric conversion units are separated only by an element isolation region 100 formed by ion implantation. In FIG. 6, the same reference numerals are given to parts corresponding to FIG. 2.

[0055] 6, in a conventional solid-state imaging device, in order to allow signal charges that exceed the saturation charge amount during charge accumulation to overflow laterally, the potential of the transfer gate is set deeper than the potential of the element isolation region 100 between two adjacent photoelectric conversion units 40. In this way, signal charges that exceed the saturation charge amount of a photoelectric conversion unit 40 do not flow toward the adjacent photoelectric conversion unit 40, but are swept out to the floating diffusion unit 30 through the transfer gate, thereby suppressing blooming.

[0056] Thus, when lateral overflow is adopted in a conventional solid-state imaging device, it is necessary to set the potential of the transfer gate deeper than the potential of the element isolation region 100 between two adjacent photoelectric conversion units 40. For this reason, it is necessary to set the potential of the transfer gate deeper by supplying a predetermined potential to the transfer gate electrode during charge accumulation, and the saturation charge amount (Qs) is accordingly reduced.

[0057] On the other hand, in the solid-state imaging device 1 of the present embodiment, adjacent photoelectric conversion units 40 are separated by an element separation unit 19. As a result, during charge accumulation, even if the potential of the transfer gate is shallow, signal charges that exceed the saturation charge amount of the photoelectric conversion unit 40 do not flow toward the adjacent photoelectric conversion unit 40, but are swept out to the floating diffusion unit 30.

[0058] In the solid-state imaging device 1 of the present embodiment, the photoelectric conversion section 40 is separated by the element isolation section 19 made of the insulating film 21, so that the potential of the element isolation section 19 is shallower by Δx1 than in the conventional case. Therefore, it is not necessary to deepen the potential of the transfer gate during charge accumulation. As shown in FIG. 6, the potential of the transfer gate can be shallower by Δx2 than in the conventional case, and as a result, the solid-state imaging device 1 of the present embodiment can increase the saturation charge amount compared to the conventional case. That is, in the solid-state imaging device 1 of the present embodiment, the saturation charge amount can be improved while suppressing blooming. In addition, it is not necessary to increase the electric field in the photoelectric conversion section 40 to improve the saturation characteristics, and the concentration of the n-type semiconductor region constituting the photoelectric conversion section 40 can be set low, so that it is possible to maintain white spots at a low level.

[0059] In addition, in the solid-state imaging device 1 of this embodiment, the fixed charge film 20 having a negative charge is formed in the groove portion 39. Therefore, the negative bias effect of the fixed charge film 20 can suppress the generation of an interface state, and the generation of a dark current caused by the interface state can be suppressed. Furthermore, an inversion layer (p-type) is formed on the surface in contact with the fixed charge film 20, and a positive charge is induced. Therefore, even if the p-well layer 29 and the pixel separation layer 18 made of a p-type semiconductor region are formed with a p-type impurity concentration that is about one order of magnitude lower than that of the conventional solid-state imaging device, the pixel separation function and the effect of suppressing dark current can be sufficiently exhibited.

[0060] In addition, in this embodiment, the p-well layer 29 and pixel separation layer 18 can be formed with a lower impurity concentration than in conventional solid-state imaging devices, so the n-type semiconductor region 22 constituting the photoelectric conversion unit 40 is not eroded by the p-type semiconductor region. This improves the amount of saturated charge. Furthermore, the p-type impurity concentration of the p-well layer 29 and pixel separation layer 18 can be set low, so that the generation of a strong electric field in the p-well layer 29 and pixel separation layer 18 can be suppressed, and the generation of noise can be suppressed.

[0061] Furthermore, by forming the element isolation portion 19 so as to be in contact with the p-well layer 29 which is at ground potential, the inversion layer (p-type) formed around the element isolation portion 19 is fixed and pinned at the ground potential, thereby suppressing the generation of dark current.

[0062] Furthermore, in the solid-state imaging device 1 of this embodiment, the element isolation portion 19 can be formed in a region that overlaps with the pixel transistor in the light incidence direction. Therefore, the element isolation portion 19 can be formed without affecting the layout of the pixel transistor, and there is no need to provide a separate region for the element isolation portion 19, so the pixel area does not increase.

[0063] The above describes an example in which four photoelectric conversion sections 40 share the required pixel transistors as one unit, but this is not limited to this, and various configurations are possible, such as an example in which two pixels are shared as one unit or a case in which pixel transistors are not shared.

[0064] [1-4 Variation 1] As a solid-state imaging device according to Modification 1 of the present embodiment, an example in which a two-pixel sharing unit in which a pixel transistor is shared by two photoelectric conversion units will be described. Fig. 7 shows a planar layout of the solid-state imaging device according to Modification 1. In Fig. 7, parts corresponding to those in Fig. 3 are given the same reference numerals and duplicated explanations will be omitted.

[0065] 7, the transfer transistor is composed of a floating diffusion section 30 formed in the center of two photoelectric conversion sections 40 formed in one row and two columns, and a transfer gate electrode 16. Among the pixel transistors, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4 are formed for each of the two photoelectric conversion sections 40 that share the floating diffusion section 30. The reset transistor Tr2, the amplification transistor Tr3, and the selection transistor Tr4 are disposed on one side of a group composed of two photoelectric conversion sections 40. Even in the case of two-pixel sharing, the element isolation section 19 is formed in a lattice shape so as to surround the photoelectric conversion section 40 of each pixel, and in the region in which the pixel transistor is formed, it is arranged in a region overlapping the pixel transistor.

[0066] The cross-sectional configuration including the transfer transistor Tr1 of the solid-state imaging device according to the first modification is also similar to that shown in FIG. Even in such a solid-state imaging device in which two shared pixels are used as one unit, the photoelectric conversion unit 40 of each pixel is insulated by the element isolation unit 19, so that the signal charge generated in each photoelectric conversion unit 40 is unlikely to leak into the photoelectric conversion unit 40 of an adjacent pixel. This makes it possible to obtain the same effects as in this embodiment, such as suppressing blooming while maintaining saturation characteristics.

[0067] [1-5 Variation 2] As a solid-state imaging device according to Modification 2 of the present embodiment, an example in which a pixel transistor is formed for each photoelectric conversion unit 40 of each pixel will be described. Fig. 8 shows a planar layout of a pixel region of the solid-state imaging device according to Modification 2. In Fig. 8, parts corresponding to those in Fig. 3 are given the same reference numerals, and duplicated explanations will be omitted.

[0068] In the second modification, a transfer transistor Tr1, a reset transistor Tr2, and an amplification transistor Tr3 are formed for each pixel, and no selection transistor is configured. The pixel transistors formed for each photoelectric conversion unit 40 are formed in one direction of the photoelectric conversion unit 40. The element isolation unit 19 is formed in a lattice shape so as to surround the photoelectric conversion unit 40 of each pixel, and is disposed in a region that partially overlaps with the pixel transistor.

[0069] Also, although the cross-sectional configuration of the solid-state imaging device according to the second modification is not shown, in the solid-state imaging device in the second modification, one floating diffusion section 30 is formed for each photoelectric conversion section 40. In the second modification as well, the photoelectric conversion section 40 of each pixel is insulated by the element isolation section 19, so that the signal charge generated in each photoelectric conversion section 40 is less likely to leak into the photoelectric conversion section 40 of an adjacent pixel. This makes it possible to obtain the same effects as in the present embodiment, such as suppressing blooming while maintaining saturation characteristics.

[0070] In this way, even in solid-state imaging devices having different layouts, the element isolation section 19 for the photoelectric conversion section 40 can have the same configuration.

[0071] 2. Second embodiment: solid-state imaging device Next, a solid-state imaging device according to a second embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device of this embodiment is the same as that of Fig. 1, and therefore will not be illustrated. Fig. 9 is a cross-sectional configuration diagram of a main part of a solid-state imaging device 52 of this embodiment. In Fig. 9, parts corresponding to those in Fig. 2 are given the same reference numerals, and duplicated explanations will be omitted.

[0072] A solid-state imaging device 52 of this embodiment is an example in which the configuration of an element isolation section 49 is different from that of the first embodiment. In the solid-state imaging device 52 of this embodiment, the element isolation section 49 is composed of a fixed charge film 20, an insulating film 48, and a light-shielding layer 50, which are embedded in this order in the groove section 39. The light-shielding layer 50 is formed in the depth direction of the groove section 39 in which the fixed charge film 20 and the insulating film 48 are formed, and is connected to a light-shielding film 25 formed on the back surface side of the substrate 12.

[0073] 10A to 10C are cross-sectional views showing the manufacturing process of the solid-state imaging device 52 of this embodiment. In this embodiment, the process up to the formation of the groove 39 is similar to the process described with reference to FIGS. 4A and 4B, so the subsequent processes will be described first.

[0074] After forming the groove 39 in the region surrounding the photoelectric conversion section 40, as shown in FIG. 10A, the fixed charge film 20 is formed so as to cover the inner wall surface of the groove 39 and the back surface side of the substrate 12. This fixed charge film 20 is formed in the same manner as in the first embodiment. Next, an insulating film 48 is formed in the groove 39 and on the back surface side of the substrate 12 so as to cover the fixed charge film 20. At this time, the insulating film 48 formed in the groove 39 is formed to a thickness that does not completely fill the groove 39. This insulating film 48 can be formed by using, for example, a sputtering method.

[0075] 10B, a light-shielding material layer 24a is formed so as to fill the entire groove 39 and cover the back surface side of the substrate 12. The light-shielding material layer 24a can be formed in the same manner as in the first embodiment, but it is preferable to use a material that has good embedding properties.

[0076] 10C, the light-shielding material layer 24a is patterned so that the light-shielding material layer remains at the boundary between adjacent pixels, thereby forming the light-shielding layer 50 embedded in the groove 39 and the light-shielding film 25 electrically connected to the light-shielding layer 50. Thereafter, the planarization film 26, the color filter layer 27, and the on-chip lens 28 are formed in this order using a normal manufacturing method, thereby completing the solid-state imaging device 52 of this embodiment.

[0077] In the solid-state imaging device 52 of this embodiment, a ground potential or a negative potential is supplied to the light-shielding film 25 and the light-shielding layer 50. By supplying a ground potential or a negative potential to the light-shielding film 25 and the light-shielding layer 50, it is possible to stabilize the hole pinning effect on the surface of the element isolation section 19. Furthermore, when a negative potential is supplied to the light-shielding film 25 and the light-shielding layer 50, an inversion layer is more likely to be formed on the surface of the substrate 12 that contacts the element isolation section 19, and the dark current suppression effect can be improved.

[0078] Furthermore, in this embodiment, since the light-shielding layer 50 is formed in the groove portion 39, it is possible to prevent obliquely incident light from being incident on the adjacent photoelectric conversion portion 40, thereby suppressing optical color mixing. In addition, the same effects as those of the first embodiment can be obtained.

[0079] 3. Third embodiment: solid-state imaging device Next, a solid-state imaging device according to a third embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device of this embodiment is the same as that of Fig. 1, and therefore will not be illustrated. Fig. 11 is a cross-sectional configuration diagram of a main part of a solid-state imaging device 55 of this embodiment. In Fig. 11, parts corresponding to those in Fig. 2 are given the same reference numerals, and duplicated explanations will be omitted.

[0080] The solid-state imaging device 55 of this embodiment is an example in which the pixel isolation layer 18 made of a p-type semiconductor region formed on the substrate 12 is not formed in the solid-state imaging device 1 according to the first embodiment. That is, in the solid-state imaging device 55 of this embodiment, the photoelectric conversion section 56 is isolated for each pixel only by the element isolation section 19. However, even in this case, the end of the element isolation section 19 on the front surface side is formed so as to contact the p-well layer 29 of the pixel transistor.

[0081] In the solid-state imaging device 55 of this embodiment, the photoelectric conversion section 56 is composed of a p-type semiconductor region 23 formed on the front side of the substrate 12, and an n-type semiconductor region 51 formed from the lower part of the p-type semiconductor region 23 to the rear side of the substrate 12. That is, in this embodiment, the n-type semiconductor region 51 serving as the charge accumulation region in the photoelectric conversion section 56 is formed larger than the n-type semiconductor region 22 serving as the charge accumulation region of the photoelectric conversion section 40 in the first embodiment. This makes it possible to further improve the amount of saturated charge.

[0082] In this embodiment, a pixel isolation layer is not formed to isolate the photoelectric conversion units 56 of each pixel with a p-type impurity region, and a p-type semiconductor region for suppressing dark current is not formed on the back side of the substrate 12. However, since the insulating film 20 having a negative fixed charge is formed in the element isolation unit 19, an inversion layer is formed on the surface in contact with the fixed charge film 20, and the generation of dark current can be suppressed. In this way, if at least the end of the element isolation unit 19 on the front side of the substrate 12 is in contact with a p-type semiconductor region such as a p-well layer 29 that electrically isolates adjacent n-type semiconductor regions 51, the leakage of charges between the photoelectric conversion units 56 can be sufficiently suppressed. In addition, the same effects as those of the first embodiment can be obtained.

[0083] 4. Fourth embodiment: solid-state imaging device Next, a solid-state imaging device according to a fourth embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device of this embodiment is the same as that of Fig. 1, and therefore will not be illustrated. Fig. 12 is a cross-sectional configuration diagram of a main part of a solid-state imaging device 57 of this embodiment. In Fig. 12, parts corresponding to those in Fig. 2 are given the same reference numerals, and duplicated explanations will be omitted.

[0084] The solid-state imaging device 57 of the present embodiment is an example in which a part of the element isolation portion 59 penetrates the substrate 12. As shown in Fig. 12, in a region not overlapping with a pixel transistor (the floating diffusion portion 30 of the transfer transistor Tr1 in Fig. 12), the element isolation portion 59 is formed to penetrate the substrate 12. That is, the element isolation portion 19 in the region not overlapping with the pixel transistor is composed of a fixed charge film 20 and an insulating film 21 which are embedded in order in a groove portion 60 formed to penetrate the substrate 12.

[0085] On the other hand, in the region overlapping with the pixel transistor, the end portion on the front surface side of the element isolation portion 19 is formed so as to contact the p-well layer 29 of the pixel transistor, as in the first embodiment. At this time, the end portion on the front surface side of the element isolation portion 19 is formed so as not to reach the floating diffusion portion 30 or the source / drain region that constitutes the pixel transistor.

[0086] 13 and 14 are cross-sectional views showing the manufacturing process of the solid-state imaging device 57 of this embodiment. In this embodiment, the process up to the process of forming the grooves 39 and 60 is the same as the process described with reference to FIG. 4A, so the process thereafter will be described.

[0087] In this embodiment, the substrate 12 on which the wiring layer 13 and the support substrate 31 are formed is inverted and thinned to a predetermined thickness, and then, as shown in Fig. 13A, grooves 39, 60 of different depths are formed. In a region where an element isolation portion 59 penetrating the substrate 12 is to be formed, a groove 60 penetrating the substrate 12 is formed, and in a region where an element isolation portion 19 that does not penetrate the substrate is to be formed, a groove 39 is formed to a depth that reaches the p-well layer 29 of the pixel transistor. These grooves 39, 60 of different depths can be formed by performing an etching process divided into multiple stages.

[0088] Next, as shown in FIG. 13B, the fixed charge film 20 and the insulating film 21 are formed in the grooves 39 and 60 having different depths in the same manner as in FIG. 5C, whereby the element isolation parts 19 and 59 having different depths can be formed.

[0089] Thereafter, a light-shielding material layer is formed on the entire upper surface of the insulating film 21, and then the light-shielding material layer is patterned into a desired shape, thereby opening the photoelectric conversion unit 40 as shown in Fig. 14C, and forming a light-shielding film 25 that provides light shielding between adjacent pixels. Thereafter, a color filter layer 27 and an on-chip lens 28 are formed by a normal method, thereby completing the solid-state imaging device 57 shown in FIG.

[0090] In the solid-state imaging device 57 of this embodiment, in the region other than the region overlapping with the pixel transistor, the element isolation portion 59 is formed penetrating the substrate 12, so that it is possible to further reduce leakage of signal charges between adjacent photoelectric conversion portions 40. This can enhance the effect of suppressing blooming. In addition, it is possible to obtain the same effects as the first embodiment.

[0091] 5. Fifth embodiment: solid-state imaging device Next, a solid-state imaging device according to a fifth embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device of this embodiment is the same as that of Fig. 1, and therefore will not be illustrated. Fig. 15 is a cross-sectional configuration diagram of a main part of a solid-state imaging device 64 of this embodiment. In Fig. 15, parts corresponding to those in Fig. 2 are given the same reference numerals, and duplicated explanations will be omitted.

[0092] The solid-state imaging device 64 of this embodiment is an example in which, in a solid-state imaging device 52 of the second embodiment, a device isolation portion 62 that penetrates the substrate 12 in a part of the pixel region (e.g., an edge) is provided, and a light-shielding layer 63 that is exposed on the surface side of the substrate 12 is formed within the device isolation portion 62.

[0093] The element isolation portion 62 penetrating the substrate 12 is composed of a groove portion 60 formed penetrating the substrate 12, and a fixed charge film 20, an insulating film 48, and a light-shielding layer 63 formed in this groove portion 60 in this order, and the light-shielding layer 63 is formed so as to be exposed on the surface side of the substrate 12. The light-shielding layer 63 formed so as to be exposed on the surface side of the substrate 12 is connected to a desired wiring 15 via a contact portion 61 formed in the interlayer insulating film 14 constituting the wiring layer 13. A ground potential or a negative potential is supplied to the light-shielding layer 63 from the wiring 15, so that the ground potential or a negative potential is supplied to the light-shielding layer 50 and the light-shielding film 25 formed in the pixel region.

[0094] When manufacturing the solid-state imaging device 64 of this embodiment, first, the grooves 39 and 60 having different depths are formed in the same manner as in FIG. 13A, and then the fixed charge film 20 and the insulating film 48 are formed in the same manner as in FIG. 10A. After that, only the fixed charge film 20 and the insulating film 48 formed on the bottom surface of the groove 60 penetrating the substrate 12 are removed by etching back. Then, in a state in which the wiring layer 13 is exposed on the bottom surface of the groove 60 penetrating the substrate 12, a light-shielding material is embedded in the grooves 39 and 60, and a light-shielding material is formed on the back side of the substrate 12, and patterned into a desired shape, thereby forming the light-shielding layers 50 and 63 and the light-shielding film 25. As a result, the light-shielding layer 50 penetrating the substrate 12 can be drawn to the wiring layer 13 side, and a desired potential can be supplied to the light-shielding layer 50 from the wiring 15 of the wiring layer 13. In this embodiment, in the process of forming the wiring layer 13, the contact portion 61 connected to the light-shielding layer 63 is formed in advance.

[0095] In the solid-state imaging device 64 of this embodiment, a part of the element isolation parts 62 is formed to penetrate the substrate 12, so that the light-shielding layer 63 can be drawn out to the wiring layer 13 side of the substrate 12. In addition, the electrical connection between the light-shielding film 25 and the light-shielding layers 50 and 63 and the wiring 15, and the element isolation parts 19 and 62 can be manufactured in the same process, which makes it possible to reduce the number of processes. In addition, the same effects as those of the solid-state imaging devices according to the first and second embodiments can be obtained.

[0096] 6. Sixth embodiment: Solid-state imaging device Next, a solid-state imaging device according to a sixth embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device of this embodiment is the same as that of Fig. 1, and therefore will not be illustrated. Fig. 16 is a cross-sectional configuration diagram of a main part of a solid-state imaging device 41 of this embodiment. In Fig. 16, parts corresponding to those in Fig. 2 are given the same reference numerals, and duplicated explanations will be omitted.

[0097] A solid-state imaging device 41 of this embodiment differs from that of the first embodiment in the configuration of an element isolation section 42. In this embodiment, the element isolation section 42 includes a first fixed charge film 43, a second fixed charge film 44, a first insulating film 45, and a second insulating film 46, which are formed by being embedded in the groove section 39 in this order. In this embodiment, the side surface of the groove section 39 is tapered, and the opening diameter is formed to become smaller in the depth direction of the substrate 12. Each film formed in the groove section 39 and on the back surface of the substrate 12 will be described below together with the manufacturing method thereof.

[0098] The first fixed charge film 43 is formed so as to cover the inner wall surface of the groove portion 39 and the rear surface of the substrate 12, and is formed by using a CVD method or an ALD method. The first fixed charge film 43 may be formed of the same material as the fixed charge film 20 in the first embodiment.

[0099] When the first fixed charge film 43 is formed by using the CVD method or the ALD method, a SiO2 film that reduces the interface state is formed simultaneously during the film formation. This SiO2 film is preferably formed to a thickness of about 1 nm. When excluding the thickness of the SiO2 film formed at the substrate interface, the first fixed charge film 43 is preferably formed to a thickness of 3 nm or more, for example, 3 nm or more and 20 nm or less.

[0100] The second fixed charge film 44 is formed in the groove 39 and on the back surface of the substrate 12 so as to cover the first fixed charge film 43, and is formed, for example, by using a physical vapor deposition (PVD) method. As with the first fixed charge film 43, the second fixed charge film 44 may be formed from the same material as the fixed charge film 20 in the first embodiment. The second fixed charge film 44 may be formed from the same material as the first fixed charge film 43, or may be formed from a different material.

[0101] The second fixed charge film 44 is preferably formed to a thickness of, for example, 40 nm or more and 60 nm or less on the back surface of the substrate 12. By forming the second fixed charge film 44 to a thickness of 40 nm or more and 60 nm or less, the pinning effect on the back surface side of the substrate 12 and the effect of the anti-reflection film described later can be obtained more reliably.

[0102] The first insulating film 45 is formed in the groove 39 and on the back surface of the substrate 12 so as to cover the second fixed charge film 44, and is made of an anisotropic oxide film formed by a PVD method or a CVD method, for example, an oxide film containing a TEOS (Tetra Ethyl Ortho Silicate) material or a silane material. The first insulating film 45 is preferably formed on the back surface of the substrate 12 with a thickness of, for example, 0 nm or more and 600 nm or less.

[0103] The second insulating film 46 is formed in the groove 39 and on the back surface of the substrate 12 so as to cover the first insulating film 45, and in this embodiment, is formed of an isotropic oxide film, such as a silicon oxide film, formed by the ALD method or the CVD method. In this embodiment, the groove 39 is entirely filled with the second insulating film 46. The second insulating film 46 is preferably formed on the back surface of the substrate 12 with a thickness of, for example, 0 nm to 300 nm, and is formed so that the combined thickness of the first insulating film 45 and the second insulating film 46 is 10 nm to 900 nm, preferably 50 nm to 700 nm, and more preferably 100 nm to 500 nm.

[0104] In addition, the laminated film formed on the back surface side of the substrate 12 and inside the groove 39 and made up of the first fixed charge film 43, the second fixed charge film 44, the first insulating film 45 and the second insulating film 46 also serves as an anti-reflection film. In the present embodiment, a case where two insulating films, the first insulating film 45 and the second insulating film 46, are formed has been described, but the present disclosure is not limited to this, and it is sufficient to form either the first or second insulating film 45, 46. Also, a case where an anisotropic oxide film is formed as the first insulating film 45 and an isotropic oxide film is formed as the second insulating film 46 has been described, but the reverse may be true. Furthermore, the inner surface of the groove portion 39 may have a structure in which all or part of the first fixed charge film 43, the second fixed charge film 44, the first insulating film 45 and the second insulating film 46 are laminated, or a structure in which none of the above films are laminated.

[0105] 7. Seventh embodiment: solid-state imaging device Next, a solid-state imaging device according to a seventh embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device of this embodiment is the same as that of Fig. 1, and therefore will not be illustrated. Fig. 17 is a cross-sectional configuration diagram of a main part of a solid-state imaging device 47 of this embodiment. In Fig. 17, parts corresponding to those in Fig. 2 are given the same reference numerals, and duplicated explanations will be omitted.

[0106] The solid-state imaging device 47 of this embodiment differs from the first embodiment in that the element isolation section 53 has a hollow structure. In this embodiment, as shown in Fig. 17, the element isolation section 53 has a fixed charge film 20 and an insulating film 54 which are formed by being embedded in order in a groove section 39 formed in the depth direction from the rear surface side of the substrate 12, and a hollow section (so-called void) 58 is formed inside the groove section 39.

[0107] The insulating film 54 is formed so as to cover the inner wall surface of the groove 39 and the fixed charge film 20 formed on the back surface of the substrate 12. In order to form a hollow portion 58 in the groove 39, the insulating film 54 is formed to a thickness that does not completely fill the groove 39 inside the groove 39, and is formed so as to close the groove 39 at the open end of the groove 39. The insulating film 54 can be formed from the same material as the insulating film 21 used in the first embodiment.

[0108] 18A and 18B show the manufacturing process of the solid-state imaging device 47 of this embodiment. The process up to the formation of the groove 39 is the same as that of the first embodiment, and therefore a duplicated description will be omitted. After the groove 39 is formed, as shown in FIG. 18A, a fixed charge film 20 is formed by using a CVD method, a sputtering method, an ALD method, or the like so as to cover the inner periphery and bottom surface of the groove 39 and the rear surface of the substrate 12.

[0109] 18B, an insulating film 54 is formed by using a CVD method, a sputtering method, a coating method, or the like so as to cover the inner wall surface of the groove portion 39 and the fixed charge film 20 formed on the back surface of the substrate 12. In the film forming process of this insulating film 54, the film forming conditions are set so that the opening end side of the groove portion 39 is blocked before the inside of the groove portion 39 is completely filled with the insulating film 54. In this way, by optimizing the film forming conditions, it is possible to form an element isolation portion 53 having a hollow portion 58 as shown in FIG. 18B.

[0110] The inside of the hollow portion 58 formed in the element isolation portion 53 may be filled with air or may be in a vacuum state. In order to prevent light from entering the portion close to the incident side, it is more preferable that the hollow portion exists from the silicon surface (the interface between the substrate 12 and the fixed charge film 20) on the back side to the upper portion (the light incident side).

[0111] Thereafter, the solid-state imaging device 47 of this embodiment shown in Fig. 17 is completed by the same process as in the first embodiment. In this embodiment, the refractive index of the hollow portion 58 is 1, and the refractive indexes of the fixed charge film 20 and the insulating film 54 are both 1 or more, so that light reflection is likely to occur in the element isolation portion 53, and optical color mixing can be suppressed. As a result, in this embodiment, the optical light blocking property can be improved in the element isolation portion 53. Also, in this embodiment, the same effects as in the first embodiment can be obtained.

[0112] In this embodiment, the fixed charge film 20 is formed in the element isolation portion 53, but it is not necessary to form the fixed charge film 20. In this case as well, an insulating material having a refractive index greater than 1 is used as a material for forming the insulating film, and the insulating film is formed so as to form a hollow portion inside the groove portion 39, thereby improving the optical light blocking property and suppressing optical color mixing.

[0113] 8. Eighth embodiment: solid-state imaging device Next, a solid-state imaging device according to an eighth embodiment of the present disclosure will be described. The overall configuration of the solid-state imaging device of this embodiment is the same as that of Fig. 1, and therefore will not be illustrated. Fig. 19 is a cross-sectional configuration diagram of a main part of a solid-state imaging device 65 of this embodiment. In Fig. 19, parts corresponding to those in Fig. 2 are given the same reference numerals, and duplicated explanations will be omitted.

[0114] A solid-state imaging device 65 of this embodiment is the same as that of the seventh embodiment in that the element isolation section 66 has a hollow structure, but is different in the film structure and the film formation method thereof in the element isolation section 66. In this embodiment, as shown in Fig. 19, the element isolation section 66 has a first film 67 and a second film 68 formed by being embedded in order in a groove section 39 formed in the depth direction from the rear surface side of the substrate 12, and a hollow section 58 is formed inside the groove section 39.

[0115] The first film 67 is formed so as to cover the inner wall surface of the groove portion 39 and the rear surface of the substrate 12, and the second film 68 is laminated on the first film 67 and formed on the inner wall surface of the groove portion 39 and the rear surface of the substrate 12. In the groove portion 39, the opening end side of the groove portion 39 is blocked by the first film 67 and the second film 68 with a hollow portion 58 formed therein.

[0116] As will be described later, the first film 67 is formed by an anisotropic film formation method and is provided so as to narrow the opening diameter at the opening end side of the groove portion 39. On the other hand, the second film 68 is formed by an isotropic film formation method and is provided so as to close the opening end of the groove portion 39 narrowed by the first film 67.

[0117] The first film 67 and the second film 68 can be formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, resin, etc. The first film 67 and the second film 68 may be formed using the same material or different materials. When the first film 67 and the second film 68 are formed using different materials, it is preferable to select materials that satisfy the conditions that the film stress of the first film 67 is smaller than the film stress of the second film 68 and the refractive index of the first film 67 is larger than the refractive index of the second film 68. In this embodiment, as an example, a case where both the first film 67 and the second film 68 are formed using silicon oxide will be described.

[0118] 20A and 20B show the manufacturing process of a solid-state imaging device 65 of this embodiment. The process up to the formation of the groove 39 is similar to that of the first embodiment, and therefore a duplicated description will be omitted. After the formation of the groove 39, a first film 67 made of silicon oxide is formed as shown in FIG. 20A. The first film 67 is formed by an anisotropic film formation method, such as a plasma CVD method or a PVD method.

[0119] Since the first film 67 is formed anisotropically, the film thickness of the first film 67 on the bottom surface of the groove 39 and on the back surface of the substrate 12 is thicker than the film thickness of the first film 67 on the inner peripheral surface of the groove 39. Therefore, due to the difference in film formation rate between the back surface of the substrate 12 and the inner peripheral surface of the groove 39, the first film 67 has an overhanging shape on the opening end side of the groove 39, as shown in Fig. 20A, and the opening diameter on the opening end side of the groove 39 is smaller than the opening diameter on the bottom surface side of the groove 39. Here, the first film 67 is formed to a thickness that does not completely block the groove 39.

[0120] 20B, a second film 68 made of silicon oxide is formed. The second film 68 is formed using an isotropic method, for example, an ALD method. Since the second film 68 is formed isotropically, the second film 68 is formed on the inner wall surface of the groove portion 39 and the back surface of the substrate 12 with approximately the same thickness on the first film 67.

[0121] The second film 68 is formed to a thickness that closes the groove 39 at the opening end side of the groove 39. In this embodiment, the first film 67 narrows the opening diameter of the groove 39 at the opening end side to be smaller than the opening diameter of the bottom side of the groove 39. Therefore, the second film 68 closes the opening end side while maintaining the hollow structure of the groove 39. This forms a hollow portion 58 in the groove 39. Even if the first film 67 is isotropically formed and the second film 68 is anisotropically formed, it is possible to close the opening end side while maintaining the hollow structure of the groove 39. In this embodiment, too, in order to prevent light from entering the area close to the incident side, it is more preferable that the hollow portion exists from the silicon surface (the interface between the substrate 12 and the first film 67) on the back side to the upper part (the light incident side).

[0122] Thereafter, a solid-state imaging device 65 of this embodiment shown in Fig. 19 is completed by the same steps as in the first embodiment. In this embodiment, too, the hollow portion 58 is formed in the element isolation portion 66, so that the same effect as in the seventh embodiment can be obtained.

[0123] In this embodiment, the element isolation section 66 is formed of two layers of films, the first film 67 and the second film 68, but may be formed of three or more layers of films as necessary. When the element isolation section 66 is formed of two or more layers of films as in this embodiment, if the stress of the material deposited first is lower than the stress of the material deposited later, the stress on the substrate 12 can be suppressed, and the occurrence of dark current and white spots due to the stress can be suppressed. Furthermore, by making the refractive index of the material deposited later lower than the refractive index of the material deposited earlier, optical color mixing can be suppressed.

[0124] Also in this embodiment, a film having a negative fixed charge (corresponding to the fixed charge film 20 in FIG. 2) may be formed between the first film 67 and the substrate 12. The same material as in the first embodiment can be used for this fixed charge film.

[0125] Furthermore, the second film 68 may be formed of a metal material such as tungsten (W), aluminum (Al), titanium (Ti), or an oxide or nitride thereof. When the second film 68 is formed of a metal material, it is necessary to remove the metal material film formed on the light incident side of the photoelectric conversion unit 40. Below, as a modified example, a case where the first film 67 is formed of silicon oxide and the second film 68 is formed of a metal material will be described.

[0126] [8-1 Modifications] Fig. 21 is a cross-sectional view of a solid-state imaging device 70 according to a modified example. In Fig. 21, parts corresponding to those in Fig. 19 are given the same reference numerals, and duplicated explanations will be omitted. In the solid-state imaging device 70 according to the modified example, a second film 71 constituting an element isolation portion 72 is different from that of this embodiment.

[0127] In the modified example, the second film 71 is made of, for example, tungsten (W) and is formed so as to cover the first film 67 on the inner wall surface of the groove portion 39 and in the light-shielding region on the back surface side of the substrate 12. That is, on the back surface side of the substrate 12, the second film 71 is formed in a region corresponding to the position where the light-shielding film 25 is formed, and is provided in a lattice shape so as to open the photoelectric conversion portion 40.

[0128] In the modified example, as in the present embodiment, the second film 71 is formed on the surface of the first film 67 using an isotropic film formation method. Then, on the rear surface side of the substrate 12, a light-shielding material layer that becomes the light-shielding film 25 is formed on the entire upper surface of the second film 71, and then the light-shielding material layer and the second film 71 are simultaneously patterned to remove the second film 71 from above the photoelectric conversion section 40. Thereafter, the solid-state imaging device 70 shown in FIG. 21 can be fabricated by the same process as in the first embodiment.

[0129] As shown in the modification, when the film formed in the groove 39 is formed using a metal material, the metal material above the photoelectric conversion unit 40 can be removed by patterning the film simultaneously with the patterning process of the light-shielding film 25 formed on the back surface side of the substrate 12. In addition, in the modification, the light-shielding film 25 is formed, but if sufficient light shielding can be achieved with only the second film 71, the light-shielding film 25 does not need to be provided separately. In this case, the number of layers of films formed on the light incident surface side of the substrate 12 can be reduced, so that the distance between the surface of the on-chip lens 28 and the substrate 12 can be shortened, and the sensitivity can be improved.

[0130] Also, in the solid-state imaging device 70 according to the modification, similarly to the second embodiment, a ground potential or a negative potential may be supplied to the second film 71 made of a metal material. By supplying a ground potential or a negative potential to the second film 71, the hole pinning effect on the surface of the element isolation portion 72 can be stabilized, and dark current can be suppressed.

[0131] In the seventh and eighth embodiments, the opening end side of groove 39 is closed by a film formed in groove 39, but it is sufficient if hollow portion 58 in groove 39 can be closed by a film formed on the back surface side of substrate 12. Therefore, it is not always necessary for the opening end side of groove 39 to be closed by a film formed in groove 39.

[0132] Although the solid-state imaging devices according to the first to eighth embodiments have been described above using CMOS-type solid-state imaging devices as examples, they can also be applied to back-illuminated CCD-type solid-state imaging devices. In this case, too, the same effects as those in the first to fifth embodiments can be obtained by forming an element isolation section that electrically isolates the photoelectric conversion section by embedding an insulating film in a groove section formed on the surface opposite to the light incidence surface.

[0133] Furthermore, in the solid-state imaging devices according to the first to eighth embodiments, a lateral overflow structure is used in which the signal charge overflowing into the floating diffusion section is overflowed. However, the present disclosure is not limited to such a configuration, and the signal charge may be overflowed into the source-drain region of another pixel transistor. For example, the signal charge overflowing into a region to which a VDD potential is supplied, such as the drain region of a reset transistor, may be overflowed.

[0134] In addition, in the solid-state imaging devices according to the first to eighth embodiments, a configuration in which negative charges (electrons) are used as signal charges has been shown, but the present disclosure can also be applied to a case in which positive charges (holes) are used as signal charges. When holes are used as signal charges, a material having a positive fixed charge may be used as the fixed charge film, and the p-type region and the n-type region in the substrate may be configured inversely. In other words, a configuration in which a material having the same fixed charge as the signal charge is used as the fixed charge film may be used.

[0135] In addition, although the device isolation section is configured to form a fixed charge film in the groove and further embed an insulating film, the configuration of the present disclosure can be achieved by embedding only the fixed charge film in the groove. It is also possible to combine the first to eighth embodiments as appropriate. In addition, in the first to eighth embodiments, the device isolation section is formed in a lattice shape surrounding the photoelectric conversion section, but it does not have to be in a lattice shape, and various configurations are possible.

[0136] Furthermore, the present disclosure is not limited to application to solid-state imaging devices that detect the distribution of the amount of incident visible light and capture it as an image, but can also be applied to solid-state imaging devices that capture the distribution of incident amounts of infrared rays, X-rays, particles, etc. In a broad sense, the present disclosure can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture them as images.

[0137] Furthermore, the present disclosure is not limited to a solid-state imaging device that scans each unit pixel of a pixel region in sequence by row and reads out a pixel signal from each unit pixel, but can also be applied to an XY address type solid-state imaging device that selects an arbitrary pixel by pixel and reads out a signal from the selected pixel by pixel. The solid-state imaging device may be formed as a single chip, or may be in the form of a module having an imaging function in which a pixel region and a signal processing unit or an optical system are packaged together.

[0138] In addition, the present disclosure is not limited to application to solid-state imaging devices, but can also be applied to imaging devices. Here, the imaging device refers to a camera system such as a digital still camera or video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-mentioned modular form mounted on the electronic device, i.e., a camera module, may also be considered as an imaging device.

[0139] 9. Ninth embodiment: Electronic device Next, an electronic device according to a ninth embodiment of the present disclosure will be described. Fig. 22 is a schematic configuration diagram of an electronic device 200 according to the ninth embodiment of the present disclosure.

[0140] The electronic device 200 according to this embodiment includes a solid-state imaging device 203, an optical lens 201, a shutter device 202, a drive circuit 205, and a signal processing circuit 204. The electronic device 200 according to this embodiment illustrates an embodiment in which the solid-state imaging device 1 according to the first embodiment of the present disclosure described above is used as the solid-state imaging device 203 in an electronic device (camera).

[0141] The optical lens 201 focuses image light (incident light) from a subject on the imaging surface of the solid-state imaging device 203. This causes the signal charge to accumulate for a certain period in the solid-state imaging device 203. The shutter device 202 controls the light irradiation period and light blocking period for the solid-state imaging device 203. The drive circuit 205 supplies drive signals that control the transfer operation of the solid-state imaging device 203 and the shutter operation of the shutter device 202. The drive signals (timing signals) supplied from the drive circuit 205 transfer signals from the solid-state imaging device 203. The signal processing circuit 204 performs various signal processing. The video signal that has undergone signal processing is stored in a storage medium such as a memory, or is output to a monitor.

[0142] In the electronic device 200 of this embodiment, the solid-state imaging device 203 suppresses blooming and improves saturation characteristics, thereby improving image quality.

[0143] The electronic device 200 to which the solid-state imaging device 1 can be applied is not limited to a camera, but can also be applied to imaging devices such as digital still cameras and camera modules for mobile devices such as mobile phones.

[0144] In this embodiment, the solid-state imaging device 1 in the first embodiment is used in an electronic device as the solid-state imaging device 203, but the solid-state imaging devices manufactured in the second to eighth embodiments described above can also be used.

[0145] The present disclosure may also be configured as follows. (1) A substrate; A plurality of photoelectric conversion units formed on the substrate; having the plurality of photoelectric conversion units include a first photoelectric conversion unit and a second photoelectric conversion unit, The first photoelectric conversion unit and the second photoelectric conversion unit are formed adjacent to each other, a first groove portion between the first photoelectric conversion portion and the second photoelectric conversion portion; a first insulating film having a fixed charge formed so as to cover an inner wall surface of the first groove and a light incident surface side of the substrate; In a cross section cut in a light incident direction, a semiconductor region of a first conductivity type is formed in a region adjacent to the periphery of the first groove portion and on the light incident surface side of the substrate. Solid-state imaging device. (2) a semiconductor region of a first conductivity type is formed between the first photoelectric conversion portion and the first groove portion in a cross section in a light incidence direction; In a cross section in a light incidence direction, a semiconductor region of a first conductivity type is formed between the second photoelectric conversion section and the first groove section. A solid-state imaging device according to (1). (3) The bottom of the first groove is formed so as to be in contact with a semiconductor region of a first conductivity type in a cross section in a light incidence direction. A solid-state imaging device according to (1) or (2). (4) A part of the first groove is formed by being embedded in a semiconductor region of a first conductivity type. The solid-state imaging device according to any one of (1) to (3). (5) The charge storage regions of the plurality of photoelectric conversion units are formed of a semiconductor region of a second conductivity type that is an opposite conductivity type to the first conductivity type. A solid-state imaging device according to any one of (1) to (4). (6) A second insulating film is formed so as to cover the first insulating film. The solid-state imaging device according to any one of (1) to (5). (7) The first insulating film is formed containing hafnium oxide. A solid-state imaging device according to any one of (1) to (6). (8) The second insulating film is formed containing any one of silicon oxide, silicon nitride, and silicon oxynitride. A solid-state imaging device according to (6). (9) the plurality of photoelectric conversion units includes a third photoelectric conversion unit, the third photoelectric conversion unit is formed adjacent to the second photoelectric conversion unit, a second groove portion between the second photoelectric conversion portion and the third photoelectric conversion portion; a first insulating film having a fixed charge formed so as to cover an inner wall surface of the second groove; a semiconductor region of a first conductivity type is formed in the second groove portion so as to be in contact with a periphery of the second groove portion in a cross section cut in a light incident direction; The first groove portion and the second groove portion are formed at different depths in the light incidence direction. The solid-state imaging device according to any one of (1) to (8). (10) An interlayer insulating film and a plurality of wiring layers are formed on the opposite side of the light incident surface of the substrate. The solid-state imaging device according to any one of (1) to (9). (11) The interlayer insulating film and the wiring layers are formed on the opposite side of the light incident surface of the substrate from the photoelectric conversion units. A solid-state imaging device according to (10). (12) A pixel transistor is formed on the opposite side of the substrate from the light incident surface. A solid-state imaging device according to (10) or (11). (13) The pixel transistor is formed in a region overlapping the first groove in a light incident direction. A solid-state imaging device according to (12). (14) The second groove is formed to a depth that reaches the interlayer insulating film. The solid-state imaging device according to any one of (10) to (13). (15) A light-shielding film is formed above the light-incident surface side of the first groove portion. The solid-state imaging device according to any one of (1) to (14). (16) A floating diffusion is formed below the first groove portion on the opposite side to the light incidence surface. The solid-state imaging device according to any one of (1) to (15). (17) The first insulating film is formed on the light incident surface side of the first photoelectric conversion section and the second photoelectric conversion section. The solid-state imaging device according to any one of (1) to (16). (18) The second insulating film is formed by being embedded in the first trench. The solid-state imaging device according to any one of (6) to (17). (19) A third insulating film is formed on the light incident surface side of the substrate. The solid-state imaging device according to any one of (1) to (18). (20) An optical lens; A solid-state imaging device according to any one of (1) to (19), a signal processing circuit for processing an output signal output from the solid-state imaging device; Electronic devices, including [Explanation of symbols]

[0146] 1, 52, 55, 57, 64...solid-state imaging device, 2...pixel, 3...pixel region, 4...vertical drive circuit, 5...column signal processing circuit, 6...horizontal drive circuit, 7...output circuit, 8...control circuit, 10...horizontal signal line, 11, 12...substrate, 13...wiring layer, 14...interlayer insulating film, 15...wiring, 16...transfer gate electrode, 17...gate insulating film, 18...pixel isolation layer, 19...element isolation section, 20...fixed charge film, 21...insulating film, 22...n-type semiconductor region, 23, 24...p-type semiconductor region, 25...light-shielding film, 26...planarizing film, 27...color filter layer, 28... On-chip lens, 29 p-well layer, 30 floating diffusion portion, 31 support substrate, 32 reset gate electrode, 33 amplifying gate electrode, 34 select gate electrode, 35, 36, 37 source / drain regions, 39, 60 groove portion, 40 photoelectric conversion portion, 48 insulating film, 49 element isolation portion, 50 light shielding layer, 51 n-type semiconductor region, 51 light shielding material layer, 52 solid-state imaging device, 200 electronic device, 201 optical lens, 202 shutter device, 203 solid-state imaging device, 204 signal processing circuit, 205 driving circuit

Claims

1. A substrate; A first photoelectric conversion unit provided on the substrate; a second photoelectric conversion unit provided on the substrate and adjacent to the first photoelectric conversion unit; a wiring layer provided on a surface of the substrate opposite to the light incidence surface; a first element isolation trench provided between the first photoelectric conversion unit and the second photoelectric conversion unit; a first insulating film having a fixed charge, the first insulating film being provided above a light incident surface of the first photoelectric conversion unit and the second photoelectric conversion unit and in the first element isolation trench; the first element isolation trench includes a light-shielding layer to which a negative potential is supplied; The light-shielding layer is connected to a light-shielding film provided on the substrate. Solid-state imaging device.

2. The first element isolation trench has a trench portion penetrating the substrate. The solid-state imaging device according to claim 1 .

3. Silicon oxide is formed on the inner wall of the first element isolation trench. The solid-state imaging device according to claim 2 .

4. The light-shielding film contains a metal.

4. The solid-state imaging device according to claim 1.

5. The first insulating film is an oxide film.

5. The solid-state imaging device according to claim 1.

Images