Method and apparatus for measuring the position of a substrate on a heater pedestal - Patents.com
Patent Information
- Application Number
- JP2023082439
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2019-08-20
- Filing Date
- 2023-05-18
- Publication Date
- 2025-03-06
- Estimated Expiration
- 2039-08-22
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Abstract
Description
[Technical field]
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 62 / 726,887, filed September 4, 2018, which claims the benefit of U.S. Provisional Application No. 16 / 545,824, filed August 20, 2019, the entire contents of which are incorporated herein by reference. [Background technology]
[0002] FIELD OF THE DISCLOSURE
[0002] Embodiments relate to the field of semiconductor manufacturing, and more particularly to a method and apparatus for centering a wafer on a heated pedestal.
[0003] 2. Description of Related Art In the processing of substrates, such as semiconductor wafers, the substrate may be placed on a heated pedestal for various manufacturing steps. Typically, the heated pedestal includes a flat surface on which the substrate rests and an annular ring (also referred to as a pocket) that surrounds the substrate. The annular ring is generally thicker than the substrate being processed.
[0004] Ideally, to provide uniform processing across the substrate, the substrate should be centered on the annular ring; that is, the center point of the substrate should coincide with the center point of the annular ring. Currently, alignment of the substrate to the annular ring is performed by eye, which does not provide the precision required to ensure uniform processing. To verify that the substrate placement is proper, an on-wafer uniformity test can be performed. Such a test requires several hours to perform and is expensive due to the expense of the test wafer. Summary of the Invention
[0005] An embodiment disclosed herein includes a method of determining a position of a sensor wafer relative to a pedestal. In one embodiment, the method includes placing a sensor wafer on a pedestal, the sensor wafer having a first surface supported by the pedestal, a second surface opposite the first surface, and an end surface connecting the first surface to the second surface, with a plurality of sensor regions formed on the end surface, and the pedestal having a major surface and an annular wall surrounding the sensor wafer. In one embodiment, the method further includes determining a gap distance between each of the plurality of sensor regions and the annular wall. In one embodiment, the method may further include determining a center-point offset of a center point of the sensor wafer relative to a center point of the annular wall from the gap distance.
[0006] Embodiments disclosed herein include a placement controller. In one embodiment, the placement controller comprises a sensor interface that receives sensor information from a sensor wafer that comprises a plurality of outward-facing sensors along an edge of the sensor wafer. In one embodiment, the placement controller further comprises a center point module that utilizes the sensor information to identify a center point of the sensor wafer relative to a center point of a heated pedestal on which the sensor wafer rests, and the placement controller controls a positioning robot that places the sensor wafer on the pedestal.
[0007] An embodiment disclosed herein includes a method for calibrating a wafer positioning robot for positioning a wafer on a pedestal. In one embodiment, the method includes positioning a sensor wafer at a first location on a pedestal with a wafer positioning robot, the sensor wafer comprising a first surface supported by the pedestal, a second surface opposite the first surface, and an end surface connecting the first surface to the second surface, a plurality of sensor regions formed on the end surface, and the pedestal comprising a major surface and an annular wall surrounding the sensor wafer. In one embodiment, the method further includes determining a gap distance between each of the plurality of sensor regions and the annular wall. In one embodiment, the method further includes determining a center-point offset of a center point of the sensor wafer relative to a center point of the annular wall from the gap distance. In one embodiment, the method further includes generating a second location by modifying the first location by the center-point offset. In one embodiment, the method further includes removing the sensor wafer from the pedestal with the wafer positioning robot. In one embodiment, the method further includes placing the wafer at a second location on the pedestal with the wafer positioning robot. [Brief description of the drawings]
[0008] [Figure 1A] FIG. 2 is a top view of a sensor wafer on a heated pedestal according to one embodiment. [Figure 1B] FIG. 1B is a cross-sectional view of the sensor wafer and heating pedestal of FIG. 1A in accordance with one embodiment. [Diagram 2] FIG. 2 is a plan view of a sensor wafer having edge sensors according to one embodiment. [Diagram 3] FIG. 2 is a perspective view of a sensor wafer having edge sensors according to one embodiment. [Figure 4A] FIG. 2 is a partial cross-sectional view of a sensor wafer having edge sensors according to one embodiment. [Figure 4B] FIG. 2 is a partial cross-sectional view of a sensor wafer having edge sensors and field guards according to one embodiment. [Figure 4C]FIG. 2 is a partial cross-sectional view of a sensor wafer having edge sensors and a top surface recess in accordance with one embodiment. [Diagram 5] 1 is a schematic diagram of a processing tool and a placement controller for determining an offset of a sensor wafer relative to a pedestal according to one embodiment. [Figure 6] FIG. 13 is a flow diagram of a process for determining the offset of a sensor wafer relative to a pedestal according to one embodiment. [Figure 7] FIG. 13 is a flow diagram of a process for calibrating a wafer positioning robot using a sensor wafer according to one embodiment. [Figure 8] FIG. 1 illustrates a block diagram of an exemplary computer system that may be used in conjunction with a process that includes determining an offset of a sensor wafer relative to a pedestal in accordance with one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] A system including a sensor wafer having an edge sensor and a method of using such a sensor wafer to measure the offset of the sensor wafer relative to a pedestal are described according to various embodiments. In the following description, numerous specific details are set forth to provide a comprehensive understanding of the embodiments. It will be apparent to one of ordinary skill in the art that the embodiments may be practiced without these specific details. In other instances, well-known aspects have not been described in detail so as not to unnecessarily obscure the embodiments. Furthermore, it should be understood that the various embodiments illustrated in the accompanying figures are illustrative representations and are not necessarily drawn to scale.
[0010] As mentioned above, the alignment of the wafer on the heater pedestal is currently verified by visual inspection. Only after many test wafers have been processed will it be possible to verify that the process kit is properly centered with respect to the annular ring of the pedestal. This process requires several hours of down time for the processing tool and is expensive.
[0011] Thus, the embodiments disclosed herein include a sensor wafer that can directly measure the offset of the sensor wafer relative to the pedestal. In this manner, a single inspection procedure can be performed to ensure that the sensor wafer is centered within a desired tolerance. If the placement of the sensor wafer is found to be outside of the desired tolerance, the positioning robot used to place the sensor wafer on the pedestal can be provided with an offset that allows it to properly align subsequently placed wafers without the need for extensive testing. Thus, the embodiments disclosed herein can improve the accuracy of wafer centering, thereby reducing downtime of the processing tool and improving the uniformity of the process performed by the processing tool.
[0012] 1A, a top view of a sensor wafer 110 supported on a pedestal 100 is shown according to one embodiment. In one embodiment, the pedestal 100 can be any surface on which a wafer is placed for processing. For example, the pedestal 100 can be a heated pedestal. In one embodiment, the pedestal 100 can include a major surface 151 on which the wafer is placed and an annular ring 152 that surrounds the wafer.
[0013] In one embodiment, the sensor wafer 110 may include a number of outward-facing sensors that are used to determine the offset of the sensor wafer 110 relative to the pedestal 100. As shown in FIG. 1A, the diameter of the sensor wafer 110 may be less than the inner diameter of the annular ring 152. In one embodiment, the sensor wafer 110 may have substantially the same dimensions as a production wafer. For example, the sensor wafer 110 may have a diameter that is a standard wafer diameter (e.g., 300 mm, etc.). Thus, the sensor wafer 110 may be misaligned with the annular ring 152. For example, the center point 114 of the sensor wafer 110 may not coincide with the center point 154 of the annular ring 152.
[0014] 1B, a cross-sectional view of the pedestal 100 and the sensor wafer 110 is shown to more clearly illustrate the misalignment of the sensor wafer 110. As shown, a first (i.e., bottom) surface 113 of the sensor wafer 110 rests on a major surface 151 of the pedestal 100. An annular ring 152 surrounds the sensor wafer 110 such that an inner surface 153 of the annular ring faces an edge surface 112 of the sensor wafer 110. In one embodiment, the height of the inner surface 153 may be greater than the thickness of the sensor wafer 110. That is, the second (i.e., top) surface 111 of the sensor wafer 110 may be below the top surface of the annular ring 152.
[0015] 1B, an inner surface 153 of the annular ring 152 is spaced from the edge surface 112 of the sensor wafer by a first gap G1 and a second gap G2. When the first gap G1 and the second gap G2 are not equal, the sensor wafer 110 is misaligned. For example, the center point 114 of the sensor wafer 110 is offset from the center point 154 of the annular ring 152 by a distance D.
[0016] In one embodiment, the offset distance D may be determined by measuring the gap G between the edge 112 of the sensor wafer 110 and the inner surface 153 of the annular ring 152 at multiple locations. In a particular embodiment, the gap G is measured at multiple sensor areas formed at the edge of the sensor wafer 110. Figures 2 through 4C provide exemplary illustrations of a sensor wafer 110 having edge sensor areas according to various embodiments.
[0017] 2, a plan view of a sensor wafer 210 having multiple edge sensor regions 2351-235n is shown according to one embodiment. In one embodiment, the edge sensor regions 235 are distributed around the periphery of the sensor wafer 210. Each sensor region 235 comprises one or more sensors that are used to measure the gap between the edge of the sensor wafer 210 and an annular ring of pedestals surrounding the sensor wafer 210. One or more of the sensors in the edge sensor regions 235 may be capacitive sensors. In a particular embodiment, the edge sensor regions 235 may comprise self-referencing capacitive sensors.
[0018] In the illustrated embodiment, four edge sensor areas 235 positioned at 90 degree intervals are shown. However, it should be understood that more than two edge sensor areas 235 may be used to measure the offset of the center of the process kit relative to the center of the sensor wafer 210. One skilled in the art will recognize that providing more edge sensor areas 235 will result in more accurate measurements. In one embodiment, the sensor wafer 210 may also include a notch 216. The position of the notch 216 relative to the sensor areas 235 may be known by the sensor wafer 210. Thus, the rotational orientation of the sensor wafer 210 may also be determined.
[0019] In one embodiment, each of the edge sensor regions 235 may be communicatively connected to a computing module 238 of the sensor wafer 210 with wiring 237. In one embodiment, the computing module 238 may comprise one or more of a power source 232 (e.g., a battery), a processor / memory 234 (e.g., circuitry, memory, etc. for performing and / or storing measurements made at the edge sensor regions 235), and a wireless communication module 233 (e.g., Bluetooth, WiFi, etc.). In one embodiment, the computing module 238 may be recessed within the sensor wafer 210. Additionally, although shown in the center of the sensor wafer 210, it should be understood that the computing module 238 may be located at any convenient location within the sensor wafer 210.
[0020] 3 , a perspective view of a sensor wafer 310 is shown highlighting details of an exemplary edge sensor region 335 according to one embodiment. In one embodiment, the sensor wafer 310 may include a first surface 313 (e.g., a bottom surface), a second surface 311 (e.g., a top surface), and an edge surface 312 connecting the first surface 313 to the second surface 311. In one embodiment, a notch 316 may be formed in the sensor wafer 310.
[0021] In one embodiment, edge sensor regions 335 may be formed along the edge surface 312 connecting the first surface 313 to the second surface 311. In one particular embodiment, each edge sensor region 315 may include a probe 341. The probe 341 (i.e., the probe in each edge sensor region) may be a self-referencing capacitive probe. That is, the output phase of the current supplied to a first probe 341 in a first edge sensor region 335 may be offset 180 degrees from the output phase of the current supplied to a second probe 341 in an adjacent second edge sensor region 335. In this manner, distance measurements from the edge surface 312 to the inner surface of the annular ring (not shown) may be made without the need to ground a pedestal. In the illustrated embodiment, the edge sensor region 335 is shown as having a single probe. However, in some embodiments, each edge sensor region 335 may include one or more probes 341. Although reference is made specifically herein to self-referencing capacitive sensors, it should be understood that the embodiments disclosed herein include any suitable sensor technology (e.g., laser sensors, optical sensors, etc.).
[0022] 4A-4C, exemplary partial cross-sectional views of a sensor wafer 410 are shown in accordance with various embodiments. In FIG. 4A, the partial cross-sectional view illustrates that a sensor region 435 is substantially coplanar with an edge surface 412. In one embodiment, the sensor region 435 emits an electric field 449 from the edge surface 412 such that the sensor can measure the gap between the edge surface 412 and the surface of a process kit.
[0023] 4B, a partial cross-sectional view of sensor wafer 410 having electric field guard 447 is shown according to one embodiment. In one embodiment, electric field guard 447 may be a conductive layer formed between bottom surface 413 of sensor wafer 410 and edge sensor region 435. The electric field 449 in edge sensor region 435 may be modified by electric field guard 447. In particular, electric field guard 447 may modify electric field 449 in edge sensor region 435 to extend electric field 449 laterally from edge surface 412 toward the inner surface of the annular ring. Thus, electric field guard 447 prevents sensors in edge sensor region 435 from sensing the major surface of the pedestal on which sensor wafer 410 is supported, eliminating erroneous readings.
[0024] 4C, a partial cross-sectional view of a sensor wafer 410 having a top surface recess 448 according to one embodiment is shown. In one embodiment, the top surface recess 448 may be formed in the second surface 411 directly adjacent to the sensor region 435. The top surface recess 448 may be created to prevent a sensor in the sensor region 435 from sensing the top surface 411 and providing an erroneous reading. In one embodiment, the top surface recess 448 may extend back a distance R. For example, the distance R may be approximately equal to the maximum sensing distance of the edge sensing region 435. For example, R may be about 5 mm or less.
[0025] 5, there is shown a schematic block diagram of a processing tool 590 having a placement controller 570 for performing a process of measuring the offset of a sensor wafer on a pedestal according to one embodiment. In one embodiment, a pedestal 500 may be positioned within the processing tool 590. The pedestal may include a major surface 551 that supports a wafer and an annular ring 552 that surrounds the wafer.
[0026] In one embodiment, the placement controller 570 may provide instructions to a positioning robot 576 to place the sensor wafer 510 on the major surface 551 of the pedestal 500. The sensor wafer 510 may be a sensor wafer similar to the sensor wafers described above. For example, the sensor wafer 510 may include a number of edge sensor areas for measuring gaps G1-Gn between an edge of the sensor wafer 510 and an inner surface 553 of the annular ring 552.
[0027] In one embodiment, the sensor information from the sensor wafer 510 may be obtained by a sensor interface 571 of the placement controller 570. For example, the sensor interface 571 may receive the sensor information from the sensor wafer 510 (e.g., wirelessly using a wireless communication module). The placement controller 570 may utilize the sensor information (e.g., gaps G1-Gn) in the wafer center point module 572 to identify the center point of the sensor wafer 510 relative to the center point of the annular ring 552. The placement controller 570 may use the results from the wafer center point module 572 to generate an offset value 574 that is fed to a database 575. In one embodiment, if the total offset value 574 exceeds a predetermined threshold, the offset value 574 may be used by the placement controller 570 to correct where the positioning robot places the substrate on the pedestal 500. In one embodiment, the threshold may be an offset of + / - 200 microns.
[0028] Referring now to FIG. 6, a process flow diagram of a process 680 for determining a center point offset of a sensor wafer relative to the center point of an annular ring of a pedestal is shown according to one embodiment.
[0029] In one embodiment, process 680 begins with operation 681 (performed, for example, by positioning robot 576) which includes placing a sensor wafer having multiple edge sensor regions on a pedestal. The sensor wafer may be any sensor wafer described according to embodiments disclosed herein. In one embodiment, the sensor wafer may be placed on a support surface using a positioning robot controlled by a placement controller, similar to the embodiment described with respect to FIG.
[0030] In one embodiment, process 680 may continue with operation 682 (e.g., performed by sensor interface 571 of placement controller 570), which includes using each of the multiple edge sensor regions to determine a gap distance between the edge of the sensor wafer and an inner surface of the annular ring of the pedestal. For example, the edge sensor regions may include self-referencing capacitive sensors. The edge sensor regions may have a field guard below the edge sensor region to modify the electric field of the capacitive sensor to prevent the capacitive sensor from reading the major surface supporting the sensor wafer. Further embodiments may include a top surface recess proximate the edge sensor region to eliminate erroneous measurements of the top surface of the sensor wafer.
[0031] In one embodiment, process 680 may continue with operation 683 (e.g., performed by wafer center point module 572 of placement controller 570), which includes determining a center point offset of the sensor wafer relative to the center point of the annular ring using the gap distances from the multiple edge sensor regions. In one embodiment, the center point offset may be determined by the positioning controller and stored in a database.
[0032] Referring now to FIG. 7, a process flow diagram of a process 780 for calibrating a wafer positioning robot using a sensor wafer is shown according to one embodiment.
[0033] In one embodiment, process 780 may begin with operation 781 (performed, for example, by positioning robot 576) which includes placing a sensor wafer in a first position on a pedestal surface with a wafer positioning robot. In one embodiment, the sensor wafer may be any sensor wafer having an outward facing sensor, such as those described herein. In one embodiment, the pedestal may include a major surface on which the sensor wafer rests and an annular ring around the sensor wafer.
[0034] In one embodiment, process 780 may continue with operation 782 (e.g., performed by sensor interface 571 of placement controller 570) which includes using multiple edge sensor regions to identify multiple gap distances between the sensor wafer and the inner surface of the annular ring of the pedestal. For example, the edge sensor region of the sensor wafer may comprise a self-referencing capacitive sensor. The edge sensor region may have a field guard below the edge sensor region to modify the electric field of the capacitive sensor to prevent the capacitive sensor from reading the major surface supporting the sensor wafer. Further embodiments may include a top surface recess proximate the edge sensor region to eliminate erroneous measurements of the top surface of the sensor wafer.
[0035] In one embodiment, process 780 may continue with operation 783 (e.g., performed by wafer center point module 572 of placement controller 570), which includes determining a sensor wafer center point offset relative to the center point of the annular ring using gap distances from multiple edge sensor regions.
[0036] In one embodiment, process 780 may continue with operation 784 (e.g., performed by placement controller 570), which includes generating a second position by modifying the first position by a center point offset (e.g., offset value 574). In one embodiment, operation 784 may be performed to reduce the center point offset of a wafer that is subsequently placed on the pedestal. In some embodiments, the second position is generated when the center point offset exceeds a predetermined threshold. For example, if the center point offset is less than 200 microns, there may be no need to further calibrate the wafer positioning robot. In one embodiment, offset value 574 may be stored in database 575 for future use.
[0037] In one embodiment, process 780 may continue with operation 785 (eg, performed by positioning robot 576), which includes removing the sensor wafer from the pedestal with the wafer positioning robot.
[0038] In one embodiment, process 780 may then continue with operation 786 (e.g., performed by positioning robot 576), which includes placing the wafer at a second position on the pedestal with the wafer positioning robot. In one embodiment, the wafer may be a production wafer (i.e., a wafer on which a device is fabricated). Because the wafer positioning robot is calibrated, the resulting placing of the wafer at the second position may be assumed to have a high degree of accuracy. For example, the subsequently placed device wafer may be positioned with an accuracy of + / - 200 microns.
[0039] Referring now to FIG. 8, a block diagram of an exemplary computer system 860 of a processing tool according to one embodiment is shown. In one embodiment, the computer system 860 may be used as a placement controller. In one embodiment, the computer system 860 is coupled to the processing tool and controls processing at the processing tool. The computer system 860 may be connected (e.g., networked) to other machines in a network 861 (e.g., a local area network (LAN), an intranet, an extranet, or the Internet). The computer system 860 may operate in the role of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 860 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a server, a network router, a switch, or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify operations to be performed by that machine. Additionally, although only a single machine is shown as computer system 860, the term "machine" should also be interpreted to include any collection of machines (e.g., computers) that individually or in concert execute a set (or sets) of instructions to perform any one or more of the methods described herein.
[0040] The computer system 860 may include a computer program product, or software 822, having a non-transitory machine-readable medium having instructions stored thereon, which may be used to program the computer system 860 (or other electronic devices) to perform processes according to the embodiments. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustic, or other form of a propagated signal (e.g., infrared signal, digital signal, etc.)), etc.
[0041] In one embodiment, computer system 860 includes a system processor 802, a main memory 804 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 818 (e.g., data storage device), which communicate with each other via a bus 830.
[0042] The system processor 802 represents one or more general-purpose processing devices, such as a microsystem processor, a central processing unit, etc. More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor implementing other instruction sets, or a combination of instruction sets. The system processor 802 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal system processor (DSP), a network system processor, etc. The system processor 802 is configured to execute processing logic 826 for performing the operations described herein.
[0043] The computer system 860 may further include a system network interface device 808 for communicating with other devices or machines. The computer system 860 may also include a video display unit 810 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), and a signal generating device 816 (e.g., a speaker).
[0044] The secondary memory 818 may include a machine-accessible storage medium 831 (or more specifically a computer-readable storage medium) on which is stored one or more sets of instructions (e.g., software 822) that implement any one or more of the methods or functions described herein. The software 822 may also reside, completely or at least partially, within the main memory 804 and / or the system processor 802 during execution by the computer system 860, and the main memory 804 and the system processor 802 may also constitute machine-readable storage media. The software 822 may further be transmitted or received over the network 861 via the system network interface device 808.
[0045] Although in the exemplary embodiment, the machine-accessible storage medium 831 is shown to be a single medium, the term "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be interpreted to include any medium that is capable of storing or encoding a set of instructions that are executed by a machine and that cause the machine to perform any one or more of the methods. Thus, the term "machine-readable storage medium" should be interpreted to include, but is not limited to, solid-state memories, optical media, and magnetic media.
[0046] In the foregoing specification, certain exemplary embodiments have been described. It will be apparent that various modifications may be made to the exemplary embodiments without departing from the scope of the following claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.
Claims
1. A placement controller, a sensor interface configured to receive sensor information from a sensor wafer having a plurality of outward facing sensors along an edge of the sensor wafer, the sensor interface comprising: a recess formed in a top surface of the sensor wafer adjacent each of the plurality of outward facing sensors, the recess not extending to a center of the sensor wafer but extending a distance R in the direction of a center of the sensor wafer; a center point module configured to utilize the sensor information to identify a center point of the sensor wafer relative to a center point of a pedestal on which the sensor wafer rests; A placement controller configured to control a positioning robot that places the sensor wafer on the pedestal.
2. The placement controller of claim 1 , wherein the placement controller generates position offset values that are stored in a database.
3. The placement controller of claim 2 , wherein the position offset value is used to control the positioning robot as it places the wafer on the pedestal.
4. The arrangement controller of claim 1 , wherein the pedestal is a heater pedestal.
5. 10. The arrangement controller of claim 1, wherein the plurality of outward-facing sensors of the sensor wafer are self-referencing capacitive sensors.
6. The arrangement controller of claim 1 , wherein the plurality of outward facing sensors includes at least three outward facing sensors.
7. The arrangement controller of claim 1 , wherein the arrangement controller is for determining a gap distance between each of the plurality of outward-facing sensors and an annular wall.
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