Imaging device

Abstract

To provide an imaging device capable of reducing noises.SOLUTION: A disclosed imaging device includes: a pixel area including multiple pixels; and a signal line extending across two or more pixels among the plurality of pixels. Each of the plurality of pixels includes: a semiconductor substrate; a photoelectric conversion part; a first transistor including first and second impurity regions; a wiring layer; and a capacitive element. The wiring layer includes a part of the signal line. The capacitive element is placed between the wiring layer and the semiconductor substrate in plan view and includes a first electrode, a dielectric layer, and a second electrode placed between the first electrode and the semiconductor substrate. The second electrode is electrically connected to any one of the first and second impurity regions, and at least one of the first and second electrodes covers the first impurity area.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to an imaging device, and more particularly to an imaging device including a photoelectric conversion unit supported by a semiconductor substrate. [Background technology]

[0002] CCD (Charge Coupled Device) circuit or CMOS (Complementary MOS) circuit An imaging device having a structure in which a photoelectric conversion layer is disposed above a semiconductor substrate on which a photoelectric conversion layer is formed has been proposed. An imaging device having a photoelectric conversion layer above a semiconductor substrate is also called a stacked type imaging device. For example, Patent Document 1 below discloses a solid-state imaging element having such a stacked type structure.

[0003] A stacked-type imaging device accumulates charges generated by photoelectric conversion in a charge accumulation region, and reads out the accumulated charges using a readout circuit including a CCD circuit or a CMOS circuit. The photoelectric conversion layer is generally disposed on an insulating layer that covers a semiconductor substrate on which the readout circuit is formed. The photoelectric conversion layer on the insulating layer is electrically connected to the readout circuit via a connection portion provided in the insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-151771 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the field of imaging devices, there is a demand for noise reduction. [Means for solving the problem]

[0006] An imaging device according to a non-limiting exemplary embodiment of the present disclosure includes a pixel region including a plurality of pixels, and a signal line extending across two or more pixels among the plurality of pixels. Each of the plurality of pixels includes a semiconductor substrate, a photoelectric conversion unit, a first transistor, a wiring layer, and a capacitance element. The photoelectric conversion unit converts incident light into an electric signal. The first transistor is disposed in the semiconductor substrate and includes a first impurity region in which a signal charge is accumulated, and a second impurity region disposed in the semiconductor substrate. The wiring layer includes a part of the signal line. The capacitance element is disposed between the wiring layer and the semiconductor substrate in a normal direction of the semiconductor substrate, and includes a first electrode, a second electrode disposed between the first electrode and the semiconductor substrate, and a dielectric layer disposed between the first electrode and the second electrode. One of the first impurity region and the second impurity region is configured to function as a source region of the first transistor, and the other of the first impurity region and the second impurity region is configured to function as a drain region of the first transistor, the second electrode is electrically connected to either the first impurity region or the second impurity region, and at least one selected from the group consisting of the first electrode and the second electrode covers the first impurity region when viewed along a normal direction of the semiconductor substrate.

[0007] The general or specific aspects may be embodied in an element, device, system, integrated circuit, or method. Also, the generic or specific aspects may be realized by any combination of elements, devices, apparatus, systems, integrated circuits, and methods.

[0008] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings, and the benefits and / or advantages may be provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of them. Effect of the Invention

[0009] According to one aspect of the present disclosure, an imaging device capable of further reducing noise is provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an exemplary circuit configuration of an imaging device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing an example of a circuit configuration of a pixel. [Diagram 3] FIG. 3 is a schematic cross-sectional view of one of a plurality of pixels included in the imaging device. [Figure 4] FIG. 4 is a schematic plan view showing an example of the layout of each element in a pixel. [Diagram 5] FIG. 5 is a diagram for explaining the relationship between pixels and various signal lines connected to the pixels. [Figure 6] FIG. 6 is a plan view showing an example of the arrangement relationship between the wiring layer, the upper electrode, and the impurity region when the photoelectric conversion unit is removed from the pixel and viewed from the normal direction of the semiconductor substrate. [Figure 7] FIG. 7 is a plan view illustrating an example of an arrangement of a connection portion for a first capacitive element. [Figure 8] FIG. 8 is a plan view showing an example of a chip having a pixel region including a plurality of pixels. [Figure 9] FIG. 9 is a schematic cross-sectional view for explaining one manufacturing process of a pixel including an MIM structure having no opening in an interlayer insulating layer. [Figure 10] FIG. 10 is a schematic cross-sectional view illustrating another manufacturing process of a pixel including an MIM structure having no opening in an interlayer insulating layer. [Figure 11] FIG. 11 is a schematic cross-sectional view for explaining a manufacturing process of a pixel to which an MIM structure having an opening is applied as a first capacitance element. [Figure 12] FIG. 12 is a schematic cross-sectional view illustrating another manufacturing process of a pixel to which an MIM structure having an opening is applied as a first capacitance element. [Figure 13]FIG. 13 is a plan view showing a modified example of the imaging device. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a modified example of the imaging device. [Figure 15] FIG. 15 is a schematic cross-sectional view of a pixel of an imaging device according to another embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram showing an exemplary circuit configuration of the pixel shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Before describing the embodiments of the present disclosure in detail, an overview of one aspect of the present disclosure will be described. The overview of one aspect of the present disclosure is as follows.

[0012] [Item 1] The imaging device according to the first aspect of the present disclosure includes a pixel region including a plurality of pixels, and a signal line arranged across two or more of the plurality of pixels and extending from inside the pixel region to outside the pixel region, each of the plurality of pixels including a semiconductor substrate, a photoelectric conversion unit, a first transistor, a wiring layer, and a capacitance element.

[0013] The photoelectric conversion unit is supported by the semiconductor substrate and includes a first electrode, a second electrode arranged closer to the semiconductor substrate than the first electrode, and a photoelectric conversion layer arranged between the first electrode and the second electrode.

[0014] The first transistor includes a first impurity region disposed in the semiconductor substrate, and a second impurity region disposed in the semiconductor substrate.

[0015] The wiring layer is disposed between the semiconductor substrate and the second electrode and includes a portion of the signal line.

[0016] The capacitive element is arranged between the wiring layer and the semiconductor substrate in a normal direction of the semiconductor substrate, and includes a third electrode, a fourth electrode arranged between the third electrode and the semiconductor substrate, and a dielectric layer arranged between the third electrode and the fourth electrode.

[0017] one of the first impurity region and the second impurity region is configured to function as a source region of the first transistor, and the other of the first impurity region and the second impurity region is configured to function as a drain region of the first transistor; the first impurity region is electrically connected to the second electrode; the fourth electrode is electrically connected to either the first impurity region or the second impurity region; At least one selected from the group consisting of the third electrode and the fourth electrode covers the first impurity region when viewed along a normal direction of the semiconductor substrate.

[0018] According to the configuration of item 1, the third electrode and / or the fourth electrode can function as a light-shielding layer. At least one of the third electrode and the fourth electrode covers the first impurity region, so that the incidence of light into the first impurity region can be suppressed, and the generation of false signals can be suppressed. Furthermore, according to the configuration of item 1, the capacitive element is disposed closer to the semiconductor substrate than the wiring layer including a part of the signal line extending to the outside of the pixel region, so that the incidence of light obliquely incident on the pixel into the first impurity region can be more effectively suppressed.

[0019] [Item 2] In the imaging device according to item 1, Each of the plurality of pixels may further include a second transistor including a gate electrode electrically connected to the second electrode.

[0020] [Item 3] In the imaging device according to item 1 or 2, The at least one selected from the group consisting of the third electrode and the fourth electrode may cover at least a portion of the second impurity region when viewed along the normal direction.

[0021] According to the configuration of item 3, at least one of the third electrode and the fourth electrode covers the second impurity region, so that it is possible to suppress the incidence of light into the second impurity region. By suppressing the incidence of light into the second impurity region, it is possible to prevent the potential of the charge accumulation region from indirectly fluctuating due to the generation of charges in the second impurity region.

[0022] [Item 4] The imaging device according to item 2 is The semiconductor device may further include a connection portion that electrically connects the second electrode to the first impurity region and electrically connects the second electrode to the gate electrode of the second transistor. .

[0023] [Item 5] In the imaging device according to item 4, At least one selected from the group consisting of the third electrode and the fourth electrode may include an opening.

[0024] According to the configuration of item 5, even if an interlayer insulating layer is provided between the photoelectric conversion unit and the semiconductor substrate and a capacitive element is disposed in this interlayer insulating layer, it is possible to suppress the protrusion of the interlayer insulating layer in the portion above the pixel region relative to the portion above the peripheral region. In other words, it is possible to reduce the step of the interlayer insulating layer between the pixel region and the peripheral region and suppress degradation of image quality caused by, for example, shading.

[0025] [Item 6] In the imaging device according to item 5, The connection portion may pass through the opening.

[0026] According to the configuration of item 6, a larger electrode area can be secured for the capacitive element.

[0027] [Item 7] In the imaging device according to any one of items 4 to 6, the fourth electrode has a first surface facing the third electrode and a second surface opposite to the first surface, and is electrically connected to the second impurity region; At least a portion of the connection portion may face the second surface and extend in a plane perpendicular to the normal direction.

[0028] According to the configuration of item 7, a capacitance can be formed between a part of the connection portion and a part of the fourth electrode.

[0029] [Item 8] In the imaging device according to item 7, The fourth electrode may be electrically connected to the second impurity region on the second surface.

[0030] According to the configuration of item 8, electrical coupling between the fourth electrode and other electrodes and / or wiring can be suppressed, and the introduction of noise can be further reduced.

[0031] [Item 9] The imaging device according to item 7 or 8, a feedback circuit that negatively feeds back an output of the second transistor; the feedback circuit includes a third transistor including a source and a drain; One of the source and the drain may be connected to the second impurity region.

[0032] According to the configuration of Item 9, the kTC noise can be cancelled using a feedback circuit.

[0033] [Item 10] In the imaging device according to any one of items 4 to 6, The fourth electrode has a first surface facing the third electrode and a second surface opposite to the first surface. and may be electrically connected to the connection portion.

[0034] [Item 11] In the imaging device according to item 10, The fourth electrode may be connected to the connection portion on the second surface.

[0035] According to the configuration of item 11, electrical coupling between the fourth electrode and other electrodes and / or wiring can be suppressed, and the introduction of noise can be further reduced.

[0036] [Item 12] The imaging device according to item 10 or 11 is a feedback circuit that negatively feeds back an output of the second transistor; The second impurity region may be electrically connected to an output line of the feedback circuit.

[0037] According to the configuration of item 12, the kTC noise can be cancelled using a feedback circuit.

[0038] [Item 13] In the imaging device according to any one of items 7 to 12, the dielectric layer covers a surface of the fourth electrode other than the second surface, The third electrode may cover a side surface of the fourth electrode that connects the first surface and the second surface.

[0039] According to the configuration of item 13, electrical coupling between the fourth electrode and other electrodes and / or wiring can be suppressed, and the introduction of noise can be further reduced.

[0040] [Item 14] In the imaging device according to any one of items 1 to 13, The signal line may be a control line that drives the two or more pixels, a power supply line that supplies a voltage to the two or more pixels, or an output line that reads out a signal from the two or more pixels.

[0041] [Item 15] In the imaging device according to any one of items 1 to 14, The at least one selected from the group consisting of the third electrode and the fourth electrode may cover the entirety of the first impurity region when viewed along the normal direction.

[0042] In this disclosure, all or part of a circuit, unit, device, member or part, or all or part of a functional block in a block diagram may be realized by one or more electronic circuits including a semiconductor device, a semiconductor integrated circuit (IC), or a large scale integration (LSI). The LSI or IC may be integrated into one chip, or may be configured by combining multiple chips. For example, functional blocks other than memory elements may be integrated into one chip. Here, the electronic circuit that performs processing is referred to as an LSI or IC, but the name of the electronic circuit that performs processing may vary depending on the degree of integration. The electronic circuit that performs processing may be referred to as a system LSI, a VLSI (very large scale integration), or a LSI (large scale integration). It may be called Field Programmable Gate Array (FPGA), where the specific contents of the processing are programmed after the LSI is manufactured, or reconfigurable LSI, where the connection relationship inside the LSI can be reconfigured or the circuit divisions inside the LSI can be set up. A logic device can also be used for the same purpose.

[0043] Furthermore, all or part of the functions or operations of the circuit, unit, device, component, or part can be executed by software processing. In this case, the software is recorded in one or more non-transitory recording media such as ROMs, optical disks, hard disk drives, etc., and when the software is executed by a processor, the functions specified in the software are executed by the processor and peripheral devices. The system or device may include one or more non-transitory recording media on which the software is recorded, a processor, and necessary hardware devices, such as interfaces.

[0044] Hereinafter, the embodiments of the present disclosure will be described in detail. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of components, steps, and order of steps shown in the following embodiments are examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components. In the following description, components having substantially the same functions are indicated by common reference symbols, and descriptions may be omitted.

[0045] As will be described later with reference to the drawings, an imaging device according to a typical embodiment of the present disclosure has a plurality of pixels, each of which includes a semiconductor substrate having a plurality of impurity regions and a photoelectric conversion unit supported by the semiconductor substrate. An interlayer insulating layer having a connection portion therein is located between the semiconductor substrate and the photoelectric conversion unit. The impurity region of the semiconductor substrate is electrically connected to the photoelectric conversion unit via the connection portion and includes a first impurity region that functions as one of the source region and drain region of the reset transistor, and a second impurity region that functions as the other of the source region and drain region. The first impurity region constitutes at least a part of the charge accumulation region, and a signal, for example a voltage signal, according to the amount of charge accumulated in the charge accumulation region is read out as an image signal.

[0046] Each pixel includes, in an interlayer insulating layer sandwiched between a semiconductor substrate and a photoelectric conversion unit, a capacitance element including an electrode at least a part of which overlaps with the first impurity region and / or the second impurity region in a top view, and a wiring layer located between the photoelectric conversion unit and the capacitance element, the wiring layer including a part of a signal line extending to the outside of a pixel region composed of a plurality of pixels. The electrode of the capacitance element functions as a light shielding layer, thereby suppressing the generation of false signals caused by the incidence of light into the first or second impurity region, and an image with reduced noise can be obtained. In particular, since the capacitance element is disposed closer to the semiconductor substrate than the wiring layer including a part of the signal line extending to the outside of the pixel region, the incidence of light incident obliquely on the pixel into the first impurity region can be more effectively suppressed.

[0047] (Embodiment 1) FIG. 1 illustrates an outline of an exemplary circuit configuration of an imaging device according to an embodiment of the present disclosure. The imaging device 100 illustrated in FIG. 1 has a plurality of pixels 10 and peripheral circuits. The pixels 10 are arranged, for example, two-dimensionally to form a pixel region. Here, an example is shown in which four pixels 10 are arranged in a matrix of two rows and two columns. Needless to say, the number and arrangement of the pixels 10 are not limited to this example. The arrangement of the pixels 10 may be one-dimensional. In this case, the imaging device 100 may be used as a line sensor.

[0048] Each of the pixels 10 is connected to a power supply line 22, and during operation, a predetermined power supply voltage is supplied to each of the pixels 10 via the power supply line 22. In addition, each of the pixels 10 is provided with an accumulation control The accumulation control line 17 is connected to the pixel 10. As will be described in detail later, each of the pixels 10 includes a photoelectric conversion unit that photoelectrically converts incident light, and a signal detection circuit that detects a signal generated by the photoelectric conversion unit. In a typical embodiment, the accumulation control line 17 applies a predetermined voltage in common to the photoelectric conversion units of each pixel 10.

[0049] 1, the peripheral circuits of the imaging device 100 include a vertical scanning circuit 16, a plurality of load circuits 19, a plurality of column signal processing circuits 20, a plurality of inverting amplifiers 24, and a horizontal signal readout circuit 21. The load circuits 19, the column signal processing circuits 20, and the inverting amplifiers 24 are arranged for each column of the pixels 10 arranged two-dimensionally. The vertical scanning circuit 16 is also called a row scanning circuit, and the column signal processing circuit 20 is also called a row signal storage circuit. The horizontal signal readout circuit 21 is also called a column scanning circuit.

[0050] An address signal line 30 and a reset signal line 26 are connected to the vertical scanning circuit 16. The vertical scanning circuit 16 selects a plurality of pixels 10 arranged in each row on a row-by-row basis by applying a predetermined voltage to the address signal line 30. By selecting a plurality of pixels 10 on a row-by-row basis, the signal voltage of the selected pixels 10 is read out and the signal charge is reset, which will be described later.

[0051] In the illustrated example, a feedback control line 28 and a sensitivity adjustment line 32 are further connected to the vertical scanning circuit 16. In an example described later, the vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, thereby forming a feedback loop that negatively feeds back the output of the pixel 10. In addition, the vertical scanning circuit 16 can supply a predetermined voltage to the multiple pixels 10 via the sensitivity adjustment line 32.

[0052] The imaging device 100 has vertical signal lines 18 provided for each column of the pixels 10. A load circuit 19 is electrically connected to each vertical signal line 18. The pixels 10 are electrically connected to a column signal processing circuit 20 via the corresponding vertical signal line 18. The column signal processing circuit 20 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion. A horizontal signal readout circuit 21 is electrically connected to the column signal processing circuits 20 provided for each column of the pixels 10. The horizontal signal readout circuit 21 sequentially reads out signals from the column signal processing circuits 20 to a horizontal common signal line 23.

[0053] In the configuration illustrated in FIG. 1, an inverting amplifier 24 is provided corresponding to each column of the pixels 10. A negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18, and a predetermined voltage Vref is supplied to a positive input terminal of the inverting amplifier 24. Vref is, for example, a positive voltage of 1V or close to 1V. An output terminal of the inverting amplifier 24 is connected to a pixel 10 having a connection to the negative input terminal of the inverting amplifier 24 via one of a plurality of feedback lines 25 provided corresponding to a plurality of columns of the pixels 10. The inverting amplifier 24 constitutes a part of a feedback circuit that negatively feeds back the output from the pixel 10. The inverting amplifier 24 may be called a feedback amplifier. Details of the operation of the inverting amplifier 24 will be described later.

[0054] Fig. 2 shows an example of a circuit configuration of the pixel 10. The pixel 10A shown in Fig. 2 includes a photoelectric conversion unit 15 and a signal detection circuit 200. In the configuration shown in Fig. 2, the imaging device 100 includes a feedback circuit 202 that negatively feeds back the output of the signal detection circuit 200.

[0055] The photoelectric conversion unit 15 has a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c as a pixel electrode. The first electrode 15a of the photoelectric conversion unit 15 is connected to an accumulation control line 17, and the second electrode 15c of the photoelectric conversion unit 15 is connected to a charge accumulation node 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, Positive and negative charges, typically hole-electron pairs, can be collected by the second electrode 15c, with charges of either polarity. When holes are used as signal charges, for example, the potential of the first electrode 15a may be set higher than that of the second electrode 15c. The following illustrates an example in which holes are used as signal charges. For example, a voltage of about 10V is applied to the first electrode 15a via the accumulation control line 17. This causes the signal charges to accumulate in the charge accumulation node 44. Electrons may also be used as signal charges.

[0056] The signal detection circuit 200 includes a signal detection transistor 34 that amplifies and outputs a signal generated by the photoelectric conversion unit 15, and a first capacitive element 41. In the example shown, the signal detection circuit 200 further includes a reset transistor 36, a feedback transistor 38, a second capacitive element 42 having a smaller capacitance value than the first capacitive element 41, and an address transistor 40. The reset transistor 36 corresponds to the first transistor in this disclosure, and the signal detection transistor 34 corresponds to the second transistor in this disclosure.

[0057] In this embodiment, each pixel 10A has one or more capacitive elements therein. As will be described in detail later, if the first capacitive element 41 has a relatively large capacitance value, for example, kTC noise can be effectively reduced. In the following, an example will be described in which an N-channel metal-oxide-semiconductor field effect transistor (MOSFET) is used as a transistor such as the signal detection transistor 34.

[0058] The gate of the signal detection transistor 34 is connected to the charge accumulation node 44. In other words, the gate of the signal detection transistor 34 is connected to the second electrode 15c. The drain of the signal detection transistor 34 is connected to the power supply wiring 22 as a source follower power supply, and the source is electrically connected to the vertical signal line 18. The signal detection transistor 34 and the load circuit 19 (not shown in FIG. 2) configure a source follower circuit.

[0059] In this example, an address transistor 40 is connected between the source of the signal detection transistor 34 and the vertical signal line 18. The gate of the address transistor 40 is connected to the address signal line 30. When signal charges are accumulated in the charge accumulation node 44, a voltage according to the amount of accumulated signal charges is applied to the gate of the signal detection transistor 34. The signal detection transistor 34 amplifies this voltage. When the address transistor 40 is turned on, the voltage amplified by the signal detection transistor 34 is selectively read out as a signal voltage.

[0060] 2, one of the electrodes of the first capacitance element 41 is connected to a sensitivity adjustment line 32. Typically, during operation of the imaging device 100, the potential of the sensitivity adjustment line 32 is fixed to a constant potential, such as 0 V. The sensitivity adjustment line 32 can be used to control the potential of the charge storage node 44. The other of the electrodes of the first capacitance element 41 is connected to one of the electrodes of the second capacitance element 42. Hereinafter, a node including a connection point between the first capacitance element 41 and the second capacitance element 42 may be referred to as a reset drain node 46.

[0061] The other of the electrodes of the second capacitance element 42 is connected to the charge storage node 44. That is, of the electrodes of the second capacitance element 42, the electrode that is not connected to the reset drain node 46 is electrically connected to the second electrode 15c of the photoelectric conversion unit 15. In this example, the reset transistor 36 is connected in parallel to the second capacitance element 42.

[0062] In the configuration illustrated in Figure 2, pixel 10A includes a feedback transistor 38. As shown, one of the source and drain of feedback transistor 38 is connected to a reset drain node 46. The other of the source and drain of feedback transistor 38 is connected to feedback line 25. The gate of the transistor 38 is connected to the feedback control line 28 mentioned above.

[0063] (Device structure of pixel 10A) Next, an example of the device structure of the pixel 10A will be described with reference to FIGS.

[0064] Fig. 3 is a schematic cross-sectional view of one of the pixels 10A included in the imaging device 100. Fig. 4 is a schematic cross-sectional view of an example of the layout of each element in the pixel 10A. Fig. 3 corresponds to a cross-sectional view taken along line III-III in Fig. 4.

[0065] The imaging device 100 has a semiconductor substrate 2. As the semiconductor substrate 2, for example, a silicon substrate can be used. The semiconductor substrate 2 is not limited to a substrate whose entirety is a semiconductor. The semiconductor substrate 2 may be an insulating substrate having a semiconductor layer provided on its surface. Here, a P-type silicon substrate is exemplified as the semiconductor substrate 2.

[0066] Each of the pixels 10A includes a part of the semiconductor substrate 2 and a photoelectric conversion unit 15. Each of the pixels 10A is electrically isolated from the other pixels 10A by an element isolation region 2t formed in the semiconductor substrate 2. As shown in FIG. 3, an interlayer insulating layer 4 that covers the semiconductor substrate 2 is typically disposed between the semiconductor substrate 2 and the photoelectric conversion unit 15. In this example, the interlayer insulating layer 4 has a structure in which insulating layers 4a, 4b, 4c, 4d, and 4e are stacked. Each of the insulating layers 4a, 4b, 4c, 4d, and 4e is an insulating layer formed of, for example, silicon dioxide. In this example, the photoelectric conversion unit 15 is located on the insulating layer 4e located farthest from the semiconductor substrate 2.

[0067] Impurity regions 2a, 2b, and 2c are formed in the semiconductor substrate 2. The impurity regions 2a, 2b, and 2c are typically all N-type diffusion regions. A gate insulating layer 36g and a gate electrode 36e of the reset transistor 36 are provided in a region between the impurity regions 2a and 2b on the semiconductor substrate 2. A gate insulating layer 38g and a gate electrode 38e of the feedback transistor 38 are provided in a region between the impurity regions 2b and 2c on the semiconductor substrate 2. The impurity region 2a functions as one of the drain region and the source region of the reset transistor 36, and the impurity region 2b functions as the other of the drain region and the source region of the reset transistor 36. In this example, the reset transistor 36 and the feedback transistor 38 are electrically connected to each other by sharing the impurity region 2b. The impurity region 2a corresponds to the first impurity region in this disclosure, and the impurity region 2b corresponds to the second impurity region in this disclosure.

[0068] The impurity region 2c of the semiconductor substrate 2 functions as one of the drain region and the source region of the feedback transistor 38. The impurity region 2c is connected to a feedback line 25 that spans multiple pixels 10A via a plug disposed in the interlayer insulating layer 4. As will be described in detail later with reference to the drawings, the feedback line 25 is a signal line that extends to the outside of the pixel region.

[0069] 3, the portion of the feedback line 25 located within the pixel 10A of interest is part of the wiring layer 52 located between the second electrode 15c of the photoelectric conversion unit 15 and the semiconductor substrate 2. In this example, the wiring layer 52 also includes the portion of the vertical signal line 18 located within the pixel 10A of interest. That is, in this example, the vertical signal line 18 also belongs to the same layer as the feedback line 25 within the pixel 10A. Like the feedback line 25, the vertical signal line 18 is also a signal line that extends to the outside of the pixel region.

[0070] 5 shows the relationship between the pixel 10A and various signal lines connected to the pixel 10A. As described above, a plurality of pixels 10A form a pixel region 240. For simplicity, in FIG. Although four of the multiple pixels 10A are shown, in reality, for example, 300,000 pixels 10A for the VGA standard, or about 36 million pixels 10A for 8K, may be arranged in a matrix in the pixel region 240. Here, the pixel region 240 can be defined as a region having a repeating structure of multiple units, each of which has a signal detection transistor 34. The above-mentioned peripheral circuit is arranged in a peripheral region outside the pixel region 240.

[0071] As shown in the figure, the power supply wiring 22, the feedback line 25, and the vertical signal line 18 extend in the vertical direction in FIG. 5, that is, in the column direction of the pixels 10A. Each of the feedback lines 25 and each of the vertical signal lines 18 provided for each column of the pixels 10A are connected to two pixels 10A arranged along the column direction. On the other hand, the reset signal line 26, the feedback control line 28, and the address signal line 30 typically extend in the row direction of the pixels 10A. These signal lines are connected to two pixels 10A arranged along the row direction. Similarly, the sensitivity adjustment lines 32 also extend in the column direction or row direction of the pixels 10A, and each of them is connected to two pixels 10A arranged along the column direction or two pixels 10A arranged along the row direction.

[0072] The vertical signal line 18, the power supply line 22, the feedback line 25, the reset signal line 26, the feedback control line 28, the address signal line 30, and the sensitivity adjustment line 32 are all signal lines provided to cross a plurality of pixels 10A. The above-mentioned wiring layer 52 includes at least a portion of these signal lines. The wiring layer 52 may include a portion of the feedback control line 28 or a portion of the address signal line 30, which are control lines for driving two or more pixels, instead of a portion of the feedback line 25 and a portion of the vertical signal line 18, which is an output line for reading out signals from two or more pixels. Each of the feedback control line 28, the feedback line 25, the reset signal line 26, the address signal line 30, and the sensitivity adjustment line 32 corresponds to a control line in the present disclosure. The power supply line 22 corresponds to a power supply line in the present disclosure.

[0073] Referring again to Fig. 3, a gate insulating layer 34g and a gate electrode 34e of the signal detection transistor 34 are further provided on the main surface of the semiconductor substrate 2. As can be seen from Fig. 4, the drain region and the source region of the signal detection transistor 34 are located on the front side and the back side of the paper surface of Fig. 3, respectively. In this example, the set of the reset transistor 36 and the feedback transistor 38 and the set of the signal detection transistor 34 and the address transistor 40 are separated by an element isolation region 2t. The element isolation region 2t can be formed, for example, by ion implantation of an acceptor under predetermined implantation conditions.

[0074] Each pixel 10A has a connection portion 50 in the interlayer insulating layer 4, which electrically connects the impurity region 2a of the semiconductor substrate 2 to the second electrode 15c of the photoelectric conversion unit 15. The impurity region 2a functions as at least a part of a charge accumulation region that accumulates signal charges generated by the photoelectric conversion unit 15.

[0075] The connection portion 50 includes, as a part thereof, a polysilicon plug 210 having one end connected to the impurity region 2a of the semiconductor substrate 2, a polysilicon plug 212 having one end connected to the gate electrode 34e of the signal detection transistor 34, and a wiring 50a connecting the polysilicon plugs 210 and 212 to each other, and electrically connects the impurity region 2a and the gate electrode 34e to each other. That is, the impurity region 2a functioning as the drain region or source region of the reset transistor 36 and the gate electrode 34e of the signal detection transistor 34 are electrically connected to the second electrode 15c of the photoelectric conversion unit 15 via the connection portion 50. The wiring 50a may be a part of a polysilicon layer imparted with conductivity by doping with impurities.

[0076] The portion of the connection portion 50 located between the wiring 50a and the second electrode 15c is typically 3, and is formed of a metal such as copper. Therefore, the wiring layer 52 may also be a layer including wiring formed of a metal such as copper. The number of wiring layers disposed in the interlayer insulating layer 4 and the number of insulating layers in the interlayer insulating layer 4 are not limited to the number of layers exemplified in FIG. 3, and can be set arbitrarily.

[0077] The photoelectric conversion unit 15 supported by the semiconductor substrate 2 includes a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c. The photoelectric conversion unit 15 typically has a structure in which the photoelectric conversion layer 15b is sandwiched between the first electrode 15a and the second electrode 15c.

[0078] The first electrode 15a of the photoelectric conversion unit 15 is provided on the side where light from the subject arrives, in other words, on the light receiving surface 15h side of the photoelectric conversion layer 15b. The first electrode 15a is typically formed of a transparent conductive material such as indium tin oxide (ITO). The first electrode 15a may be formed directly on the photoelectric conversion layer 15b, or another layer may be disposed between the first electrode 15a and the photoelectric conversion layer 15b.

[0079] The photoelectric conversion layer 15b is formed of an organic material or an inorganic material such as amorphous silicon, etc. The photoelectric conversion layer 15b may include a layer made of an organic material and a layer made of an inorganic material.

[0080] The second electrode 15c is located closer to the semiconductor substrate 2 than the first electrode 15a and the photoelectric conversion layer 15b, and is spatially separated from the second electrodes 15c of other adjacent pixels 10A, and is thus electrically separated from them. The second electrode 15c collects charges generated by photoelectric conversion in the photoelectric conversion layer 15b. The second electrode 15c may be made of a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to provide electrical conductivity.

[0081] The first electrode 15a and the photoelectric conversion layer 15b are typically formed across a plurality of pixels 10A. However, at least one of the first electrode 15a and the photoelectric conversion layer 15b may be spatially separated from one another among a plurality of pixels 10A, similar to the second electrode 15c.

[0082] In this embodiment, the first capacitance element 41 is located between a wiring layer including at least a part of a signal line connected to two or more pixels, among the wiring layers arranged in the interlayer insulating layer 4, and the semiconductor substrate 2. In the configuration illustrated in Fig. 3, the first capacitance element 41 is located between a wiring layer 52 including a part of the vertical signal line 18 and a part of the feedback line 25, and the semiconductor substrate 2. In other words, in this embodiment, the first capacitance element 41 is located closer to the semiconductor substrate 2 than the wiring layer including a part of the signal line connected to two or more pixels.

[0083] The first capacitance element 41 has an upper electrode 41a, a lower electrode 41c, and a dielectric layer 41b disposed between the upper electrode 41a and the lower electrode 41c. In this example, in a cross-sectional view, the upper electrode 41a is located between the wiring layer 52 and the semiconductor substrate 2, and the lower electrode 41c is located between the upper electrode 41a and the semiconductor substrate 2. Note that the terms "upper" and "lower" in this specification are used to indicate the relative positions between members and are not intended to limit the attitude of the imaging device of the present disclosure. The same applies to the terms "upper" and "lower" in this specification. The upper electrode 41a corresponds to the third electrode in this disclosure, and the lower electrode 41c corresponds to the fourth electrode in this disclosure.

[0084] The upper electrode 41a and / or the lower electrode 41c of the first capacitance element 41 may be part of a wiring layer located between the second electrode 15c of the photoelectric conversion unit 15 and the gate electrode 34e of the signal detection transistor 34. In the configuration illustrated in FIG 3, the first capacitance element 41 has an opening 230, for example, in its center.

[0085] 3 is connected to the upper electrode 41a. The lower electrode 41c here spreads in a plane perpendicular to the normal direction of the semiconductor substrate 2, and is connected to the impurity region 2b through a via, a plug, or the like in the interlayer insulating layer 4.

[0086] In the configuration illustrated in FIG. 3, at least a portion of the upper electrode 41a of the first capacitance element 41 is located above the impurity region 2a. Thus, in this embodiment, for example, the upper electrode 41a has a shape that covers a part or the whole of the impurity region 2a that constitutes at least a part of the charge storage region when viewed along the normal direction of the semiconductor substrate 2. The upper electrode 41a and the lower electrode 41c may be, for example, a metal electrode or a metal nitride electrode. In other words, the first capacitance element 41 may have a "Metal-Insulator-Metal (MIM) structure" in which a dielectric is sandwiched between two electrodes formed of a metal or a metal compound. For example, by adopting the MIM structure, This allows the upper electrode 41a and / or the lower electrode 41c to function as a light-shielding layer, and can prevent light incident on the pixel 10A from being incident on the impurity region 2a.

[0087] As already explained, in each pixel 10A, the signal charge generated by the incidence of light on the photoelectric conversion layer 15b through the first electrode 15a of the photoelectric conversion unit 15 is collected by the second electrode 15c, and the collected signal charge is accumulated in the charge accumulation region. However, a part of the irradiated light may pass through the photoelectric conversion layer 15b without being absorbed by the photoelectric conversion layer 15b. In addition, as described above, a gap may exist between two adjacent second electrodes 15c. Therefore, light that enters the photoelectric conversion unit 15 and passes through the gap between the second electrodes 15c may be diffusely reflected between the photoelectric conversion unit 15 and the semiconductor substrate 2, and may reach, for example, the impurity region 2a. In this specification, for convenience of explanation, light that passes through the photoelectric conversion unit 15 and reaches the impurity region of the semiconductor substrate 2 may be called "stray light".

[0088] When such light is incident on the impurity region 2a, charges are generated in the impurity region 2a by photoelectric conversion. As described with reference to FIG. 3, the gate electrode 34e of the signal detection transistor 34 is connected to the impurity region 2a by the connection part 50, and the signal detection transistor 34 amplifies and outputs a signal corresponding to the amount of charge accumulated in the impurity region 2a. Therefore, the extra charge generated in the impurity region 2a due to the stray light causes a false signal to be generated. In other words, the incidence of light on the impurity region 2a results in noise being added to the original signal, resulting in a deterioration in image quality.

[0089] 6 shows an example of the positional relationship between the wiring layer 52, the upper electrode 41a, and the impurity region 2a when the photoelectric conversion unit 15 is removed from the pixel 10A and viewed in the normal direction of the semiconductor substrate 2. In the configuration shown in FIG. 6, the wiring layer 52 includes a part of the vertical signal line 18 and a part of the feedback line 25 extending in the column direction, and a wiring 52a connected to the connection unit 50. The wiring 52a is a part of the wiring layer 52 located at the same layer as the vertical signal line 18 and the feedback line 25, and constitutes a part of the connection unit 50.

[0090] In this example, the impurity region 2a constituting a part of the charge storage region is located at a position overlapping the wiring 52a in a top view. In particular, in this example, the entire impurity region 2a is covered by the wiring 52a. The shapes of the wiring 52a, a part of the vertical signal line 18, and a part of the feedback line 25 shown in FIG. 6 are merely examples. A part of the vertical signal line 18 or a part of the feedback line 25 may have a shape that covers the entire impurity region 2a. In this way, the wiring layer 52 may cover the entire impurity region 2a.

[0091] 6, according to this embodiment, at least a portion of the upper electrode 41a of the first capacitance element 41 overlaps with the impurity region 2a in a top view, so that the upper electrode 41a can be used as a light-shielding electrode and can suppress the incidence of light into the impurity region 2a. Since the incidence of light into the imaging device 100 is suppressed, the occurrence of false signals can be prevented. Suppression of stray light contributes to improving the reliability of the imaging device 100.

[0092] In the example shown in FIG. 3, at least a part of the lower electrode 41c is also located above the impurity region 2a. That is, the lower electrode 41c may also have a shape that covers the entire impurity region 2a when viewed along the normal direction of the semiconductor substrate 2. The lower electrode 41c may function as a light shielding layer by having a shape that covers a part or the entire impurity region 2a when viewed from above, and may suppress the incidence of light into the impurity region 2a. In this example, at least a part of the upper electrode 41a and at least a part of the lower electrode 41c cover the impurity region 2a when viewed from above. However, it is not essential that both the upper electrode 41a and the lower electrode 41c cover the impurity region 2a when viewed from above. If at least one of the upper electrode 41a and the lower electrode 41c has a shape that covers the impurity region 2a when viewed along the normal direction of the semiconductor substrate 2, an effect of preventing the generation of false signals can be expected.

[0093] 3, the first capacitance element 41 is disposed between the wiring layer 52 including a part of the vertical signal line 18 and the semiconductor substrate 2. In other words, in this example, the first capacitance element 41 is located closer to the semiconductor substrate 2 than the wiring layer including a part of the signal line spanning two or more pixels. Therefore, a light blocking effect can be obtained at a position closer to the semiconductor substrate 2, and a high light blocking effect can be exhibited even against stray light that travels obliquely with respect to the normal direction of the semiconductor substrate 2. Therefore, deterioration of image quality due to parasitic sensitivity caused by stray light can be more effectively prevented.

[0094] Examples of materials for forming the upper electrode 41a are Ti, TiN, Ta, TaN, and Mo. The lower electrode 41c may be formed of a similar material so that at least a part of the lower electrode 41c overlaps the impurity region 2a in a top view, and the lower electrode 41c may be used as a light-shielding electrode. The upper electrode 41a and the lower electrode 41c may have a thickness in the range of about 10 nm to 100 nm. The thickness of the upper electrode 41a and the lower electrode 41c may be in the range of about 30 nm to 100 nm. The thickness of the upper electrode 41a and the lower electrode 41c may be appropriately set according to the materials constituting them. For example, by forming a TaN electrode with a thickness of about 100 nm as the upper electrode 41a, sufficient light-shielding properties can be achieved in the upper electrode 41a. The same applies to the lower electrode 41c.

[0095] 3, the upper electrode 41a has a shape that covers the impurity region 2b when viewed along the normal direction of the semiconductor substrate 2. This configuration can prevent light that enters the photoelectric conversion unit 15 and passes through the gap between the second electrodes 15c from entering the impurity region 2b. In other words, generation of charges due to photoelectric conversion in the impurity region 2b can be prevented.

[0096] Since the impurity region 2b constitutes a part of the reset drain node 46, when charge is generated in the impurity region 2b by photoelectric conversion, the potential of the reset drain node 46 fluctuates. As can be seen from FIG. 2, the charge storage node 44 is electrically coupled to the reset drain node 46 via the second capacitance element 42. Therefore, when the potential of the reset drain node 46 fluctuates due to the generation of charge, the potential of the charge storage node 44 may fluctuate in accordance with the fluctuation in the potential of the reset drain node 46. That is, there is a risk of noise being mixed in due to the incidence of light on the impurity region 2b.

[0097] 3, the upper electrode 41a is shaped to cover the impurity region 2b in top view, thereby making it possible to suppress the inclusion of noise due to the incidence of light into the impurity region 2b. The same effect can be obtained by forming the upper electrode 41a and the lower electrode 41c so as to cover the impurity region 2b. Alternatively, as shown in FIG. 3, both the upper electrode 41a and the lower electrode 41c may be formed so as to cover the impurity region 2b in top view. Note that FIG. 3 shows a structure in which the upper electrode 41a has a larger area than the lower electrode 41c when viewed from the normal direction of the semiconductor substrate 2. However, it is not essential that the area of ​​the upper electrode 41a is larger than the lower electrode 41c when viewed from the normal direction of the semiconductor substrate 2. The area of ​​the upper electrode 41a may be smaller than the area of ​​the lower electrode 41c.

[0098] 3, a via 220 electrically connected to the impurity region 2b is connected to a lower surface 41d of the lower electrode 41c. A dielectric layer 41b covers the surface of the lower electrode 41c except for the lower surface 41d. An upper electrode 41a covers an upper surface 41e of the lower electrode 41c and a side surface connecting the upper surface 41e and the lower surface 41d.

[0099] During operation of the imaging device 100, a predetermined voltage is supplied to the upper electrode 41a via a sensitivity adjustment line 32 (not shown in FIG. 3). Typically, the potential of the upper electrode 41a is fixed at a constant value by supplying a predetermined voltage. For example, by fixing the potential of the upper electrode 41a at a constant value, the upper electrode 41a can function as a shield electrode, and an effect of reducing the inclusion of noise caused by electrical coupling with the lower electrode 41c can be obtained. It is also possible to adjust the sensitivity of the imaging device 100 by adjusting the voltage supplied to the upper electrode 41a via the sensitivity adjustment line 32.

[0100] As in this example, a contact for electrical connection with the impurity region 2b in the first capacitance element 41 is provided on the lower surface 41d side of the lower electrode 41c, and the upper electrode 41a covers the upper side of the lower electrode 41c, thereby suppressing electrical coupling between the lower electrode 41c and other electrodes and / or wiring. For example, as illustrated in FIG. 3, a wiring layer such as the wiring layer 52 may be disposed between the upper electrode 41a and the photoelectric conversion unit 15. As illustrated in FIG. 3, by covering the upper side of the lower electrode 41c with the upper electrode 41a and interposing the upper electrode 41a, it is possible to suppress electrical coupling between the lower electrode 41c and a wiring layer above the upper electrode 41a, such as the wiring layer 52.

[0101] Furthermore, in this example, not only the upper surface 41e of the lower electrode 41c but also the side surface connecting the upper surface 41e and the lower surface 41d is covered by the upper electrode 41a, so that the electrostatic shielding effect for the lower electrode 41c is improved, and electrical coupling between the lower electrode 41c and other electrodes and / or wiring can be more effectively suppressed. By connecting the via 220 to the lower surface 41d of the lower electrode 41c, the complication of wiring can also be avoided.

[0102] In this specification, the terms "upper surface" and "lower surface" are used to distinguish between the main surfaces of layered or plate-like members in a pixel, and are not used with the intention of limiting the orientation of the imaging device of the present disclosure. In this specification, "upper surface" refers to the main surface of the two main surfaces of the layer of interest that is closer to the photoelectric conversion section 15 than the semiconductor substrate 2. "Lower surface" refers to the main surface of the two main surfaces of the layer of interest that is closer to the semiconductor substrate 2 than the photoelectric conversion section 15, that is, the main surface opposite to the "upper surface".

[0103] By arranging the first capacitance element 41 within the interlayer insulating layer 4, physical interference with the gate electrodes of transistors such as the reset transistor 36 can be avoided. Therefore, compared to the case where the first capacitance element 41 is arranged on the main surface of the semiconductor substrate 2, the degree of freedom in designing the electrode shapes of the upper electrode 41a and the lower electrode 41c is improved, making it easier to ensure a larger electrode area. Furthermore, the range of materials to be selected for the upper electrode 41a, the dielectric layer 41b, and the lower electrode 41c is broadened, making it easier to form a first capacitance element 41 having a larger capacitance value within a pixel. As will be described later, by improving the capacitance value of the first capacitance element 41, it is possible to reduce noise using negative feedback. In noise cancellation, a higher noise reduction effect can be obtained.

[0104] On the other hand, as for the second capacitive element 42, as described later, from the viewpoint of obtaining a higher noise reduction effect in noise cancellation using negative feedback, it is advantageous for the capacitance value to be smaller. In the configuration illustrated in FIG. 3, the second capacitive element 42 is composed of a part of the lower electrode 41c, a part of the wiring 50a, and a part of the insulating layer 4b sandwiched therebetween. The wiring 50a of the connection portion 50 extends, for example, in a plane perpendicular to the normal direction of the semiconductor substrate 2, and has a part facing the lower electrode 41c of the first capacitive element 41. According to such a shape and arrangement of the electrodes and wiring, a capacitance is formed between a part of the lower electrode 41c and a part of the wiring 50a, and this capacitance can be used as the second capacitive element 42.

[0105] As described above, the adoption of a design in which the first capacitance element 41 is located in the interlayer insulating layer 4 broadens the range of material choices for the dielectric layer 41b. For example, the dielectric layer 41b may be formed using a material different from the material constituting the interlayer insulating layer 4. For example, the dielectric layer 41b may be formed from a metal oxide or a metal nitride. An example of a material for forming the dielectric layer 41b is an oxide or nitride containing one or more selected from the group consisting of Zr, Al, La, Ba, Ta, Ti, Bi, Sr, Si, Y, and Hf. The material for forming the dielectric layer 41b may be a binary compound, a ternary compound, or a quaternary compound.

[0106] The dielectric layer 41b can be formed by, for example, atomic layer deposition (ALD). ALD makes it possible to stack different atoms in layers of several atoms each. Specifically, precursor molecules of a raw material compound are introduced into a vacuum chamber in which a substrate is placed. The introduced precursor is adsorbed onto the surface of the substrate in the vacuum chamber. After that, a chemical reaction is performed to leave only the desired atoms in the precursor, thereby forming a film of one atomic layer.

[0107] Here, a film of oxide of Hf is used as the dielectric layer 41b of the first capacitance element 41. In forming the film of oxide of Hf, tetrakisethylmethylamido hafnium is used as a precursor, and plasma discharge is performed after the precursor is introduced. By performing plasma discharge in an oxygen atmosphere, the oxidation of Hf is promoted. By repeating the above-mentioned process, HfO2 is laminated layer by layer. For example, the introduction of the gaseous precursor and the plasma discharge are performed for 250 minutes. By repeating this process 10 times, a film having a thickness of 22 nm is formed as the dielectric layer 41b. The dielectric layer 41b may include two or more films made of different materials. By forming the dielectric layer 41b as a laminated film of two or more layers, a dielectric layer that makes use of the advantages of the materials constituting each layer is obtained.

[0108] As described above, the first capacitance element 41 has an opening 230, for example, in its center. That is, in this example, openings are provided in the upper electrode 41a, the dielectric layer 41b, and the lower electrode 41c. For example, with respect to the dielectric layer 41b, by applying photolithography introduced in a general semiconductor process, it is possible to form the dielectric layer 41b having an opening while leaving, for example, a film of an oxide of Hf in a desired region.

[0109] In addition, the dielectric layer 41b may be damaged in the process of removing the resist by being exposed to the plasma or radicals used in the ashing. The dielectric layer 41b may also be exposed to a resist stripping solution for removing the resist residue. If the dielectric layer 41b is damaged, the leakage current between the upper electrode 41a and the lower electrode 41c may increase. In the configuration illustrated in FIG. 3, an electrical coupling is formed between the lower electrode 41c of the first capacitance element 41 and the wiring 50a of the connection portion 50. Therefore, if a leakage current occurs between the upper electrode 41a and the lower electrode 41c of the first capacitance element 41, noise due to the leakage current may be mixed into the output signal.

[0110] For example, by providing a protective layer on the top surface of the dielectric layer 41b, it is possible to suppress damage to the dielectric layer 41b caused by removing the resist. As a material for forming the protective layer, a material having a relatively high electrical conductivity, such as a metal such as Cu or Al or polysilicon, may be selected. By using a material having a relatively high electrical conductivity as the material for the protective layer, it is possible to avoid a decrease in the capacitance value of the first capacitance element 41 caused by interposing the protective layer between the upper electrode 41a and the lower electrode 41c.

[0111] As described above, the connection portion 50 has a structure that connects the impurity region 2a in the semiconductor substrate 2 to the second electrode 15c of the photoelectric conversion portion 15. Here, the connection portion 50 penetrates the first capacitance element 41 at the position of the opening 230 of the first capacitance element 41 provided in the interlayer insulating layer 4, and electrically connects the impurity region 2a and the second electrode 15c to each other.

[0112] (Effect of Providing the Opening 230 in the First Capacitative Element 41) FIG. 7 shows an example of the arrangement of the connection portion 50 with respect to the first capacitance element 41. In the configuration illustrated in FIG. 7, the first capacitance element 41 of each pixel 10A surrounds the connection portion 50. In this example, the outer shapes of the upper electrode 41a and the opening 230 when viewed from the normal direction of the semiconductor substrate 2 are both rectangular. Needless to say, the outer shapes of the upper electrode 41a and the opening 230 when viewed from above are not limited to the shapes shown in FIG. 7, and any shape can be applied. In addition, the shape of the upper electrode 41a and the shape of the lower electrode 41c do not need to match when viewed from above. It is sufficient that the upper electrode 41a includes a portion that faces at least a part of the lower electrode 41c. The shape of the dielectric layer 41b when viewed from the normal direction of the semiconductor substrate 2 can also be set arbitrarily. The dielectric layer 41b in each pixel may be a continuous single layer, or may include multiple portions arranged at different positions in the same layer.

[0113] 7, the connection portion 50 may be disposed so as to penetrate the first capacitance element 41 at the position of the opening 230 provided in the first capacitance element 41. By disposing the connection portion 50 in the opening 230, it is easier to increase the electrode area of ​​the first capacitance element 41 and obtain a larger capacitance value than when the connection portion 50 is disposed between the first capacitance elements 41 of the adjacent pixels 10A. This is because, when attempting to connect the impurity region 2a of the semiconductor substrate 2 to the photoelectric conversion unit 15 by disposing the connection portion 50 between the adjacent pixels 10A, it is necessary to increase the interval between the adjacent first capacitance elements 41, making it difficult to increase the electrode area of ​​the first capacitance element 41.

[0114] The first capacitance element 41 may have two or more openings. However, when the pixel 10A has a connection portion other than the connection portion 50, such as a via that connects a wiring layer located below the first capacitance element 41 and a wiring layer located above the first capacitance element 41, the connection portion may be disposed in an opening other than the opening 230 through which the connection portion 50 penetrates. By disposing the connection portion other than the connection portion 50 in an opening other than the opening 230, electrical coupling between the connection portion 50 and the connection portion other than the connection portion 50 can be suppressed by a part of the first capacitance element 41 interposed therebetween, and the intrusion of noise into the charge accumulation region can be suppressed.

[0115] Furthermore, by providing the opening 230 in the first capacitive element 41, it is possible to expect effects such as an improvement in yield and suppression of shading. This point will be described below.

[0116] FIG. 8 shows an example of a chip 110 having a pixel region 240 including a plurality of pixels 10A. As described above, the pixel region 240 may include approximately 300,000 to 36 million pixels. In the example shown in FIG. 8, the pixel region 240 is a region having a repeating structure with the pixel 10A as a unit. As shown in the figure, the chip 110 further has a peripheral region 242 on the periphery and outside of the pixel region 240, where no pixels 10A are arranged. The peripheral region 242 may be a region on the semiconductor substrate 2 described above.

[0117] 9 and 10 show, as a reference example, a part of a manufacturing process of a pixel including an MIM structure without an opening in an interlayer insulating layer. When a capacitive element having an MIM structure is disposed in an interlayer insulating layer, as shown in FIG. 9, for example, an MIM structure 41r is formed on an insulating layer 400, and then an insulating layer 402 is formed to cover the MIM structure 41r. Here, no opening is provided in each of the MIM structures 41r.

[0118] The thickness of the MIM structure 41r, i.e., the distance from the lower surface of the lower electrode to the upper surface of the upper electrode in the MIM structure 41r, may be, for example, in the range of about 30 nm to 150 nm. Since the MIM structure 41r is disposed on the region 410 in which the pixel region 240 is to be formed, a step is generated on the upper surface of the insulating layer 402 between the region 420 that is to become the peripheral region 242 and the region 410. The size of this step, i.e., the difference in height between the portion of the upper surface of the insulating layer 402 located on the region 410 and the portion located on the region 420, may be in the range of about 30 nm to 150 nm depending on the thickness of the MIM structure 41r.

[0119] After the insulating layer 402 is formed, the upper surface of the insulating layer 402 is planarized by chemical mechanical polishing (CMP), etch-back, or the like. However, if no opening is provided in the MIM structure, the step on the upper surface of the insulating layer 402 may not be sufficiently reduced even by the planarization process. If the step on the upper surface of the insulating layer 402 is relatively large, a focus error may occur in photolithography when forming a wiring pattern or the like on the insulating layer 402, making it impossible to form a desired pattern, or even if an imaging device is finally obtained, shading may occur in the captured image. In other words, the yield may decrease.

[0120] 11 and 12 show a part of a manufacturing process of a pixel to which an MIM structure 41q having an opening 230 is applied as the first capacitive element 41. Note that it is assumed here that the total area of ​​the MIM structure 41q occupying the entire pixel region 240 in top view is equal to the total area of ​​the MIM structure 41r (see FIGS. 9 and 10) occupying the entire pixel region 240.

[0121] When the opening 230 is provided in the first capacitance element 41, as shown in FIG. 11, a number of protrusions 41p having shoulders 430 are formed on the upper surface of the insulating layer 4c covering the MIM structure 41q on the insulating layer 4b in a portion above the region 410. Since the upper surface of the insulating layer 4c has a number of shoulders 430, the removal rate of the portion of the upper surface of the insulating layer 4c above the region 410 is improved in the step of planarizing the insulating layer 4c, compared with the flat portion above the region 420. As a result, as shown in FIG. 12, the step on the upper surface of the insulating layer 4c is easily alleviated, and problems such as focus deviation and shading in the subsequent photolithography can be suppressed. FIG. 12 shows a schematic state after the planarization step is performed, and for comparison, the position of the upper surface of the insulating layer 402 shown in FIG. 10 is shown in the figure by a two-dot chain line.

[0122] In this manner, by providing the opening 230 in the first capacitive element 41, it is possible to reduce the step between the region to become the pixel region and the region to become the peripheral region, which is generated on the upper surface of the insulating layer covering the first capacitive element 41. In other words, the formation of the opening 230 in the first capacitive element 41 contributes to improving the flatness of the insulating layer covering the first capacitive element 41.

[0123] When the radius of a circle having an area equal to the opening area of ​​the opening 230 in a top view is d and the thickness of the first capacitance element 41, that is, the distance from the lower surface of the lower electrode 41c to the upper surface of the upper electrode 41a is h, (d / h) may be 1.4 or more. By providing the opening 230 in the first capacitance element 41, the flatness of the upper surface of the insulating layer covering the first capacitance element 41 is improved, so that a wiring pattern or the like can be more reliably formed above the insulating layer. Therefore, the yield can be improved. In addition, by reducing the step of the interlayer insulating layer between the pixel region 240 and the peripheral region 242 of the imaging device, deterioration of image quality caused by shading can be prevented.

[0124] (Noise cancellation using negative feedback) Here, an overview of noise cancellation using negative feedback will be described with reference to Fig. 2. An exemplary noise cancellation operation, which will be outlined below, is performed, for example, following a so-called electronic shutter that resets the signal charge in the charge accumulation region before the start of imaging. The noise cancellation operation is typically also performed after the pixel signal is read out after the end of the exposure period and after the signal charge accumulated during the exposure period is reset.

[0125] The resetting of the signal charge after the exposure period is performed as follows: First, exposure is performed with the reset transistor 36, feedback transistor 38, and address transistor 40 in an off state, and after the exposure period is completed, the address transistor 40 is turned on to read out a signal corresponding to the signal charge accumulated during the exposure period.

[0126] Thereafter, the reset transistor 36 and the feedback transistor 38 are turned on by controlling the potentials of the reset signal line 26 and the feedback control line 28. As a result, the charge storage node 44 and the feedback line 25 are connected via the reset transistor 36 and the feedback transistor 38, and a feedback loop is formed. Note that the formation of the feedback loop is performed sequentially for each of the multiple pixels 10A that share the feedback line 25.

[0127] By forming a feedback loop, the output of the signal detection transistor 34 is negatively fed back. Here, the feedback circuit 202 can be said to be a negative feedback amplifier circuit including the signal detection transistor 34, the inverting amplifier 24, and the feedback transistor 38. The feedback transistor 38 corresponds to the third transistor in this disclosure. By negatively feeding back the output of the signal detection transistor 34, the potential of the charge storage node 44 converges to a potential at which the voltage of the vertical signal line 18 becomes equal to Vref. In other words, the potential of the charge storage node 44 is reset. It can also be said that the signal charge is reset.

[0128] In this example, the voltage Vref applied to the positive input terminal of the inverting amplifier 24 corresponds to the reference voltage in the reset state. The specific value of the voltage Vref can be set arbitrarily within the range between the power supply voltage and the ground, i.e., 0 V. The power supply voltage is, for example, 3.3 V.

[0129] Next, the reset transistor 36 is turned off. Turning off the reset transistor 36 generates kTC noise. Therefore, the voltage of the charge storage node 44 after resetting is added with the kTC noise caused by turning off the reset transistor 36. After turning off the reset transistor 36, the kTC noise is canceled as follows.

[0130] 2, while the feedback transistor 38 is on, the feedback loop continues to be formed. Therefore, the kTC noise generated by turning off the reset transistor 36 is reduced to a magnitude of 1 / (1+A) where A is the gain of the feedback circuit 202. In this example, the voltage of the vertical signal line 18 immediately before turning off the reset transistor 36, in other words, immediately before the noise cancellation starts, is approximately equal to the voltage Vref applied to the positive input terminal of the inverting amplifier 24. By keeping the voltage of the vertical signal line 18 at the start of noise cancellation close to the target voltage Vref after noise cancellation, the kTC noise can be canceled in a relatively short time.

[0131] Next, the feedback transistor 38 is turned off. However, the magnitude of the kTC noise added to the voltage of the charge storage node 44 due to the feedback transistor 38 being turned off is (Cfd / C1) smaller than that in the case where the first capacitance element 41 and the second capacitance element 42 are not provided in the pixel 10A and the feedback transistor 38 is directly connected to the charge storage node 44. 1 / 2 ×(C2 / ( In the above formula, Cfd, C1, and C2 respectively represent the capacitance value of the charge storage node 44, the capacitance value of the first capacitance element 41, and the capacitance value of the second capacitance element 42, and "x" in the formula represents multiplication.

[0132] From the above formula, it can be seen that the larger the capacitance value C1 of the first capacitance element 41, the smaller the generated noise itself, and the smaller the capacitance value C2 of the second capacitance element 42, the larger the attenuation rate. Therefore, by appropriately setting the capacitance value C1 of the first capacitance element 41 and the capacitance value C2 of the second capacitance element 42, it is possible to sufficiently reduce the kTC noise generated by turning off the feedback transistor 38.

[0133] After the feedback transistor 38 is turned off, a signal from which the kTC noise has been cancelled is read out. The level of the signal obtained at this time corresponds to the signal level in the dark. Since the time required to read out the reset voltage is short, the signal after noise cancellation may be read out while the address transistor 40 continues to be on. A signal from which the fixed noise has been removed is obtained by taking the difference between the signal read out after exposure and before the start of resetting and the signal read out at this time. In this way, a signal from which the kTC noise and fixed noise have been removed is obtained.

[0134] In addition, when the reset transistor 36 and the feedback transistor 38 are in an off state, the first capacitance element 41 is connected to the charge storage node 44 via the second capacitance element 42. Here, assume that the charge storage node 44 and the first capacitance element 41 are directly connected without the second capacitance element 42. In this case, when the first capacitance element 41 is directly connected, the capacitance value of the entire signal charge storage region is (Cfd+C1). In other words, if the first capacitance element 41 has a relatively large capacitance value C1, the capacitance value of the entire signal charge storage region also becomes large, and therefore a high conversion gain cannot be obtained. In other words, it is difficult to obtain a high S / N ratio.

[0135] On the other hand, when the first capacitance element 41 is connected to the charge storage node 44 via the second capacitance element 42 as illustrated in FIG. 2, the capacitance value of the entire signal charge storage region in such a configuration is expressed as (Cfd+(C1C2) / (C1+C2)). Here, when the second capacitance element 42 has a relatively small capacitance value C2 and the first capacitance element 41 has a relatively large capacitance value C1, the capacitance value of the entire signal charge storage region is approximately (Cfd+C2). That is, the increase in the capacitance value of the entire signal charge storage region is small. In this way, by connecting the first capacitance element 41 to the charge storage node 44 via the second capacitance element 42 having a relatively small capacitance value, it is possible to suppress the decrease in conversion gain.

[0136] (Modification) As described with reference to FIG. 3, the second electrode 15c of each pixel 10A is typically spatially separated from the second electrodes 15c of other adjacent pixels 10A for electrical isolation. Therefore, there is generally a gap between the adjacent second electrodes 15c. Therefore, light passing through the gap may be diffusely reflected repeatedly within the pixel 10A and reach the impurity region 2a or the impurity region 2b of the semiconductor substrate 2.

[0137] For example, a light-shielding electrode is used as the upper electrode 41a and / or the lower electrode 41c of the first capacitance element 41, and the electrode area of ​​the first capacitance element 41 in a top view is made larger than the area of ​​the second electrode 15c of the photoelectric conversion unit 15, thereby reducing the gap between the pixels 10A and reducing stray light. In particular, since each of the upper electrodes 41a is configured to receive a predetermined voltage via the sensitivity adjustment line 32, the distance between adjacent upper electrodes 41a can be made sufficiently smaller than the distance between adjacent second electrodes 15c. However, even with this configuration, it is difficult to completely eliminate stray light, since light can pass through the gaps formed between adjacent upper electrodes 41a.

[0138] Figures 13 and 14 show modified examples of the imaging device 100. Figure 14 is a schematic cross-sectional view corresponding to Figure 13. As shown in Figure 14, for example, the shield electrode 14 may be disposed in the same layer as the second electrode 15c of the photoelectric conversion unit 15.

[0139] 13 shows an example of the arrangement between the upper electrode 41a, the second electrode 15c, and the shield electrode 14 when the photoelectric conversion layer 15b and the first electrode 15a are removed from the pixel 10A and viewed from the normal direction of the semiconductor substrate 2. In the example shown, the shield electrode 14 is formed in a grid shape including a plurality of portions extending along the boundary between the pixels 10A in a top view, and covers the gap between two adjacent upper electrodes 41a. By covering the gap between two adjacent upper electrodes 41a with the shield electrode 14, it is possible to further reduce the incidence of light into the gap between two adjacent upper electrodes 41a, thereby further reducing stray light.

[0140] The shield electrode 14 is configured to be supplied with a constant voltage during operation of the imaging device 100. Therefore, a gap for electrical insulation is provided between the second electrode 15c and the shield electrode 14. Most of the light passing through the gap between the second electrode 15c and the shield electrode 14 can be blocked by the upper electrode 41a or the lower electrode 41c of the first capacitance element 41. A plurality of strip-shaped electrodes extending in the row direction across a plurality of columns may be formed as the upper electrode 41a. In this case, no gap is generated between the upper electrodes 41a between the pixels 10A adjacent to each other in the row direction, so that stray light can be further reduced.

[0141] In addition, by providing a shield electrode maintained at a constant potential between pixels, it is possible to prevent the charge generated in the photoelectric conversion layer 15b of a pixel from being collected by the second electrode 15c of another pixel different from the pixel. For example, the charge generated near the boundary of the pixel and moving toward another pixel electrode different from the pixel electrode to which it should originally move, for example, toward a pixel electrode in an adjacent pixel, can be collected by the shield electrode 14. Therefore, unintended charge movement to an adjacent pixel is suppressed, and the occurrence of color mixing is reduced.

[0142] (Embodiment 2) Fig. 15 is a schematic cross-sectional view of a pixel of an imaging device according to another embodiment of the present disclosure. The main difference between the pixel 10A described above and the pixel 10B shown in Fig. 15 is that the pixel 10B does not have the second capacitance element 42, and the lower electrode 41c of the first capacitance element 41 is connected to the connection portion 50 by the via 320 without passing through the reset transistor 36.

[0143] In the configuration illustrated in FIG. 15, the via 320 is located between the lower electrode 41c and the wiring 50a of the connection portion 50, and one end of the via 320 is connected to the lower surface 41d of the lower electrode 41c. This is the same as the above-described embodiment in that a contact is provided on the lower surface 41d side of the lower electrode 41c, and the upper electrode 41a covers the upper side of the lower electrode 41c. The via 320 connected to the connection portion 50 can function as a part of the charge storage region. That is, by providing the via 320 between the lower electrode 41c and the connection portion 50, the effect of increasing the capacitance value of the charge storage region can be obtained.

[0144] In a configuration in which the lower electrode 41c of the first capacitance element 41 is connected to the connection portion 50 by the via 320, the larger the capacitance value of the first capacitance element 41, the higher the maximum amount of charge that can be stored in the entire charge storage region. This is advantageous for shooting under low light conditions.

[0145] It is also possible to connect the first capacitance element 41 to the connection portion 50 without the reset transistor 36 by connecting the upper electrode 41a to the connection portion 50 and connecting the lower electrode 41c to the sensitivity adjustment line 32 (not shown in FIG. 15). However, as in the configuration shown in FIG. 15, by connecting the lower electrode 41c to the connection portion 50 and covering the lower electrode 41c with the upper electrode 41a, electrical coupling between the lower electrode 41c and a wiring layer such as the wiring layer 52 arranged above the upper electrode 41a is suppressed, so that a noise reduction effect can be expected compared to the case where the upper electrode 41a is connected to the connection portion 50. The effect of reducing coupling can be further improved by forming the upper electrode 41a in a shape that covers the side surface connecting the upper surface 41e and the lower surface 41d of the lower electrode 41c.

[0146] Fig. 16 is a diagram showing an exemplary circuit configuration of the pixel 10B shown in Fig. 15. As shown in Fig. 16, one of the drain and source of the reset transistor 36 is connected to the charge storage node 44, and the other is connected to the feedback line 25 without passing through the feedback transistor 38 in the first embodiment. In addition, of the electrodes of the first capacitance element 41, the electrode that is not connected to the sensitivity adjustment line 32 is connected to the charge storage node 44.

[0147] (Noise cancellation using negative feedback) Next, a noise cancellation operation in the circuit configuration illustrated in Fig. 16 will be described. Here, the feedback circuit 302 illustrated in Fig. 16 is a negative feedback amplifier circuit including a signal detection transistor 34, an inverting amplifier 24, and a reset transistor 36. As will be understood from the following description, the reset transistor 36 in the example described here also functions as the feedback transistor 38 in the first embodiment.

[0148] For example, after the exposure period ends, the reset transistor 36 is turned on. By turning on the reset transistor 36, the charge storage node 44 and the feedback line 25 are connected via the reset transistor 36, and a feedback loop is formed in which the signal of the photoelectric conversion unit 15 is fed back. Here, the signal of the photoelectric conversion unit 15 is negatively fed back.

[0149] By electrically connecting the charge storage node 44 and the feedback line 25, the potential of the charge storage node 44 converges to a potential at which the voltage of the vertical signal line 18 becomes equal to Vref. In other words, the potential of the charge storage node 44 is reset.

[0150] Thereafter, the reset transistor 36 is turned off to execute noise cancellation. At this time, the potential of the reset signal line 26 is gradually lowered from a high level to a low level so as to cross the threshold voltage of the reset transistor 36.

[0151] When the potential of the reset signal line 26 is gradually decreased from high to low, the reset transistor 36 gradually changes from an ON state to an OFF state. While the reset transistor 36 is ON, the state in which the feedback loop is formed continues. At this time, the resistance of the reset transistor 36 increases with the decrease in the voltage applied to the reset signal line 26. When the resistance of the reset transistor 36 increases, the operating band of the reset transistor 36 narrows, and the frequency range of the feedback signal becomes narrower.

[0152] When the voltage applied to the reset signal line 26 reaches a low level, the reset transistor 36 is turned off. In other words, the formation of the feedback loop is eliminated. By turning off the reset transistor 36 in a state in which the operating band of the reset transistor 36 is lower than the operating band of the signal detection transistor 34, the kTC noise remaining in the charge storage node 44 is reduced. It is possible to reduce the noise.

[0153] In this example, the voltage of the vertical signal line 18 immediately before the voltage applied to the reset signal line 26 is changed toward a low level, that is, immediately before noise cancellation starts, is approximately equal to the voltage Vref applied to the non-inverting input terminal of the inverting amplifier 24. In this way, by keeping the voltage of the vertical signal line 18 at the start of noise cancellation close to the target voltage Vref after noise cancellation, it is possible to complete the cancellation of kTC noise in a relatively short time, even with control that gradually reduces the voltage applied to the reset signal line 26.

[0154] Each of the signal detection transistor 34, the reset transistor 36, the address transistor 40, and the feedback transistor 38 may be an N-channel MOSFET or a P-channel MOSFET. It is not necessary that all of them are unified into either an N-channel MOSFET or a P-channel MOSFET. [Industrial Applicability]

[0155] According to the embodiment of the present disclosure, the introduction of noise caused by the incidence of stray light into the impurity region is suppressed. The imaging device of the present disclosure is useful for, for example, an image sensor, a digital camera, etc. The imaging device of the present disclosure can be used in a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, etc. [Explanation of symbols]

[0156] 2. Semiconductor Substrate 2a, 2b, 2c impurity region 4 Interlayer insulation layer 10, 10A, 10B pixels 15 Photoelectric conversion unit 15a 1st electrode 15b Photoelectric conversion layer 15c 2nd electrode 24 Inverting Amplifier 25 Feedback Line 32 Sensitivity adjustment line 34 Signal detection transistor 36 Reset transistor 38 Feedback Transistor 40 Address transistor 41 First Capacitor 41a Upper electrode 41b Dielectric layer 41c lower electrode 41d Bottom surface 41e Top 42 Second Capacitor 44 Charge Storage Node 50 Connection 52 wiring layer 100 Imaging device 230 Aperture 240 pixel area 242 Surrounding Area

Claims

1. A pixel region including a plurality of pixels; a signal line extending across two or more pixels among the plurality of pixels; Equipped with Each of the plurality of pixels is A semiconductor substrate; A photoelectric conversion unit that converts incident light into an electric signal; a first transistor including a first impurity region disposed in the semiconductor substrate and configured to accumulate signal charges, and a second impurity region disposed in the semiconductor substrate; a wiring layer including a part of the signal line; a first insulating layer and a second insulating layer disposed between the first insulating layer and the second insulating layer in a normal direction of the semiconductor substrate; a first electrode; a second electrode disposed between the first electrode and the semiconductor substrate; and a capacitive element including a dielectric layer disposed between the first electrode and the second electrode; Including, one of the first impurity region and the second impurity region functions as a source region of the first transistor, and the other of the first impurity region and the second impurity region functions as a drain region of the first transistor; the second electrode is electrically connected to either the first impurity region or the second impurity region; the first electrode and the second electrode cover the entire first impurity region when viewed along a normal direction of the semiconductor substrate; Imaging device.

2. The first electrode and the second electrode are electrodes made of a metal or a metal compound. The imaging device according to claim 1 .

3. At least one selected from the group consisting of the first electrode and the second electrode covers at least a portion of the second impurity region when viewed along the normal direction.

3. The imaging device according to claim 1.

4. the second electrode has a first surface facing the first electrode and a second surface opposite to the first surface, and is electrically connected to the second impurity region; 4. The imaging device according to claim 1.

5. the second electrode is electrically connected to the second impurity region on the second surface; The imaging device according to claim 4.

6. a feedback circuit for negatively feeding back an output of a second transistor that amplifies a signal corresponding to an amount of charge stored in the first impurity region; the feedback circuit includes a third transistor including a source and a drain; one of the source and the drain is connected to the second impurity region; 6. The imaging device according to claim 4.

7. the second electrode has a first surface facing the first electrode and a second surface opposite to the first surface, and is electrically connected to the first impurity region; 4. The imaging device according to claim 1.

8. a feedback circuit for negatively feeding back an output of a second transistor that amplifies a signal corresponding to an amount of charge stored in the first impurity region; the second impurity region is electrically connected to an output line of the feedback circuit; The imaging device according to claim 7.

9. the dielectric layer covers a surface of the second electrode other than the second surface, The first electrode covers a side surface of the second electrode connecting the first surface and the second surface.

9. The imaging device according to claim 4.

10. the signal line is a control line for driving the two or more pixels, a power supply line for supplying a voltage to the two or more pixels, or an output line for reading out a signal from the two or more pixels; The imaging device according to claim 1 .

Images