Semiconductor Device

Abstract

To enable a large-area substrate and form an oxide semiconductor layer having excellent crystallinity to enable manufacturing of a transistor having an intended high field-effect mobility to achieve the practical use of a large-sized display device, a high-performance semiconductor device and the like.SOLUTION: A semiconductor device is manufactured by the steps of: forming a first multi-component oxide semiconductor layer on a substrate; forming a single-component oxide semiconductor layer on the first multi-component oxide semiconductor layer; performing a heat treatment of not less than 500°C and not more than 1000°C, favorably not less than 550°C and not more than 750°C to grow crystal from a surface toward the inside to form a multi-component oxide semiconductor layer having a first crystal region and a single-component oxide semiconductor layer having a single crystal region; and laminate on the single-crystal oxide semiconductor layer having the single crystal region, a multi-component oxide semiconductor layer having a second single crystal region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] A semiconductor device having a circuit that includes a semiconductor element such as a transistor as at least one element. For example, the present invention relates to a power device mounted on a power supply circuit, a memory, and a semiconductor device and a method for manufacturing the same. , thyristors, converters, semiconductor integrated circuits including image sensors, liquid crystal display panels or a light-emitting display device having a light-emitting element. This relates to electronic devices.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] As typified by liquid crystal display devices, transistors formed on glass substrates are amorphous. It is made of amorphous silicon, polycrystalline silicon, etc. Although the resulting transistor has low field-effect mobility, it can be used on large glass substrates. In addition, although the field effect mobility of a transistor using polycrystalline silicon is high, it is difficult to use a glass substrate. However, it has the drawback that it is not suitable for large areas.

[0004] For a transistor using silicon, a transistor using an oxide semiconductor is manufactured. The technology is attracting attention for its application to electronic and optical devices. For example, as an oxide semiconductor, , zinc oxide, and In-Ga-Zn-O oxide were used to fabricate transistors, and The technology used for pixel switching elements is disclosed in Patent Documents 1 and 2. . [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] Larger display devices are also becoming more common. Even in home televisions, the diagonal of the display screen is 4. Televisions ranging from 0 to 50 inches are also beginning to become popular.

[0007] The field-effect mobility of transistors using conventional oxide semiconductors is 10 to 20 cm 2 / Vs Transistors using oxide semiconductors are superior to amorphous silicon transistors. Since the field effect mobility is 10 times higher than that of conventional MOS transistors, the pixel shift can be reduced even in large display devices. As a switching element, sufficient performance can be obtained.

[0008] However, when a transistor using an oxide semiconductor is used as a driving device of a semiconductor device, for example, a large There is a limit to its use as a switching element in a drive circuit for a display device or the like.

[0009] One embodiment of the present invention is to provide an oxide semiconductor having excellent crystallinity that enables a substrate to have a large area. The layer is formed, and a transistor having a desired high field effect mobility can be manufactured. One of the goals is to commercialize display devices and high-performance semiconductor devices. [Means for solving the problem]

[0010] One embodiment of the present invention is a method for forming a first multi-component oxide semiconductor layer over a substrate, A single-component oxide semiconductor layer is formed on the semiconductor layer, and the layer is heated at 500° C. or higher and 1000° C. or lower, preferably Heat treatment is carried out at temperatures between 550°C and 750°C to allow crystal growth from the surface to the inside. A multi-component oxide semiconductor layer having a single crystal region and a single-component oxide semiconductor layer having a single crystal region a first single-crystal region on the single-component oxide semiconductor layer; The multi-component oxide semiconductor layer is stacked. a single-component oxide semiconductor layer having a single crystal region, and a second single crystal region; The single crystal region of the multi-component oxide semiconductor layer has flat single crystals with a uniform crystal orientation on the surface. The flat single crystal region has an ab plane parallel to its surface, and the first single crystal a multi-component oxide semiconductor layer having a crystalline region, a single-component oxide semiconductor layer having a single crystal region, and a multi-component oxide semiconductor layer having a second single crystal region, the multi-component oxide semiconductor layer having a c-axis oriented in a direction perpendicular to the surface of the multi-component oxide semiconductor layer; In addition, a multi-component oxide semiconductor layer having a first single crystal region and a first single crystal region are formed on the first oxide semiconductor layer. The c-axis directions of the first oxide semiconductor layer and the second multi-component oxide semiconductor layer having a single crystal region are , coincident with the depth direction.

[0011] forming a single-component oxide semiconductor layer on the first multi-component oxide semiconductor layer; and heating the layer at 500° C. or higher for 1000° C. ℃ or less, preferably 550℃ to 750℃, from the surface to the inside. Crystal growth is performed using a single crystal layer to form a single-component oxide semiconductor layer having a single crystal region. The single crystal region with a uniform crystal orientation formed on the surface of the single-component oxide semiconductor layer is Since the crystal grows in the depth direction from the surface, it is not affected by the underlying material of the single-component oxide semiconductor layer. Furthermore, a single-crystal region can be formed. The first multi-component oxide semiconductor layer is used as a seed to form epitaxial growth or annealing from the surface of the first multi-component oxide semiconductor layer. In order to perform crystal growth of the first multi-component oxide semiconductor layer by the first multi-component oxide semiconductor layer, Therefore, the single crystal region can be formed without being affected by the underlying material of the compound semiconductor layer.

[0012] The second multi-component oxide semiconductor layer having a single crystal region is a single-component oxide semiconductor layer having a single crystal region. After forming the second multi-component oxide semiconductor layer on the conductor layer, the second multi-component oxide semiconductor layer is heated at 100° C. or more and 500° C. or less, preferably Alternatively, a heat treatment at 150°C or higher and 400°C or lower is carried out to obtain a single-component oxide having a single crystal region. Crystal growth is performed from the surface of the semiconductor layer toward the surface of the second multi-component oxide semiconductor layer above the surface of the semiconductor layer. That is, a single-component oxide semiconductor layer having a single crystal region can be formed by For the multi-component oxide semiconductor layer 2, it corresponds to a seed crystal.

[0013] The second multi-component oxide semiconductor layer having a single crystal region is a single-component oxide semiconductor layer having a single crystal region. The compound semiconductor layer is heated at 200° C. or higher and 600° C. or lower, preferably 200° C. or higher and 550° C. or lower. Deposition is performed while heating, typically by sputtering, to form a single crystal region. epitaxially or axially grown from the surface of a single-component oxide semiconductor layer having A multi-component oxide semiconductor layer having a second single crystal region can be formed. The single-component oxide semiconductor layer having a single crystal region is a multi-component oxide semiconductor layer having a second single crystal region. It corresponds to a seed crystal for the conductor layer.

[0014] A multi-component oxide semiconductor layer having a first single crystal region and a multi-component oxide semiconductor layer having a second single crystal region. The oxide semiconductor layer is grown by crystal growth using a single-component oxide semiconductor layer having a single crystal region as a seed crystal. Therefore, the single-crystal oxide semiconductor layer has substantially the same crystal orientation as the single-crystal oxide semiconductor layer. .

[0015] Thereafter, a multi-component oxide semiconductor layer having a first single crystal region and a single-component oxide semiconductor layer having a single crystal region are formed. the multi-component oxide semiconductor layer having the second single crystal region and the second multi-component oxide semiconductor layer into island shapes. a source electrode and a drain electrode on the multi-component oxide semiconductor layer having the second single crystal region; After forming the gate insulating layer and gate electrode, a top gate structure transistor is formed. A transistor can be fabricated.

[0016] Also, after forming a gate electrode and a gate insulating layer on the substrate, a first unit is formed on the gate insulating layer. A multi-component oxide semiconductor layer having a crystalline region, a single-component oxide semiconductor layer having a single crystal region, and A multi-component oxide semiconductor layer having a second single crystal region is formed, and the first single crystal region is formed. a multi-component oxide semiconductor layer having a single crystal region, a single-component oxide semiconductor layer having a single crystal region, and a second single crystal The multi-component oxide semiconductor layer having the region is etched into an island shape, and a source electrode and a drain electrode are formed. By forming the above, a bottom-gate transistor can be manufactured.

[0017] Further, one embodiment of the present invention is a multi-component oxide semiconductor layer having a first single crystal region, a single crystal region, and a multi-component oxide semiconductor layer having a first single crystal region. a gate electrode; and a gate electrode provided between the oxide semiconductor stack and the gate electrode. and a thin film transistor having a gate insulating layer electrically connected to the oxide semiconductor stack. The semiconductor device includes a transistor.

[0018] A multi-component oxide semiconductor layer having a first single crystal region, a single-component oxide semiconductor layer having a single crystal region, a heat treatment for forming a multi-component oxide semiconductor layer having a second single crystal region; The heat treatment for forming the film is carried out in an atmosphere containing almost no hydrogen or moisture (nitrogen atmosphere, oxygen atmosphere, etc.). It is preferable to carry out the heat treatment in a dry atmosphere or a dry air atmosphere. Hydrogen, water, hydroxyl groups, hydrides, etc. are released from the compound semiconductor layer and the multi-component oxide semiconductor layer. a multi-component oxide semiconductor layer having a first single-crystal region; a single-component oxide semiconductor layer having a single crystal region, and a multi-component oxide semiconductor layer having a second single crystal region; The heat treatment can be performed in an inert atmosphere at a high temperature. It is also possible to switch to an oxygen-containing atmosphere midway through the heating process. When heat treatment is performed in air, the oxide semiconductor layer is oxidized, and oxygen defects can be repaired. The oxide semiconductor layer having a single crystal region that has been subjected to the heat treatment can be subjected to TDS (Thermal Deposition Synchronization). Measurements were performed up to 450°C using ion desorption spectroscopy (Ion Desorption Spectroscopy). However, of the two peaks due to water, at least one peak appears around 300°C. Not detected.

[0019] A multi-component oxide semiconductor layer having a first single crystal region and a multi-component oxide semiconductor layer having a second single crystal region. When the oxide semiconductor layer contains In, the electron clouds of In are mutually separated in the flat single crystal region. By overlapping and connecting the two, the electrical conductivity σ increases. The field effect mobility can be increased.

[0020] A multi-component oxide semiconductor layer having a highly purified first single crystal region, a first single crystal region, and a second single crystal region. a water-containing multi-component oxide semiconductor layer having a single crystal region and a second multi-component oxide semiconductor layer having a single crystal region; The element concentration is 1 x 10 18 cm -3 Below, 1×10 16 cm -3 Below, and even more effectively 0 and the carrier density is 1×10 14 cm -3 Less than 1 x 10 12 cm -3 less than , and more preferably 1.45 × 10 below the measurement limit 10 cm -3 can be less than The band gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. be.

[0021] Note that the transistor according to one embodiment of the present invention is an insulated gate field effect transistor (Ins ated-Gate Field-Effect Transistor(IGFET) ), including thin film transistors (TFTs). [Effects of the Invention]

[0022] Whether the underlying substrate material is oxide, nitride, or metal, it can be highly We will fabricate transistors with high field effect mobility and use them in large-scale display devices and high-performance semiconductor devices. Be realized. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 3]1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C are diagrams illustrating a crystal growth process of an oxide semiconductor layer. [Figure 5] 1A to 1C are diagrams illustrating a crystal growth process of an oxide semiconductor layer. [Figure 6] 1A to 1C are diagrams illustrating a crystal growth process of an oxide semiconductor layer. [Figure 7] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor layer. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A and 1B are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. [Figure 19] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 21]1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A and 1B are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A and 1B illustrate one embodiment of an electronic device. [Figure 24] 1A and 1B illustrate one embodiment of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in the following manner. It should be noted that the present invention is not limited to the following description. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. It will be used throughout and repeated explanations will be omitted.

[0025] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0026] In addition, terms such as first, second, and third used in this specification are used in order to avoid confusion of components. It is not a numerical limitation. For example, "first" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0027] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. It refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage" or Voltage may be read as potential.

[0028] (Embodiment 1) FIG. 1 is a cross-sectional view illustrating a transistor 150, which is one aspect of a semiconductor device. The transistor 150 is an n-channel IGFET (Insulator-Gate-Field Effect Transistor) in which the carriers are electrons. It is assumed that the However, it is also possible to fabricate a p-channel IGFET. In the following description, a transistor with a top-gate structure is used as the transistor 150.

[0029] The transistor 150 shown in FIG. 1 is a multi-component oxide having a first single crystal region on a substrate 100. a single-component oxide semiconductor layer 103a having a single crystal region, a single-component oxide semiconductor layer 105a having a single crystal region, and a second A multi-component oxide semiconductor layer 107a having a single crystal region is formed by stacking (oxide semiconductor layer On top of that, wirings 108a and 108b functioning as source and drain electrodes are provided. In addition, the multi-component oxide semiconductor layer 107a having the second single crystal region and the wiring 1 A gate insulating layer 112 is formed on the gate insulating layer 112. The multi-component oxide semiconductor layer 10 having the first single crystal region is connected to the gate insulating layer 112 via the gate insulating layer 112. 3a, a single-component oxide semiconductor layer 105a having a single crystal region, and a second single-component oxide semiconductor layer 106a having a single crystal region. A gate electrode 114 is formed in a region facing the multi-component oxide semiconductor layer 107a. An insulating layer 116 may be provided on the gate insulating layer 112 and the gate electrode 114 .

[0030] Next, a method for manufacturing an oxide semiconductor stack having a single crystal region and a method for manufacturing the oxide semiconductor stack will be described. A thin film transistor formed using the above will be described with reference to FIGS.

[0031] A first multi-component oxide semiconductor layer 102 is formed on a substrate 100. A single-component oxide semiconductor layer 104 is formed over the layer 102 (see FIG. 2A).

[0032] The substrate 100 must have at least enough heat resistance to withstand subsequent heat treatment. When a glass substrate is used as the substrate 100, a substrate having a distortion point of 730° C. or higher is used. The glass substrate is preferably made of, for example, aluminosilicate glass, aluminophore glass, or the like. Glass materials such as borosilicate glass and barium borosilicate glass are used. It is preferable to use a glass substrate containing more BaO than O3.

[0033] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material can be used. Alternatively, crystallized glass can be used. Furthermore, the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material It is also possible to use a material having an insulating layer formed on its surface.

[0034] As will be described later, according to this embodiment, a first multi-component oxide film is provided on the substrate 100. The crystallization of the compound semiconductor layer 102 and the single-component oxide semiconductor layer 104 depends on the material of the underlying substrate. Since the substrate 100 is not affected by the temperature, various materials can be used as the substrate 100 as described above.

[0035] The first multi-component oxide semiconductor layer 102 and the single-component oxide semiconductor layer 104 are formed by sputtering. The first multi-component oxide semiconductor layer 102 is formed by heating to form a hexagonal non-crystalline oxide semiconductor layer. The hexagonal non-wurtzite crystal structure is called a homologous structure. The non-wurtzite crystal structure is a crystal structure that is not wurtzite.

[0036] The first multi-component oxide semiconductor layer 102 is made of a quaternary metal oxide, In—Sn—Ga -Zn-O system, ternary metal oxides such as In-Ga-Zn-O system and In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O system, binary metal oxides In-Zn-O system, Sn-Zn-O system , Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, etc. Here, the multi-component oxide semiconductor layer is a layer made of a plurality of metal oxides. An n-element metal oxide is composed of n kinds of metal oxides. Multi-component oxide semiconductors contain impurities of 1% or less of elements other than the main component metal oxide, preferably 1% or less. Preferably, 0.1% may be included.

[0037] The first multi-component oxide semiconductor layer 102 is a ternary metal oxide, and is composed of InM X Zn Y O Z (Y=0.5 to 5), where M is Selected from group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). The content of In, M, Zn, and O is optional. , including the case where the content of M is zero (i.e., x=0). On the other hand, the contents of In and Zn are zero. In other words, the above notation does not include In-Ga-Zn-O based oxide semiconductors or In-Z These include nO-based oxide semiconductors.

[0038] The sputtering method is an RF sputtering method that uses a high frequency power supply as the sputtering power source. There are two methods: DC sputtering and pulsed DC sputtering, which applies a bias voltage in a pulsed manner. The RF sputtering method is mainly used to form insulating layers, while the DC The sputtering method is mainly used to form a metal layer.

[0039] The first multi-component oxide semiconductor layer 102 is formed by sputtering. For example, a target of a metal oxide containing zinc can be used. The composition ratio of the metal oxide target containing In and Zn is In:Ga:Zn=1:x:y (where x is 0 or more, y is 0.5 or more and 5 or less). For example, In:Ga:Zn=1:1:0.5[ A target having a composition ratio of In:Ga:Zn=1:1:1 [atomic ratio] or a target having a composition ratio of In:Ga:Zn=1:1:2 [atomic ratio] A target with a composition ratio of In:Ga:Zn=1:0.5:2 [atom ratio] In this embodiment, a target having the above structure can be used. In order to effectively crystallize the metal oxide, it is preferable to use a metal oxide target that is prone to crystallization. stomach.

[0040] The single-component oxide semiconductor layer 104 is a single-component oxide semiconductor layer that can be transformed into a hexagonal wurtzite crystal structure by heating. It is preferable to form it from a single-component oxide semiconductor, a typical example of which is zinc oxide. An oxide semiconductor is a semiconductor that is made up of one kind of metal oxide. The body may contain 1% or preferably 0.1% of elements other than metal oxides as impurities. Single-component oxide semiconductors are easier to crystallize than multi-component oxide semiconductors, and the crystallinity is The single-component oxide semiconductor layer 104 can be improved by 2, and serves as a seed for crystal growth of the second multi-component oxide semiconductor layer 106 to be formed later. Since it is used as a thin film, the thickness is sufficient for crystal growth, typically between one atomic layer and 10 nm. The thickness of the single-component oxide semiconductor layer 104 is preferably 2 nm or more and 5 nm or less. This can increase the throughput in the film formation process and the heat treatment.

[0041] The single-component oxide semiconductor layer 104 is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or or formed by sputtering in an atmosphere of rare gas (typically argon) and oxygen It is possible.

[0042] In addition, similarly to the first multi-component oxide semiconductor layer 102, the oxide semiconductor in the metal oxide target The relative density of the conductor is 80% or more, preferably 95% or more, and more preferably 99.9% or more. It is preferable to do so.

[0043] Similarly to the first multi-component oxide semiconductor layer 102, a single-component oxide semiconductor layer was formed while heating the substrate. By forming the conductor layer 104, crystal growth is promoted in the first heat treatment to be performed later. It is possible.

[0044] Next, a first heat treatment is performed. The temperature of the first heat treatment is 500° C. or more and 1000° C. or less. The temperature is preferably 600°C or higher and 850°C or lower. The heating time is 1 minute or higher and 24 hours or lower. do.

[0045] The first heat treatment may be performed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a nitrogen atmosphere. atmosphere, dry air atmosphere, or a mixture of a rare gas (typically argon) and oxygen atmosphere; Alternatively, a mixed atmosphere of rare gas and nitrogen is preferable.

[0046] In this embodiment, the first heat treatment is performed in a dry air atmosphere at 700° C. for 1 hour. Carry out the process.

[0047] After the single-component oxide semiconductor layer 104 was heated while gradually increasing its temperature, the first poly The elemental oxide semiconductor layer 102 may be heated at a constant temperature. By setting the heating rate to 0.5° C. / h or more and 3° C. / h or less, the single-component oxide semiconductor layer 104 gradually Since crystals grow and the single-component oxide semiconductor layer 105 is formed, the crystallinity can be further improved. can.

[0048] The heat treatment device used for the first heat treatment is not particularly limited, and may be any device that can be used for the first heat treatment. The apparatus may include a device for heating the object to be treated by conduction or thermal radiation. As processing equipment, electric furnaces and GRTA (Gas Rapid Thermal Annealing) al) equipment, LRTA (Lamp Rapid Thermal Anneal) equipment, etc. A rapid thermal anneal (RTA) device such as the L RTA devices are available in halogen lamps, metal halide lamps, xenon arc lamps, and carbon Light emitted from lamps such as arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps (electric The GRTA device uses high-temperature gas to heat the object to be treated. This is an apparatus for performing heat treatment.

[0049] By the first heat treatment, the single-component oxide semiconductor layer 104 Crystal growth begins from the surface of the first multi-component oxide semiconductor layer 102. Since the semiconductor layer 104 is easily crystallized, the entire single-component oxide semiconductor layer 104 is crystallized. The single-component oxide semiconductor layer 105 having a single crystal region is formed. The Pt-based oxide semiconductor layer 105 has a hexagonal wurtzite crystal structure (see FIG. 2B).

[0050] By the heat treatment, crystals grow from the surface of the single-component oxide semiconductor layer 104, and a single crystal is formed. The single crystal region is formed by crystal growth from the surface to the inside, and the crystal grows to a thickness of more than one atomic layer. The plate-shaped crystal regions have an average thickness of 10 nm or less, preferably 2 nm to 5 nm. The single crystal region has an ab plane parallel to its surface and a c plane perpendicular to the surface. In this embodiment, the single-component oxide semiconductor layer 1 is oriented in the axial direction by the first heat treatment. Almost all of 04 becomes crystals (also called CG (Co-growing) crystals). The single-crystal region on the surface of the oxide semiconductor layer 104, which has a relatively uniform crystal orientation, extends from the surface to the depth direction. Since the crystals grow in the film, they can be formed without being affected by the underlying material.

[0051] Subsequently, first heat treatment is performed to form the single-component oxide semiconductor layer 105 having a single crystal region. The crystal growth of the first multi-component oxide semiconductor layer 102 is directed toward the substrate 100 as shown by the arrow. The single-crystal oxide semiconductor layer 105 has a crystal structure in which the crystal structure is oriented in a direction perpendicular to the surface. Since the axes are aligned, the single-component oxide semiconductor layer 105 having a single crystal region can be used as a seed. The first oxide semiconductor layer 105 is formed so that the crystal axis of the first oxide semiconductor layer 105 is substantially the same as that of the single crystal semiconductor layer 105. The multi-component oxide semiconductor layer 102 is grown by crystal growth (epitaxial growth or axial growth). That is, the first multi-component oxide semiconductor layer 102 can be made to have a c-axis alignment. As a result, the first single crystal region with c-axis orientation is formed. A multi-component oxide semiconductor layer 103 having a first single crystal region can be formed. The multi-component oxide semiconductor layer 103 has a hexagonal crystal structure, not a wurtzite crystal structure (FIG. 2( See C).

[0052] For example, the multi-component oxide semiconductor layer having the first single crystal region may be an In—Ga—Zn—O system. When using oxide semiconductor materials, InGaO3(ZnO) m The crystal (InG InZnO4, InGaZn5O8, etc.) and crystals represented by In2Ga2ZnO7. Such crystals have a hexagonal structure, and the c-axis of the crystals is aligned as follows by the first heat treatment: The orientation is such that it is approximately perpendicular to the surface of the single-component oxide semiconductor layer.

[0053] Next, as shown in FIG. 2D, a first oxide semiconductor layer is formed on the single-crystal oxide semiconductor layer 105. The second multi-component oxide semiconductor layer 106 is formed by annealing. The second multi-component oxide semiconductor layer 106 has a hexagonal non-wurtzite crystal structure due to heat. The second oxide semiconductor layer can be formed by a method similar to that of the single-component oxide semiconductor layer 104. The thickness of the multi-component oxide semiconductor layer 106 is determined by the practitioner depending on the device to be manufactured. For example, the first multi-component oxide semiconductor layer 102 and the single-component oxide semiconductor layer 10 The total thickness of the first and second multi-component oxide semiconductor layers 104 and 106 is 10 nm or more and 200 nm or less. Let's say.

[0054] The second multi-component oxide semiconductor layer 106 is made of the same material as the first multi-component oxide semiconductor layer 102. and forming method can be used appropriately.

[0055] Next, a second heat treatment is performed. The temperature of the second heat treatment is 100° C. or higher and 500° C. or lower, preferably Preferably, the temperature is 150°C or higher and 400°C or lower. The heating time is 1 minute or higher and 100 hours or lower. The time is preferably 5 hours or more and 20 hours or less, and typically 10 hours.

[0056] In the second heat treatment, the atmosphere can be the same as that in the first heat treatment. In addition, the same heating device as that used in the first heat treatment can be used as appropriate.

[0057] By performing the second heat treatment, a monocrystalline structure having a single crystal region is formed as shown by the arrow in FIG. Crystal growth from the multi-component oxide semiconductor layer 105 toward the surface of the second multi-component oxide semiconductor layer 106 The single-component oxide semiconductor layer 105 having a single crystal region begins to Since the single-component oxide semiconductor layer 105 has a c-axis orientation, the single-component oxide semiconductor layer 105 having a single crystal region can be used as a seed. The second multi-component oxide semiconductor layer 106 is formed in the same manner as the first multi-component oxide semiconductor layer 102. The second oxide semiconductor layer 105 is formed so that the crystal axis of the second oxide semiconductor layer 105 is substantially the same as that of the single crystal region. The multi-component oxide semiconductor layer 106 is grown by crystal growth (epitaxial growth or axial growth). That is, the second multi-component oxide semiconductor layer 106 can be c-axis oriented. By the above steps, a crystal having a second single crystal region can be grown. A multi-component oxide semiconductor layer 107 having a second single crystal region can be formed. The Pb-based oxide semiconductor layer 107 does not have a wurtzite crystal structure but has a hexagonal crystal structure (see FIG. 2E). ).

[0058] For example, an In-Ga-Zn-O based multi-component oxide semiconductor layer having a second single crystal region may be used. When using oxide semiconductor materials, InGaO3(ZnO) m The crystal (InGa ZnO4, InGaZn5O8, etc.) and crystals represented by In2Ga2ZnO7. Such crystals have a hexagonal structure, and the c-axis of the crystals is aligned with the first The crystalline silicon is oriented in a direction substantially perpendicular to the surface of the multi-component oxide semiconductor layer 2.

[0059] Here, the c-axis of the first multi-component oxide semiconductor layer 102 and the second multi-component oxide semiconductor layer 103 is The crystals oriented in a direction almost perpendicular to the surface of 06 are either In, Ga, or Zn. It has a laminated structure of layers parallel to the a-axis and b-axis. Specifically, In2Ga2ZnO7, InGaZnO4, In The GaZn5O8 crystal consists of a layer containing In and a layer not containing In (Ga or a layer containing Zn) are stacked in the c-axis direction.

[0060] In the In-Ga-Zn-O oxide semiconductor, the layer containing In has ab-plane This is because the In-Ga-Zn-O oxide semiconductor has good electrical conductivity. is mainly controlled by In, and the 5s orbital of In is By having overlaps with the path, a career path is formed. The transistor shown in the figure is a multi-component oxide having a first single-crystal region that is highly crystalline. a single-component oxide semiconductor layer having a single crystal region, and a second single crystal region; Since it has a multi-component oxide semiconductor layer, it can be in an amorphous, microcrystalline, or polycrystalline state. In comparison, the number of impurities and defects is small. a single-component oxide semiconductor layer having a single crystal region, a single-component oxide semiconductor layer having a second single crystal region, and a The carrier mobility of the multi-component oxide semiconductor layer is improved, and the on-current and field effect of the transistor are improved. This can increase the fruit mobility.

[0061] Here, the first multi-component oxide semiconductor layer 103 having a single crystal region and the a single-component oxide semiconductor layer 105 having a first single crystal region and a multi-component oxide semiconductor layer 106 having a second single crystal region; The interface of the layer 107 is indicated by a dotted line. The layer 105 is made of ZnO, and the multi-component oxide semiconductor layer 103 has a first single crystal region. The multi-component oxide semiconductor layer 107 having the single crystal region of In-Ga-Zn-O system oxide semiconductor When used as a conductor, the pressure and temperature of the heat treatment can be used to produce ZnO or In-Ga-Zn-O oxide. This is because the zinc contained in the semiconductor diffuses up to 450°C during TDS measurement. When the measurement was carried out, In and Ga were not detected, but zinc was found to be This can be confirmed by the fact that a peak is detected at 1000 kJ / cm2. It has been confirmed that lead is detected at temperatures around 200°C. a multi-component oxide semiconductor layer having a first single crystal region, a single-component oxide semiconductor layer having a single crystal region, the boundary between the semiconductor layer and the multi-component oxide semiconductor layer having the second single-crystal region cannot be distinguished, They may be considered to be the same layer 109 .

[0062] Through the above steps, the multi-component oxide semiconductor layer 103 having the first single crystal region and the single crystal region are obtained. a single-component oxide semiconductor layer 105 having a first single crystal region and a multi-component oxide semiconductor layer 106 having a second single crystal region; Layer 107 can be formed.

[0063] Here, the first heat treatment causes the single-component oxide semiconductor layer 104 having a single crystal region to have a plate-like structure. The mechanism by which the crystalline regions are formed will be described with reference to FIGS.

[0064] The atomic motion during the first heat treatment was investigated using classical molecular dynamics. In quantum mechanics, the forces acting on atoms are determined by defining empirical potentials that characterize the interactions between atoms. Here, we apply the laws of classical mechanics to each atom and evaluate it as Newton's The motion (time evolution) of each atom was verified by numerically solving the equation of motion. In this case, the Born-Mayer-Huggins potential is used as an empirical potential. A gal was used.

[0065] As shown in Figure 4, amorphous zinc oxide (hereinafter referred to as a-ZnO) contains single crystals with a width of 1 nm. A model in which crystalline zinc oxide (hereinafter referred to as c-ZnO) is arranged at equal intervals as crystal nuclei 160. The density of a-ZnO and c-ZnO was 5.5 g / cm 3 Also, The vertical direction was defined as the c-axis direction.

[0066] Next, in the model shown in Figure 4, the c-ZnO was fixed and heated at 700℃ under three-dimensional periodic boundary conditions. A classical molecular dynamics simulation for 100 psec (time step width 0.2 fsec x 500,000 steps) The results of the simulation are shown in Figures 5 and 6.

[0067] Figure 5(A), Figure 5(B), and Figure 5(C) are for 20 psec, 40 psec, and 60 psec, respectively. Figure 6(A) and Figure 6(B) show the change in atomic configuration over the ec course. The changes in atomic configuration after 100 psec and 100 psec are shown. The length and direction of the arrow indicate the distance and direction of crystal growth.

[0068] The crystal growth rates in the vertical direction (c-axis

[0001] ) and the horizontal direction perpendicular to it are shown in Table 1. .

[0069] [Table 1]

[0070] In FIG. 5, arrows 162, 166, and 170 in the vertical direction (c-axis direction) are Arrows 164a, 164b, 168a, 168b, 172a, 172b (perpendicular to the axial direction) Since the length of b is long, lateral crystal growth is preferred. It can be seen that crystal growth is completed between adjacent crystal nuclei.

[0071] In FIG. 6, the crystalline regions formed on the surface are used as seeds, and as shown by arrows 174 and 176, It can be seen that the crystals grow in the vertical direction (c-axis direction).

[0072] In addition, from Table 1, it is clear that the crystal growth is more rapid in the horizontal direction, which is perpendicular to the vertical direction (c-axis

[0001] ), than in the vertical direction. From these results, it can be seen that the growth rate is about 4.9 times faster. The crystal growth proceeds in a direction parallel to the ab plane. The process progresses and a plate-shaped single crystal region is formed. Next, the plate-shaped single crystal region formed on the surface (a-b plane) The crystal grows in the c-axis direction, which is perpendicular to the surface (a-b plane), using this as a seed. ZnO is thought to be easily oriented along its c-axis. After preferential crystal growth, crystal growth occurs along the c-axis perpendicular to the surface (epitaxial growth, This process (also called axial growth) forms a plate-shaped single crystal region.

[0073] Next, the multi-component oxide semiconductor layer 103 having the first single crystal region and the multi-component oxide semiconductor layer 104 having the second single crystal region are The crystal axis of the multi-component oxide semiconductor layer 107 is the same as that of the single-component oxide semiconductor layer having a single crystal region. The mechanism by which the crystal grows so that the crystal axis is approximately the same as that of 105 will be explained using FIG. .

[0074] Figure 7(A) shows the structure of zinc oxide (ZnO) with a hexagonal crystal structure, which is a typical example of a single-component oxide semiconductor layer. The unit cell structure on the ab plane as viewed from the c-axis direction is shown in Figure 7(B), and the c-axis direction is the vertical direction. The crystal structure is shown below.

[0075] FIG. 7C shows a typical example of the first multi-component oxide semiconductor layer and the second multi-component oxide semiconductor layer. The structure of a certain InGaZnO4 on the ab plane as viewed from the c-axis direction is shown.

[0076] From Fig. 7(A) and Fig. 7(C), it can be seen that the lattice constants of ZnO and InGaZnO4 are approximately The values ​​are similar, which indicates that the ab-plane ZnO and InGaZnO4 are highly compatible. In addition, InGaZnO4 and ZnO are hexagonal crystals, and ZnO has a crystal structure parallel to the c-axis. Since the first multi-component oxide semiconductor layer and the second multi-component oxide semiconductor layer have a good bond, The example shown in the table, InGaZnO4, can be grown as a crystal with high consistency in the c-axis direction. Therefore, the multi-component oxide semiconductor layer 103 having the first single crystal region and the second single crystal region The crystal axes of the multi-component oxide semiconductor layer 107 having the above-mentioned structure are the same as those of the single-component oxide semiconductor layer 107 having the above-mentioned structure. The crystal grows so that the crystal axis of the nitride semiconductor layer 105 is substantially the same as that of the nitride semiconductor layer 105 .

[0077] By the above process, a multi-layered semiconductor having a first single crystal region can be obtained without being affected by the material of the underlying substrate. a single-component oxide semiconductor layer having a single crystal region, a single-component oxide semiconductor layer having a second single crystal region, A stack of multi-component oxide semiconductor layers having the above structure can be formed.

[0078] Next, a photoresist film was formed on the multi-component oxide semiconductor layer 107 having the second single crystal region shown in FIG. After forming a resist mask by a lithography process, the resist mask is used to a multi-component oxide semiconductor layer 103 having a single crystal region; The semiconductor layer 105 and the multi-component oxide semiconductor layer 107 having the second single crystal region are etched. The multi-component oxide semiconductor layer 103a having island-shaped first single-crystal regions and the single-crystal regions are formed by a single-component oxide semiconductor layer 105a having a first single crystal region and a multi-component oxide semiconductor layer 105b having a second single crystal region; The multi-component oxide semiconductor layer 103a having the first single crystal region, the single crystal region, and the oxide semiconductor layer 107a are formed. a single-component oxide semiconductor layer 105a having a crystalline region and a second multi-component oxide semiconductor layer 105b having a single-crystal region; The oxide semiconductor layer 107a is also referred to as an oxide semiconductor stack 110 (see FIG. 1).

[0079] Next, a conductive layer is formed on the oxide semiconductor stack 110, and then the conductive layer is etched into a predetermined shape. Wirings 108a and 108b are formed by etching.

[0080] The wirings 108a and 108b are made of aluminum, chromium, copper, tantalum, titanium, or molybdenum. tungsten, or an alloy containing the above metal elements, The alloy may be formed by combining the above-mentioned metal elements. , magnesium, zirconium, and beryllium. The wirings 108a and 108b may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum layer containing silicon, an aluminum layer Two-layer structure with a titanium layer laminated on top, two-layer structure with a titanium layer laminated on top of a titanium nitride layer, Two-layer structure with a tungsten layer on a titanium layer, and a tungsten layer on a tantalum nitride layer A two-layer structure, consisting of a titanium layer and an aluminum layer on top of the titanium layer, There are also three-layer structures, such as aluminum with a titanium layer on top. , tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a combination of multiple alloy layers or nitride layers may be used.

[0081] The wirings 108a and 108b are made of indium tin oxide or indium containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the light-transmitting conductive material and the metal element may be laminated together.

[0082] Next, a gate insulating layer 112 is formed on the oxide semiconductor stack 110 and the wirings 108a and 108b. Form.

[0083] The gate insulating layer 112 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride layer. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or a stacked layer. The portion of the gate insulating layer 112 in contact with the oxide semiconductor stack 110 preferably contains oxygen. Preferably, the insulating layer is formed of a silicon oxide layer, and particularly preferably, the insulating layer is formed of a silicon oxide layer. This allows oxygen to be supplied to the oxide semiconductor stack 110, improving the characteristics. do.

[0084] The gate insulating layer 112 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. By using high-k materials, gate leakage can be reduced. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an alumina oxide layer. The gate insulating layer 112 may have a stacked structure with one or more of the aluminum layers. The thickness of the gate insulating layer 112 is preferably greater than or equal to 50 nm and less than or equal to 500 nm. This can reduce the gate leakage current.

[0085] Next, a gate insulating layer 112 is formed on a region overlapping with the oxide semiconductor stack 110. The electrode 114 is formed.

[0086] The gate electrode 114 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above-mentioned metal elements, or It can be formed by using an alloy of metal elements. A metal element selected from one or more of nesium, zirconium, and beryllium The gate electrode 114 may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum layer containing silicon, a titanium layer on an aluminum layer, Two-layer structure with titanium layer on titanium nitride layer, two-layer structure with titanium layer on titanium nitride layer Two-layer structure with a tungsten layer stacked on top of a tantalum nitride layer The structure is a titanium layer, an aluminum layer on top of the titanium layer, and a titanium layer on top of that. There are also three-layer structures that form aluminium, titanium, tantalum, tungsten, etc. One or more elements selected from the group consisting of silicon, molybdenum, chromium, neodymium, and scandium Combined alloy layers or nitride layers may also be used.

[0087] The gate electrode 114 is made of indium tin oxide, indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide containing titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used.

[0088] After this, an insulating layer 116 may be formed as a protective layer. A transistor 150 having an oxide semiconductor stack having the above structure in a channel formation region is manufactured. The metal oxides reported so far are either amorphous or polycrystalline. Only those in a crystalline state or those that are treated at high temperatures of around 1400°C to obtain single crystals. However, as described above, a single-component oxide semiconductor layer having a flat single crystal region can be formed. After that, the single crystal region is used as a seed for crystal growth, and a comparatively large area substrate is used. A transistor having an oxide semiconductor with a single crystal region in a channel formation region can be fabricated at a relatively low temperature. It can be made.

[0089] (Embodiment 2) In this embodiment, a method for manufacturing a semiconductor device according to one embodiment of the disclosed invention is A method for manufacturing a transistor including the oxide semiconductor stack will be described with reference to FIGS. and explain.

[0090] An insulating layer 101 is formed on the substrate 100. Next, as in the first embodiment, a film is formed on the insulating layer 101. A first multi-component oxide semiconductor layer 102 is formed on the first multi-component oxide semiconductor layer 102. A single-component oxide semiconductor layer 104 is formed on the oxide semiconductor layer 104 (see FIG. 8A).

[0091] As the substrate 100, the substrate 100 described in Embodiment Mode 1 can be used as appropriate.

[0092] The insulating layer 101 serves to reduce the inclusion of impurities in the layers formed on the substrate 100 and also to prevent the substrate The insulating layer 101 is formed to improve the adhesion of the layer formed on the silicon oxide layer 100. an oxide insulating layer such as a silicon oxynitride layer, a silicon nitride layer, or a silicon nitride oxide layer; The insulating layer is formed of a nitride such as an aluminum nitride layer or an aluminum nitride oxide layer. The insulating layer 101 may have a laminated structure, for example, the nitride insulating layer 101 described above may be formed on the substrate 100 side. and one or more of the oxide insulating layers described above. The thickness of the insulating layer 101 is not particularly limited, but may be, for example, 10 nm or more and 500 nm or less. The insulating layer 101 is not an essential component, so the insulating layer It is also possible to configure the device without providing 101.

[0093] The insulating layer 101 can be formed by a sputtering method, a CVD method, a coating method, a printing method, or the like. Cut.

[0094] When the insulating layer 101 is formed by a sputtering method, hydrogen, water, or the like remaining in the treatment chamber may be easily removed. It is preferable to form the insulating layer 101 while removing hydroxyl groups or hydrides. This is to prevent the insulating layer 101 from containing hydrogen, water, hydroxyl groups, hydrides, and the like. To remove hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the processing chamber, an adsorption-type vacuum is used. It is preferable to use a pump. As an adsorption type vacuum pump, for example, a cryopump is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage may be a turbopump plus a cold trap. In a processing chamber evacuated using a pump, hydrogen, water, hydroxyl radicals, hydrides, etc. are exhausted. When the insulating layer 101 is formed in this treatment chamber, the concentration of impurities contained in the insulating layer 101 can be reduced. Cut.

[0095] The sputtering gas used to form the insulating layer 101 is hydrogen, water, hydroxyl groups, and water. High-purity gas is used, with impurities such as chlorine removed to the level of a few ppm or a few ppb. It is preferable that

[0096] In this embodiment, the substrate 100 is transferred to a processing chamber, and hydrogen, water, hydroxyl groups, hydrides, etc. are removed. A sputtering gas containing high-purity oxygen removed was introduced, and a silicon target was used. A silicon oxide layer is formed as an insulating layer 101 on a substrate 100. During this process, the substrate 100 may be heated.

[0097] The first multi-component oxide semiconductor layer 102 and the single-component oxide semiconductor layer 104 are formed by sputtering. In the case of forming the first multi-component oxide semiconductor layer 102 and the second multi-component oxide semiconductor layer 103 by a heating method, the first multi-component oxide semiconductor layer 102 and the second multi-component oxide semiconductor layer 103 are formed by heating the substrate. Impurities such as hydrogen, water, a hydroxyl group, and hydride contained in the single-component oxide semiconductor layer 104 are reduced. This can promote crystal growth in the first heat treatment that is performed later. can be done.

[0098] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95%. It is preferable that the relative density is 99.9% or more, and more preferably 99.9% or more. When the first multi-component oxide semiconductor layer 102 and the single-component oxide semiconductor layer 1 are used, The impurity concentration in 04 can be reduced, resulting in transistors with better electrical characteristics and higher reliability. can be obtained.

[0099] In addition, the first multi-component oxide semiconductor layer 102 and the single-component oxide semiconductor layer 104 are formed Before the formation of the target, the target remains on the inner wall of the sputtering equipment, on the surface of the target, and in the target material. It is preferable to perform a preheat treatment to remove hydrogen, water, hydroxyl groups, hydrides, etc. The preheating process involves heating the chamber to 200 to 600°C under reduced pressure. Alternatively, you can repeat the introduction and exhaust of nitrogen or inert gas. After cooling the substrate or the sputtering device, the first multi-component oxidation is carried out without exposing the substrate to the atmosphere. The compound semiconductor layer 102 and the single-component oxide semiconductor layer 104 are formed. It is better to use oil or fat as the cooling liquid instead of water. Repeating the process will produce a certain effect, but it is even better if you do it while heating.

[0100] Similarly to the insulating layer 101, the first multi-component oxide semiconductor layer 102 and the single-component oxide semiconductor layer 103 are Before, during, or after forming the body layer 104, a sputtering apparatus It is preferable to remove hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the sputtering. To remove residual moisture from the ring device, it is preferable to use an adsorption type vacuum pump. As a result, hydrogen, water, hydroxyl radicals, hydrides, etc. are exhausted, and the first multi-component oxide The concentrations of impurities contained in the semiconductor layer 102 and the single-component oxide semiconductor layer 104 can be reduced.

[0101] Next, the first heat treatment is performed in the same manner as in the first embodiment. The temperature of the first heat treatment is 500 The heating temperature is set to 1000°C or higher, preferably 600°C or higher and 850°C or lower. The first heat treatment is performed for 1 minute or more and 24 hours or less. The oxide semiconductor layer 103 and the single-component oxide semiconductor layer 105 having a single crystal region are formed. This can be done (see FIG. 8(B)).

[0102] In the first heat treatment, the first multi-component oxide semiconductor layer 102 and the single-component oxide semiconductor layer The conductor layer 104 is grown as a crystal, and impurities other than the main component of the oxide semiconductor, typically High purity can be achieved by removing hydrogen, water, hydroxyl groups, and hydrides.

[0103] The first heat treatment may be performed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a nitrogen atmosphere. atmosphere, dry air atmosphere, or a mixture of a rare gas (typically argon) and oxygen atmosphere; Alternatively, a mixed atmosphere of rare gas and nitrogen is preferable. High purity impurities such as acid groups and hydrides have been removed to the order of a few ppm or a few ppb. A pure gas atmosphere is preferred.

[0104] In this embodiment, the first heat treatment is performed in a dry air atmosphere at 700° C. for 1 hour. Carry out the process.

[0105] Next, similarly to Embodiment 1, a second oxide semiconductor layer is formed on the single-component oxide semiconductor layer 105 having a single crystal region. The multi-component oxide semiconductor layer 106 is formed.

[0106] Next, a second heat treatment is performed in the same manner as in the first embodiment. A multi-component oxide semiconductor layer 107 having a crystalline region can be formed (see FIG. 8C). .).

[0107] In addition, the second heat treatment causes crystal growth of the second multi-component oxide semiconductor layer 106. impurities other than the main components of the oxide semiconductor, typically hydrogen, water, hydroxyl groups, and hydrides, are removed. This allows for high purity.

[0108] In the first and second heat treatments, the inside of the furnace was kept in a nitrogen atmosphere during the temperature rise. During cooling, the atmosphere inside the furnace may be changed to an oxygen atmosphere, and the atmosphere may be changed to a nitrogen atmosphere. After water or dehydrogenation is performed, the atmosphere is switched to an oxygen atmosphere to perform the first multi-component a first oxide semiconductor layer 102, a second oxide semiconductor layer 104, and a second multi-component oxide semiconductor layer 106 can be made into an i-type by supplying oxygen inside.

[0109] Through the above steps, the multi-component oxide semiconductor layer 103 having the first single crystal region and the single crystal region are obtained. a single-component oxide semiconductor layer 105 having a first single crystal region and a multi-component oxide semiconductor layer 106 having a second single crystal region; A layer 107 can be formed (see FIG. 8(C)).

[0110] Next, a photolithography process is performed on the multi-component oxide semiconductor layer 107 having the second single crystal region. After forming a resist mask by the step, the first single crystal region is formed using the resist mask. a multi-component oxide semiconductor layer 103 having a single crystal region; a single-component oxide semiconductor layer 105 having a single crystal region; The multi-component oxide semiconductor layer 107 having the first and second single crystal regions is etched to form island-shaped first and second single crystal regions. a multi-component oxide semiconductor layer 103a having a single crystal region; a multi-component oxide semiconductor layer 105a having a second single crystal region; and a multi-component oxide semiconductor layer 107a having a second single crystal region. (See FIG. 8(D)). The resist mask may also be formed by an inkjet method. When a resist mask is formed by the inkjet method, a photomask is not used, so the manufacturing process is The manufacturing cost can be reduced. a single-component oxide semiconductor layer 105a having a single crystal region, and a second polycrystalline oxide semiconductor layer 105b having a single crystal region. The elemental oxide semiconductor layer 107 a is also referred to as an oxide semiconductor stack 110 .

[0111] The etching may be performed using a wet etching method or a dry etching method. The etching solution for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. The solution was ammonia hydrogen peroxide solution (31% by weight hydrogen peroxide solution: 28% by weight ammonia water: water = 5: 2:2) can be used. ITO07N (manufactured by Kanto Chemical Co., Ltd.) can also be used. stomach.

[0112] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. It may be reused. Materials such as indium contained in the waste liquid after etching may be recovered and reused. By reusing materials, resources can be used more effectively and costs can be reduced.

[0113] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride CCl4 and the like are preferred.

[0114] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur or the like can be used.

[0115] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0116] Next, a conductive layer 108 is formed on the insulating layer 101 and the island-shaped oxide semiconductor layer (FIG. 8( See E). The conductive layer 108 will later become the wirings 108a and 108b.

[0117] The conductive layer 108 is formed using the materials for the wirings 108a and 108b described in Embodiment 1 as appropriate. The conductive layer 108 can be formed by a sputtering method, a CVD method, or a vacuum deposition method. In this embodiment, the conductive layer 108 is formed by a sputtering method. A 50 nm thick titanium layer, a 100 nm thick aluminum layer, and a 50 nm thick titanium layer A metal layer consisting of three layers is used.

[0118] Next, a resist mask is formed over the conductive layer 108 by a photolithography process. The conductive layer is etched using a mask to form a layer that functions as a source electrode and a drain electrode. Wirings 108a and 108b are formed (see FIG. 9(A)). Alternatively, photolithography is used. By forming the wirings 108a and 108b by a printing method or an ink jet method without using a printing process, , the number of steps can be reduced.

[0119] The resist used to form the resist mask for etching is exposed to ultraviolet light, Kr It is preferable to use F laser light or ArF laser light. When exposing to light of less than 25 nm, extreme ultraviolet light with an extremely short wavelength of several nm to several tens of nm ( It is preferred to expose the resist using UV light (Extreme Ultraviolet). Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length (L) of the transistor can be set to 10 nm or more and 1000 nm (1 μm) or less. By reducing the channel length in this way, the operation of the transistor In addition, the transistor using the oxide semiconductor can be Because the current is extremely small, it is possible to suppress the increase in power consumption due to miniaturization.

[0120] When the conductive layer 108 is etched, the oxide semiconductor stack 110 is not removed. The materials and etching conditions of the oxide semiconductor stack 110 and the conductive layer 108 are adjusted as appropriate. Depending on the material and etching conditions, the oxide semiconductor stack 1 may be removed in this step. A part of 10 may be etched to have a groove (recess).

[0121] In addition, the crystals in contact with the wirings 108a and 108b on the side surfaces of the oxide semiconductor stack 110 The region may be in an amorphous state.

[0122] The etching of the conductive layer 108 here can be either dry etching or wet etching. In order to form the wirings 108a and 108b in the desired shape, The etching conditions (etching solution, etching time, temperature, etc.) are adjusted appropriately according to the material. To reduce.

[0123] In this embodiment, the etchant is an ammonia hydrogen peroxide solution (ammonia, water, hydrogen peroxide solution). The conductive layer 108 is etched using the mixed solution of the above to form wirings 108a and 108b. do.

[0124] Next, as shown in FIG. 9B, the insulating layer 101, the oxide semiconductor stack 110, and the wiring 1 A gate insulating layer 112 is formed on the gate electrodes 108a and 108b in the same manner as in the first embodiment.

[0125] The oxide semiconductor layer (containing hydrogen) that has been made i-type or substantially i-type by removing impurities The oxide semiconductor layer (which has been highly purified by reducing the concentration) is extremely sensitive to interface states and interface charges. Therefore, the interface with the gate insulating layer 112 is important. The gate insulating layer 112 in contact with the semiconductor laminate 110 is required to have high quality.

[0126] For example, high density plasma CVD using microwaves (for example, frequency 2.45 GHz) can be used. This is preferable because it allows the formation of a dense, high-quality insulating layer with high dielectric strength. The intimate contact between the purified oxide semiconductor layer and the high-quality gate insulating layer reduces the interface states. This is because the high density plasma C can reduce the surface roughness and improve the interface characteristics. The insulating layer obtained by VD can be formed with a uniform thickness, and therefore has excellent step coverage. In addition, the thickness of the insulating layer obtained by high-density plasma CVD can be precisely controlled. do.

[0127] Of course, if a good insulating layer can be formed as a gate insulating layer, sputtering is also possible. Other methods for forming the film, such as sputtering or plasma CVD, can be applied. When forming a silicon oxide layer, a silicon target or a quartz target is used. The target is used, and oxygen or a mixture of oxygen and argon is used as the sputtering gas. In addition, the film quality of the gate insulating layer is changed by heat treatment after the formation of the gate insulating layer. Alternatively, the insulating layer may be an insulating layer that improves the interface characteristics with the compound semiconductor laminate 110. In addition to having good film quality as a gate insulating layer, the oxide semiconductor laminate 11 Any material that can reduce the interface state density with 0 and form a good interface is acceptable.

[0128] For example, at 85°C, 2 x 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities were added to the oxide semiconductor stack 110, The bond between the main component of the oxide semiconductor laminate 110 is strengthened by a strong electric field (B: bias) and a high temperature (T: temperature). The resulting dangling bonds are cut by the This will trigger a backlash.

[0129] On the other hand, impurities in the oxide semiconductor stack 110, particularly hydrogen, water, hydroxyl groups, hydrides, etc. By eliminating these as much as possible and improving the interface characteristics with the gate insulating layer as described above, This makes it possible to obtain a transistor that is stable even during testing.

[0130] Note that if a halogen element (for example, fluorine) is added to an insulating layer provided in contact with the oxide semiconductor stack 110, or halogen-containing oxide semiconductor layer 110 is exposed. The oxide semiconductor stack 110 is halogenated by plasma treatment in a gas atmosphere containing a halogen element. The oxide semiconductor stack 110 or the oxide semiconductor stack 110 in contact with the oxide semiconductor stack 110 is Remove impurities such as hydrogen, water, hydroxyl groups, and hydrides that may exist at the interface with the insulating layer to be provided. When the insulating layer contains a halogen element, the halogen in the insulating layer may be removed. The element concentration is 5 x 10 17 cm -3 ~1×10 20 cm -3 It should be about that level.

[0131] As described above, in the oxide semiconductor stack 110 or in combination with the oxide semiconductor stack 110 The oxide semiconductor stack 110 is made to contain a halogen element at the interface with the insulating layer in contact therewith. When the insulating layer is an oxide insulating layer, the oxide semiconductor laminate 1 of the oxide insulating layer It is preferable to cover the side not in contact with 10 with a nitride insulating layer. A silicon nitride layer or the like may be provided on the oxide insulating layer in contact with the body 110. By adopting such a structure, impurities such as hydrogen, water, hydroxyl groups, and hydrides can be prevented from entering the oxide semiconductor stack. 110 can be reduced.

[0132] Before forming the gate insulating layer 112, the inner wall of the sputtering device, the target surface, A preheating process is performed to remove any moisture or hydrogen remaining in the target material. After the preheating process is completed, the substrate or the sputtering device is cooled. Thereafter, the gate insulating layer 112 is formed without exposure to the atmosphere.

[0133] Next, a gate insulating layer 112 is formed on a region overlapping with the oxide semiconductor stack 110. The gate electrode 114 is formed on the gate insulating layer 11 (see FIG. 9(C)). A conductive layer is formed on the substrate 2 by a sputtering method, a CVD method, or a vacuum deposition method, and a A resist mask is formed on the conductive layer by a photolithography process. The conductive layer can be formed by etching.

[0134] Next, a third heat treatment (preferably at 200°C) is carried out in an inert gas atmosphere or an oxygen gas atmosphere. The heat treatment may be performed at a temperature of 250°C or higher and 450°C or lower, for example, 250°C or higher and 350°C or lower. By supplying oxygen to the oxygen defects generated in the first and second heat treatments, It is possible to further reduce oxygen defects, which act as a catalyst, and achieve a structure that satisfies the stoichiometric ratio. The compound semiconductor laminate 110 can be made more i-type or substantially i-type. The third heat treatment may be performed before the formation of the gate electrode 114. This may be done after the formation of the insulating layer 116 that forms the insulating layer.

[0135] After that, an insulating layer 116 is formed on the gate insulating layer 112 and the gate electrode 114 (FIG. 9). (See (D).) The insulating layer 116 may contain hydrogen. The insulating layer 116 is formed by sputtering. The film can be formed by a deposition method, a CVD method, or the like. In this embodiment, the CVD method is used. A silicon nitride layer, which is one of nitride insulating layers obtained by the method described above, is used.

[0136] The third heat treatment is carried out in a nitrogen atmosphere at a temperature of 150° C. or higher and 450° C. or lower, preferably 250° C. or higher. The third heat treatment is preferably performed at a temperature of 440° C. or less. The third heat treatment is not limited to a nitrogen atmosphere. The heating may be carried out in an oxygen atmosphere, a rare gas atmosphere, or a dry air atmosphere.

[0137] Through the above steps, the hydrogen concentration is reduced, the oxide semiconductor is highly purified, and the oxide semiconductor has a single crystal region. The transistor 150 can be formed with a stack of layers.

[0138] Depending on the etching conditions, after FIG. 8(C), a multi-component oxide film having a second single crystal region may be formed. After etching the compound semiconductor layer 107 into islands, a single-component oxide semiconductor layer having a single crystal region is formed. 10A, the insulating layer 105 is not etched into an island shape, and the first insulating layer 105 is formed on the entire surface of the insulating layer 101. The multi-component oxide semiconductor layer 103 having a single crystal region and the single-component oxide semiconductor layer 104 having a single crystal region are This is because the first heat treatment is more effective than the second heat treatment. When the treatment temperature is high, the first single crystal region is formed in the multi-component oxide semiconductor layer 107 having the second single crystal region. The multi-component oxide semiconductor layer 103 having a single crystal region and the single-component oxide semiconductor layer This is because the crystallinity of the semiconductor layer 105 increases and the etching rate decreases.

[0139] After that, by the steps shown in FIG. 8(E) and FIG. 9, the insulating layer 10 shown in FIG. 10(B) is formed. The multi-component oxide semiconductor layer 103 having a first single crystal region and the first single crystal region are formed on the first oxide semiconductor layer 103. A single-component oxide semiconductor layer 105 is formed by stacking a single-component oxide semiconductor having a single crystal region. The multi-component oxide semiconductor layer 107a having the island-shaped second single-crystal region on the layer 105, the wiring 10 8a, 108b, and a gate insulating layer 112 are formed. The pole 114 results in a transistor 152 being formed.

[0140] Conventional oxide semiconductors are generally n-type, and transistors using oxide semiconductors have a gate Even when the voltage is 0V, current flows between the source and drain electrodes, which is called normally-on. Even if the field effect mobility is high, if the transistor is normally on, It is difficult to control the hydrogen concentration in an oxide semiconductor because hydrogen can act as a donor. It is known that oxygen vacancies are one of the factors that cause n-type formation. is known to be the cause.

[0141] Therefore, in order to make the oxide semiconductor i-type, n-type impurities such as hydrogen, water, hydroxyl groups, and hydrides are added. In the first heat treatment and the second heat treatment, the oxide semiconductor is oxidized along with the crystal growth. It is highly purified so that impurities other than the main component of oxide semiconductors are removed as much as possible. The third heat treatment removes oxygen defects to make the silicon nitride intrinsic. That is, instead of adding impurities to create the i-type, impurities such as hydrogen, water, hydroxyl groups, and hydrides are By eliminating as many oxygen defects as possible, highly purified i-type (intrinsic semiconductor) or In particular, the oxide semiconductor described in this embodiment is highly crystalline. Therefore, compared with amorphous, microcrystalline, or polycrystalline materials, The oxide semiconductor has a feature of having few defects. The threshold voltage of the transistor can be made positive, so that it is a so-called normally-off switch. It is possible to realize a chip element.

[0142] At this time, the hydrogen concentration in the oxide semiconductor is 1×10 18 cm -3 Below, 1×10 16 cm - 3 It is more preferable that the carrier density of the oxide semiconductor is 1×1 0 14 cm -3 Less than 1×10 12 cm -3 less than 1.45 × 10 10 cm -3That is, the carrier density of an oxide semiconductor is extremely close to zero. The band gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. The hydrogen concentration in the oxide semiconductor was measured by secondary ion mass spectrometry (SIMS). This was obtained using Common Ion Mass Spectroscopy. The carrier density can be measured by Hall effect measurement. The rear density is measured by CV (Capacitance-Voltage-Measurement) nt) can be determined from the measurement results.

[0143] In addition, the minimum carrier density in a typical silicon wafer (1 × 10 14 / cm 3 Process Compared with the carrier density of oxide semiconductors, oxide semiconductors have a sufficiently small carrier density (for example, 1×10 1 2 / cm 3 less than 1.45 x 10 10 / cm 3 (less than 100%). Channel length 3 μm, channel width 1 × 10 4 In a transistor with a drain voltage of 1 For any voltage between V and 10V, the off-state current (gate-source The current that flows between the source and drain when the voltage is set to 0 V or less is below the lower limit of measurement. Subthreshold swing value (S value) is 0.1V / dec. (gate insulating layer thickness 100 In this way, by purifying the oxide semiconductor, the off-state current can be reduced to 1×1 0 -20 A (10zA (zeptoamperes)) to 1 x 10 -19 About A(100zA) The off-state current is the electron-hole recombination due to direct or indirect recombination. The oxide semiconductor has a wide band gap, and the electrons flow by generation and recombination. Since large thermal energy is required for excitation, direct and indirect recombination do not occur. Therefore, when a negative potential is applied to the gate electrode (off state), the minority carry Since the number of holes, which are atoms, is substantially zero, direct and indirect recombination is unlikely to occur, and The flow becomes infinitely lower.

[0144] If the values ​​of the off-state current and drain voltage are known, the transistor can be turned off according to Ohm's law. The resistance value in the OFF state (OFF resistance R) can be calculated by the cross-sectional area A of the channel formation region and If the channel length L is known, the off-resistivity ρ can be calculated using the formula ρ=RA / L (R is the off-resistance). The off-resistivity is 1×10 9 Ω·m or more (or 1×10 10 Ω·m) is preferred Here, the cross-sectional area A is given by the following equation, where d is the film thickness of the channel forming region and W is the channel width: It can be calculated from A=dW.

[0145] The off-state current of a transistor using amorphous silicon is 10 -12 While it is only about A However, the off-state current of a transistor using an oxide semiconductor is much lower. Alternatively, by using a substantially i-type oxide semiconductor, it is possible to obtain extremely excellent off-state current characteristics. A transistor 150 can be obtained.

[0146] Furthermore, by reducing, or preferably eliminating, carriers in the oxide semiconductor, In this case, the oxide semiconductor functions as a path through which carriers pass. Oxide semiconductors are highly purified i-type (intrinsic) semiconductors that have no or very few carriers. By reducing the capacitance, the off-state current of the transistor can be made extremely low. This is the technical idea of ​​this embodiment.

[0147] In addition, the oxide semiconductor functions as a path, and the oxide semiconductor itself does not have carriers. If the i-type (intrinsic) is highly purified so that there is no or very little carriers, the carriers The electron affinity χ and Fermi level of the oxide semiconductor, Ideally, the Fermi level coincides with the intrinsic Fermi level, and the source and drain electrodes are By appropriately selecting the function, carriers are injected from the source electrode and the drain electrode. This makes it possible to appropriately fabricate n-type and p-type transistors. .

[0148] In this way, impurities other than the main components of the oxide semiconductor, typically hydrogen, water, hydroxyl groups, hydrogenated By purifying the material to the extent possible so that it does not contain any impurities, and by making it have a single crystal region, This improves the operation of the transistor. In particular, it increases the on / off ratio. In addition, it is possible to suppress the change in the threshold voltage of the transistor before and after the BT test. This makes it possible to achieve high reliability. In addition, the metal oxides reported so far are either amorphous or , polycrystalline, or those that are treated at high temperatures of around 1400°C to obtain single crystals. However, as described above, it is now possible to develop a single-component oxide semiconductor having a flat single-crystal region. After forming a layer, a large-area substrate is used to grow a crystal by using the single crystal region as a seed. By using this method, an oxide semiconductor layer having a single crystal region can be formed at a relatively low temperature.

[0149] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0150] (Embodiment 3) In this embodiment, compared with the first and second embodiments, the oxide semiconductor stack 11 A different manufacturing method for 0 will be explained with reference to FIG.

[0151] As in the second embodiment, an insulating layer 101 is formed on a substrate 100 as shown in FIG. 11(A). Next, a first multi-component oxide semiconductor layer 102 is formed on the insulating layer 101. A single-component oxide semiconductor layer 104 is formed on the single-component oxide semiconductor layer 102 .

[0152] Next, similarly to the first embodiment, a first heat treatment is performed, and as shown in FIG. 11(B), The multi-component oxide semiconductor layer 103 having a single crystal region and the single-component oxide semiconductor layer Next, a semiconductor layer 105 is formed on the single-component oxide semiconductor layer 105 having a single crystal region. A second multi-component oxide semiconductor layer 106 is formed.

[0153] Next, a resist mask is formed on the second multi-component oxide semiconductor layer 106 by a photolithography process. After forming a resist mask, a multi-component oxide having a first single crystal region is formed using the resist mask. The semiconductor layer 103, the single-component oxide semiconductor layer 105 having a single crystal region, and the second multi-component oxide semiconductor layer 106 are The oxide semiconductor layer 106 is etched to form a multi-component oxide semiconductor layer having island-shaped first single crystal regions. The conductor layer 103a, the single-component oxide semiconductor layer 105a having a single crystal region, and the second multi-component oxide semiconductor layer 105b The oxide semiconductor layer 106a is formed. After that, the resist mask is removed (FIG. 11(C) reference.).

[0154] Next, the single-component oxide semiconductor layer 105a having a single crystal region is subjected to second heat treatment. Then, the second multi-component oxide semiconductor layer 106a is crystal-grown to have a second single-crystal region. Through the above steps, a multi-component oxide semiconductor layer 107a having a first single crystal region is formed. a multi-component oxide semiconductor layer 103a having a single crystal region; a single-component oxide semiconductor layer 105a having a single crystal region; and an oxide semiconductor layer 107a having a second single crystal region. A laminated body 110 can be formed. After that, by the steps shown in FIG. 8(E) and FIG. A transistor 150 as shown in FIG. 1 can be formed.

[0155] The second multi-component oxide semiconductor layer having a single crystal region has high crystallinity and can be etched under certain etching conditions. The etching rate of the second multi-component oxide semiconductor layer is slower than that of the second multi-component oxide semiconductor layer before crystallization. Before the second heat treatment, the second multi-component oxide semiconductor layer is etched into an island shape. Therefore, the etching time can be shortened.

[0156] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0157] (Fourth embodiment) In this embodiment, compared with the first to third embodiments, the oxide semiconductor stack 11 A different manufacturing method for 0 will be explained with reference to FIG.

[0158] As in the second embodiment, an insulating layer 101 is formed on a substrate 100. Next, forming a first multi-component oxide semiconductor layer on the first multi-component oxide semiconductor layer; Next, similarly to the first embodiment, a first heat treatment is performed to form a first single crystal. A multi-component oxide semiconductor layer 103 having a crystalline region and a single-component oxide semiconductor layer having a single-crystal region A layer 105 is formed (see FIG. 12(A)).

[0159] Next, a single-crystal oxide semiconductor layer 105 having a single crystal region is formed by a photolithography process. After forming a resist mask, a first single crystal region is formed on the silicon substrate using the resist mask. The multi-component oxide semiconductor layer 103 having a single crystal region and the single-component oxide semiconductor layer 105 having a single crystal region are As shown in FIG. 12(B), a multi-component oxide film having island-shaped first single crystal regions is formed. The oxide semiconductor layer 103b and the single-component oxide semiconductor layer 105b having a single crystal region are formed. Thereafter, the resist mask is removed.

[0160] Next, a second polyimide film was formed on the single-component oxide semiconductor layer 105b having a single crystal region and the insulating layer 101. The elemental oxide semiconductor layer 106 is formed.

[0161] Next, a resist mask is formed on the second multi-component oxide semiconductor layer 106 by a photolithography process. After forming a resist mask, a multi-component oxide film having a first single crystal region is formed using the resist mask. a single-component oxide semiconductor layer 103b, a single-component oxide semiconductor layer 105b having a single crystal region, and a second polycrystalline oxide semiconductor layer 106b. The multi-component oxide semiconductor layer 106 is etched to form a multi-component oxide semiconductor layer having island-shaped first single-crystal regions. a single-component oxide semiconductor layer 103a having island-shaped single-crystal regions; and The island-shaped second multi-component oxide semiconductor layer 106a is formed. After that, the resist mask is removed. (See Figure 12(C)).

[0162] Next, the single-component oxide semiconductor layer 105a having a single crystal region is subjected to second heat treatment. Then, the second multi-component oxide semiconductor layer 106a is crystal-grown to have a second single-crystal region. Through the above steps, a multi-component oxide semiconductor layer 107a having a first single crystal region is formed. a multi-component oxide semiconductor layer 103a having a single crystal region; a single-component oxide semiconductor layer 105a having a single crystal region; and an oxide semiconductor layer 107a having a second single crystal region. A laminated body 110 can be formed (see FIG. 12(D)). After that, as shown in FIG. The process shown in FIG. 9 allows the formation of a transistor 150 as shown in FIG.

[0163] The second multi-component oxide semiconductor layer having a single crystal region has high crystallinity and can be etched under certain etching conditions. The etching rate of the second multi-component oxide semiconductor layer is slower than that of the second multi-component oxide semiconductor layer before crystallization. Before the second heat treatment, the second multi-component oxide semiconductor layer is etched into an island shape. Therefore, the etching time can be shortened.

[0164] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0165] (Embodiment 5) In this embodiment, a method for manufacturing a multi-component oxide semiconductor layer having a second single crystal region is implemented. A configuration different from the first configuration will be described with reference to FIGS.

[0166] As in the second embodiment, as shown in FIG. 8(A), an insulating layer 101 is formed on a substrate 100. Next, a first multi-component oxide semiconductor layer 102 is formed on the insulating layer 101. A single-component oxide semiconductor layer 104 is formed on the oxide semiconductor layer 102 .

[0167] Next, similarly to the first embodiment, a first heat treatment is performed, and as shown in FIG. The multi-component oxide semiconductor layer 103 having a single crystal region and the single-component oxide semiconductor layer The semiconductor layer 105 is formed.

[0168] Next, as shown in FIG. 13(B), the temperature is increased to 200° C. or more and 600° C. or less, preferably 200° C. or more. While heating at 550℃ or less, a single-component oxide film with a single crystal region is formed by sputtering. A multi-component oxide semiconductor layer 107 having a second single crystal region is formed on the compound semiconductor layer 105. The multi-component oxide semiconductor layer 107 having the second single-crystal region is a hexagonal non-wurtzite crystal. Here, the second multi-component oxide semiconductor layer is deposited while heating, so the single crystal The single crystal region on the surface of the single-component oxide semiconductor layer 105 having the single crystal region is used as a seed for crystal growth. The crystal axis of the single-component oxide semiconductor layer 105 having a crystalline region is the same as that of the single-component oxide semiconductor layer 105, particularly in the c-axis direction. In order to grow the crystal (also called epitaxial growth or axial growth) so that Therefore, the multi-component oxide semiconductor layer 107 having the second single crystal region can be formed. As a result, a single-component oxide semiconductor having a single crystal region in the c-axis direction can be obtained without the second heat treatment. The multi-component oxide semiconductor layer 10 has a second single-crystal region that is crystallized identically to the oxide layer 105. 7 can be formed.

[0169] After that, the transistor 150 can be manufactured through the steps of Embodiment 1.

[0170] In this embodiment, the number of heat treatments can be reduced, and therefore the throughput can be improved. It can be done.

[0171] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0172] (Embodiment 6) In the first to fifth embodiments, a manufacturing process of a transistor having a top gate structure is described. In this embodiment, a bottom-gate transistor is fabricated using FIG. The process will be explained.

[0173] In this embodiment, a glass substrate is used as the substrate 100, and the substrate 100 is previously Heat treatment is performed twice at 0°C for 6 minutes. By heating the substrate before forming the transistor, This prevents film peeling due to substrate shrinkage and mask misalignment. After forming a conductive layer on the substrate 100, a photolithography process is performed using a photomask. A gate electrode 400 is provided.

[0174] Furthermore, the insulating layer 101 shown in the second embodiment may be provided between the substrate 100 and the gate electrode 400. The insulating layer 101 can improve the adhesion between the substrate 100 and the gate electrode 400. .

[0175] The gate electrode 400 can be formed using the same material and method as the gate electrode 114 in Embodiment 1. If the end of the gate electrode 400 is tapered, This is preferable because it can increase the coverage of the insulating layer, semiconductor layer, and conductive layer that will be formed later. stomach.

[0176] Next, a gate insulating layer 401 is formed on the gate electrode 400. The gate insulating layer 401 is The materials and manufacturing method for the gate insulating layer 112 shown in Embodiment 1 can be used as appropriate. .

[0177] Next, a first multi-component oxide semiconductor layer is formed on the gate insulating layer 401 in the same manner as in the first embodiment. a single-component oxide semiconductor layer is formed on the first multi-component oxide semiconductor layer, and then a first process is performed. By performing heat treatment, the multi-component oxide semiconductor layer 403 having the first single crystal region and the single crystal region A single-component oxide semiconductor layer 405 having the above structure is formed (see FIG. 14A).

[0178] Next, a second oxide semiconductor layer was formed on the single-component oxide semiconductor layer 405 having a single crystal region in the same manner as in Embodiment 1. After the multi-component oxide semiconductor layer is formed, second heat treatment is performed to form a second single crystal region. A multi-component oxide semiconductor layer 407 is formed (see FIG. 14B).

[0179] Next, a second single-crystal oxide semiconductor layer 407 is formed on the second multi-component oxide semiconductor layer 407 by photolithography. After forming a resist mask by the process, etching is performed to form island-shaped first single crystal regions. a multi-component oxide semiconductor layer 403a having island-shaped single crystal regions; and a multi-component oxide semiconductor layer 407a having island-shaped single-crystal regions. .

[0180] Next, a gate insulating layer 401 and a multi-component oxide semiconductor layer 40 having island-shaped first single crystal regions are formed. 3a, a single-component oxide semiconductor layer 405a having island-shaped single-crystal regions, and a second single-component oxide semiconductor layer 406a having island-shaped single-crystal regions. On the multi-component oxide semiconductor layer 407a having a crystalline region, The functioning wirings 408a and 408b are formed. The wirings 108a and 108b can be formed in the same manner as the wirings 108a and 108b shown in FIG.

[0181] Next, an oxide insulating layer 412 serving as a protective insulating layer in contact with part of the oxide semiconductor layer is formed. A third heat treatment may be performed (see FIG. 14(C)).

[0182] In this embodiment, a silicon oxide layer having a thickness of 300 nm is sputtered as the oxide insulating layer 412. The substrate temperature during the formation is preferably from room temperature to 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide layer is formed by sputtering using a rare gas ( In an atmosphere of oxygen, or in a mixture of a rare gas (typically argon) and an oxygen The target can be a silicon oxide target. A silicon target or a silicon target can be used. A silicon oxide layer is formed by sputtering under an oxygen and nitrogen atmosphere using the silicon dioxide. The multi-component oxide semiconductor layer 403 having the crystallized island-shaped first single-crystal region can be formed. a) A single-component oxide semiconductor layer 405a having a crystallized island-shaped single-crystal region, and The multi-component oxide semiconductor layer 407a is formed in contact with the island-shaped second single-crystal region. The oxide insulating layer 412 has a thickness of 10 nm to 500 nm, and is typically made of silicon oxide. a silicon nitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like. Use.

[0183] The temperature of the third heat treatment is 200°C or higher and 450°C or lower, preferably 250°C or higher and 300°C or lower. The heating temperature is 50°C or less. The acid generated in the first heating treatment and the second heating treatment is removed by the heating treatment. By supplying oxygen to the elementary vacancies, the number of oxygen vacancies that act as donors is further reduced, and the stoichiometric ratio is satisfied. The first multi-component oxide semiconductor layer 403 having a single crystal region can be formed as follows. a single-component oxide semiconductor layer 405a having a single crystal region and a second single crystal semiconductor layer 405b having a single crystal region. The multi-component oxide semiconductor layer 407a can be made more i-type or substantially i-type.

[0184] Next, the insulating layer 416 is formed over the oxide insulating layer 412. After that, fourth heat treatment is performed. The insulating layer 416 may be formed by the same method as the insulating layer 116 described in Embodiment 2 (see FIG. 14D). can be formed in the same manner as above.

[0185] The fourth heat treatment is carried out in a nitrogen atmosphere at a temperature of 150° C. or higher and 450° C. or lower, preferably 250° C. or higher. The temperature is set to 440° C. or lower. The fourth heat treatment is not limited to a nitrogen atmosphere, but may be performed in an oxygen atmosphere. , a rare gas atmosphere, or a dry air atmosphere.

[0186] As a result, crystal growth occurs from the crystalline region of the single-component oxide semiconductor layer 405a having a single crystal region. The multi-component oxide semiconductor layer 403a having the first single crystal region and the second single crystal region are A transistor 450 including the multi-component oxide semiconductor layer 407a is completed.

[0187] Next, an interlayer insulating layer 418 may be formed over the insulating layer 416 (see FIG. 14(E)). The interlayer insulating layer 418 is a silicon oxide layer obtained by using a sputtering method, a CVD method, or the like. Silicon nitride oxide layer, silicon nitride layer, hafnium oxide layer, aluminum oxide layer, tantalum oxide layer The interlayer insulating layer 418 is formed using a material containing an inorganic insulating material such as tantalum. As the material, organic resins such as acrylic, polyimide, and epoxy resins can also be used. In this embodiment, a stacked structure of the oxide insulating layer 412, the insulating layer 416, and the interlayer insulating layer 418 is used. However, one embodiment of the disclosed invention is not limited to this. Alternatively, a laminated structure of four or more layers may be used.

[0188] In addition, the transistor shown in this embodiment has a gate electrode 40 as shown in FIG. One of the features of the wiring 400 is that it has an area overlapping with the wirings 408a and 408b. 8a and the step of the gate insulating layer 401, that is, the edge of the wiring 408a and the gate insulating layer 401 in the cross section. The area between the flat surface and the tapered surface of the insulating layer (shown in FIG. 14(E)) Did L OV L OV The area is generated at the step caused by the edge of the gate electrode. This is important to prevent carriers from flowing through the grain boundaries of the oxide semiconductor.

[0189] Alternatively, a back gate electrode may be formed over the oxide insulating layer 412. 15(A) and 15(B). After the state of FIG. 14(C) is obtained, the gate electrode 40 A contact hole reaching 0 is formed, and a back gate electrode 414 is formed on the oxide insulating layer 412. Next, the back gate electrode 414 and the oxide insulating layer 4 An insulating layer 416 may be formed on the insulating film 12, and a fourth heat treatment may be performed. The transistor 451 illustrated in FIG. 15B can be obtained. a multi-component oxide semiconductor layer having a first single crystal region; a single-component oxide semiconductor layer having a single crystal region; Formation of a channel formed of a conductor layer and a multi-component oxide semiconductor layer having a second single-crystal region By placing it in a position that overlaps the back gate, the back gate functions as a passivation layer. This makes it possible to prevent external hydrogen from entering the channel formation region. Threshold voltage of transistor 451 before and after BT test (bias-thermal stress test) The amount of change can be reduced.

[0190] The back gate electrode 414 has a potential different from that of the gate electrode 400 of the transistor 451. In addition, the potential of the back gate electrode 414 may be GND, 0V, or floating. In this case, before forming the back gate electrode 414, By not forming a contact hole that reaches the gate electrode 400, the gate electrode 400 and the back electrode 400 The potential of the gate electrode 414 can be made different.

[0191] Next, an interlayer insulating layer 418 for planarization is formed on the insulating layer 416, and the resulting structure shown in FIG. A cross-sectional structure can be obtained.

[0192] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0193] (Embodiment 7) In this embodiment mode, a structure of a transistor having a channel stop structure will be described with reference to FIGS.

[0194] This embodiment is only partially different from the sixth embodiment, so a detailed description is omitted here. It will be decided.

[0195] The steps are explained below in order. As in the sixth embodiment, a gate electrode 400 and a Next, in the same manner as in the sixth embodiment, a gate insulating layer 402 is formed on the gate insulating layer 402. forming a first multi-component oxide semiconductor layer on the first multi-component oxide semiconductor layer; A semiconductor layer is formed, and a first heat treatment is performed to form a first multi-component oxide semiconductor layer and a single-component oxide semiconductor layer. and crystallizing the oxide semiconductor layer to form a multi-component oxide semiconductor layer having a first single crystal region and a single crystal region. Next, a single-component oxide semiconductor layer having a single-component oxide semiconductor layer is formed. and then performing second heat treatment to crystallize the second multi-component oxide semiconductor layer. The second multi-component oxide semiconductor layer having a single crystal region is formed by annealing the first multi-component oxide semiconductor layer.

[0196] Next, an oxide insulating layer is formed and third heat treatment is performed. The same material as the oxide insulating layer 412 shown in Embodiment 6 is used for the third heat treatment. The heat treatment was performed under the same conditions as in the third heat treatment described above, and the first multi-component oxide semiconductor layer having single crystal regions was a single-component oxide semiconductor layer having a single crystal region, and a multi-component oxide semiconductor layer having a second single crystal region; a multi-component oxide semiconductor layer having a first single crystal region, a single crystal region, a single-component oxide semiconductor layer having a first single-crystal region and a multi-component oxide semiconductor layer having a second single-crystal region; Reduces oxygen defects in the

[0197] Next, a resist mask is formed over the oxide insulating layer by a photolithography process. The multi-component oxide semiconductor layer 403a having island-shaped first single-crystal regions is then etched. , the single-component oxide semiconductor layer 405a having an island-shaped single-crystal region, and the second island-shaped single-crystal region At the same time, the oxide insulating layer also has an island shape. do.

[0198] Next, the resist mask is removed, and a resist mask is formed by a photolithography process. Then, selective etching is performed to form an island-shaped oxide insulating layer 420 .

[0199] Next, an island-shaped oxide insulating layer 420 and a multi-component oxide semiconductor having an island-shaped first single crystal region are formed. the single-component oxide semiconductor layer 403a, the single-component oxide semiconductor layer 405a having island-shaped single-crystal regions, and the island-shaped second The wiring 4 is formed on the multi-component oxide semiconductor layer 407a having the single crystal region in the same manner as in Embodiment 1. 08a, 408b.

[0200] Next, an insulating layer 416 is formed over the wirings 408a and 408b and the island-shaped oxide insulating layer 420. After that, a fourth heat treatment may be performed. Note that the fourth heat treatment may also be performed as described in Embodiment 6. The conditions for the fourth heat treatment may be the same as those for the fourth heat treatment.

[0201] As a result of the above, a multi-component oxide semiconductor layer having a first single crystal region and a single-component oxide semiconductor layer having a single crystal region are obtained. a channel having a multi-component oxide semiconductor layer and a second single-crystal region; A stop-type transistor 452 is completed.

[0202] Next, an interlayer insulating layer 418 for planarization is formed on the insulating layer 416, and the cross-sectional structure shown in FIG. The structure can be obtained.

[0203] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0204] (Embodiment 8) In this embodiment, the structure applicable to the sixth and seventh embodiments will be described with reference to FIG. This will be used to explain.

[0205] In this embodiment, the multi-component oxide semiconductor layer 403b having the first single-crystal region, the single-crystal region a single-component oxide semiconductor layer 405b having a single crystal region and a multi-component oxide semiconductor layer 405c having a second single crystal region; The area of ​​the semiconductor layer 407b is smaller than that of the gate electrode 400, and the entire area of ​​the semiconductor layer 407b is the same as that of the gate electrode 400. Therefore, the gate electrode 400 is characterized by being overlapped with a metal element having a light-shielding property. By forming the first single crystal region from a metal or alloy, external light from the substrate 100 side is incident on the first single crystal region. a multi-component oxide semiconductor layer 403b having a single crystal region; a single-component oxide semiconductor layer 405b having a single crystal region; and reducing irradiation of the second multi-component oxide semiconductor layer 407b having a single crystal region. In addition, the first multi-component oxide semiconductor layer 403b having a single crystal region and the second multi-component oxide semiconductor layer 403b having a single crystal region can be formed. a single-component oxide semiconductor layer 405b having a single crystal region and a multi-component oxide semiconductor layer 405c having a second single crystal region; The semiconductor layer 407b overlaps only the flat portion of the gate electrode 400 except for the end portion. As a result, the c-axis directions perpendicular to the surface are all parallel, and the grain boundaries are formed. This results in a substantially single crystal structure with excellent crystallinity.

[0206] As a result, the first multi-component oxide semiconductor layer and the single-component oxide semiconductor layer, which are substantially single-crystal structures, are obtained. The transistor has a first oxide semiconductor layer and a second multi-component oxide semiconductor layer.

[0207] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0208] (Embodiment 9) In this embodiment, the semiconductor device described in the previous embodiment is used in a semiconductor integrated circuit. As one example of such a case, a semiconductor device having a stacked structure with a semiconductor device using a different semiconductor material is used. The arrangement will be described with reference to FIG.

[0209] 18 is a cross-sectional view showing one example of the configuration of a semiconductor device according to this embodiment. The semiconductor device shown in FIG. 1 uses a material other than an oxide semiconductor (for example, silicon) in the lower part. and a transistor 250 using an oxide semiconductor therein. The transistor 150 using an oxide semiconductor is the same as the transistor 1 shown in FIG. 50. The transistor 250 and the transistor 150 are both n-type transistors. Although the description will be given using a p-type transistor, a p-type transistor may also be used. 0 can easily be made p-type.

[0210] The transistor 250 includes a channel forming region 21 provided in a substrate 200 including a semiconductor material. 6, and the impurity region 214 and the high-concentration impurity region 215 provided so as to sandwich the channel forming region 216. The impurity region 220 (collectively referred to as the impurity region) and the channel forming region 21 6, and a gate insulating layer 208a provided on the gate insulating layer 208a. The electrode 210a and the impurity region 214 are electrically connected to a source electrode and a drain electrode. The wiring 230a and 230b function as a signal line (see FIG. 18).

[0211] Here, a sidewall insulating layer 218 is provided on the side surface of the gate electrode 210a. Also, when viewed from a direction perpendicular to the main surface of the substrate 200, the insulating layer 218 is not overlapped with the insulating layer 218. The lower region has a high concentration impurity region 220, and a metal compound in contact with the high concentration impurity region 220. The substrate 200 also has an element region 224 surrounding the transistor 250. A separation insulating layer 206 is provided, and an interlayer insulating layer 226 is provided over the transistor 250. and an interlayer insulating layer 228. The wirings 230a and 230b are , the metal compound region 22 through the openings formed in the interlayer insulating layer 228 and the insulating layer 234. 4. That is, the wirings 230a and 230b are electrically connected to the metal compound region 22. 4, the high concentration impurity region 220 and the impurity region 214 are electrically connected.

[0212] The transistor 150 is a multi-component semiconductor having a first single crystal region provided on an insulating layer 101. The oxide semiconductor layer 103a, the single-component oxide semiconductor layer 105a having a single crystal region, and the second a multi-component oxide semiconductor layer 107a having a first single crystal region and a multi-component oxide semiconductor layer 107b having a second single crystal region; the single-component oxide semiconductor layer 103a, the single-component oxide semiconductor layer 105a having a single crystal region, and the second a first single crystal region formed on the multi-component oxide semiconductor layer 107a; a multi-component oxide semiconductor layer 103a having a single crystal region, and a single-component oxide semiconductor layer 105 a and the multi-component oxide semiconductor layer 107a having the second single crystal region. and wirings 108a and 108b which function as source and drain electrodes, respectively. a multi-component oxide semiconductor layer 103a having a single crystal region; 105a, a second multi-component oxide semiconductor layer 107a having a single crystal region, a wiring 108a, A gate insulating layer 112 is provided to cover the first insulating layer 08b. A gate electrode provided in a region overlapping with the multi-component oxide semiconductor layer 107a having a single crystal region and a pole 114.

[0213] In addition, an insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Here, the gate insulating layer 112, the insulating layer 116, and the interlayer insulating layer 118 are connected to the wiring 108. a, 108b, and wiring 254d, wiring The wires 254e are formed in contact with the wirings 108a and 108b. 254d, the wiring 254e, the gate insulating layer 112, the insulating layer 116, and the interlayer insulating layer The wiring 236a, the wiring 236b, and the wiring 236c are connected through openings provided in the wiring 118. Wiring 254a, wiring 254b, and wiring 254c are formed.

[0214] An insulating layer 256 is provided on the interlayer insulating layer 118, and a buried insulating layer 256 is provided on the insulating layer 256. Wiring 258a, wiring 258b, wiring 258c, and wiring 258d are provided so that the wiring 258a, wiring 258b, wiring 258c, and wiring 258d are inserted. Here, the wiring 258a is in contact with the wiring 254a, and the wiring 258b is in contact with the wiring 254a. The wiring 258c is in contact with the wiring 254c and the wiring 254d. 8d is in contact with the wiring 254e.

[0215] That is, the wiring 108a of the transistor 150 is connected to the wiring 230c, the wiring 236c, and the wiring 25 4c, the wiring 258c, and the wiring 254d, other elements (materials other than oxide semiconductors) are connected to the wiring 254c. Furthermore, the wiring 1 of the transistor 150 is electrically connected to the 08b is electrically connected to other elements via wiring 254e and wiring 258d. In addition, the wirings related to the connection (the wiring 230c, the wiring 236c, the wiring 254c, the wiring 258c, the wiring The configuration of the lines (254d, etc.) is not limited to the above, and lines can be added or omitted as appropriate.

[0216] In addition, various wirings (for example, wiring 258a, wiring 258b, wiring 258c, wiring 258d, etc.) It is preferable to use a material containing copper for a part of these. By using copper, the conductivity can be improved. It can be formed by a silicon process or the like.

[0217] In the above, a typical embodiment of a semiconductor device having a stacked structure has been described. However, one embodiment of the disclosed invention is not limited thereto. The number and arrangement of layers, the number and connection of electrodes and wiring, etc. can be changed as appropriate. For example, as an example of the connection relationship between electrodes, the gate electrode 210a of the transistor 250 and the The resistor 150 is electrically connected to the wiring 108a or the wiring 108b. It is also possible.

[0218] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor with an oxide semiconductor, It is possible to realize semiconductor devices that require different electrical characteristics.

[0219] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0220] (Embodiment 10) In this embodiment, a semiconductor device according to one embodiment of the disclosed invention includes a memory The structure of a semiconductor device that functions as a semiconductor device will be described. a multi-component oxide semiconductor layer having a single crystal region, a single-component oxide semiconductor layer having a single crystal region, and a second single crystal oxide semiconductor layer A multi-component oxide semiconductor layer having a crystalline region (hereinafter referred to as an oxide semiconductor stack) is used. A transistor and a transistor using a material (for example, silicon) other than an oxide semiconductor stack A semiconductor device including the same will be described.

[0221] In the semiconductor device shown in FIG. 19, the gate electrode of the transistor 300 and the gate electrode of the transistor 302 The first transistor is electrically connected to one of the source electrode and the drain electrode. The line (also referred to as the 1st line: source line) and the source electrode of the transistor 300 are The second line (also referred to as the bit line) and the transistor are electrically connected. The drain electrode of the capacitor 300 is electrically connected to the third wiring (3rd Line: also referred to as a first signal line) and the source electrode or drain electrode of the transistor 302. The other of the poles is electrically connected to a fourth wiring (4th Line: also referred to as a second signal line). ) is electrically connected to the gate electrode of the transistor 302. The transistor 300 is made of a material other than the oxide semiconductor laminate (for example, silicon). 19, the transistor 302 includes an oxide semiconductor stack. Here, the transistor 302 is denoted as OStr.

[0222] The transistor 300 using a material other than an oxide semiconductor can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed. The transistor 302 including the oxide semiconductor stack has an extremely low off-state current. Therefore, when the transistor 302 is turned off, the transistor 3 It is possible to maintain the potential of the gate electrode of 00 for an extremely long period of time.

[0223] The source or drain electrode of transistor 302 is connected to the gate electrode of transistor 300. By electrically connecting the floating gate electrode to the electrode, a nonvolatile memory element can be formed. Therefore, in this embodiment, the floating gate of the transistor has the same effect as that of the floating gate of the transistor. In this embodiment, the source electrode or the drain electrode of the transistor 302 and the transistor The portion to which the gate electrode of the capacitor 300 is electrically connected is shown as a floating gate portion FG. The floating gate portion FG is considered to be buried in an insulator (so-called floating state). The floating gate FG holds the charge. Off-state current is less than 1 / 100,000th of that of transistors made of silicon semiconductors Therefore, the charge stored in the floating gate portion FG is The loss due to the signal can be ignored.

[0224] By adopting this configuration, the conventional floating gate type transistor It has been pointed out that the gate is filled with electrons by tunneling current when electrons are injected into the floating gate. Therefore, the problem of deterioration of the tunnel insulating layer can be avoided. In the semiconductor device shown in FIG. 19, the limit on the number of write operations can be ignored in principle.

[0225] A capacitance element may be added to the floating gate portion FG. By adding a capacitance element to the FG of the gate part, it becomes easier to hold the charge and the potential change of each wiring This makes it easier to suppress the potential fluctuation of the floating gate portion FG caused by the movement.

[0226] In the semiconductor device shown in FIG. 19, the potential of the gate electrode of the transistor 300 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows.

[0227] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 302 is turned on by the potential at which the transistor 302 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 300 (write After that, the potential of the fourth wiring is set to a potential that turns off the transistor 302, By turning off the transistor 302, the voltage of the gate electrode of the transistor 300 is The position is retained (retained).

[0228] Since the off-state current of the transistor 302 is extremely small, the gate electrode of the transistor 300 For example, if the potential of the gate electrode of transistor 300 is If the potential is such that the transistor 300 is turned on, the transistor 300 will remain on for a long time. The potential of the gate electrode of the transistor 300 is maintained for a certain period of time. If the potential is such that the transistor 300 is in an off state, the transistor 300 will remain in an off state for a long time. is maintained over time.

[0229] Next, the reading of information will be described. As described above, when the transistor 300 is in the ON state, Alternatively, when the off state is maintained, a predetermined potential (constant potential) is applied to the first wiring. When the transistor 300 is turned on, the potential of the second wiring changes depending on whether the transistor 300 is turned on or off. It takes the value:

[0230] In this way, in a state where information is held, the potential of the first wiring and the potential of the second wiring are By comparing, information can be read out.

[0231] Next, the rewriting of information will be explained. The rewriting of information is performed by writing and storing the above information. That is, the potential of the fourth wiring is set to the ON state when the transistor 302 is turned on. As a result, the potential of the third wiring ( The potential associated with the new information is applied to the gate electrode of the transistor 300. The potential of the wiring 4 is set to a potential at which the transistor 302 is turned off. By turning off 2, the new information is held.

[0232] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0233] Furthermore, in the semiconductor device according to this embodiment, the transistor 302 has a low off-state current. It is possible to retain information for an extremely long period of time. This eliminates the need for a refresh operation, which reduces power consumption. The semiconductor device can be used as a nonvolatile semiconductor memory device.

[0234] In addition, since information is written by the switching operation of the transistor 302, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized.

[0235] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. By using this, it is possible to read out the stored contents at high speed.

[0236] The above explanation applies to n-type transistors (n-channel transistors) that use electrons as carriers. ) is used, but instead of an n-type transistor, holes are used as carriers. It goes without saying that a p-type transistor can be used.

[0237] The semiconductor device according to this embodiment is, for example, a transistor as described in the previous embodiment. Of course, the transistor stack structure can be formed. The structure of the transistor is not necessarily limited to that shown in the above embodiment. The transistor 300 and the transistor 302 may be formed on the same surface. The semiconductor device utilizes the low off-state current of the transistor 302. However, there is no need to particularly limit the transistor 300. For example, in this embodiment, The transistor 300 is formed using a material other than a nitride semiconductor. It's okay if they are there.

[0238] In addition, in this embodiment, the semiconductor device of the minimum unit has been described. However, the present invention is not limited to this. By appropriately connecting multiple semiconductor devices, a more advanced semiconductor device can be produced. For example, a plurality of the above semiconductor devices can be used to configure a NAND type or NO type. It is possible to configure a semiconductor device that functions as an R-type memory device. It is not limited to 19 and can be changed as needed.

[0239] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0240] (Embodiment 11) In this embodiment, a transistor including an oxide semiconductor stack whose c-axis is aligned in a direction perpendicular to the surface is The transistor is used in a pixel portion and a driver circuit to produce a semiconductor device having a display function. The following describes the case where a semiconductor device (also called a display device) is manufactured. Alternatively, the entire unit can be formed on the same substrate as the pixel unit to form a system-on-panel. can.

[0241] In this embodiment, a liquid crystal display device will be described as a semiconductor device which is one embodiment of the present invention. The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 20A shows a crystal structure in which the c-axis is perpendicular to the surface formed on the first substrate 4001. Transistors 4010 and 4011 including an oriented oxide semiconductor stack, and a liquid crystal element 40 13 is sealed between the second substrate 4006 and the panel by a sealant 4005. 20(B) corresponds to a cross-sectional view taken along line MN in FIG. 20(A).

[0242] A pixel portion 4002, a signal line driver circuit 4003, and a scanning A sealing material 4005 is provided so as to surround the line driver circuit 4004. A second substrate 4002 is disposed on the signal line driver circuit 4003 and the scanning line driver circuit 4004. 006 is provided. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the scanning line The driver circuit 4004 is formed on a first substrate 4001, a sealing material 4005, and a second substrate 4006. Therefore, it is sealed together with the liquid crystal layer 4008 .

[0243] A pixel portion 4002 and a signal line driver circuit 4003 are provided on a first substrate 4001. The scanning line driver circuit 4004 has a plurality of transistors. The transistor 4010 included in the scanning line driver circuit 4004 The transistors 4010 and 4011 are shown as examples. An insulating layer 40 is formed on the transistors 4010 and 4011. 14, 4020, and 4021 are provided.

[0244] The transistors 4010 and 4011 are c-axis oriented in the direction perpendicular to the surface as shown in the sixth embodiment. A transistor including such an oxide semiconductor stack can be applied. The transistors 4010 and 4011 are n-channel transistors.

[0245] On the insulating layer 4021, a direction perpendicular to the surface of the transistor 4011 for the driver circuit is A conductive layer 4040 is provided at a position overlapping with a channel formation region of the axially aligned oxide semiconductor stack. The conductive layer 4040 is a stack of oxide semiconductor layers whose c-axes are aligned in a direction perpendicular to the surface. By providing the conductive layer 4040 at a position overlapping the channel forming region, one of the effects is that the conductive layer 4040 It acts as a passivation layer, preventing external hydrogen from penetrating into the channel formation region. Therefore, the threshold voltage of the transistor 4011 before and after the BT test can be In addition, the conductive layer 4040 can reduce the amount of change in potential of the transistor 40 It may be the same as the gate electrode 11 or may be different, and functions as the second gate electrode. The potential of the conductive layer 4040 can be set to GND, 0 V, or a floating state. It may be in a locking state.

[0246] In addition, the pixel electrode 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode 4030, the counter electrode 4031, and the liquid crystal layer 4008 are overlapped. The portion corresponding to the pixel electrode 4030 and the counter electrode 4031 corresponds to the liquid crystal element 4013. Insulating layers 4032 and 4033 functioning as alignment films are provided on the insulating layers 4032 and 4033, respectively. , 4033 sandwich the liquid crystal layer 4008 therebetween.

[0247] The liquid crystal layer 4008 may be a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, or a polymer dispersed liquid crystal. These liquid crystal materials are used, such as ferroelectric liquid crystals and antiferroelectric liquid crystals. cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase Indicates equality.

[0248] The second substrate 4006 can be made of glass or plastic.

[0249] Also, the columnar spacers 4035 obtained by selectively etching the insulating layer are The electrode 4030 and the counter electrode 4031 are provided to control the distance (cell gap). A spherical spacer may be used. It is electrically connected to a common potential line provided on the same insulating substrate as the resistor 4010. The common connection portion is used to connect the counter electrode 4031 to the conductive particles disposed between the pair of substrates. The conductive particles are applied to the sealing material 4005. To contain.

[0250] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. sec or less, and because it is optically isotropic, alignment treatment is not required, and viewing angle dependency is small. stomach.

[0251] In addition, when a liquid crystal that exhibits a blue phase is used, rubbing treatment of the alignment film is not required. This prevents electrostatic damage caused by the soldering process, and prevents the LCD display from being damaged during the manufacturing process. This reduces the number of defects and damages to the device, thereby improving the productivity of liquid crystal display devices. In particular, a transistor including an oxide semiconductor stack can be easily affected by static electricity. This can cause the electrical characteristics of the transistor to fluctuate significantly and deviate from the design range. and a blue phase liquid crystal material for a liquid crystal display device having a transistor using an oxide semiconductor stack. It is more effective to use

[0252] Although the liquid crystal display device shown in this embodiment is a transmissive liquid crystal display device, a reflective liquid crystal display device may also be used. The display device may be a semi-transmissive liquid crystal display device.

[0253] In addition, in the liquid crystal display device described in this embodiment mode, a polarizing plate is provided on the outer side (viewing side) of the substrate, and The polarizing plate is located on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and the polarizing plate may be provided on the The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding layer that functions as a block matrix may be provided.

[0254] In this embodiment, in order to reduce the surface unevenness of the transistor and To improve reliability, the transistor is covered with an insulating layer ( The insulating layer 4020, the insulating layer 4014, and the insulating layer 4021 are used to cover the insulating layer. The protective layer is designed to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective layer is preferably a dense film. layer, silicon nitride layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, A single layer of aluminum nitride, aluminum oxynitride, or aluminum oxynitride; may be formed by laminating layers.

[0255] Here, a laminate of insulating layers is formed as a protective layer. Then, a silicon oxide layer is formed by sputtering. When a protective layer is used, oxygen is added to the oxide semiconductor layer in contact with the protective layer, and oxygen defects are reduced. can be done.

[0256] Further, an insulating layer 4014 is formed as the second layer of the protective layer. 14, a silicon nitride layer, which is one of the nitride insulating layers, is formed using the plasma CVD method. Furthermore, if a silicon nitride layer is used as a protective layer, sodium etc. ions into the semiconductor region and prevent them from changing the electrical characteristics of the transistor. It is possible.

[0257] An insulating layer 4021 is formed as a planarizing insulating layer. In addition to the above organic materials, low dielectric constant materials (low -k materials), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass) It is possible to use a plurality of insulating layers made of these materials. Then, the insulating layer 4021 may be formed.

[0258] The pixel electrode 4030 and the counter electrode 4031 are made of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A conductive material having light-transmitting properties, such as indium-doped indium tin oxide, can be used. do.

[0259] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or Various signals and potentials to be applied to the pixel portion 4002 are supplied from an FPC 4018 .

[0260] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode 403 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive layer as the transistors 4010 and 4011. The source electrode and the drain electrode are formed from the same conductive layer.

[0261] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. are electrically connected.

[0262] If necessary, a color filter is provided corresponding to each pixel. A polarizing plate and a diffusing plate are provided on the outside of the first and second substrates 4001 and 4006. The source is composed of cold cathode fluorescent lamps and LEDs, forming an LCD display module.

[0263] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0264] A liquid crystal display device can be manufactured by the above steps. However, the present invention can also be applied to semi-transmissive and reflective liquid crystal display devices.

[0265] The transistor including the oxide semiconductor stack whose c-axis is aligned in the direction perpendicular to the surface, which is described in Embodiment 6, Since the sintered body has a high field effect mobility, it can be used to make a liquid crystal display, as in the present embodiment. By manufacturing a liquid crystal display device, a liquid crystal display device with excellent display characteristics can be realized. In this configuration, when a still image is displayed, the output of the signals supplied to the signal lines and scanning lines is stopped. By operating the driver circuit section so as to stop the power consumption of not only the pixel section but also the driver circuit section, The force can also be reduced.

[0266] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0267] (Embodiment 12) The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a semiconductor device are shown. This will be explained with reference to FIG. 21. FIG. 21(A) shows a vertically extending portion formed on a surface of a first substrate. Transistor and electroluminescent device including oxide semiconductor stack with c-axis oriented perpendicular to the direction A light emitting element such as a sense element (also called an EL element) is placed between the second substrate and the light emitting element by a sealing material. 21(B) is a cross-sectional view of the panel at HI in FIG. 21(A). This corresponds to a plan view.

[0268] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Packaging (enclosing) with a highly airtight protective film or covering material that minimizes outgassing is preferred.

[0269] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. 21B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0270] The transistors 4509 and 4510 are c-axis oriented in the direction perpendicular to the surface as shown in the sixth embodiment. A transistor having high mobility including an oxide semiconductor stack having such a structure can be applied. In this embodiment, the transistors 4509 and 4510 are n-channel transistors. .

[0271] The oxide semiconductor layer overlaps with the channel formation region of the transistor 4509 for the driver circuit. A conductive layer 4540 is provided over the insulating layer 4544. The gate electrode of the second transistor 4509 may be the same as or different from the gate electrode of the second transistor 4509. The conductive layer 4540 can also function as a gate electrode. V, or may be floating.

[0272] The transistor 4509 has an oxide semiconductor stack including a channel formation region as a protective insulating layer. The insulating layer 4541 is formed in contact with the oxide film 4541 shown in Embodiment 6. The insulating layer 4541 may be formed using the same material and method as the insulating layer 412. An insulating layer 4514 is formed. The protective insulating layer 4514 is the same as the insulating layer 4 shown in Embodiment 6. 16. Here, the protective insulating layer 4514 is formed of a material and by a method similar to that of the protective insulating layer 4516. A silicon nitride layer is formed by CVD.

[0273] Further, a planarization insulating layer for reducing surface unevenness of the transistor is formed over the protective insulating layer 4514. A functional insulating layer 4544 is formed. The insulating layer 4544 may be the same as that shown in Embodiment 11. The insulating layer 4544 may be formed using a material and a method similar to those of the insulating layer 4021. Acrylic is used.

[0274] The first electrode 4517, which is a pixel electrode of the light-emitting element 4511, is connected to the transistor 4 The light-emitting element 451 is electrically connected to the source electrode or drain electrode of the light-emitting element 451. The structure of the first electrode 4517, the EL layer 4512, and the second electrode 4513 are stacked. However, it is not limited to the configuration shown. Therefore, the structure of the light-emitting element 4511 can be changed as appropriate.

[0275] The partition wall 4520 is formed using an organic resin layer or an inorganic insulating layer. An opening is formed on the first electrode 4517, and the sidewall of the opening has a continuous curvature. It is preferable that the surface be an inclined surface.

[0276] The EL layer 4512 may be composed of a single layer or a plurality of layers stacked. It's okay to have it.

[0277] The second electrode 4 is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511. A protective layer may be formed on the insulating layer 513 and the partition wall 4520. The protective layer may be a silicon nitride layer. , a silicon nitride oxide layer, a DLC layer, etc. can be formed.

[0278] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0279] The connection terminal electrode 4515 is formed from the same conductive layer as the first electrode 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source electrodes of the transistors 4509 and 4510. and the drain electrode are formed from the same conductive layer.

[0280] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive layer 4519. are electrically connected to each other.

[0281] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 must be light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0282] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It is possible to use oil or thermosetting resin, such as acrylic or epoxy resin. For example, nitrogen can be used as a filler.

[0283] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. stomach.

[0284] Through the above steps, a light-emitting display device (display panel) can be manufactured.

[0285] The transformer using the oxide semiconductor stack whose c-axis is oriented in the direction perpendicular to the surface, which is described in Embodiment 6, Since the transistor has a high field effect mobility, it can be used to emit light as in this embodiment. By manufacturing a display device, a light-emitting display device with excellent display characteristics can be realized. In this embodiment, when a still image is displayed, the output of the signal supplied to the signal line and the scanning line is By operating the drive circuit unit so that it stops, the consumption of not only the pixel unit but also the drive circuit unit is reduced. Power consumption can also be reduced.

[0286] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0287] (Embodiment 13) In this embodiment mode, electronic paper is shown as one mode of a semiconductor device.

[0288] The oxide semiconductor layer having a c-axis oriented in the direction perpendicular to the surface obtained by the method shown in Embodiment 6 The transistor including the layered structure is an electronic interface using an element electrically connected to the switching element. The electronic paper may be used for an electrophoretic display device (electronic paper). It is also called electrophoretic display (ELD), and is as easy to read as paper, and is more accurate than other display devices. This has the advantages of being able to reduce power consumption, thickness and weight.

[0289] Electrophoretic displays can be of various types, for example, those having a positive charge. Microcapsules containing first particles and second particles having a negative charge are dissolved in a solvent or is dispersed in a solute, and by applying an electric field to the microcapsules, The particles in the microcapsules are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is measured. The first particles or the second particles may contain a dye, In the absence of an electric field, the particles do not move. are different (including colorless).

[0290] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0291] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0292] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. For example, in the sixth embodiment, Active layer obtained by a transistor including an oxide semiconductor stack whose c-axis is aligned in the direction A matrix substrate can be used.

[0293] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, a semiconductor, or the like. Conductive materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A material selected from magnetochromic materials, magnetophoretic materials, or a composite material of these materials is used. It can be formed by

[0294] FIG. 22 shows an active matrix electronic paper as one example of a semiconductor device. The transistor 581 used in the semiconductor device is the same as the transistor described in Embodiment 6. The oxide semiconductor stack with the c-axis oriented in the direction perpendicular to the surface can be fabricated in the same manner as above. The insulating layer 584 is a nitride insulating layer.

[0295] The electronic paper in FIG. 22 is a type of display device that uses a twisting ball display method. The isoball display method uses electrodes made of black and white spherical particles as display elements. A potential difference is generated between a first electrode and a second electrode. This is a method of displaying images by controlling the orientation of spherical particles.

[0296] The transistor 581 formed on the first substrate 580 is a bottom-gate transistor. The source voltage of the transistor 581 is The source or drain electrode is formed on the first electrode 587 and the insulating layers 583, 584, and 585. The first electrode 587 and the second electrode 588 are electrically connected to each other through the opening. , there is a cavity 594. Within the cavity 594, there are a black region 590a and a white region The cavity 594 is filled with spherical particles 590b and liquid. The cavity is filled with a filler 595 such as resin (see FIG. 22).

[0297] The first electrode 587 corresponds to a pixel electrode, and the second electrode 596 formed on the second substrate The second electrode 588 corresponds to a common electrode. The second electrode 588 is formed on the same insulating substrate as the transistor 581. The common connection portion is electrically connected to a common potential line provided on the pair of substrates. Electrically connecting the second electrode 588 and the common potential line through the conductive particles disposed thereon. can be done.

[0298] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules with a size of about 0 μm are used. When an electric field is applied between the first and second electrodes, the microcapsules are transformed into white microparticles. When the black particles move in the opposite direction, white or black can be displayed. The display element used is an electrophoretic display element, which is generally called electronic paper. Instead of black particles, particles that indicate one of the RGB (R stands for red, G stands for green, B stands for blue) It can be displayed in color by using the

[0299] Through the above steps, electronic paper can be produced.

[0300] In this embodiment, the oxide semiconductor layer having the c-axis oriented in the direction perpendicular to the surface shown in Embodiment 6 is used. Transistors containing the layered structure are used to produce so-called electronic paper. Since the PVD has high field-effect mobility, it can be used to manufacture electronic paper. This allows for the realization of electronic paper with excellent display characteristics.

[0301] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0302] (Embodiment 14) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0303] In this embodiment, a display device obtained in any one of the embodiments 11 to 13 The form of an electronic device incorporating the above will be described with reference to FIGS. 23 and 24. FIG.

[0304] FIG. 23(A) shows a notebook-type personal computer manufactured by mounting at least a display device as a component. It is a personal computer, and it has a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, and a 004, etc. The liquid crystal display device according to the eleventh embodiment is There are personal computers of this type.

[0305] FIG. 23(B) shows a portable information terminal (P DA), and the main body 3021 includes a display unit 3023, an external interface 3025, Operation buttons 3024 and the like are provided. A stylus 3022 is also provided as an accessory for operation. Note that the portable information terminal includes the light-emitting display device described in Embodiment 12.

[0306] FIG. 23C shows an electronic device manufactured by mounting the electronic paper shown in Embodiment 13 as a component. FIG. 23C shows one form of electronic book. For example, electronic book 270 0 is composed of two housings, housing 2701 and housing 2703. The housing 2703 is integrated with a shaft 2711 and opens and closes around the shaft 2711. This configuration allows the device to operate like a paper book. It becomes Noh.

[0307] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are also configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display (display 2705 in FIG. 23(C)), and An image can be displayed on the display unit (display unit 2707 in FIG. 23C).

[0308] FIG. 23C shows a mode in which an operating unit and the like are provided in the housing 2701. For example, the housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. A keyboard and a pointing device may be provided on one side. On the back or side of the device, there are external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion port, etc. Furthermore, the electronic book 2700 may have a function as an electronic dictionary. It may also be configured so that

[0309] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0310] FIG. 23(D) shows a mobile phone manufactured by mounting at least a display device as a component. It consists of two housings, housing 2800 and housing 2801. Housing 2801 has a display Panel 2802, speaker 2803, microphone 2804, pointing device 2806, a camera lens 2807, and an external connection terminal 2808. The body 2800 includes a solar cell 2810 for charging the mobile phone, an external memory slot 28 11, etc. The antenna is built into the housing 2801.

[0311] The display panel 2802 is equipped with a touch panel, and the image displayed on the display panel 2802 is shown in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0312] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but can also be used for video calls, recording, etc. Furthermore, the housing 2800 and the housing 2801 can be slid to each other, as shown in FIG. It can be folded from the unfolded state as shown in 3(D) to the overlapped state, making it suitable for carrying. It is possible to make the device smaller.

[0313] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0314] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0315] FIG. 23(E) shows a digital camera manufactured by mounting at least a display device as one component. It includes a main body 3051, a display unit (A) 3057, an eyepiece 3053, an operation switch 3054, and a display It is composed of a display unit (B) 3055, a battery 3056, etc.

[0316] 24 shows one form of television device. The television device 9600 has a housing A display unit 9603 is built into the 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. This shows the progress.

[0317] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0318] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0319] The display portion 9603 includes the transistor described in Embodiment 6 as a switching element of a pixel. A plurality of display units 9603 are arranged, and the display unit 9603 and the display unit 9603 are formed on the same insulating substrate as a driving circuit. A high-mobility transistor shown in Mode 6 is arranged.

[0320] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 13. This can be done.

Claims

1. a first conductive layer located over a substrate and functioning as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; a first oxide semiconductor layer having a region located above the first conductive layer with the first insulating layer interposed therebetween; a second oxide semiconductor layer having a region located on the first oxide semiconductor layer and including a multi-component oxide semiconductor material; a second conductive layer having a region in contact with the second oxide semiconductor layer and functioning as a source electrode or a drain electrode of the transistor, the second conductive layer overlaps with the first conductive layer via the first oxide semiconductor layer and the second oxide semiconductor layer; the second oxide semiconductor layer has a first region having a first crystal part aligned along a c-axis and a second region having a second crystal part aligned along the c-axis; a c-axis direction in the first crystal portion is different from a c-axis direction in the second crystal portion, the second conductive layer has a region in contact with the first region and a region in contact with the second region.

2. a first conductive layer located over a substrate and functioning as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; a first oxide semiconductor layer having a region located above the first conductive layer with the first insulating layer interposed therebetween; a second oxide semiconductor layer having a region located on the first oxide semiconductor layer and including a multi-component oxide semiconductor material; a second conductive layer having a region in contact with the second oxide semiconductor layer and functioning as a source electrode or a drain electrode of the transistor, the second conductive layer overlaps with the first conductive layer via the first oxide semiconductor layer and the second oxide semiconductor layer; the second oxide semiconductor layer has a first region having a first crystal part aligned along a c-axis and a second region having a second crystal part aligned along the c-axis; a c-axis direction in the first crystal portion is different from a c-axis direction in the second crystal portion, the second conductive layer has a region in contact with the first region and a region in contact with the second region, The first oxide semiconductor layer has a crystal portion.

Images