Method for forming thin film transistors

Abstract

To provide a method of forming a thin film transistor (TFT).SOLUTION: A method for forming a TFT 200 on a substrate 102 includes forming one or more metal oxide layers 204 and / or polysilicon layers, and depositing a gate insulator (GI) layer 206 over the one or more metal oxide layers and / or polysilicon layer by using a high-density plasma chemical vapor deposition (HDP-CVD) process using inductively coupled plasma (ICP). When the GI layer is deposited using an HDP-CVD layer, the mobility of the metal oxide layer deposited underneath is higher than expected.SELECTED DRAWING: Figure 2G

Description

[Technical field]

[0001] TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to methods, and more particularly, to methods for forming thin film transistors. [Background technology]

[0002]

[0002] A thin film transistor (TFT) is a type of metal-oxide-semiconductor field effect transistor (MOSFET) made by depositing thin films of an active semiconductor layer, a dielectric layer, and metal contacts on a supporting substrate. One application of TFTs is in liquid crystal displays (LCDs), so glass substrates are common.

[0003]

[0003] TFTs have attracted much attention in display applications due to the high resolution, low power consumption, and high speed operation of LCD and organic light emitting diode (OLED) displays. TFTs are incorporated into the panel of the display. Data line and gate line voltage signals from the display module in the display system are sent to the TFTs in pixel circuits and / or gate driver circuits around the periphery of the display panel, and the TFTs are turned on and off to control the display image. The higher mobility of the TFTs improves response and / or reduces crosstalk between pixels, reducing image distortion. Many display products, including LCD televisions (TVs) and monitors, include TFTs in their panels. Many modern high-resolution and high-quality electronic visual display devices use active matrix displays that use a large number of TFTs. One beneficial aspect of TFT technology is the use of a separate TFT for each pixel of the display. Each TFT acts as a switch or current source in the pixel circuit or gate driver circuit to control the voltage and current through the data signal lines and gate signal lines, thereby enhancing control of the display image. The high current of high mobility TFTs allows for fast updating of the display image, improving image quality by minimizing distortion of the data and gate signal voltages.

[0004]

[0004] One of the drawbacks of TFTs in the art is that the mobility of the conductive channel can be unacceptably low. Furthermore, the methods of forming the TFTs may not provide good control over the mobility of the channel. Finally, it can be difficult to change the mobility of the channel after it has already been deposited.

[0005]

[0005] Thus, there is a need in the art for a method of forming a TFT that can enhance channel mobility. Summary of the Invention

[0006]

[0006] The embodiments disclosed herein generally relate to a method of forming a TFT, the method including depositing a layer that modifies the mobility of the underlying channel.

[0007]

[0007] One exemplary method of forming a thin film transistor device includes forming a metal oxide layer on a first portion of a substrate, forming a gate insulator (GI) layer on the first portion of the substrate, forming a gate electrode on the GI layer, and etching one or more remaining portions of the GI layer. Forming the GI layer includes depositing a silicon-containing layer in a high density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP). The HDP-CVD process is performed at about 2.3 W / cm 2 to about 5.3 W / cm 2 and an ICP frequency from about 2 MHz to about 13.56 MHz.

[0008] Another exemplary method of forming a thin film transistor device includes forming a first metal oxide layer on a first portion of a substrate, the first portion of the substrate corresponding to a first thin film transistor (TFT), forming a first metal oxide layer on the first portion of the substrate in contact with the first metal oxide layer on the first portion of the substrate to form an interfacial gate insulator (GI) layer of the first TFT and forming an underlayer on a second portion of the substrate, the second portion of the substrate corresponding to a second TFT, the underlayer contacting a bottom surface of the second metal oxide layer of the second TFT, forming the interfacial GI layer and the underlayer comprising depositing a first silicon-containing layer on the first portion and the second portion, the first silicon-containing layer being deposited in a high density plasma chemical vapor deposition (HDP-CVD) process using inductively coupled plasma (ICP), the HDP-CVD process having a power of about 2.3 W / cm. 2 to about 5.3 W / cm 2and an ICP frequency of about 2 MHz to about 13.56 MHz, depositing a first silicon-containing layer on the first and second portions, the first silicon-containing layer being in contact with the first metal oxide layer on the first portion of the substrate to form an interfacial gate insulator (GI) layer of the first TFT and forming a lower layer on the second portion of the substrate, forming a second metal oxide layer of the second TFT in contact with the lower layer at the bottom surface thereof, forming a bulk GI layer of the first TFT in contact with the interfacial layer and forming a GI layer of the second TFT in contact with a top surface of the second metal oxide layer, the forming the bulk GI layer and the GI layer being in contact with the first and second portions of the substrate in a chemical vapor deposition (CVD) process using a capacitively coupled plasma (CCP). forming a first gate electrode of the first TFT on the second silicon-containing layer over the first portion and a second gate electrode of the second TFT on the second silicon-containing layer over the second portion; removing one or more remaining portions of the second silicon-containing layer from the first portion and the second portion to form an interfacial GI layer of the first TFT, a bulk GI layer of the first TFT, a GI layer of the second TFT, and a lower layer of the second TFT; and depositing an interlayer dielectric (ILD) layer over the substrate.

[0009] Yet another exemplary method of forming a thin film transistor device includes forming a polysilicon layer on a first portion of a substrate, the first portion of the substrate corresponding to a polysilicon thin film transistor (TFT), depositing a first gate insulator (GI) layer over the polysilicon layer of the first portion of the substrate and over a second portion of the substrate, the second portion of the substrate corresponding to a metal oxide (MOx) TFT, forming a first gate electrode of the polysilicon TFT on the first GI layer and forming a shield metal of the MOx TFT, forming a first interlayer dielectric (ILD) layer over the first GI layer, the first gate electrode, and the shield metal, and depositing a first ILD layer over the first GI layer, the first gate electrode, and the shield metal of the MOx TFT. forming a metal oxide layer of the TFT; and forming a second GI layer on the metal oxide layer, the second GI layer including depositing a silicon-containing layer in a high density plasma chemical vapor deposition (HDP-CVD) process using an inductively coupled plasma (ICP), the HDP-CVD process having a power density of about 2.3 W / cm 2 to about 5.3 W / cm 2 and an ICP frequency from about 2 MHz to about 13.56 MHz, forming a second GI layer on the metal oxide layer, forming a second gate electrode on the second GI layer, and forming a second ILD layer on the first ILD layer, the metal oxide layer, and the second gate electrode.

[0010]

[0010] In order that the above-mentioned features of the present disclosure may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings merely depict exemplary embodiments, and therefore should not be considered as limiting the scope thereof, as other equally effective embodiments may be permitted. [Brief description of the drawings]

[0011] [Figure 1]FIG. 2 is a schematic cross-sectional view of a chamber according to an embodiment. [Figure 2A-D] 1 is a schematic cross-sectional view showing a TFT according to an embodiment. [Fig. 2E-G] 1 is a schematic cross-sectional view showing a TFT according to an embodiment. [Figure 2H] 1 is a schematic cross-sectional view showing a TFT according to an embodiment. [Diagram 3] FIG. 2 is a flow diagram of a method for forming a TFT according to one embodiment. [Figure 4A-D] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 4E-G] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 4H-I] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 4J] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Diagram 5] FIG. 2 is a flow diagram of a method for forming two transistor structures according to one embodiment. [Figure 6] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 7] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 8] FIG. 1 is a schematic cross-sectional view of two transistor structures according to an embodiment; [Figure 9A-D] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 9E-F] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 9G-H] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 9I-J] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Fig. 9K-L] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 9M]FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 9N] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment. [Figure 10] FIG. 2 is a flow diagram of a method for forming two transistor structures according to one embodiment. [Figure 11] FIG. 2 is a schematic cross-sectional view illustrating two transistor structures according to an embodiment.

[0012]

[0022] To facilitate understanding, wherever possible, the same reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0023] The embodiments disclosed herein generally relate to a method of forming a TFT. The method includes depositing one or more metal oxide layers and / or polysilicon layers. A GI layer is deposited on the one or more metal oxide layers and / or polysilicon layers. The GI layer is deposited using HDP-CVD to unexpectedly increase the mobility of the metal oxide layer and / or polysilicon layer deposited thereunder. The selective placement of the GI layer controls the mobility of the underlying layer depending on whether the GI layer is deposited using HDP-CVD or a CVD process using CCP. The deposition of the GI layer allows for control of the mobility of the underlying layer after the layer deposition, i.e., the mobility can be enhanced after deposition in addition to during deposition. The embodiments disclosed herein may be useful, but are not limited to, for forming a TFT including a channel with enhanced mobility.

[0014]

[0024] As used herein, the term "about" refers to a variation of about ±10% from the nominal value, and it is understood that such a variation may be included in any value provided herein.

[0015]

[0025] In various embodiments of the present disclosure, layers or other materials are referred to as being etched. It is understood that etching of these materials can be accomplished using any conventional method used in semiconductor manufacturing, including, but not limited to, reactive ion etching (RIE), dry etching, wet etching, plasma etching, microloading, selective etching of any of the above, combinations of the above, and any other suitable method. Where a method step is described herein as etching two or more materials, or two or more portions of the same material, it is understood that the etching can occur simultaneously in the same etching process, or the etching can occur in separate substeps using different etching processes. For example, a process describing etching a metal and a dielectric includes a first etching substep using a first etching process to etch the metal, and the process further includes a second etching substep using a second etching process to etch the dielectric.

[0016]

[0026] 1 is a schematic cross-sectional view of a chamber 100 according to one embodiment. Suitable chambers are available from Applied Materials, Inc., Santa Clara, Calif. It is understood that the system described below is an exemplary chamber, and that other chambers, including chambers from other manufacturers, can be used with or modified to accomplish aspects of the present disclosure. The chamber 100 is configured to produce HDP.

[0017]

[0027] As shown, the chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108. The lid assembly 106 is disposed at an upper end of the chamber body 104. The substrate support assembly 108 is disposed at least partially within an interior region of the chamber body 104. The substrate support assembly 108 includes a substrate support 110 and a shaft 112. The substrate support 110 has a support surface 114 for supporting at least one substrate 102.

[0018]

[0028] In one embodiment, which can be combined with other embodiments described herein, the substrate 102 is typically about 1 mm thick. 2 The substrate 102 may be a large area substrate, such as a substrate having a surface area of ​​100 mm or more. However, the substrate 102 is not limited to any particular size or shape. For example, the term "substrate" refers to any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a glass substrate or a polymer substrate used in the manufacture of flat panel displays. The substrate 102 may include any suitable material, such as a silicon-based substrate, a semiconductor substrate, an insulating substrate, a germanium-based substrate, and one or more generic layers that would typically be present in a complementary metal oxide semiconductor (CMOS) device structure. The substrate 102 may include a transparent material, such as a rigid glass or a flexible polyimide (PI), which may be useful if the substrate is used in an LCD or OLED display application, such as a television, tablet, laptop, cell phone, or other display. The substrate 102 may have any number of metal, semiconductor, or insulating layers thereon.

[0019]

[0029] The lid assembly 106 includes a diffuser 116 at an upper end of the chamber body 104. The diffuser 116 includes one or more diffuser inlets 118 that are coupleable to at least one gas source 120. The diffuser 116 delivers one or more gases from the gas source 120 to a processing region 124 between the diffuser 116 and the substrate support 110. The one or more gases are delivered to the processing region 124 through a number of holes (not shown) in the diffuser 116. A flow controller 122, such as a mass flow control (MFC) device, is disposed between each of the diffuser inlets 118 and the gas source 120 to control the flow of gas from the gas source 120 to the diffuser 116. A pump 126 is in fluid communication with the processing region 124. The pump 126 is operable to control the pressure within the processing region 124 and to evacuate gases and by-products from the processing region 124.

[0020]

[0030] The lid assembly 106 includes at least one cavity 128 having one or more inductively coupled plasma generating components (alternatively referred to as coils) 130 formed therein. The coils 130 are supported by at least one dielectric plate 132. Each dielectric plate 132 provides a physical barrier having structural strength to withstand structural loads caused by the presence of atmospheric pressure within the cavity 128 and the presence of vacuum pressure in the interior region of the chamber body 104. Each coil 130 is connected to a power source 134 and a ground 138. In an embodiment, which can be combined with other embodiments described herein, each coil 130 is connected to the power source 134 through a matching box 136 having a matching circuit for adjusting electrical characteristics, such as impedance, of the coil 130. In some embodiments, a first capacitor 137 is electrically connected between the coil 130 and the matching box 136. In some embodiments, an end capacitor 139 is electrically connected between the coil 130 and the ground 138. Each coil 130 is configured to generate an electromagnetic field that energizes the gas in the processing region 124 to generate a high density plasma (HDP).

[0021]

[0031] In one embodiment, the electron density generated in the chamber is about 1E11 / cm 3 In one embodiment, the ion plasma density produced in the chamber is greater than about 1E11 / cm 3 In one embodiment, the ICP power density used to generate the HDP is greater than about 5.3 W / cm 2 In one embodiment, the ICP frequency used to generate the HDP is from about 2 MHz to about 13.56 MHz.

[0022]

[0032] The controller 190 is coupled to the chamber 100 and configured to control aspects of the chamber 100 during processing. As shown, the controller 190 includes a central processing unit (CPU) 191, a memory 192, and support circuits (alternatively referred to as I / O) 193. The CPU 191 is one of any form of computer processor used in industrial environments to control various processes and hardware (e.g., pattern generators, motors, and other hardware) and monitor processes (e.g., processing time and substrate position or location). The memory 192 is connected to the CPU 191 and is one or more of readily available memories such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. Software instructions and data for instructing the CPU 191 can be coded and stored in the memory 192. The CPU 191 can also include any of the conventional memory types. ※ Support circuits 193 are connected to support the CPU in a manner that includes conventional cache, power supplies, clock circuits, input / output circuits, subsystems, etc. A program (or computer instructions) readable by the controller 190 determines what tasks are executable on the substrate 102. The program may be software readable by the controller 190 and may include, for example, code for monitoring and controlling process parameters (e.g., pressure, temperature, gas flow rates) of the chamber 100.

[0023]

[0033] 2A-2H are schematic cross-sectional views illustrating a method of forming a TFT 200 according to one embodiment. FIG. 3 is a flow diagram of a method 300 of forming a TFT 200 according to the embodiment. For ease of explanation, FIGS. 2A-2H, 3, 8, and 11 will be described with reference to the chamber 100 of FIG. 1. However, it should be noted that ICP-CVD chambers other than the chamber 100 may be utilized with the method 300. The method 300 may be stored or accessible to the controller 190 as a computer-readable medium that includes instructions that, when executed by the CPU 191, cause the chamber 100 to perform the method 300.

[0024]

[0034] As shown, a TFT 200 is formed on a substrate 102 (FIG. 2A).

[0025]

[0035] The method 300 begins at step 310 where a metal oxide layer 204 is formed, as shown in FIG. 2B. The metal oxide layer 204 is formed by any conventional method used in the art. In some embodiments, the metal oxide layer 204 is deposited on the substrate 102. In one embodiment, which may be combined with other embodiments described herein, the metal oxide layer 204 includes oxygen (O) and at least one of indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf). Examples of the metal oxide layer 204 include, but are not limited to, In-Ga-Zn-O, In-Zn-O, In-Ga-Sn-O, In-Zn-Sn-O, In-Ga-Zn-Sn-O, In-Sn-O, Hf-In-Zn-O, Ga-Zn-O, In-O, Al-Sn-Zn-O, Zn-O, Zn-Sn-O, Al-Zn-O, Al-Zn-Sn-O, Hf-Zn-O, Sn-O, and Al-Sn-Zn-In-O. Step 310 may include doping the metal oxide layer 204 with an n-type or p-type dopant, such as boron (B) or nitrogen (N). The metal oxide layer 204 may have a thickness of about 30 nm to about 50 nm. A metal oxide layer film may be formed in a first substep and etched in a second substep to form the metal oxide layer 204. In other embodiments, the metal oxide layer 204 is deposited using selective deposition to create a metal oxide layer 204 having a desired shape.

[0026]

[0036] In step 340, the GI layer 206 is deposited, as shown in FIG. 2C. The GI layer 206 is deposited on at least a portion of the metal oxide layer 204. The GI layer 206 is in direct contact with the metal oxide layer 204. The GI layer 206 is a material selected from the group consisting of silicon, silicon oxide (Si x O y ), silicon nitride (SiN x ), other insulating materials, or combinations thereof. The GI layer 206 may have a thickness from about 200 Å to about 8000 Å. Step 340 is performed using high density plasma chemical vapor deposition (HDP-CVD).

[0027]

[0037] Step 340 includes providing nitrous oxide (NO) at about 0.40 sccm / cm 2 to about 0.60sccm / cm 2 Silane (SiH4) at a flow rate of about 0.01sccm / cm 2 to about 0.01sccm / cm 2 at a flow rate of about 20 to about 900 seconds, with a N2O to SiH4 ratio of about 5 to about 40, a chamber pressure of about 75 mTorr to about 150 mTorr, a chamber temperature of about 70° C. to about 350° C., and a substrate temperature of about 80° C. to about 160° C. Step 340 includes flowing a gas comprising the above-mentioned SiO2 gas at a flow rate of about 2 W / cm2 using HDP-CVD. 2 to about 6 W / cm 2 , for example, about 2.3 W / cm 2 to about 5.3 W / cm 2 At an ICP power density of about 1000 W to about 1500 W, at an ICP frequency of about 1 MHz to about 15 MHz, for example about 2 MHz to about 13.56 MHz, at an applied bias power of about 0 W to about 200 W, and at an ICP power of about 4000 W to about 10000 W. In some embodiments, silicon tetrafluoride (SiF4), disilane (Si2H6), oxygen gas (O2), ozone (O3), Ar, nitrogen gas (N2), ammonia (NH3), He, or a mixture of the above, are flowed in parallel. The distance between the substrate and the gas source can be about 7000 mm to about 8000 mm.

[0028]

[0038] The GI layer 206 may be deposited at a rate of about 700 Å / min to about 1500 Å / min. The refractive index of the GI layer may be about 1.8 to about 2.0. The silicon-hydrogen (Si—H) bond fraction may be about 0.1% to about 12%. The silicon-nitrogen (Si—N) bond fraction may be about 10% to about 25%. The silicon-oxygen (Si—O) bond peak position as measured by spectroscopy may be about 1050 1 / cm to about 1100 1 / cm. The stress of the GI layer 206 is about −450 MPa to about 700 MPa. When the GI layer 206 is Si x N y Exemplary process variables for step 340, including: x O y Exemplary process variables for step 340, including: TIFF0007642044000001.tif116170

[0029]

[0039] Table 1:Si x N y Example process variables for step 340 for a GI tier including: A blank cell indicates that the variable does not apply. TIFF0007642044000002.tif106170

[0030]

[0040] Table 2:Si x O y Example process variables for step 340 for a GI tier including: A blank cell indicates that the variable does not apply.

[0031]

[0041] In a capacitively coupled plasma chemical vapor deposition (CCP-CVD) process, opposing electrodes, such as parallel plate electrodes, are provided, one coupled to ground and the other to a power source, and a gas is introduced between them to essentially form a capacitor. By supplying power to the powered electrodes, electrical energy is capacitively coupled to the gas to form a plasma. The ion density of the plasma is a function of the power delivered to the gas. In ICP, on the other hand, a coil surrounds or is on the gas volume in which the plasma is formed, and electrical energy flowing through the coil electromagnetically couples to the gas, ionizing or otherwise energizing the gas atoms or molecules. Again, the ion density of the plasma is a function of the energy coupled to the gas. In a CCP system, one of the electrodes is usually also the substrate support, so the power that can be coupled to the gas is limited by the potential adverse effects that the power may have on the substrate. In contrast, with ICP, the power for ionizing the gas atoms and molecules is decoupled from the circuitry that holds the substrate, and a higher power can be used to energize the plasma, resulting in a higher ion density in the plasma without adversely affecting the substrate. In this manner, HDP can be produced from an ICP source (ie, HDP-CVD process).

[0032]

[0042] SiO using HDP-CVD x It has been found that the deposition of a GI layer 206 containing InGaZnO results in an unexpected increase in the mobility of the underlying metal oxide layer 204. The mobility of the metal oxide layer 204 (e.g., InGaZnO4) is 15 cm 2 / Vs less than approx. 150cm 2 / Vs, for example, up to about 450 cm 2 / Vs, or even higher. Furthermore, the mobility at saturation of the metal oxide layer 204 can be approximately 3000 cm 2 / Vs. The same metal oxide layer 204 may have a SiO x When using a CCP-based CVD process to deposit the GI layer 206, there is no such increase in mobility or mobility at saturation. It is believed that the deposition of the GI layer 206 using HDP-CVD induces a chemical transformation of the underlying metal oxide layer 204, resulting in higher mobility. The interface between the metal oxide layer 204 and the GI layer 206 may have an increased carrier density and higher mobility in the metal oxide layer. For a metal oxide layer 204 containing indium (In), the diffusion of In atoms from the metal oxide layer to the GI layer 206 may increase carrier generation and therefore higher mobility. Furthermore, structural changes may occur in the metal oxide layer 204, such as healing atomic defects by atomic diffusion, leading to further higher mobility.

[0033]

[0043] In step 350, the gate electrode 208 is formed, as shown in FIG. 2D. In some embodiments, the gate electrode 208 is formed on the GI layer 206. The gate electrode 208 can be any conductive material including molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), metal alloys including MoW, combinations of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, conductive metal oxides such as indium tin oxide (InSnO) (ITO) and indium zinc oxide (InZnO) (IZO), or any combination thereof. In some embodiments, the gate electrode 208 is deposited in a single step. In other embodiments, the material of the gate electrode 208 is deposited in a first substep to form a metal layer, and one or more remaining portions of the metal layer are etched to create the gate electrode 208. The gate electrode 208 is configured to be connected to a gate line signal as a power supply (not shown) to provide a voltage across the layers of the TFT 200 .

[0034]

[0044] In step 360, as shown in FIG. 2E, one or more remaining portions 206 of the GI layer 206 (FIG. 2D) are * is etched. In some embodiments, the gate electrode 208 acts as a mask to etch the GI layer 206 to a desired size and shape. In some embodiments, the wet etch rate (WER) of the GI layer 206 is about 200 Å / min to about 7000 Å / min. Step 360 may include a dry etch.

[0035]

[0045] At step 370, an interlayer dielectric (ILD) layer 210 is formed, as shown in FIG. 2F. In some embodiments, the ILD layer 210 is formed over the gate electrode 208 and the metal oxide layer 204. The ILD layer 210 may be a single layer of silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO yThe ILD layer 210 may include an insulating material such as silicon oxynitride (SiON), other insulating materials, or a combination thereof. In some embodiments, the ILD layer 210 is deposited using the same process parameters as step 330. The ILD layer 210 may be planarized, such as by chemical mechanical polishing (CMP). The ILD layer 210 may be deposited using a CVD process using HDP-CVD or CCP.

[0036]

[0046] Sequence 380 results in the formation of source electrode 212, drain electrode 214, source electrode via 216, and drain electrode via 218 in ILD layer 210, as shown in FIG. 2G. Sequence 380 may include any conventional method of forming gate and drain electrode structures used in the art. In some embodiments, in a first step, a portion of ILD layer 210 is etched to expose a portion of metal oxide layer 204. In a second step, the portion of the ILD that exposes the portion of metal oxide layer 204 is filled with a conductive material to form source electrode 212, drain electrode 214, source electrode via 216, and drain electrode via 218. The conductive material may include any combination of conductive materials including Mo, Cr, Cu, Ti, Ta, W, alloy metals including MoW, combinations of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, conductive metal oxides such as ITO or IZO, or any combination thereof.

[0037]

[0047] In step 390, the passivation layer 220 is formed, as shown in FIG. 2H. In some embodiments, the passivation layer 220 is formed over the ILD layer 210, the source electrode 212, and the drain electrode 214. The passivation layer 220 may include any material used for the ILD layer 210 or the buffer layer 202. The passivation layer 220 may be deposited using a CVD process using HDP-CVD or CCP. In some embodiments, the passivation layer 220 is deposited using the same process parameters as step 330. The passivation layer 220 may be planarized, such as by chemical mechanical polishing (CMP).

[0038]

[0048] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and below the metal oxide layer 204. The buffer layer may be silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0039]

[0049] In some embodiments, the TFT 200 further includes a secondary buffer layer (not shown) disposed over the buffer layer and below the metal oxide layer 204. A shield metal (not shown) is disposed over the buffer layer, in the secondary buffer layer, and below the metal oxide layer 204. The secondary buffer layer may include any of the buffer layer materials described above. The shield metal may include any of the gate electrode 208 materials described above. The shield metal reduces exposure of the TFT 200 to unwanted electromagnetic waves.

[0040]

[0050] 4A-4J are cross-sectional views of two transistor structures 400 according to one embodiment. FIG. 5 is a flow diagram of a method 500 of forming two transistor structures 400 according to the same embodiment. For ease of explanation, FIGS. 4A-4J, 5, 6, and 7 are described with reference to chamber 100 of FIG. 1. However, it should be noted that ICP-CVD chambers other than chamber 100 may be utilized with method 500. Method 500 may be stored or accessible to controller 190 as a computer-readable medium that includes instructions that, when executed by CPU 191, cause chamber 100 to perform method 500.

[0041]

[0051] As shown, the two transistor structure 400 includes a substrate 102 (FIG. 4A).

[0042]

[0052] 4B, the method 500 begins with step 510 where a first metal oxide layer 204A is formed. In some embodiments, the first metal oxide layer 204A is formed over a first portion 491 of the substrate 102 (or over the buffer layer 202, if present). Step 510 may be performed similarly to step 310.

[0043]

[0053] In step 540, the GI layer 206 (alternatively referred to as the interfacial GI layer) is deposited, as shown in FIG. 4C. The GI layer is deposited on at least a portion of the first metal oxide layer 204A. The GI layer 206 is in direct contact with the metal oxide layer 204A. Step 540 may be performed similarly to step 340.

[0044]

[0054] In step 550, a second metal oxide layer 204B is formed, as shown in Figure 4D. In some embodiments, the second metal oxide layer 204B is formed on the second portion 492 of the substrate 102 over the GI layer 206. Step 550 may be performed similarly to step 510.

[0045]

[0055] In step 555, a secondary GI layer (alternatively referred to as a bulk layer) 406 is deposited, as shown in FIG. 4E. The secondary GI layer 406 is deposited on the GI layer 206 and the second metal oxide layer 204B. The secondary GI layer 406 is in direct contact with the second metal oxide layer 204B. The secondary GI layer 406 may include any material included in the GI layer 206. The deposition of the secondary GI layer includes a CVD process using CCP. Step 555 may be performed similarly to step 340.

[0046]

[0056] In step 560, a first gate electrode 208A and a second gate electrode 208B are formed, as shown in Figure 4F. In some embodiments, the first and second gate electrodes 208A, 208B are formed on the secondary GI layer 406. The first gate electrode 208A is formed on the first metal oxide layer 204A and the second gate electrode 208B is formed on the second metal oxide layer 204B. Step 560 can be performed similarly to step 350.

[0047]

[0057] In step 570, one or more remaining portions 206 of the GI layer 206 are removed, as shown in FIG. 4G. * and one or more remaining portions 406 of the secondary GI layer 406 (FIG. 4F). * is etched. In some embodiments, the first gate electrode 208A and the second gate electrode 208B act as a mask to etch the GI layer 206 to a desired size and shape to form the first GI layer portion (alternatively referred to as interfacial GI layer) 206A, the first secondary GI portion (alternatively referred to as bulk GI layer) 406A, the lower layer 206B, and the GI layer 406B. Similarly, in some embodiments, the first gate electrode 208A and the second gate electrode 208B act as a mask to etch the secondary GI layer 406 to a desired size and shape to form the first GI layer portion 206A, the first secondary GI portion 406A, the lower layer 206B, and the GI layer 406B. Forming the lower layer 206B and the first GI layer portion 206A in a single step 570 reduces the total number of masking and etching steps. Additionally, reduced masking and etching steps increase throughput and reduce operator cost of ownership (CoO). Step 570 also reduces the size of the two transistor structures 400, and therefore reduces the space required for a display to contain the two transistor structures 400. Step 570 can be performed similarly to step 360.

[0048]

[0058] In step 580, an ILD layer 210 is formed, as shown in Figure 4H. In some embodiments, the ILD layer is formed over the first and second gate electrodes 208A, 208B. Step 580 can be performed similarly to step 370.

[0049]

[0059] The sequence 590 results in the formation of a first source electrode 212A, a second source electrode 212B, a first drain electrode 214A, a second drain electrode 214B, a first source electrode via 216A, a second source electrode via 216B, a first drain electrode via 218A, and a second drain electrode via 218B in the ILD layer 210, as shown in FIG. 4I. The sequence 590 may include any conventional method of forming gate and drain electrode structures used in the art. In some embodiments, a portion of the ILD layer 210 is etched in a first step such that a portion of the first metal oxide layer 204A is exposed and a portion of the second metal oxide layer 204B is exposed. In a second step, the portions of the ILD exposing the first metal oxide layer 204A are filled with a conductive material to form source electrodes 212A, 212B, drain electrodes 214A, 214B, source electrode vias 216A, 216B, and drain electrode vias 218A, 218B. Sequence 590 may be performed similarly to sequence 380.

[0050]

[0060] In step 595, the passivation layer 220 is formed, as shown in FIG. 4J. In some embodiments, the passivation layer 220 is formed over the ILD layer 210, the source electrodes 212A, 212B, and the drain electrodes 214A, 214B. Step 595 may be performed similarly to step 390. Thus, two TFTs 401A, 401B are formed in the two transistor structures 400. The two TFTs 401A, 401B may be connected in series or in parallel. The two TFTs 401A, 401B may receive the same input voltage signal, or may receive different voltage signals.

[0051]

[0061] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A. The buffer layer may be silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0052]

[0062] In some embodiments, the two transistor structure 400 further includes a secondary buffer layer (not shown) disposed over the buffer layer and beneath the metal oxide layer 204A and the lower layer 206B. One or more shield metals (not shown) are disposed over the buffer layer, within the secondary buffer layer, and beneath one or both of the metal oxide layers 204A, 204B.

[0053]

[0063] 6 illustrates one embodiment of a two transistor structure 600. The method 500 can also be used to form the two transistor structure 600, as described in more detail below.

[0054]

[0064] As shown, the two transistor structure 600 includes a first TFT 601A and a second TFT 601B. The first TFT 601A can be similar to the first TFT 401A (FIG. 4J). However, because the first TFT 601A does not include a secondary GI layer, step 555 can be omitted.

[0055]

[0065] The second TFT 601B can be similar to the second TFT 401B (FIG. 4J), except that the second metal oxide layer 204B is disposed over the ILD layer 210, and therefore step 550 is performed after step 560. Also, the second source electrode 212B and the second drain electrode 214B are in direct contact with the second metal oxide layer 204B, and no source or drain electrode vias are included.

[0056]

[0066] In some embodiments, the two transistor structure 600 further includes a secondary buffer layer (not shown) disposed over the buffer layer. One or more shield metals (not shown) are disposed over the buffer layer, in the secondary buffer layer, and under one or both of the metal oxide layers 204A, 204B.

[0057]

[0067] The two TFTs 601A, 601B may be connected in series or in parallel. The two TFTs 601A, 601B may receive the same input voltage signal or different voltage signals.

[0058]

[0068] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A. The buffer layer may be silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0059]

[0069] 7 illustrates one embodiment of a two transistor structure 700. The method 500 can also be used to form the two transistor structure 700, as described in more detail below.

[0060]

[0070] As shown, the two transistor structure 700 includes a first TFT 701A and a second TFT 701B. The first TFT 701A is similar to the first TFT 401A (FIG. 4J). However, the first TFT 701A does not include a secondary GI layer, so step 555 can be omitted. The two transistor structure 700 also includes an etch stop layer (ESL) 710 disposed above the ILD layer 210 and below the passivation layer 220. The ESL 710 can be formed in a step following step 550. The formation of the ESL 710 can be performed similarly to step 370. The ESL 710 can include any material included in the ILD layer 210. The first source electrode 212A and the first drain electrode 214A are disposed on the ESL 710. Disposed within the ESL 710 and the ILD layer 210 are a first source electrode via 216A and a first drain electrode via 218A.

[0061]

[0071] The second TFT 701B is similar to the second TFT 401B (FIG. 4J), except that a second metal oxide layer 204B is disposed over the ESL 710, and therefore step 550 is performed after step 560. A second source electrode 212B and a second drain electrode 214B are disposed over the ESL 710. A second source electrode via 216B and a second drain electrode via 218B are disposed within the ESL 710.

[0062]

[0072] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A. The buffer layer may be silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0063]

[0073] In some embodiments, the two transistor structure 700 further includes a secondary buffer layer (not shown) disposed over the buffer layer. One or more shield metals (not shown) are disposed over the buffer layer, in the secondary buffer layer, and under one or both of the second metal oxide layers 204A, 204B.

[0064]

[0074] The two TFTs 701A, 701B may be connected in series or in parallel. The two TFTs 701A, 701B may receive the same input voltage signal or different voltage signals.

[0065]

[0075] 8 illustrates one embodiment of a two transistor structure 800. The method 300 can also be used to form the two transistor structure 800, as described in more detail below.

[0066]

[0076] As shown, the two transistor structure 800 includes a first TFT 801A and a second TFT 801B. The first TFT 801A may be similar to TFT 200 (FIG. 2H). The second TFT 801B may be similar to TFT 200 (FIG. 2H) except that it does not include a GI layer and a gate electrode. The two transistor structure 800 may be formed using the method 300, where step 310 further includes depositing a second metal oxide layer 204B.

[0067]

[0077] In some embodiments, a buffer layer (not shown) is disposed over the substrate 102 and under the metal oxide layer 204A. The buffer layer may be silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof.

[0068]

[0078] The two transistor structure 800 further includes a buffer layer 202 disposed on the substrate 102. The buffer layer 202 is made of silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y 2B, the buffer layer 202 may include an insulating material such as silicon oxynitride (SiON), other insulating materials, or a combination thereof. A secondary buffer layer 203 is disposed over the buffer layer 202. The secondary buffer layer 203 may include any of the materials included in the buffer layer 202. A shield metal 808B is disposed over the buffer layer 202, within the secondary buffer layer 203, and below the metal oxide layer 204B. The shield metal 908B is configured to be connected to a gate line signal as a power supply (not shown) for providing a voltage across the layers of the TFT 801B.

[0069]

[0079] In some embodiments, the two transistor structure 800 further includes an additional shielding metal disposed above the buffer layer 202, within the secondary buffer layer 203, and below the first metal oxide layer 204A.

[0070]

[0080] The two TFTs 801A, 801B may be connected in series or in parallel, and may receive the same input voltage signal or different voltage signals.

[0071]

[0081] 9A-9N are schematic cross-sectional views of two transistor structures 900 according to one embodiment. FIG. 10 is a flow diagram of a method 1000 of forming two transistor structures 900 according to the same embodiment. The method steps are described in conjunction with FIGS. 1, 9A-9N, and 10, however, one skilled in the art will appreciate that any system configured to perform the steps of method 1000 in any order falls within the scope of the embodiments described herein. For ease of explanation, FIGS. 9A-9N and 10 are described with reference to chamber 100 of FIG. 1. However, it should be noted that ICP-CVD chambers other than chamber 100 can be utilized in conjunction with method 1000. Method 1000 may be stored or accessible to controller 190 as a computer-readable medium that includes instructions that, when executed by CPU 191, cause chamber 100 to perform method 1000.

[0072]

[0082] As shown, the two transistor structure 900 includes a substrate 102 (FIG. 9A).

[0073]

[0083] 9B, the method 1000 begins at step 1005 where a polysilicon layer 904A is deposited. In some embodiments, the polysilicon layer 904A is deposited over the substrate 102 (or over the buffer layer 202, if present). The polysilicon layer 904A may be deposited using any desired method. Step 1005 includes doping the polysilicon layer 904A with an n-type or p-type dopant (e.g., B or N), such as by ion implantation.

[0074]

[0084] In step 1010, a first GI layer 206 is deposited, as shown in FIG. 9C. In some embodiments, the first GI layer is deposited on at least a portion of the polysilicon layer 904A. Step 1010 may be performed similarly to step 340.

[0075]

[0085] In step 1020, the first gate electrode 208A and the shield metal 908B are formed, as shown in FIG. 9D. In some embodiments, the first gate electrode 208A and the shield metal 908B are formed on the first GI layer 206. The first gate electrode 208A is formed on the polysilicon layer 904A. In some embodiments, a metal layer is deposited in a first substep, and one or more remaining portions of the metal layer are removed to form the first gate electrode 208A and the shield metal 908B in a second substep. Step 1020 may be performed similarly to step 350.

[0076]

[0086] In step 1025, a secondary ILD layer 910 is formed, as shown in Figure 9E. In some embodiments, the secondary ILD layer 910 is formed over the first gate electrode 208A and the shield metal 908B. The secondary ILD layer 910 includes any of the materials of the ILD layer 210. Step 1025 may be performed similarly to step 370.

[0077]

[0087] The sequence 1030 results in the formation of a secondary source electrode 912A, a secondary drain electrode 914A, a secondary source electrode via 916A, and a secondary drain electrode via 918A in the secondary ILD layer 910, as shown in FIG. 9F. The sequence 1030 may include any conventional method of forming gate and drain electrode structures used in the art. In some embodiments, a portion of the secondary ILD layer 910 is etched in a first step to expose a portion of the polysilicon layer 904A. The portion of the secondary ILD layer 910 is filled with a conductive material in a second step to form the secondary source electrode 912A, the secondary drain electrode 914A, the secondary source electrode via 916A, and the secondary drain electrode via 918A. The secondary source electrode 912A, the secondary drain electrode 914A, the secondary source electrode via 916A, and the secondary drain electrode via 918A include any of the materials included in the first source electrode 212A, the first drain electrode 214A, the first source electrode via 216A, and the first drain electrode via 218A. The sequence 1030 may be performed similarly to the sequence 380.

[0078]

[0088] In step 1035, a secondary buffer layer 203 is formed, as shown in Figure 9G. In some embodiments, the secondary buffer layer 203 is deposited over the secondary source electrode 912A, the secondary drain electrode 914A, the secondary source electrode via 916A, and the secondary drain electrode via 918A. The secondary buffer layer 203 can be deposited using a CVD process using HDP-CVD or CCP.

[0079]

[0089] In step 1040, a second metal oxide layer 204B is formed, as shown in Figure 9H. In some embodiments, the second metal oxide layer 204B is formed on the secondary buffer layer 203. Step 1040 can be performed similarly to step 510.

[0080]

[0090] In step 1050, the secondary GI layer 406 is deposited, as shown in FIG. 9I. The secondary GI layer 406 is deposited on the second metal oxide layer 204B. The secondary GI layer 406 is in direct contact with the second metal oxide layer 204B. Step 1050 may be performed similarly to step 555.

[0081]

[0091] In step 1060, the second gate electrode 208B is formed, as shown in FIG. 9J. In some embodiments, the second gate electrode 208B is formed on the secondary GI layer 406. The second gate electrode 208B is formed on the second metal oxide layer 204B. Step 1060 can be performed similarly to step 350.

[0082]

[0092] In step 1065, as shown in FIG. 9K, one or more remaining portions 406 of the secondary GI layer 406 (FIG. 9J) are * is etched. In some embodiments, the second gate electrode 208B acts as a mask to etch the secondary GI layer 406 to a desired size and shape. Step 1065 can be performed similarly to step 360.

[0083]

[0093] In step 1070, an ILD layer 210 is formed, as shown in Figure 9L. In some embodiments, the ILD layer 210 is formed over the second gate electrode 208B and the metal oxide layer 206B. Step 1070 may be performed similarly to step 370.

[0084]

[0094] Sequence 1075 results in the formation of source electrodes 212A, 212B, drain electrodes 214A, 214B, source electrode vias 216A, 216B, and drain electrode vias 218A, 218B in ILD layer 210, as shown in FIG. 9M. Sequence 1075 may include any conventional method of forming gate and drain electrode structures used in the art. First source electrode via 216A and first drain electrode via 218A electrically contact secondary source electrode 912A and secondary drain electrode 914A, respectively. Sequence 1075 may be performed similarly to sequence 380.

[0085]

[0095] In step 1080, a passivation layer 220 is formed, as shown in Figure 9N. In some embodiments, the passivation layer 220 is deposited over the ILD layer 210, the source electrodes 212A, 212B, and the drain electrodes 214A, 214B. Step 1080 may be performed similarly to step 390. Thus, a first TFT (alternatively referred to as a polysilicon TFT) 901A and a second TFT (alternatively referred to as a metal oxide (MOx) TFT) 901B are formed in the two transistor structure 400.

[0086]

[0096] In some embodiments, shield metal 908B is formed over secondary ILD layer 910. In these embodiments, step 1020 is separated into two substeps, with the substep in which shield metal 908B is formed being performed after step 1025.

[0087]

[0097] In some embodiments, sequence 1030 is not performed, and thus the secondary source electrode, secondary source electrode via, secondary drain electrode, and secondary drain electrode via are not formed. In these embodiments, the first source electrode via 216A and the first drain electrode via 218A are further disposed in the secondary ILD layer 910 and the secondary buffer layer 203. Thus, the first source electrode via 216A and the first drain electrode via 218A are in direct electrical contact with the polysilicon layer 904A.

[0088]

[0098] In some embodiments, the polysilicon layer 904 is P-type doped (eg, with B) and the metal oxide layer 204B is N-type doped (eg, with N).

[0089]

[0099] The two TFTs 901A, 901B may be connected in series or in parallel, and may receive the same input voltage signal or different voltage signals.

[0090]

[0100] 11 illustrates one embodiment of a two transistor structure 1100. The method 300 can also be used to form the two transistor structure 1100, as described in more detail below.

[0091]

[0101] As shown, the two transistor structure 1100 includes a first TFT 1101A and a second TFT 1101B. The first TFT 1101A may be similar to TFT 200 (FIG. 2I). However, instead of the first metal layer, a polysilicon layer 904A is included. Thus, step 310 forms only a second metal oxide layer 904B. Step 1005 is also included. The second TFT 1101B is similar to TFT 200 (FIG. 2I). The two transistor structure 1100 further includes a buffer layer 202 disposed over the substrate 102 and below the ILD layer 210. The two transistor structure 1100 further includes a shield metal 908B. The shield metal 908B is disposed over the substrate 102, in the buffer layer 202, and below the metal oxide layer 904B. The GI layer 206A does not increase the mobility of the polysilicon layer 904A that is below the GI layer 206A.

[0092]

[0102] In some embodiments, the GI layer 206 is etched in step 360 such that there is a GI layer both over the entire surface 904S of the polysilicon layer 904A and over the metal oxide layer 204B.

[0093]

[0103] In some embodiments, the GI layer 206 is not etched, and therefore the GI layer 206 is disposed as one layer over both the polysilicon layer 904A and the metal oxide layer 204B.

[0094]

[0104] The two TFTs 1101A, 1101B may be connected in series or in parallel, and may receive the same input voltage signal or different voltage signals.

[0095]

[0105] The two TFTs in each of the two transistor structures described above (e.g., the two transistor structures 400, 600, 700, 800, 900, 1100) are used as gate drivers in a liquid crystal display (LCD) or organic light emitting diode (OLED) display pixel circuit or panel (GIP) circuit. For example, each TFT in the two transistor structures can be used as a switching TFT or a driving TFT in an OLED pixel circuit. Each of the two transistor structures includes a TFT having a first TFT (e.g., TFT 401A, 601A, 701A, 801A, 901B, 1101B) having a higher mobility than the second TFT (e.g., TFT 401B, 601B, 701B, 801B, 901A, 1101A). The first TFT has a higher mobility than the second TFT because in the first TFT, a GI layer is deposited over the metal oxide layer, the GI layer being deposited by HDP-CVD. The GI layer in direct contact with the metal oxide layer, the HDP-CVD deposited GI layer, increases the mobility of the underlying metal oxide layer, as described in detail above in the description of method 300. According to one embodiment, the first TFT has a mobility greater than about 30 cm2 / Vs and the second TFT has a mobility less than about 30 cm2 / Vs.

[0096]

[0106] In any of the methods 300, 500, 1000 described above, one or more optional steps may be included. Optionally, any of the disclosed metal oxide layers may be pretreated. Pretreatment may involve the addition of a gas containing nitrous oxide (NO) at about 0.40 sccm / cm. 2 to about 0.60sccm / cm 2 At a flow rate of 0 sccm / cm, gas containing argon gas (Ar) was used. 2 (i.e., no parallel flow of Ar) to about 0.60 sccm / cm 2 at a chamber pressure of about 1 mTorr to about 300 mTorr, at a temperature of about 25° C. to about 400° C., for about 1 second to about 600 seconds. In one example, the pretreatment includes flowing a gas comprising nitrous oxide (NO) at a flow rate of about 0.40 sccm / cm 2 to about 0.60sccm / cm 2The flow rate of the gas containing argon gas (Ar) was about 0 sccm / cm 2 (i.e., no parallel flow of Ar) to about 0.60 sccm / cm 2 at a flow rate of about 10 mTorr to about 150 mTorr, at a chamber pressure of about 50° C. to about 300° C., for about 1 second to about 45 seconds. In some embodiments, nitrogen dioxide (NO2), neon gas (Ne), helium gas (He), or a mixture of the above may also be flowed in parallel. The pretreatment may increase the mobility of the pretreated metal oxide layer. The pretreatment may be performed in a static chamber or may be performed with a source in a dynamic chamber, such as chamber 100 described above.

[0097]

[0107] Optionally, a seed layer may be deposited on any of the metal oxide layers disclosed herein. The seed layer is deposited on at least a portion of the metal oxide layer. The seed layer improves adhesion of a layer (e.g., a GI layer) deposited thereon. The seed layer may have a thickness of about 1 nm to about 100 nm. The deposition of the seed layer may include a CVD process using CCP. For example, the deposition of the seed layer may include a CVD process using CCP, and then a GI layer is deposited on the interfacial seed layer, and the GI layer is deposited by a HDP-CVD process. Due to the thinness of the seed layer, the metal oxide layer below the seed layer is still subject to the HDP-CVD process, advantageously increasing the mobility of the metal oxide layer. In any of the above embodiments, removal of one or more remaining portions of the seed GI layer may also be performed.

[0098]

[0108] The metal oxide layer formation, optional metal oxide layer pretreatment, optional seed layer deposition, and GI layer deposition (collectively hereinafter the MO / GI steps) can be performed in a single chamber (e.g., chamber 100) without a vacuum break. In another embodiment, the MO / GI steps can be performed in an integrated system having multiple chambers without a vacuum break, and each MO / GI step can be performed in any of the chambers. Alternatively, any of the MO / GI steps can be performed in any number of chambers, and a vacuum break can be included between the MO / GI steps.

[0099]

[0109] In one example, the formation of the metal oxide layer is performed in a first chamber, the substrate is transferred under vacuum to a second chamber, and the GI layer is deposited in the second chamber. In another example, the formation of the metal oxide layer is performed in a first chamber, the substrate is transferred under vacuum to a second chamber, and the GI layer is deposited in the second chamber.

[0100]

[0110] As mentioned above, a method for forming a TFT and a method for forming a two transistor structure are provided, the method includes depositing one or more metal oxide layers and / or polysilicon layers, and a GI layer is deposited on the one or more metal oxide layers using a HDP-CVD process.

[0101]

[0111] The deposition of the GI layer using HDP-CVD results in unexpectedly high mobility for the metal oxide and / or polysilicon layers deposited thereon. By selectively placing the GI layer, the mobility of the underlying layer is controlled depending on whether the GI layer is deposited by HDP-CVD or by a CVD process using CCP. The deposition of the GI layer allows for control of the mobility of the underlying layer after the layer deposition, i.e., mobility can be enhanced after deposition in addition to during deposition.

[0102]

[0112] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, as determined by the following claims.

Claims

1. 1. A method of forming a thin film transistor, comprising: forming a metal oxide layer over a first portion of a substrate; depositing a seed layer on the metal oxide layer, the depositing of the seed layer comprising a CVD process using CCP, the seed layer having a thickness of less than 100 nm; depositing a gate insulator (GI) layer on the seed layer, where forming the GI layer comprises depositing a silicon-containing layer with an inductively coupled plasma (ICP) high density plasma chemical vapor deposition (HDP-CVD) process, the HDP-CVD process comprising: 2.3 W / cm ２ ~5.3 W / cm ２ and the ICP power density of An ICP frequency of 2 MHz to 13.56 MHz; depositing a gate insulator (GI) layer on the seed layer, the gate insulator (GI) layer having forming a gate electrode on the GI layer; Etching one or more remaining portions of the GI layer. The method includes:

2. 10. The method of claim 1, further comprising pretreating the metal oxide layer prior to depositing the GI layer, wherein pretreating the metal oxide layer comprises exposing the metal oxide layer to a pretreatment ICP.

3. The pretreatment ICP is nitrous oxide (N ２ 3. The method of claim 2, wherein the gas is formed from nitrogen (N), argon (Ar), or a combination thereof.

4. 10. The method of claim 1, further comprising depositing a bulk GI layer over the GI layer, wherein depositing the bulk GI layer comprises a chemical vapor deposition (CVD) process using a capacitively coupled plasma (CCP).

5. The method of claim 1 , wherein depositing the GI layer comprises heating the substrate to a temperature between 70° C. and 350° C.

6. forming an interlevel dielectric (ILD) layer over the gate electrode; forming a source electrode, a source electrode via, a drain electrode, and a drain electrode via in the ILD layer; forming a passivation layer over the source electrode, the drain electrode, and the ILD layer; The method of claim 1 further comprising:

7. forming a polysilicon layer or an additional metal oxide layer on a second portion of the substrate; The method of claim 1 further comprising:

8. 1. A method of forming a thin film transistor device, comprising: forming a first metal oxide layer on a first portion of a substrate, the first portion of the substrate corresponding to a first thin film transistor (TFT); depositing a seed layer on the first metal oxide layer, the depositing of the seed layer comprising a CVD process using CCP, the seed layer having a thickness of less than 100 nm; depositing an interfacial gate insulator (GI) layer of the first TFT over the first portion of the substrate in contact with the seed layer; forming an underlayer on a second portion of the substrate, the second portion of the substrate corresponding to a second TFT, the underlayer contacting a bottom surface of a second metal oxide layer of the second TFT, and forming the interfacial GI layer and the underlayer; depositing a first silicon-containing layer over the first portion and the second portion, the first silicon-containing layer being deposited with an inductively coupled plasma (ICP) high density plasma chemical vapor deposition (HDP-CVD) process, the HDP-CVD process comprising: 5.3 W / cm ２ and the ICP power density of An ICP frequency of 2 MHz to 13.56 MHz; forming an underlayer over the second portion of the substrate, comprising depositing a first silicon-containing layer over the first portion and the second portion, the first silicon-containing layer having forming the second metal oxide layer of the second TFT such that the bottom surface is in contact with the lower layer; depositing a bulk GI layer of the first TFT in contact with the interfacial GI layer and in contact with a top surface of the second metal oxide layer to form a GI layer of the second TFT, wherein forming the bulk GI layer and the GI layer comprises depositing a second silicon-containing layer on the first portion and the second portion by a chemical vapor deposition process (CVD) using a capacitively coupled plasma (CCP); forming a first gate electrode of the first TFT on the first portion and a second gate electrode of the second TFT on the second portion; removing one or more remaining portions of the second silicon-containing layer from the first portion and the second portion to form the interfacial GI layer of the first TFT, the bulk GI layer of the first TFT, the GI layer of the second TFT, and the lower layer of the second TFT; forming a layer of interlayer dielectric (ILD) over the substrate; The method includes:

9. The method of claim 8 , wherein depositing the interfacial GI layer and forming the underlayer are included in the same process.

10. 9. The method of claim 8, comprising molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), or alloys thereof.

11. The bulk GI layer is made of silicon oxide (Si ｘ O ｙ 9. The method of claim 8, wherein the first metal oxide layer comprises In-Ga-Zn-O.

12. The method of claim 8 , wherein the bulk GI layer has a higher atomic concentration of indium (In) atoms than the interfacial GI layer.

13. 1. A method of forming a thin film transistor device, comprising: forming a polysilicon layer over a first portion of a substrate, the first portion of the substrate corresponding to a polysilicon thin film transistor (TFT); depositing a first gate insulator (GI) layer over the polysilicon layer of the first portion of the substrate and over a second portion of the substrate, the second portion of the substrate corresponding to a metal oxide (MOx) TFT; forming a first gate electrode on the first GI layer of the polysilicon TFT and forming a shield metal of the MOx TFT; forming a first interlayer dielectric (ILD) layer over the first GI layer, the first gate electrode, and the shield metal; forming a metal oxide layer of the MOx TFT on the first ILD layer of the second portion of the substrate; depositing a seed layer on the metal oxide layer, the depositing of the seed layer comprising a CVD process using CCP, the seed layer having a thickness of less than 100 nm; forming a second GI layer on the seed layer, where forming the second GI layer comprises depositing a silicon-containing layer with an inductively coupled plasma (ICP) high density plasma chemical vapor deposition (HDP-CVD) process, the HDP-CVD process comprising: 2.3 W / cm ２ ~5.3 W / cm ２ and the ICP power density of An ICP frequency of 2 MHz to 13.56 MHz; forming a second GI layer on the seed layer, the second GI layer having forming a second gate electrode on the second GI layer; forming a second ILD layer over the first ILD layer, the metal oxide layer, and the second gate electrode; The method includes:

14. The method of claim 13 , wherein the shield metal comprises molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), or alloys thereof.

15. The method of claim 13, wherein forming the first ILD layer comprises a HDP-CVD process.

16. The method of claim 13 further comprising forming a passivation layer over the second ILD layer.

17. The method of claim 13 further comprising forming a buffer layer over the first ILD layer.

18. The MOxTFT is 30 cm ２ The method of claim 13 , wherein the MOS transistor has a mobility greater than 1 V.

19. The method of claim 13 , wherein depositing the first GI layer comprises the HDP-CVD process.

Images