Memory peripheral circuit having three-dimensional transistors and method for forming same

Abstract

In a particular embodiment, a three-dimensional (3D) memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including peripheral circuitry, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuitry includes 3D transistors. The array of memory cells is coupled to the peripheral circuitry across the bonding interface.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority to International Application No. PCT / CN2021 / 093323, entitled "Memory Peripheral Circuit with Three-Dimensional Transistors and Method for Forming Same," filed May 12, 2021, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to memory devices and methods for manufacturing same. [Background technology]

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as memory cell feature sizes approach lower limits, planar processes and manufacturing techniques become difficult and expensive. As a result, the memory density of planar memory cells approaches an upper limit.

[0004] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. 3D memory architectures include a memory array and peripheral circuitry to facilitate operation of the memory array. Summary of the Invention

[0005] In one embodiment, a 3D memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including a peripheral circuit, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuit includes a 3D transistor. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

[0006] In another aspect, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including a peripheral circuit, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuit includes a 3D transistor. The array of memory cells is coupled to the peripheral circuit across the bonding interface. The system also includes a memory controller coupled to the memory device and configured to control the array of memory cells via the peripheral circuit.

[0007] In yet another aspect, a method for forming a 3D memory device is disclosed. A first semiconductor structure including an array of memory cells is formed on a first substrate. A second semiconductor structure including peripheral circuitry is formed on a second substrate. The peripheral circuitry includes 3D transistors. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the array of memory cells is coupled to the peripheral circuitry across a bond interface. [Brief description of the drawings]

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure. [Figure 1A] 1 illustrates a schematic diagram of a cross-section of a 3D memory device according to some embodiments of the present disclosure. [Figure 1B] 1 illustrates a schematic diagram of a cross section of another 3D memory device in accordance with some aspects of the present disclosure. [Diagram 2] 1 illustrates a schematic circuit diagram of a memory device including peripheral circuits in accordance with some aspects of the present disclosure. [Diagram 3] 1 illustrates a block diagram of a memory device including a memory cell array and peripheral circuits in accordance with some aspects of the disclosure. [Figure 4] FIG. 1 illustrates a perspective view of a planar transistor according to some aspects of the present disclosure. [Diagram 5] 1 illustrates a perspective view of a 3D transistor according to some embodiments of the present disclosure. [Figure 6A] 6 illustrates a cross-sectional side view of the 3D transistor of FIG. 5 in accordance with some embodiments of the present disclosure. [Figure 6B] 6 illustrates a cross-sectional side view of the 3D transistor of FIG. 5 in accordance with some embodiments of the present disclosure. [Figure 7A] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7B] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7C] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7D] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7E] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7F] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7G] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7H] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 7I] 1A-1D show cross-sectional side views of various 3D transistors according to various embodiments of the present disclosure. [Figure 8A] 1 illustrates a cross-sectional side view of a 3D memory device according to some embodiments of the present disclosure. [Figure 8B] 1 illustrates a cross-sectional side view of another 3D memory device in accordance with some aspects of the present disclosure. [Figure 8C] 1 illustrates a cross-sectional side view of yet another 3D memory device in accordance with some aspects of the present disclosure. [Figure 9] FIG. 1 illustrates a block diagram of peripheral circuitry that is provided with various voltages in accordance with some aspects of the present disclosure. [Figure 10] 1 illustrates a block diagram of a memory device including input / output (I / O) circuitry in accordance with some aspects of the disclosure. [Figure 11A] 11 illustrates a perspective view of a 3D transistor in the I / O circuit of FIG. 10 in accordance with some aspects of the present disclosure. [Figure 11B] 11 illustrates a side view of a 3D transistor in the I / O circuit of FIG. 10 in accordance with some aspects of the present disclosure. [Figure 12A] 1 shows a perspective view of a planar transistor. [Figure 12B] 1 shows a side view of a planar transistor. [Figure 13] 1 illustrates a block diagram of a memory device including a word line driver and a page buffer in accordance with some aspects of the disclosure. [Figure 14] 14 shows a schematic circuit diagram of the word line driver and page buffer of FIG. 13 in accordance with some aspects of the present disclosure. [Figure 15] 1 illustrates a schematic floor plan view of a memory device having multiple planes and a page buffer in accordance with some aspects of the present disclosure. [Figure 16] 1 illustrates a schematic plan view of a memory device having an array of memory cells and peripheral circuits including page buffers and word line drivers in accordance with some aspects of the present disclosure. [Figure 17] 1 shows a design layout of planar transistors in a word line driver or page buffer. [Figure 18] 14 illustrates a design layout of 3D transistors in the word line driver or page buffer of FIG. 13 in accordance with some aspects of the present disclosure. [Figure 19] 1 is a cross-sectional side view of a 3D memory device including string drivers having 3D transistors in accordance with some aspects of the disclosure. [Figure 20A] 14 illustrates a perspective view of a 3D transistor in the page buffer of FIG. 13 in accordance with some aspects of the present disclosure. [Figure 20B] 14 illustrates a side view of a 3D transistor in the page buffer of FIG. 13 in accordance with some aspects of the present disclosure. [Figure 21A] 14 illustrates a perspective view of a 3D transistor in the word line driver of FIG. 13 in accordance with some aspects of the present disclosure. [Figure 21B]14 illustrates a side view of a 3D transistor in the word line driver of FIG. 13 in accordance with some aspects of the present disclosure. [Figure 22A] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22B] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22C] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22D] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22E] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22F] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22G] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Fig. 22H] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22I] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 22J] 1 illustrates a manufacturing process for forming a 3D transistor according to some embodiments of the present disclosure. [Figure 23] 1 illustrates a flowchart of a method for forming an exemplary 3D memory device in accordance with some aspects of the present disclosure. [Figure 24A] 1 illustrates a flowchart of a method for forming a 3D transistor according to some aspects of the present disclosure. [Figure 24B] 13 shows a flowchart of another method for forming a 3D transistor according to some aspects of the present disclosure. [Diagram 25] FIG. 1 illustrates a block diagram of an exemplary system having a memory device in accordance with some aspects of the present disclosure. [Figure 26A] 1 illustrates a diagram of an exemplary memory card having a memory device in accordance with some aspects of the disclosure. [Figure 26B] 1 illustrates an exemplary solid-state drive (SSD) having a memory device in accordance with some aspects of the present disclosure.

[0009] The present disclosure will now be described with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be applied to a variety of other applications. The functional and structural features described in this disclosure can be combined, coordinated, and modified with each other, and in ways not specifically shown in the drawings, such that these combinations, coordinations, and modifications are within the scope of the present disclosure.

[0011] Generally, terms may be understood, at least in part, from usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context. Furthermore, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly described, depending at least in part on the context.

[0012] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in the broadest possible manner, such that "on" not only means "directly on" something, but also includes the meaning "on" of something with intermediate features or layers between, and "above" or "over" not only means "above" or "over" something, but also can include the meaning "above" or "over" something without intermediate features or layers between (i.e., directly on top of something).

[0013] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0014] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added onto the substrate can be patterned or left unpatterned. Additionally, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0015] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer can be a uniform or non-uniform region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or between the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along tapered surfaces. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0016] Compared to logic devices such as microprocessors, the complementary metal-oxide semiconductor (CMOS) technology node used for peripheral circuits of memory devices such as NAND flash memory has the advantage that the memory peripheral circuits are low cost and have low leakage current (also known as off-state current I off) has not progressed much (e.g., 60 nm or more). With the development of 3D memory devices such as 3D NAND flash memory devices, more stacks (e.g., word lines) require more peripheral circuits to operate the 3D memory device, thereby requiring smaller unit sizes of peripheral circuits. For example, the number and / or size of page buffers needs to increase to match the increased number of memory cells. In some cases, the chip area occupied by the page buffers can be dominant in 3D NAND flash memories, for example, exceeding 50% of the total chip area. In another example, the number of string drivers in a word line driver is proportional to the number of word lines in a 3D NAND flash memory. Thus, the continuous increase in word lines also increases the area occupied by the word line drivers, as well as the complexity of the metal routing, sometimes even the number of metal layers. Furthermore, in some 3D memory devices where the memory cell array and the peripheral circuits are fabricated on different substrates and bonded together, the continuous increase in the peripheral circuit area, especially the page buffer area, becomes a bottleneck for reducing the overall chip size.

[0017] However, shrinking the peripheral circuit size according to the trend of advanced technology nodes used for logic devices will result in significant cost increase and higher leakage current, which is undesirable for memory devices. Furthermore, unlike logic devices, which can reduce their operating voltage as CMOS technology nodes advance, 3D NAND flash memory devices cannot reduce the voltage provided to the memory peripheral circuits because they require relatively high voltages (e.g., greater than 5V) for certain memory operations such as programming and erasing. As a result, it becomes unfeasible to shrink the size of the memory peripheral circuits according to the trend of evolving CMOS technology nodes, as in conventional logic devices.

[0018] On the other hand, there is an increasing demand for faster I / O speeds for 3D NAND flash memories, and the saturation drain current (I dsat, also known as on-current I on However, planar transistors commonly used in existing memory peripheral circuits such as I / O circuits suffer from high leakage currents as their saturation drain currents continue to increase, which is undesirable for memory devices.

[0019] In summary, the continuous advancement of memory devices such as 3D NAND flash memory simultaneously requires high speed, low leakage current, high voltage, and small size without increasing cost for increasingly challenging memory periphery circuits. Neither the all-planar transistor solutions used in existing memory periphery circuits nor the advanced CMOS technology node solutions used in logic devices can simultaneously meet the above requirements.

[0020] To address one or more of the aforementioned problems, the present disclosure introduces a solution to replace traditional planar transistors with 3D transistors (also known as non-planar transistors) in at least some of the memory peripheral circuits, such as I / O circuits, page buffers, and word line drivers. In some implementations, the fabrication process of the 3D transistors disclosed herein is compatible with planar transistors, so that the planar transistors and the 3D transistors are fabricated in the same process flow, achieving a hybrid configuration of the memory peripheral circuits having both 3D and planar transistors.

[0021] Compared with planar transistors, 3D transistors can have a larger gate control area to achieve better channel control with smaller subthreshold swing. During the off state, the channel is fully depleted, so the leakage current of 3D transistors can be greatly reduced. Therefore, memory peripheral circuits such as I / O circuits using 3D transistors instead of planar transistors can achieve much better speed (saturation drain current) / leakage current performance. For example, according to some studies done by the inventors with the same dimensions and the same leakage current, the saturation drain current of 3D transistors can be more than twice (e.g., three times) that of planar transistors.

[0022] In addition to the faster switching speed due to the larger saturation drain current, the size of the memory peripheral circuits can also be reduced by replacing planar transistors with 3D transistors. For example, some studies performed by the inventors have shown that the saturation drain current of 3D transistors can be more than twice (e.g., three times) the saturation drain current and leakage current of planar transistors of the same dimensions. Therefore, for certain memory peripheral circuits, such as page buffers and word line drivers, where size reduction is more desirable than speed increase, the size of the peripheral circuits can be reduced while maintaining the same leakage current and fixed drain current. Furthermore, some studies performed by the inventors have shown that a simple solution of reducing the transistor dimensions of planar transistors is not feasible, since the leakage current can be dramatically increased due to narrow channel effects, for example, when the gate width is less than 180 nm.

[0023] On the other hand, the 3D transistors disclosed herein can be fabricated using less advanced CMOS technology nodes (e.g., above 14 nm) compared to logic devices to meet the low leakage current, high voltage, and low cost requirements of memory peripheral circuits. For example, advanced CMOS technology nodes (e.g., below 22 nm) can reduce the transistor dimensions, but the voltage must be reduced (e.g., to 0.9 V) to avoid increasing leakage current. However, voltage reduction is not acceptable for memory peripheral circuits that need to operate at a specific voltage level during memory operations. Also, advanced CMOS technology nodes and related processes and structures such as stressors for strain control and high dielectric constant (high-k) / metal gate (HKMG) can increase the manufacturing complexity and reduce the manufacturing yield, thus increasing the cost, which may not be suitable for cost-sensitive memory peripheral circuits.

[0024] Consistent with the scope of the present disclosure, according to some aspects of the present disclosure, the peripheral circuits having 3D transistors and memory cell arrays can be formed on different wafers and bonded together in a face-to-face manner. Thus, the thermal budget of manufacturing the memory cell array does not affect the manufacturing of the peripheral circuits. For existing memory devices in which the peripheral circuits and the memory cell array are fabricated on the same wafer, the reduction in transistor dimensions is limited by the thermal budget of forming the memory cell array. In contrast, the present disclosure allows the dimensions of the transistors (e.g., 3D transistors) constituting the memory peripheral circuits to be reduced without being constrained by the thermal budget of the memory cell array. Furthermore, in some implementations, after bonding, certain peripheral circuits with reduced dimensions of the 3D transistors (e.g., string drivers of word line drivers) can be arranged to face the staircase structure of the memory cell array formed on another substrate, thereby simplifying metal routing.

[0025] FIG. 1A illustrates a schematic diagram of a cross section of a 3D memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 corresponds to an example of a bonded chip. Components of the 3D memory device 100 (e.g., a memory cell array and peripheral circuits) can be formed separately on different substrates and then bonded to form a bonded chip. The 3D memory device 100 can include a first semiconductor structure 102 including an array of memory cells (memory cell array). In some implementations, the memory cell array includes an array of NAND flash memory cells. For ease of explanation, a NAND flash memory cell array can be used as an example to explain the memory cell array in the present disclosure. However, it is understood that the memory cell array is not limited to a NAND flash memory cell array, and can include any other suitable type of memory cell array, such as a dynamic random access memory (DRAM) cell array, a static random access memory (SRAM) cell array, a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, or any combination thereof, to name a few.

[0026] The first semiconductor structure 102 can be a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into pages or fingers, which are then organized into blocks, in which each NAND memory cell is electrically connected to a separate line called a bit line (BL). All cells having the same vertical position in a NAND memory cell can be electrically connected through their control gates by a word line (WL). In some implementations, a plane includes a certain number of blocks that are electrically connected through the same bit line. The first semiconductor structure 102 can include one or more planes, and the peripheral circuits required to perform all read / program (write) / erase operations can be included in the second semiconductor structure 104.

[0027] In some implementations, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating gate transistor. According to some implementations, the array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (e.g., 32-128 memory cells) connected in series (similar to a NAND gate) and two select transistors. According to some implementations, each of the 2D NAND memory strings is disposed in the same plane (in 2D) on the substrate. In some implementations, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically (in 3D) above the substrate through a stack structure, e.g., a memory stack. Depending on the 3D NAND technology (e.g., the number of layers / hierarchies in the memory stack), the 3D NAND memory strings typically include 32-256 NAND memory cells, each of which includes a floating gate transistor or a charge trapping transistor.

[0028] As shown in FIG. 1A, the 3D memory device 100 may also include a second semiconductor structure 104 that includes peripheral circuits of the memory cell array of the first semiconductor structure 102. The peripheral circuits (also known as control and sensing circuits) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an I / O circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., subcircuit) of the aforementioned functional circuitry, or any active or passive component (e.g., transistor, diode, resistor, or capacitor) of the circuit. The peripheral circuits in the second semiconductor structure 104 may use, for example, CMOS technology that may be implemented using logic processes (e.g., technology nodes such as 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, etc.). As described above and in detail below, consistent with the scope of the present disclosure, the technology node used to fabricate the peripheral circuitry in the second semiconductor structure 104 is greater than 22 nm in order to reduce leakage current, maintain specified voltage levels (e.g., 1.2 V or greater), and reduce cost.

[0029] As shown in FIG. 1A, the 3D memory device 100 further includes a bond interface 106 vertically between the first semiconductor structure 102 and the second semiconductor structure 104. As described in detail below, the first and second semiconductor structures 102 and 104 can be fabricated separately (in parallel in some implementations) such that the thermal budget for fabricating one of the first and second semiconductor structures 102 and 104 does not limit the process for fabricating the other of the first and second semiconductor structures 102 and 104. Furthermore, a large number of interconnects (e.g., bond contacts) can be formed through the bond interface 106 to provide direct short-distance (e.g., micron-level) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, as opposed to long-distance (e.g., millimeter or centimeter-level) chip-to-chip data buses on a circuit board such as a printed circuit board (PCB), thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104 can occur via interconnects (e.g., bond contacts) across the bond interface 106. Vertical integration of the first semiconductor structure 102 and the second semiconductor structure 104 allows for smaller chip sizes and higher memory cell densities.

[0030] It is understood that the relative positions of the stacked first and second semiconductor structures 102, 104 are not limited. Figure 1B shows a schematic cross-sectional view of another exemplary 3D memory device 101 according to some implementations. Unlike the 3D memory device 100 of Figure 1A in which the second semiconductor structure 104 including peripheral circuits is above the first semiconductor structure 102 including the memory cell array, in the 3D memory device 101 of Figure 1B, the first semiconductor structure 102 including the memory cell array is above the second semiconductor structure 104 including peripheral circuits. Nevertheless, according to some implementations, a bonding interface 106 is formed vertically between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D memory device 101, and the first semiconductor structure 102 and the second semiconductor structure 104 are bonded vertically via a bond (e.g., a hybrid bond). Hybrid bonding, also known as "metal / dielectric hybrid bonding", is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive) that can simultaneously obtain metal-metal (e.g., Cu-Cu) and dielectric-dielectric (e.g., SiO2-SiO2) bonds. Data transfer between the memory cell array in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104 can be achieved through interconnects (e.g., bond contacts) across the bond interface 106.

[0031] FIG. 2 shows a schematic circuit diagram of a memory device 200 including peripheral circuits according to some aspects of the disclosure. The memory device 200 can include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The 3D memory devices 100 and 101 can be examples of memory devices 200 in which the memory cell array 201 and the peripheral circuit 202 can be included in the first and second semiconductor structures 102 and 104, respectively. The memory cell array 201 can be a NAND flash memory cell array in which the memory cells 206 are provided in the form of an array of 3D NAND memory strings 208, each extending vertically above a substrate (not shown). In some implementations, each 3D NAND memory string 208 includes multiple memory cells 206 coupled in series and stacked vertically. Each memory cell 206 can hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons captured within the area of ​​the memory cell 206. Each memory cell 206 can be either a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0032] In some implementations, each memory cell 206 is a single level cell (SLC), which has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC), which can store more than a single bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple level cell (TLC)), or four bits per cell (also known as a quad level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0033] As shown in FIG. 2, each 3D NAND memory string 208 can include a source select gate (SSG) transistor 210 at its source end and a drain select gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and the DSG transistor 212 can be configured to activate a selected 3D NAND memory string 208 (column of the array) during read and program operations. In some implementations, the sources of the SSG transistors 210 of the 3D NAND memory strings 208 in the same block 204 are coupled to the same source line (SL) 214, e.g., a common SL, e.g., to ground. According to some implementations, the DSG transistors 212 of each 3D NAND memory string 208 are coupled to respective bit lines 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each 3D NAND memory string 208 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the DSG transistor 212) or a deselect voltage (e.g., 0V) to each DSG transistor 212 via one or more DSG lines 213, and / or by applying a select voltage (e.g., above the threshold voltage of the SSG transistor 210) or a deselect voltage (e.g., 0V) to each SSG transistor 210 via one or more SSG lines 215.

[0034] As shown in FIG. 2, the 3D NAND memory string 208 can be organized into multiple blocks 204, each of which can have a common source line 214. In some implementations, each block 204 is the basic data unit for erase operations, i.e., all memory cells 206 on the same block 204 are erased at the same time. The memory cells 206 can be coupled via word lines 218 that select which row of memory cells 206 is affected by read and program operations. In some implementations, each word line 218 is coupled to a row 220 of memory cells 206, which is the basic data unit for program and read operations. Each word line 218 can include multiple control gates (gate electrodes) in each memory cell 206 in the respective row 220 and a gate line coupling the control gates.

[0035] The peripheral circuitry 202 may be coupled to the memory cell array 201 via bit lines 216, word lines 218, source lines 214, SSG lines 215, and DSG lines 213. As previously described, the peripheral circuitry 202 may include any suitable circuitry for facilitating operation of the memory cell array 201 by applying voltage and / or current signals via bit lines 216 to and sensing voltage and / or current signals via bit lines 216 from each target memory cell 206 via word lines 218, source lines 214, SSG lines 215, and DSG lines 213. The peripheral circuitry 202 may include various types of peripheral circuits formed using CMOS technology. For example, FIG. 3 illustrates several exemplary peripheral circuits 202 including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It is understood that in some examples, additional peripheral circuits 202 may also be included.

[0036] The page buffer 304 can be configured to buffer data read from or programmed into the memory cell array 201 according to control signals from the control logic 312. In one example, the page buffer 304 may store one page of program data (write data) to be programmed into one row 220 of the memory cell array 201. In another example, the page buffer 304 also performs program verify operations to ensure that data has been properly programmed into the memory cells 206 coupled to the selected word line 218.

[0037] The row decoder / word line driver 308 may be controlled by the control logic 312 and configured to select or deselect a block 204 of the memory cell array 201 and to select or deselect a word line 218 of the selected block 204. The row decoder / word line driver 308 may be further configured to drive the memory cell array 201. For example, the row decoder / word line driver 308 may drive a memory cell 206 coupled to a selected word line 218 using a word line voltage generated from a voltage generator 310. In some implementations, the row decoder / word line driver 308 may include decoders and string drivers (drive transistors) coupled to local word lines and word lines 218.

[0038] The voltage generator 310 may be configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) to be supplied to the memory cell array 201 under the control of the control logic 312. In some implementations, the voltage generator 310 is part of a voltage source that provides voltages at various levels for different peripheral circuits 202, as described in more detail below. Consistent with the scope of the present disclosure, in some implementations, the voltages supplied by the voltage generator 310 to, for example, the row decoder / word line driver 308 and the page buffer 304 are above a certain level sufficient to perform memory operations. For example, the voltage supplied to the page buffer 304 may be between 2V and 3.3V, such as 3.3V, and the voltage supplied to the row decoder / word line driver 308 may be greater than 3.3V, such as between 3.3V and 30V.

[0039] The column decoder / bit line driver 306 may be controlled by the control logic 312 and configured to select one or more 3D NAND memory strings 208 by applying bit line voltages generated from the voltage generator 310. For example, the column decoder / bit line driver 306 may apply column signals to select a set of N bits of data from the page buffer 304 to be output in a read operation.

[0040] The control logic 312 may be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. The registers 314 may be coupled to the control logic 312 and may include status, command, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202.

[0041] The interface 316 can be coupled to the control logic 312 and can be configured to interface the memory cell array 201 with a memory controller (not shown). In some implementations, the interface 316 functions as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) to the control logic 312 and relay status information received from the control logic 312 to the memory controller and / or host. The interface 316 can also be coupled to the page buffer 304 and the column decoder / bit line driver 306 via a data bus 318 and functions as an I / O interface and data buffer to buffer and relay program data received from the memory controller and / or host to the page buffer 304 and relay data read from the page buffer 304 to the memory controller and / or host. In some implementations, the interface 316 and the data bus 318 are part of the I / O circuitry of the peripheral circuit 202.

[0042] Consistent with the scope of the present disclosure, at least one peripheral circuit 202 of the memory device 200 may have 3D transistors instead of planar transistors to simultaneously achieve high speed, low leakage current, high voltage, and small size without increasing cost. In some implementations, all planar transistors in each peripheral circuit 202 are replaced with 3D transistors. That is, the peripheral circuit 202 may not have any planar transistors at all. In some implementations, the manufacturing process of the 3D transistors disclosed herein is compatible with planar transistors, so that the planar transistors and the 3D transistors are manufactured in the same process flow to achieve a hybrid configuration of memory peripheral circuits having both 3D transistors and planar transistors. That is, the peripheral circuits 202 may have planar transistors. For example, one or more peripheral circuits 202 may have 3D transistors, while other peripheral circuits 202 may still have planar transistors. It is understood that in some examples, both 3D transistors and planar transistors may be used in the same peripheral circuit 202. For example, FIG. 4 illustrates a perspective view of a planar transistor according to some embodiments of the present disclosure, and FIG. 5 illustrates a perspective view of a 3D transistor according to some embodiments of the present disclosure.

[0043] As shown in Figure 4, the planar transistor 400 can be a metal-oxide-semiconductor field-effect transistor (MOSFET) on a substrate 402, which can include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. Note that x- and y-axes are added in Figure 4 to further illustrate the spatial relationships of the components of a semiconductor device (e.g., the planar transistor 400). The substrate 402 has two sides (e.g., a top surface and a bottom surface) that extend laterally in the x-direction (horizontal or width direction). As used herein, whether one component (e.g., layer or device) is "on," "above," or "below" another component (e.g., layer or device) of a semiconductor device (e.g., planar transistor 400) is determined relative to the substrate of the semiconductor device (e.g., substrate 402) in the y-direction (vertical or thickness direction) when the substrate is located at the lowest plane of the semiconductor device in the y-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0044] To reduce current leakage, trench isolation 404, such as shallow trench isolation (STI), may be formed in the substrate 402 and between adjacent planar transistors 400. The trench isolation 404 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some implementations, the high-k dielectric material includes any dielectric having a higher dielectric constant or k value (k>7) than that of silicon nitride. In some implementations, the trench isolation 404 includes silicon oxide.

[0045] As shown in FIG. 4, the planar transistor 400 may also include a gate structure 408 on the substrate 402. In some implementations, the gate structure 408 is on the top surface of the substrate 402. Although not shown, the gate structure 408 may include a gate dielectric on the substrate 402, i.e., above and in contact with the top surface of the substrate 402. The gate structure 408 may include a gate electrode on the gate dielectric, i.e., above and in contact with the gate dielectric. The gate dielectric may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. In some implementations, the gate dielectric includes silicon oxide, i.e., gate oxide. The gate electrode may include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide. In some implementations, the gate electrode includes doped polysilicon, i.e., gate poly.

[0046] As shown in FIG. 4, the planar transistor 400 may further include a pair of source and drain 406 in the substrate 402. The source and drain 406 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain 406 may be separated by a gate structure 408 in a plan view. In other words, according to some implementations, the gate structure 408 is formed between the source and drain 406 in a plan view. A channel 410 of the planar transistor 400 in the substrate 402 may be formed laterally between the source and drain 406 below the gate structure 408 when a gate voltage applied to a gate electrode of the gate structure 408 exceeds a threshold voltage of the planar transistor 400. As shown in FIG. 4, the gate structure 408 may be above and in contact with an upper surface (active area) of a portion of the substrate 402 in which the channel 410 may be formed. That is, according to some implementations, the gate structure 408 is in contact with only one side of the active area, i.e., in the plane of the top surface of the substrate 402. The gate structure 408 further includes a gate dielectric (e.g., a gate oxide, not shown in FIG. 4) between the gate electrode and the channel 410. Although not shown in FIG. 4, it is understood that the planar transistor 400 may include additional components, such as wells and spacers.

[0047] As shown in FIG. 5, the 3D transistor 500 can be a MOSFET on a substrate 502, which can include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator SOI, or any other suitable material. In some implementations, the substrate 502 includes single crystal silicon. Trench isolation 504, such as STI, can be formed in the substrate 502 and between adjacent 3D transistors 500 to reduce current leakage. The trench isolation 504 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some implementations, the high-k dielectric material includes any dielectric with a higher dielectric constant or k value (k>7) than that of silicon nitride. In some implementations, the trench isolation 404 includes silicon oxide.

[0048] As shown in FIG. 5, unlike the planar transistor 400, the 3D transistor 500 can further include a 3D semiconductor body 505 above the substrate 502. That is, in some implementations, the 3D semiconductor body 505 extends at least partially above the top surface of the substrate 502 to expose not only the top surface of the 3D semiconductor body 505 but also two side surfaces. As shown in FIG. 5, for example, the 3D semiconductor body 505 may be a 3D structure also known as a "fin" to expose its three sides. As described below with respect to the manufacturing process of the 3D transistor 500, the 3D semiconductor body 505 is formed from the substrate 502 and thus has the same semiconductor material as the substrate 502 according to some implementations. In some implementations, the 3D semiconductor body 505 includes single crystal silicon. Since a channel can be formed in the 3D semiconductor body 505, the 3D semiconductor body 505 (e.g., fin) can be viewed as the active region of the 3D transistor 500, in contrast to the substrate 502.

[0049] FIG. 6A shows a cross-sectional side view of the 3D transistor 500 in FIG. 5 in the AA plane according to some embodiments of the present disclosure. FIG. 6B shows a cross-sectional side view of the 3D transistor 500 in FIG. 5 in the BB plane according to some embodiments of the present disclosure. As shown in FIG. 5 and FIG. 6B, the 3D transistor 500 can also include a gate structure 508 on the substrate 502. Unlike the planar transistor 400 in which the gate structure 408 contacts only one side of the active region, i.e., in the plane of the top surface of the substrate 402, the gate structure 508 of the 3D transistor 500 can contact multiple sides of the active region, i.e., in multiple planes of the top and side surfaces of the 3D semiconductor body 505. In other words, the active region of the 3D transistor 500, i.e., the 3D semiconductor body 505, can be at least partially surrounded by the gate structure 508.

[0050] The gate structure 508 may include a gate dielectric 602 over the 3D semiconductor body 505, for example, in contact with a top surface and two side surfaces of the 3D semiconductor body 505. The gate structure 508 may also include a gate electrode 604 over and in contact with the gate dielectric 602. The gate dielectric 602 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some implementations, the gate dielectric 602 includes silicon oxide, i.e., a gate oxide. The gate electrode 604 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some implementations, the gate electrode 604 includes doped polysilicon, i.e., a gate poly.

[0051] As shown in FIG. 5 and FIG. 6A, the 3D transistor 500 may further include a pair of source and drain 506 (doped regions, also known as source and drain electrodes) in the substrate 502. The source and drain 506 may be doped with any suitable P-type dopant, such as B or Ga, or any suitable N-type dopant, such as P or Ar. The source and drain 506 may be separated by a gate structure 508 in a plan view. In other words, according to some implementations, the gate structure 508 is formed between the source and drain 506 in a plan view. As a result, when a gate voltage applied to the gate electrode 604 of the gate structure 508 exceeds a threshold voltage of the 3D transistor 500, multiple channels of the 3D transistor 500 in the 3D semiconductor body 505 may be formed laterally between the source and drain 506 surrounded by the gate structure 508. Unlike the planar transistor 400, which can only form a single channel on the top surface of the substrate 402, the 3D transistor 500 can form multiple channels on the top and side surfaces of the 3D semiconductor body 505. In some implementations, the 3D transistor 500 includes a multi-gate transistor. That is, unlike the planar transistor 400, which includes only a single gate, the 3D transistor 500 can have multiple gates on multiple sides of the 3D semiconductor body 505 due to the 3D structure of the 3D semiconductor body 505 and the gate structure 508 surrounding multiple sides of the 3D semiconductor body 505. As a result, compared to the planar transistor 400, the 3D transistor 500 can have a larger gate control area to achieve better channel control with smaller subthreshold swing. Since the channel is fully depleted during the off state, the leakage current (I off ) can be significantly reduced. Meanwhile, the dimensions of the 3D transistor 500 can be significantly reduced from the planar transistor 400 while still maintaining the same electrical performance (e.g., channel control, subthreshold swing, and / or leakage current) as the planar transistor 400.

[0052] As mentioned above, 3D transistors (e.g., FinFETs) are also used in logic devices (e.g., microprocessors) using advanced technology nodes (e.g., below 22 nm), however, due to the different transistor requirements between logic devices and memory periphery circuits, it is understood that the design of the 3D transistor 500 may exhibit unique features not found in 3D transistors used in logic devices. From a materials perspective, in some implementations, unlike 3D transistors (e.g., FinFETs) in logic devices using advanced technology nodes (e.g., below 22 nm) that use HKMG (i.e., high-k dielectrics for the gate dielectric and metal for the gate electrode), the 3D transistor 500 in the memory periphery circuits uses gate poly and gate oxide instead of HKMG to reduce manufacturing cost and complexity.

[0053] In terms of transistor dimensions, the 3D transistor 500 in the memory peripheral circuit cannot be scaled down according to the same trend of logic devices (e.g., microprocessors) using advanced technology nodes (e.g., below 22 nm). The difference in dimensions allows the 3D transistor 500 to be used at higher voltages (e.g., 3.3V or higher) that are not commonly used and are undesirable for 3D transistors (e.g., FinFETs) in logic devices using advanced technology nodes (e.g., below 22 nm). The difference in dimensions can also significantly reduce the manufacturing cost and complexity of the 3D transistor 500 in the memory peripheral circuit.

[0054] For example, in some implementations, the width (W) of the 3D semiconductor body 505 is greater than 10 nm, as shown in FIG. 6B. For example, the width of the 3D semiconductor body 505 may be between 30 nm and 1,000 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1,000 nm, any range bounded at the lower end by any of these values, or any range defined by any two of these values). The width of the 3D transistor 500 may be significantly greater (e.g., more than one time, or more than one order of magnitude greater) than the width of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm).

[0055] In some implementations, as shown in FIG. 6B, the height (H) of the 3D semiconductor body 505 is greater than 40 nm. For example, the height of the 3D semiconductor body 505 may be between 50 nm and 1,000 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1,000 nm, any range bounded at the lower end by any of these values, or any range defined by any two of these values). The height of the 3D transistor 500 may be significantly greater (e.g., more than one time, or more than one order of magnitude greater) than the height of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm).

[0056] In some implementations, the thickness (T) of the gate dielectric 602 is greater than 1.8 nm, as shown in FIG. 6B. For example, the thickness of the gate dielectric 602 may be between 2 nm and 100 nm (e.g., 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded at the lower end by any of these values, or any range defined by any two of these values). The thickness of the gate dielectric 602 may be significantly greater (e.g., more than one time, or more than one order of magnitude greater) than the thickness of a 3D transistor (e.g., FinFET) used in logic devices using advanced technology nodes (e.g., less than 22 nm). As a result, with the thicker gate dielectric 602, the 3D transistor 500 can sustain higher voltages (e.g., 3.3 V or greater) than 3D transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., below 22 nm).

[0057] In some implementations, the channel length (L) of the 3D transistor 500 is greater than 30 nm, as shown in Figure 6A. For example, the channel length of the 3D transistor 500 can be between 50 nm and 1,500 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1,000 nm, 1,100 nm, 1,200 nm, 1,300 nm, 1,400 nm, 1,500 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The channel length of the 3D transistor 500 may be significantly larger (e.g., more than one time, or more than an order of magnitude larger) than the channel length of 3D transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., less than 22 nm).

[0058] Although not shown in Figures 5, 6A, and 6B, it is understood that the 3D transistor 500 can include further components such as wells and spacers. It is also understood that unlike 3D transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., below 22 nm) that include stressors including GaAs or SiGe (aka strain elements) in the source and drain to enhance carrier mobility or use strained silicon technology to apply strain to the channel, the 3D transistor 500 may not include stressors in the source and drain 506 and / or may not use strained semiconductor materials in the 3D semiconductor body 505 due to its relatively large dimensions and to reduce manufacturing complexity and cost.

[0059] It is further understood that FIG. 5, FIG. 6A, and FIG. 6B show an example of a 3D transistor (e.g., FinFET) that can be used in the memory peripheral circuitry, and any other suitable 3D transistor, such as a gate-all-around (GAA) FET, can also be used in the memory peripheral circuitry. For example, FIG. 7A-FIG. 7I show cross-sectional side views of various 3D transistors according to various aspects of the disclosure. Similar to the 3D transistor 500 in FIG. 5, FIG. 6A, and FIG. 6B, the 3D transistor in FIG. 7A-FIG. 7I can be a multi-gate transistor having a 3D semiconductor body above a substrate and a gate structure in contact with two or more sides of the 3D semiconductor body. The gate structure can include a gate dielectric and a gate electrode. For example, FIG. 7A, FIG. 7B, and FIG. 7C show a gate-all-around (GAA) silicon-on-nothing (SON) transistor, a multiple independent gate FET (MIGET), and a FinFET, each of which can be considered as a double-gate transistor. For example, Figures 7D, 7E, and 7F show a tri-gate FET, a free-gate FET, and an Ω-FET, each of which are considered triple-gate transistors. For example, Figures 7G, ​​7H, and 7I show a quadruple-gate FET, a cylindrical FET, and a multi-bridge / stacked nanowire FET, each of which are considered surrounding-gate transistors. As can be seen from Figures 7A-7I, the cross-section of the 3D semiconductor body in side view can have a square, rectangular (or trapezoidal), circular (or elliptical), or any other suitable shape. Consistent with the scope of the present disclosure, it is understood that with respect to 3D semiconductor bodies having circular or elliptical shapes in their cross-section, the 3D semiconductor body can still be considered to have multiple sides such that a gate structure contacts two or more sides of the 3D semiconductor body. It is understood that in some examples, multiple 3D transistors (e.g., multiple FinFETs) may share a single 3D semiconductor body (e.g., fins), i.e., may be formed on a single 3D semiconductor body.For example, multiple FinFETs may be placed in parallel on the same fin, and there may not be any trench isolation (e.g., STI) formed between multiple FinFETs sharing the same fin to distribute the FinFETs.

[0060] As described above with respect to FIG. 1A and FIG. 1B, the 3D transistor 500 may be an example of a transistor in a peripheral circuit of a second semiconductor structure 104 bonded to a first semiconductor structure 102 having a memory cell array. For example, FIG. 8A shows a cross-sectional side view of an exemplary 3D memory device 800 according to some implementations. It is understood that FIG. 8A is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnects). As an example of the 3D memory device 100 described above with respect to FIG. 1A, the 3D memory device 800 is a bonded chip including a first semiconductor structure 802 and a second semiconductor structure 804 stacked over the first semiconductor structure 802. According to some implementations, the first and second semiconductor structures 802 and 804 are bonded at a bonded interface 806 therebetween. As shown in FIG. 8A, the first semiconductor structure 802 may include a substrate 808, which may include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0061] The first semiconductor structure 802 can include a device layer 810 above a substrate 808. In some implementations, the device layer 810 includes a first peripheral circuit 812 (e.g., page buffer 304, word line driver 308, and / or I / O circuitry 316 and 318) and a second peripheral circuit 814 (e.g., control logic 312, registers 314, etc.). In some implementations, the first peripheral circuit 812 includes a plurality of 3D transistors 816 (e.g., corresponding to 3D transistor 500), and the second peripheral circuit 814 includes a plurality of planar transistors 818 (e.g., corresponding to planar transistor 400). Trench isolation 860 and 862 (e.g., STI) and doped regions (e.g., wells, sources, and drains of transistors 816 and 818) can also be formed on or in the substrate 808. In some implementations, trench isolation 860 is on substrate 808 between two laterally adjacent 3D transistors 816, and trench isolation 862 extends into substrate 808 between two laterally adjacent planar transistors 818 in a planar view. In some implementations, trench isolation 862 and trench isolation 860 have different depths (e.g., their bottom surfaces are in different planes in the y direction) to separate different types of transistors, planar transistors 818 and 3D transistors 816, respectively. For example, as shown in FIG. 8A, trench isolation 862 may have a deeper depth than trench isolation 860. It is understood that, depending on different manufacturing processes, in some examples, trench isolation 862 and trench isolation 860 have the same depth (e.g., their bottom surfaces are in the same plane in the y direction).

[0062] In some implementations, the first semiconductor structure 802 further includes an interconnect layer 820 above the device layer 810 for transferring electrical signals between the peripheral circuits 812 and 814. The interconnect layer 820 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (VIA) contacts. The term "interconnect" as used herein may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 820 may further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which interconnect lines and via contacts may be formed. That is, the interconnect layer 820 may include interconnect lines and via contacts in multiple ILD layers. In some implementations, the devices in the device layer 810 are coupled to each other via interconnects in the interconnect layer 820. For example, peripheral circuit 812 may be coupled to peripheral circuit 814 through interconnect layer 820 .

[0063] As shown in FIG. 8A, the first semiconductor structure 802 may further include a bonding layer 822 at the bonding interface 806 and above the interconnect layer 820 and the device layer 810. The bonding layer 822 may include a plurality of bonding contacts 824 and a dielectric that electrically insulates the bonding contacts 824. The bonding contacts 824 may include a conductive material. The remaining region of the bonding layer 822 may be formed of a dielectric material. The bonding contacts 824 and the surrounding dielectric within the bonding layer 822 may be used for hybrid bonding. Similarly, as shown in FIG. 8A, the second semiconductor structure 804 may also include a bonding layer 826 at the bonding interface 806 and above the bonding layer 822 of the first semiconductor structure 802. The bonding layer 826 may include a plurality of bonding contacts 828 and a dielectric that electrically insulates the bonding contacts 828. The bonding contacts 828 may include a conductive material. The remaining region of the bonding layer 826 may be formed of a dielectric material. The bonding contact 828 and the surrounding dielectric in the bonding layer 826 can be used for hybrid bonding. According to some implementations, the bonding contact 828 contacts the bonding contact 824 at the bonding interface 806.

[0064] The second semiconductor structure 804 may be bonded on the first semiconductor structure 802 in a face-to-face manner at a bonding interface 806. In some implementations, the bonding interface 806 is disposed between the bonding layers 822 and 826 as a result of a hybrid bond (also known as a "metal / dielectric hybrid bond"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as a solder or adhesive) that can simultaneously obtain a metal-metal bond and a dielectric-dielectric bond. In some implementations, the bonding interface 806 is where the bonding layers 822 and 826 are brought together and bonded. In practice, the bonding interface 806 may be a layer having a certain thickness that includes a top surface of the bonding layer 822 of the first semiconductor structure 802 and a bottom surface of the bonding layer 826 of the second semiconductor structure 804.

[0065] In some implementations, the second semiconductor structure 804 further includes an interconnect layer 830 above the bonding layer 826 for transferring electrical signals. The interconnect layer 830 can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the interconnects in the interconnect layer 830 also include local interconnects, such as bit lines, bit line contacts, and word line contacts. The interconnect layer 830 can further include one or more ILD layers through which the interconnect lines and via contacts can be formed. In some implementations, the first peripheral circuit 812 is a page buffer 304, and the 3D transistors 816 of the first peripheral circuit 812 are coupled to bit lines of the second semiconductor structure 804. In some implementations, the first peripheral circuit 812 is a word line driver 308, and the 3D transistors 816 of the first peripheral circuit 812 are coupled to word lines (e.g., conductive layer 834) of the second semiconductor structure 804.

[0066] In some implementations, the second semiconductor structure 804 includes a NAND flash memory device in which memory cells are provided above the interconnect layer 830 and the bonding layer 826 in the form of an array of 3D NAND memory strings 838. According to some implementations, each 3D NAND memory string 838 extends vertically through multiple pairs, each including a conductive layer 834 and a dielectric layer 836. The stacked and interleaved conductive layers 834 and dielectric layers 836 are also referred to herein as stack structures, e.g., memory stacks 832. According to some implementations, the interleaved conductive layers 834 and dielectric layers 836 in the memory stack 832 alternate in the vertical direction. Each conductive layer 834 can include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the stack conductive layer 834 can extend laterally as a word line and terminate in one or more staircase structures of the memory stack 832.

[0067] In some implementations, each 3D NAND memory string 838 is a "charge trap" type NAND memory string including a semiconductor channel and a memory film. In some implementations, the semiconductor channel includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. In some implementations, the memory film is a composite dielectric layer including a tunnel layer, a storage layer (also known as a "charge trap / storage layer"), and a blocking layer. Each 3D NAND memory string 838 can have a cylindrical shape (e.g., a pillar shape). According to some implementations, the semiconductor channel, the tunnel layer, the storage layer, and the blocking layer of the memory film are arranged in this order along a direction from the center of the pillar toward the outer surface. In some implementations, the 3D NAND memory string 838 further includes a plurality of control gates (each of which is a part of a word line). Each conductive layer 834 in the memory stack 832 can function as a control gate for each memory cell of the 3D NAND memory string 838.

[0068] In some implementations, the second semiconductor structure 804 further includes a semiconductor layer 848 disposed above the memory stack 832 and the 3D NAND memory string 838. The semiconductor layer 848 can be a thinned substrate on which the memory stack 832 and the 3D NAND memory string 838 are formed. In some implementations, the semiconductor layer 848 includes single crystal silicon. The semiconductor layer 848 can also include insulating and doped regions (e.g., not shown, but serving as an array common source (ACS) for the 3D NAND memory string 838). It is understood that the 3D NAND memory string 838 is not limited to a "charge trap" type 3D NAND memory string, and may be a "floating gate" type 3D NAND memory string in other examples. The semiconductor layer 848 can include polysilicon as a source plate of a "floating gate" type 3D NAND memory string.

[0069] As shown in FIG. 8A, the second semiconductor structure 804 can further include a pad-out interconnect layer 850 above the semiconductor layer 848. The pad-out interconnect layer 850 can include interconnects, such as contact pads 852, to one or more ILD layers. The pad-out interconnect layer 850 and the interconnect layer 830 can be formed on both sides of the semiconductor layer 848. In some implementations, the interconnects in the pad-out interconnect layer 850 can transfer electrical signals between the 3D memory device 800 and external circuits, for example, for pad-out purposes. In some implementations, the second semiconductor structure 804 further includes one or more contacts 854 extending through the semiconductor layer 848 to electrically connect the pad-out interconnect layer 850 and the interconnect layers 830 and 820. As a result, the peripheral circuits 812 and 814 can be coupled to an array of 3D NAND memory strings 838 via the interconnect layers 830 and 820 and the junction contacts 828 and 824. That is, the array of 3D NAND memory strings 838 can be coupled to the 3D transistor 816 and the planar transistor 818 across the bond interface 806. Additionally, the peripheral circuits 812 and 814 and the array of 3D NAND memory strings 838 can be coupled to external circuitry via contacts 854 and pad-out interconnect layer 850.

[0070] FIG. 8B illustrates a cross-section of another exemplary 3D memory device 801 according to some aspects of the present disclosure. It is understood that FIG. 8B is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnects). As an example of the 3D memory device 101 described above in relation to FIG. 1B, the 3D memory device 801 is a bonded chip including a second semiconductor structure 803 and a first semiconductor structure 805 stacked over the second semiconductor structure 803. Similar to the 3D memory device 800 described above in FIG. 8A, the 3D memory device 801 corresponds to an example of a bonded chip in which the first semiconductor structure 805 and the second semiconductor structure 803 are formed separately and bonded in a face-to-face manner at a bonding interface 807. It is understood that details of similar structures (e.g., materials, manufacturing processes, functions, etc.) in both the 3D memory devices 800 and 801 will not be repeated below.

[0071] The second semiconductor structure 803 can include a substrate 809 and a memory stack 811 including alternating conductive layers 813 and dielectric layers 815 above the substrate 809. In some implementations, an array of 3D NAND memory strings 817 each extend vertically through the alternating conductive layers 813 and dielectric layers 815 in the memory stack 811 above the substrate 809. Each 3D NAND memory string 817 can include a semiconductor channel and a memory film. The 3D NAND memory strings 817 can be "charge trap" type 3D NAND memory strings or "floating gate" type 3D NAND memory strings.

[0072] In some implementations, the second semiconductor structure 803 also includes an interconnect layer 827 above the memory stack 811 and the 3D NAND memory string 817 for transferring electrical signals to and from the 3D NAND memory string 817, where the interconnect layer 827 can include a plurality of interconnects, including interconnect lines and via contacts. In some implementations, the interconnects in the interconnect layer 827 also include local interconnects, such as bit lines, bit line contacts, and word line contacts. In some implementations, the second semiconductor structure 803 further includes a bonding layer 829 above the interconnect layer 827 and the memory stack 811 at the bonding interface 807 and the 3D NAND memory string 817. The bonding layer 829 can include a plurality of bonding contacts 855 and a dielectric that surrounds and electrically insulates the bonding contacts 855.

[0073] 8B, the first semiconductor structure 805 has another bonding layer 851 above the bonding layer 829 at the bonding interface 807. The bonding layer 851 can include a plurality of bonding contacts 853 and a dielectric that surrounds and electrically insulates the bonding contacts 853. According to some implementations, the bonding contacts 853 contact the bonding contacts 855 at the bonding interface 807. In some implementations, the first semiconductor structure 805 also includes an interconnect layer 857 above the bonding layer 851 for transferring electrical signals. The interconnect layer 857 can include a plurality of interconnects, including interconnect lines and via contacts.

[0074] The first semiconductor structure 805 may further include a device layer 831 above the interconnect layer 857 and the bonding layer 851. In some implementations, the device layer 831 includes a first peripheral circuit 835 (e.g., page buffer 304, word line driver 308, and / or I / O circuits 316 and 318) and a second peripheral circuit 837 (e.g., control logic 312, registers 314, etc.). In some implementations, the peripheral circuit 835 includes a plurality of 3D transistors 839 (e.g., corresponding to 3D transistor 500), and the peripheral circuit 837 includes a plurality of planar transistors 841 (e.g., corresponding to planar transistor 400). Trench isolations 861 and 863 (e.g., STI) and doped regions (e.g., wells, sources, and drains of transistors 839 and 841) may be formed on or in the semiconductor layer 833 (e.g., a thinned substrate). In some implementations, trench isolation 861 is below semiconductor layer 833 between two laterally adjacent 3D transistors 839, and trench isolation 863 extends into semiconductor layer 833 between two laterally adjacent planar transistors 841 in a planar view. In some implementations, trench isolation 861 and trench isolation 863 have different depths (e.g., their top surfaces are in different planes in the y direction) to separate different types of transistors, planar transistor 841 and 3D transistor 839, respectively. For example, as shown in FIG. 8B, trench isolation 863 can have a deeper depth than trench isolation 861. It is understood that, depending on different manufacturing processes, in some examples, trench isolation 863 and trench isolation 861 have the same depth (e.g., their top surfaces are in the same plane in the y direction).

[0075] In some implementations, the first peripheral circuit 835 is a page buffer 304, and the 3D transistor 839 of the first peripheral circuit 835 is coupled to a bit line of the second semiconductor structure 803. In some implementations, the first peripheral circuit 835 is a word line driver 308, and the 3D transistor 839 of the first peripheral circuit 835 is coupled to a word line (e.g., the conductive layer 834) of the second semiconductor structure 803.

[0076] In some implementations, the first semiconductor structure 805 further includes a semiconductor layer 833 disposed above the device layer 831. The semiconductor layer 833 can be above and in contact with the peripheral circuits 835 and 837. The semiconductor layer 833 can be a thinned substrate on which the transistors 839 and 841 are formed. In some implementations, the semiconductor layer 833 includes single crystal silicon. The semiconductor layer 833 can also include insulating and doped regions.

[0077] As shown in FIG. 8B, the first semiconductor structure 805 can further include a pad-out interconnect layer 843 above the semiconductor layer 833. The pad-out interconnect layer 843 can include interconnects, such as contact pads 845, to one or more ILD layers. In some implementations, the interconnects in the pad-out interconnect layer 843 can transfer electrical signals between the 3D memory device 801 and external circuitry, for example, for pad-out purposes. In some implementations, the first semiconductor structure 805 further includes one or more contacts 847 extending through the semiconductor layer 833 to couple the pad-out interconnect layer 843 to the interconnect layers 857 and 827. As a result, the peripheral circuits 835 and 837 can also be coupled to the array of 3D NAND memory strings 817 via the interconnect layers 857 and 827 and the junction contacts 853 and 855. That is, the array of 3D NAND memory strings 817 can be coupled to the 3D transistor 839 and the planar transistor 841 across the bond interface 807. Additionally, the peripheral circuits 835 and 837 and the array of 3D NAND memory strings 817 can be electrically connected to external circuitry via contacts 847 and pad-out interconnect layer 843.

[0078] As mentioned above, the memory cell array in the semiconductor structure 102 is not limited to a NAND flash memory cell array as shown in FIG. 8A and FIG. 8B, but may include any other suitable memory cell array, such as a DRAM cell array. For example, FIG. 8C illustrates a cross-section of another exemplary 3D memory device 899 according to some aspects of the present disclosure. It is understood that FIG. 8C is for illustrative purposes only and may not necessarily reflect an actual device structure (e.g., interconnects). The 3D memory device 899 is similar to the 3D memory device 800 of FIG. 8A, except that the memory cell array includes an array of DRAM cells 890 as opposed to an array of NAND memory strings 838. It is understood that details of similar structures (e.g., materials, manufacturing processes, functions, etc. of the first semiconductor structure 802) in both the 3D memory devices 800 and 899 will not be repeated below.

[0079] 8C, a second semiconductor structure 804 can be bonded onto a first semiconductor structure 802 including a 3D transistor 816 in a face-to-face manner at a bonding interface 806. In some implementations, the bonding interface 806 is disposed between bonding layers 822, 826 as a result of a hybrid bond.

[0080] In some implementations, the second semiconductor structure 804 of the semiconductor device 899 further includes an interconnect layer 830 above the bonding layer 826 to transfer electrical signals to and from the DRAM cells 890. The interconnect layer 830 can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the interconnects in the interconnect layer 830 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 830 can further include one or more ILD layers in which interconnect lines and via contacts can be formed.

[0081] The second semiconductor structure 804 of the semiconductor device 899 can further include a device layer 881 above the interconnect layer 830 and the bonding layer 826. In some embodiments, the device layer 881 includes an array of DRAM cells 890 above the interconnect layer 830 and the bonding layer 826. In some embodiments, each DRAM cell 890 includes a DRAM select transistor 886 and a capacitor 888. The DRAM cells 890 can be 1T1C cells consisting of one transistor and one capacitor. It is understood that the DRAM cells 890 can be any suitable configuration, such as 2T1C cells, 3T1C cells, etc. In some implementations, the DRAM select transistor 886 is formed "on" the semiconductor layer 848, where all or a portion of the DRAM select transistor 886 is formed in (e.g., below a top surface of) and / or directly on the semiconductor layer 848. Isolation regions (e.g., STI) and doped regions (e.g., source and drain regions of DRAM select transistors 886) may also be formed in the semiconductor layer 848. In some implementations, capacitors 888 are disposed below the DRAM select transistors 886. Each capacitor 888 includes two electrodes, one of which is electrically connected to one node of a respective DRAM select transistor 886, according to some implementations. According to some implementations, the other node of each DRAM select transistor 886 is coupled to a bit line 880 of the DRAM. The other electrode of each capacitor 888 may be coupled to a common plate 882, e.g., a common ground. It is understood that the structure and configuration of the DRAM cell 890 is not limited to the example of FIG. 8C and may include any suitable structure and configuration. For example, the capacitor 888 may be a planar capacitor, a stack capacitor, a multi-fin capacitor, a cylinder capacitor, a trench capacitor, or a substrate capacitor.

[0082] In some implementations, the second semiconductor structure 804 further includes a semiconductor layer 848 disposed above the device layer 881. The semiconductor layer 848 can be in contact with and above an array of DRAM cells 890. The semiconductor layer 848 can be a thinned substrate on which the DRAM select transistor 886 is formed. In some implementations, the semiconductor layer 848 includes single crystal silicon. In some implementations, the semiconductor layer 848 can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. The semiconductor layer 848 can also include isolation regions and doped regions (e.g., as the source and drain of the DRAM select transistor 886).

[0083] As described above, unlike logic devices, memory devices such as 3D NAND flash memories are not suitable for logic devices (e.g., microprocessors) that use particularly advanced CMOS technology nodes (e.g., less than 22 nm), but require a wide range of voltages supplied to different memory peripheral circuits, including higher voltages (e.g., 3.3V or more) required for memory operation. For example, FIG. 9 shows a block diagram of a peripheral circuit supplied with various voltages according to some aspects of the present disclosure. In some implementations, a memory device (e.g., memory device 200) includes a low low voltage (LLV) source 901, a low voltage (LV) source 903, and a high voltage (HV) source 905, each of which is configured to supply a voltage at its respective level (Vdd1, Vdd2, or Vdd3, where Vdd1 < Vdd2 < Vdd3). Each voltage source 901, 903, or 905 can receive an appropriate level of voltage input from an external power source (e.g., a battery). Also, each voltage source 901, 903, or 905 can include a voltage converter and / or voltage regulator for converting the external voltage input to its respective level (Vdd1, Vdd2, or Vdd3) and maintaining and outputting a voltage at its respective level (Vdd1, Vdd2, or Vdd3) via a corresponding power rail. In some implementations, the voltage generator 310 of the memory device 200 is part of the voltage sources 901, 903, and 905.

[0084] In some implementations, the LLV source 901 is configured to provide a voltage between 0.9V and 2.0V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, 1.25V, 1.3V, 1.35V, 1.4V, 1.45V, 1.5V, 1.55V, 1.6V, 1.65V, 1.7V, 1.75V, 1.8V, 1.85V, 1.9V, 1.95V, any range bounded at the lower end by any of these values, or any range defined by any two of these values). In one example, the voltage is 1.2V. In some implementations, the LV source 903 is configured to provide a voltage between 2V and 3.3V (e.g., 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range bounded at the lower end by any of these values, or any range defined by any two of these values). In one example, the voltage is 3.3V. In some implementations, the HV source 905 is configured to provide a voltage greater than 3.3V. In one example, the voltage is 5V to 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range bounded at the lower end by any of these values, or any range defined by any two of these values). It is understood that the voltage ranges set forth above for HV source 905, LV source 903, and LLV source 901 are for illustrative purposes and are non-limiting, and any other suitable voltage ranges may be provided by HV source 905, LV source 903, and LLV source 901. Nevertheless, the voltage levels provided by at least LV source 903 and HV source 905 (e.g., 2V or greater) may not be suitable for 3D transistors (e.g., FinFETs) in logic devices using advanced CMOS technology nodes (e.g., below 22 nm).

[0085] Based on their appropriate voltage levels (Vdd1, Vdd2, or Vdd3), the memory peripheral circuits (e.g., peripheral circuits 202) can be classified into LLV circuits 902, LV circuits 904, and HV circuits 906, which can be coupled to an LLV source 901, an LV source 903, and an HV source 905, respectively. In some implementations, the HV circuits 906 include one or more drivers that are coupled to a memory cell array (e.g., memory cell array 201) via word lines, bit lines, SSG lines, DSG lines, source lines, etc., and are configured to drive the memory cell array by applying appropriate levels of voltages to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing a memory operation (e.g., read, program, or erase). In one example, the HV circuits 906 can include a word line driver (e.g., row decoder / word line driver 308) that applies a program voltage (Vprog) or a pass voltage (Vpass), e.g., in the range of 5V to 30V, to the word lines during a program operation. In another example, the HV circuitry 906 may include a bit line driver (e.g., column decoder / bit line driver 306) that applies an erase voltage (Veras) to the bit lines during an erase operation, e.g., in the range of 5V to 30V. In some implementations, the LV circuitry 904 includes a page buffer (e.g., page buffer 304) configured to buffer data read from or programmed into the memory cell array. For example, the page buffer may be supplied with a voltage of, e.g., 3.3V by the LV source 903. In some implementations, the LLV circuitry 902 includes I / O circuitry (e.g., interface 316 and / or data bus 318) configured to interface the memory cell array with a memory controller. For example, the I / O circuitry may be supplied with a voltage of, e.g., 1.2V by the LLV source 901.

[0086] At least one of the LLV circuit 902, the LV circuit 904, or the HV circuit 906 can include a 3D transistor (e.g., 3D transistor 500) disclosed herein. In some implementations, each of the LLV circuit 902, the LV circuit 904, and the HV circuit 906 includes a 3D transistor. In some implementations, each of the LLV circuit 902 and the LV circuit 904 includes a 3D transistor, while the HV circuit 906 includes a planar circuit (e.g., planar transistor 400) disclosed herein. Furthermore, the LLV circuit 902, the LV circuit 904, or the HV circuit 906 can be implemented with any suitable combination of 3D transistors and / or planar transistors disclosed herein as peripheral circuits 812, 814, 835, and 837 in FIGS. 8A-8C.

[0087] Consistent with the scope of the present disclosure, various forms of 3D transistors suitable for use in the LLV circuit 902, the LV circuit 904, and the HV circuit 906, respectively, are described in detail below. According to some aspects of the present disclosure, as shown in FIG. 10, the LLV circuit 902 of the memory device 200 may be represented by an I / O circuit including, for example, an interface 316 and a data bus 318. The I / O circuit may be configured to interface the memory cell array 201 with a memory controller. In some implementations, the I / O circuit is supplied with a voltage between 0.9V and 2.0V, e.g., 1.2V, by the LLV source 901.

[0088] 11A and 11B show perspective and side views, respectively, of a 3D transistor 1100 in the I / O circuit of FIG. 10 according to some aspects of the disclosure. The 3D transistor 1100 may be an example of the 3D transistor 500 in FIGS. 5, 6A, and 6B, and is designed to meet specific requirements of the I / O circuit or any other suitable LLV circuit 902, as described in detail below. FIG. 11B shows a cross-sectional side view of the 3D transistor 1100 of FIG. 11A in the BB plane. As shown in FIGS. 11A and 11B, the 3D transistor 1100 may include a 3D semiconductor body 1104 above a substrate 1102 and a gate structure 1108 contacting multiple sides (e.g., top and both sides) of the 3D semiconductor body 1104. It is understood that the 3D transistor 1100 may be any suitable multi-gate transistor, for example, as shown in FIGS. 7A-7I. In some implementations, the gate structure 1108 includes a gate dielectric 1107 in contact with multiple sides of the 3D semiconductor body 1104 and a gate electrode 1109 in contact with the gate dielectric 1107. As shown in Figures 11A and 11B, the top surface of the gate structure 1108 (e.g., the gate electrode 1109) is curved.

[0089] As shown in Figures 11A and 11B, the 3D transistor 1100 can include a pair of source and drain 1106 in a 3D semiconductor body 1104 separated by a gate structure 1108 in a plan view. As shown in Figure 11B, a trench isolation 1103 (e.g., STI) can be formed in the substrate 1102, whereby the gate structure 1108 can be formed on the trench isolation 1103. In some implementations, the trench isolation 1103 is also formed laterally between adjacent 3D transistors 1100 to reduce leakage current. It is understood that for ease of explanation, the trench isolation 1103 is shown in Figure 11B but not in Figure 11A. It is also understood that the 3D transistor 1100 may include additional components not shown in Figures 11A and 11B, such as wells and spacers.

[0090] For the 3D transistor 1100 used in the I / O circuit of the memory device 200, switching speed is an important characteristic. In particular, when the memory device 200 is a junction chip that can achieve high I / O throughput with reduced power consumption by using a direct short-distance (e.g., micron-level) electrical connection between two junctioned semiconductor structures, such as the 3D memory devices 800 and 801, the switching speed of the transistors forming the I / O circuit can become a bottleneck in the performance of the I / O circuit. To increase the switching speed, as mentioned above, the on-current (I on or I dsat ) needs to be increased. However, at the same time, the off-state leakage current (I off ), which is difficult to achieve with planar transistors.

[0091] For example, Figures 12A and 12B show perspective and side views, respectively, of a planar transistor 1200. The planar transistor 1200 may be an example of the planar transistor 400 of Figure 4. The planar transistor 1200 includes a gate structure 1208 on a substrate 2102, i.e., the gate structure 1208 is above and in contact with an upper surface of the substrate 1202. The gate structure 1208 includes a planar gate dielectric 1207 above and in contact with an upper surface of the substrate 1202, and a gate electrode 1209 on the planar gate dielectric 1207. The planar transistor 1200 also includes a pair of source and drain 1206 in the substrate 1202, separated by the gate structure 1208 in a plan view. A trench isolation 1203 (e.g., STI) is formed laterally in the substrate 1202 between adjacent planar transistors 1200. It is understood that for ease of illustration, trench isolation 1203 is shown in FIG. 12B but not in FIG. 12A. Due to the smaller number of channels and gates compared to the 3D transistor 1100, the channel control and subthreshold swing of the planar transistor 1200 may be inferior. As a result, according to the research conducted by the present inventors, at the same dimensions and leakage current (off current), the saturation drain current (on current) of the 3D transistor 1100 may be several times higher (e.g., more than twice) than that of the planar transistor 1200. Meanwhile, the dimensions of the 3D transistor 1100 can be reduced to maintain the same switching speed and leakage current as the planar transistor 1200. Furthermore, to further improve the electrical performance of the I / O circuit, HKMG can be used in the gate structure 1108 of the 3D transistor 1100 that is not used by the planar transistor 1200 with larger dimensions.

[0092] 11A and 11B, in some implementations, the gate electrode 1109 of the 3D transistor 1100 in the I / O circuitry of the memory device 200 includes a metal such as Cu. In some implementations, the gate dielectric 1107 of the 3D transistor 1100 includes a high-k dielectric such as hafnium zirconium dioxide, titanium dioxide, or any other dielectric having a dielectric constant higher than silicon nitride, e.g., greater than 3.9. That is, HKMG can be used to form the gate structure 1108 of the 3D transistor 1100 in the I / O circuitry of the memory device 200. It is understood that in some examples, gate poly and gate oxide can also be used as the gate structure 1108.

[0093] In some implementations, the thickness (T) of the gate dielectric 1107 is between 1.8 nm and 10 nm, as shown in Figure 11B. For example, the thickness of the gate dielectric 1107 can be between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The thickness of the gate dielectric 1107 may be greater (e.g., more than 1x) than the thickness of a 3D transistor (e.g., FinFET) used in logic devices using advanced technology nodes (e.g., less than 22 nm) and may be commensurate with the LLV voltage range applied to the I / O circuitry, as described in detail above, such as 0.9V to 2.0V (e.g., 1.2V).

[0094] In some implementations, the width (W) of the 3D semiconductor body 1104 is between 10 nm and 180 nm, as shown in FIG. 11B. The width of the 3D semiconductor body 1104 can refer to the width of the top of the 3D semiconductor body 1104 (e.g., top critical dimension (CD)), as shown in FIG. 11B. For example, the width of the 3D semiconductor body 1104 may be between 30 nm and 100 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The width of the 3D transistor 1100 may be larger (e.g., by a factor of 1 or more) than the width of a 3D transistor (e.g., FinFET) used in logic devices using advanced technology nodes (e.g., less than 22 nm). On the other hand, the width of the 3D transistor 1100 may be smaller than the width of a planar transistor 1200 used in I / O circuits of existing memory devices. It will be appreciated that in some instances, the 3D semiconductor body 1104 may have a “dumbbell” shape in which the width of the 3D semiconductor body 1104 on the two sides where the source and drain 1106 are formed is greater than the width of the semiconductor body 1104 between the source and drain 1106 due to a relatively small width of the 3D semiconductor body 1104 that is not sufficient to form the source and drain 1106.

[0095] In some implementations, the channel length of the 3D transistor 1100 between the source and drain 1106 is between 30 nm and 180 nm. The channel length of the 3D transistor 1100 is determined by the distance between the source and drain 1106, i.e., the distance between the gate structure in contact with the top surface of the channel. 1108The term "channel length" can refer to a dimension of the 3D transistor 1100. For example, the channel length of the 3D transistor 1100 may be 50 nm to 120 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The channel length of the 3D transistor 1100 may be larger (e.g., by more than a factor of 1) than the channel length of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm). On the other hand, the channel length of the 3D transistor 1100 may be shorter than the planar transistor 1200 used in the I / O circuitry of existing memory devices.

[0096] In some implementations, as shown in FIG. 11B, the height (H) of the 3D semiconductor body 1104 is between 40 nm and 300 nm. For example, the height of the 3D semiconductor body 1104 may be between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The height of the 3D semiconductor body 1104 may be higher (e.g., by a factor of 1 or more) than the height of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm).

[0097] In some implementations, as shown in FIG. 11B, the thickness (t) of the trench isolation 1103 is the same as the height of the 3D semiconductor body 1104. For example, the thickness of the trench isolation 1103 may be 50 nm to 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The thickness of the trench isolation 1103 may be greater (e.g., by a factor of 1 or more) than the thickness of a 3D transistor (e.g., FinFET) used in logic devices using advanced technology nodes (e.g., less than 22 nm).

[0098] According to some aspects of the present disclosure, as shown in FIG. 13, the LV circuit 904 of the memory device 200 may be represented by, for example, a page buffer 304. The page buffer 304 may be configured to buffer data read from or programmed into the memory cell array 201. In some implementations, the page buffer 304 is supplied with a voltage of 2V to 3.3V, for example, 3.3V, by an LV source 903. According to some aspects of the present disclosure, as shown in FIG. 13, the HV circuit 906 of the memory device 200 may be represented by, for example, a word line driver 308. The word line driver 308 may be configured to drive the memory cell array 201 through the word lines. In some implementations, the word line driver 308 is supplied with a voltage greater than 3.3V, for example, a voltage of 5V to 30V, by an HV source 905.

[0099] FIG. 14 illustrates a schematic circuit diagram of the word line driver 308 and the page buffer 304 of FIG. 13 according to some aspects of the disclosure. In some implementations, the page buffer 304 includes multiple sub-page buffer circuits 1402, each coupled to one 3D NAND memory string 208 via a respective bit line 216. That is, the memory device 200 can include bit lines 216 coupled to the respective 3D NAND memory strings 208, and the page buffer 304 can include sub-page buffer circuits 1402 coupled to the respective bit lines 216 and the 3D NAND memory strings 208. Each sub-page buffer circuit 1402 can include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic, sense circuits, etc. In some implementations, each sub-page buffer circuit 1402 is configured to store sense data, e.g., sense currents, received from the respective bit lines 216 corresponding to read data. Each sub-page buffer circuit 1402 can also be configured to output the stored sensing data during a read operation. Each sub-page buffer circuit 1402 can be further configured to store program data and output the stored program data to a respective bit line 216 during a program operation.

[0100] 14, each sub-page buffer circuit 1402 may include multiple transistors, such as 3D transistors 2000, disclosed in detail below with respect to FIGS. 20A and 20B. The 3D transistors 2000 may be an example of a 3D transistor 500 suitable for forming an element of the sub-page buffer circuit 1402 in the page buffer 304. In some implementations, the 3D transistors 2000 in the page buffer 304 are coupled to bit lines 216. Thus, the 3D transistors 2000 in the page buffer 304 may be coupled to the memory cell array 201 via the bit lines 216.

[0101] In some implementations, the word line driver 308 includes multiple string drivers 1404 (aka driving elements) each coupled to a word line 218. The word line driver 308 may also include multiple local word lines 1406 (LWL) each coupled to a string driver 1404. Each string driver 1404 may include a gate coupled to a decoder (not shown), a source / drain coupled to the respective local word line 1406, and another source / drain coupled to the respective word line 218. In some memory operations, the decoder may select a particular string driver 1404 by, for example, applying a voltage signal to each local word line 218 that is greater than the threshold voltage of the string driver 1404 and a voltage (e.g., a program voltage, a pass voltage, or an erase voltage) such that a voltage is applied to the respective local word line 1406 by each selected string driver 1404. In response, the decoder may deselect a particular string driver 1404, for example, by applying a voltage signal less than the threshold voltage of the string driver 1404, such that each deselected string driver 1404 causes its respective word line 218 to float during memory operations.

[0102] 14, each string driver 1404 may include one or more transistors, such as a 3D transistor 2100, disclosed in detail below with respect to FIGS. 21A and 21B. The 3D transistor 2100 may be an example of a 3D transistor 500 suitable for forming an element of a string driver 1404 in a word line driver 308. In some implementations, the 3D transistor 2100 in the word line driver 308 is coupled to a word line 218. Thus, the 3D transistor 2100 in the word line driver 308 may be coupled to the memory cell array 201 via the word line 218.

[0103] 15, in some implementations, the memory cell array 201 is arranged in multiple planes 1502, each having multiple blocks 204 and its own page buffer 304. That is, the memory device 200 may include multiple planes 1502 of memory cells 206 and multiple page buffers 304 respectively coupled to the multiple planes 1502. Although not shown in FIG. 15, it will be appreciated that in some examples, each plane 1502 may have its own set of page buffers 304, row decoders / word line drivers 308, and column decoders / bit line drivers 306, such that the control logic 312 may control the operation of the multiple planes 1502 in parallel in a synchronous or asynchronous manner to increase the operating speed of the memory device 200. 2 and 14, it is understood that as the number of memory cells increases due to an increase in the number of planes 1502, blocks 204, and / or 3D NAND memory strings 208 (bit lines 216), the number of page buffers 304 and the number of sub-page buffer circuits 1402 within each page buffer 304 may increase. Thus, unless the device size of each transistor forming the sub-page buffer circuit 1402 shrinks, the total area of ​​the page buffer 304 continues to increase. Similarly, the number of string drivers 1404 may increase as the number of memory cells increases due to an increase in the number of planes 1502, blocks 204, and / or rows 220 (word lines 218). Thus, unless the device size of each transistor forming the string drivers 1404 shrinks, the total area of ​​the word line drivers 308 continues to increase.

[0104] Also, in a 3D memory device 100 or 101 in which peripheral circuits and a memory cell array are stacked on top of each other in a joint chip, the size of the 3D memory device 100 or 101 depends on the larger size of the first or second semiconductor structure 102 or 104. As shown in FIG. 16, as the area of ​​the page buffer 304 increases continuously, the size of the second semiconductor structure 104 (e.g., shown in FIG. 1A and FIG. 1B) having the page buffer 304, the word line driver 308, and other peripheral circuits 1600 (e.g., I / O circuits, etc.) may eventually be larger than the size of the first semiconductor structure 102 having the memory cell array, and thus dominate the size of the 3D memory device 100 or 101. As a result, to compensate for the increasing size of memory device 200 (particularly 3D memory device 100 or 101), the device size of each transistor forming page buffer 304 and word line driver 308 must be reduced without significantly sacrificing performance, such as transistor current leakage, as well as manufacturing yield and cost, as discussed above.

[0105] As previously mentioned, 3D transistors have a larger gate control area, higher on-current, and lower off-current compared to planar transistors used to form existing memory peripheral circuits such as sub-page buffer circuits and string drivers, allowing device dimensions to be scaled down without sacrificing much of the performance, such as leakage current and manufacturing complexity and cost. For example, FIG. 17 shows a design layout of a planar transistor in a word line driver or page buffer, and in comparison, FIG. 18 shows a design layout of a 3D transistor in the word line driver 308 or page buffer 304 of FIG. 13 according to some aspects of the present disclosure.

[0106] As shown in FIG. 17 and FIG. 18, the width (W) (i.e., channel width) of the active area and / or the length (L) (i.e., channel length) of the gate structure may be affected by switching from planar transistors to 3D transistors. As a result, the width pitch (PW) and / or length pitch (PL) of the word line driver 308 or the page buffer 304 may be reduced. In some implementations, for the page buffer 304, forming the sub-page buffer circuit 1402 using planar transistors can only achieve a minimum channel width (W1) of 180 nm without introducing significant leakage current increase. In contrast, the inventors' research has shown that forming the sub-page buffer circuit 1402 using 3D transistors can keep the channel width (W2) below 180 nm without introducing significant leakage current increase. For example, for the same leakage current, by replacing planar transistors with 3D transistors when forming the subpage buffer circuit 1402, the pitch in the width direction can be reduced by 5% to 50% (e.g., 25%), thereby reducing the total area of ​​the page buffer 304. Furthermore, since the bit lines 216 can be arranged along the width direction, by reducing the pitch along the width direction of the subpage buffer circuit 1402, more bit lines 216 and 3D NAND memory strings 208 can be accommodated.

[0107] In some implementations, for word line drivers 308 that use 3D transistors instead of planar transistors to form string drivers 1404, similar to page buffer 304, the channel width can be reduced, for example from 1,900 nm to 500 nm, without introducing significant leakage current increase, thereby reducing the total area of ​​word line driver 308. Also, by replacing planar transistors with 3D transistors in string driver 1404, the channel length can be reduced. As a result, the distance between the gate structure and the well boundary can be increased by using 3D transistors, thereby increasing the margin for breakdown voltage (BV), which is an important characteristic of HV circuits 906 such as word line driver 308. Furthermore, the reduction in pitch along the length of string driver 1404 can also accommodate more word lines 218, since word lines 218 can be arranged along the length. The size reduction of the string driver 1404 allows more string drivers 1404 to face the staircase structure of the bonded 3D memory device (e.g., 3D memory devices 800 and 801), thus reducing metal routing and metal layers. In some implementations, for the word line driver 308 or any other HV circuit 906, the channel length (L2) is larger than the channel width (W2) of the 3D transistor shown in FIG. 18, which is different from the planar transistor forming the word line driver 308 (e.g., shown in FIG. 17). It is understood that for the word line driver 308 or any other HV circuit 906, unlike that shown in FIG. 18, the source / drain width (W2') of the 3D transistor may be the same as the channel width (W2, i.e., the width of the 3D semiconductor body / active area between the source and drain) of the 3D transistor, whereby the 3D semiconductor body of the 3D transistor does not have a dumbbell shape in a plan view, but rather has a uniform width along the channel length direction.

[0108] For example, FIG. 19 illustrates a cross-sectional side view of a 3D memory device 1900 including a string driver having 3D transistors according to some aspects of the disclosure. The 3D memory device 1900 may be an example of a 3D memory device 800. As illustrated in FIG. 19, the 3D memory device 1900 may include a first semiconductor structure 1902 and a second semiconductor structure 1904 bonded to each other in a face-to-face manner at a bonding interface 1915. It is understood that in other examples, the relative positions of the first and second semiconductor structures may be switched. The first semiconductor structure 1902 may include a stack structure, e.g., a memory stack 1906, including interleaved word lines 1905 and a dielectric layer 1907. In some implementations, edges of the interleaved word lines 1905 and the dielectric layer 1907 define one or more staircase structures 1908 on one or more sides of the memory stack 1906. The staircase structure 1908 can be used to interconnect word lines 1905 via word line contacts 1912. The first semiconductor structure 1902 can also include an array of memory cells, such as an array of 3D NAND memory strings 1910, each extending vertically through the memory stack 1906.

[0109] The second semiconductor structure 1904 may include a plurality of string drivers 1914 each corresponding to a word line 1905. Each string driver 1914 may include a 3D transistor for the HV circuit 906 disclosed herein. As shown in FIG. 19, by using the 3D transistor to reduce each transistor size, the string driver 1914 may face the staircase structure 1908 across the bond interface 1915 so that each word line contact 1912 can electrically connect the word line 1905 and the string driver 1914 pair without routing outside the staircase region in a plan view.

[0110] That is, all string drivers 1914 can be located directly below or directly above the staircase structure 1908. Thus, extra metal routing outside the staircase region and the resulting extra metal layers can be avoided by replacing the planar transistors with 3D transistors in the string drivers 1914. It is understood that the word line contacts 1912 in FIG. 19 are for illustrative purposes only and can include interconnects in various interconnect and bonding layers (not shown) of the 3D memory device 1900. As shown in FIGS. 8A and 8B, the first and second semiconductor structures 1902 and 1904 may include their own interconnect and bonding layers such that the 3D transistors of the string drivers 1914 can be coupled to the word lines 1905 via the first and second interconnect layers and the first and second bonding layers, respectively.

[0111] 20A and 20B show perspective and side views, respectively, of a 3D transistor 2000 in the page buffer 304 of FIG. 13 according to some aspects of the disclosure. The 3D transistor 2000 may be an example of the 3D transistor 500 in FIGS. 5, 6A, and 6B, and is designed to meet the specific requirements of the page buffer 304 or any other suitable LV circuit 904, as described in detail below. FIG. 20B shows a cross-sectional side view of the 3D transistor 2000 of FIG. 20A in the BB plane. As shown in FIGS. 20A and 20B, the 3D transistor 2000 may include a 3D semiconductor body 2004 above a substrate 2002 and a gate structure 2008 contacting multiple sides (e.g., top and both sides) of the 3D semiconductor body 2004. It is understood that the 3D transistor 2000 may be any suitable multi-gate transistor, for example, as shown in FIGS. 7A-7I. In some implementations, the gate structure 2008 includes a gate dielectric 2007 in contact with multiple sides of the 3D semiconductor body 2004 and a gate electrode 2009 in contact with the gate dielectric 2007. As shown in Figures 20A and 20B, the top surface of the gate structure 2008 (e.g., the gate electrode 2009) is curved.

[0112] As shown in Figures 20A and 20B, the 3D transistor 1100 can include a pair of source and drain 2006 in a 3D semiconductor body 2004 separated by a gate structure 2008 in a plan view. As shown in Figure 20B, a trench isolation 2003 (e.g., STI) can be formed in a substrate 2002, whereby the gate structure 2008 can be formed on the trench isolation 2003. In some implementations, the trench isolation 2003 is also formed laterally between adjacent 3D transistors 2000 to reduce leakage current. It is understood that for ease of explanation, the trench isolation 2003 is shown in Figure 20B but not in Figure 20A. It is also understood that the 3D transistor 2000 may include additional components not shown in Figures 20A and 20B, such as wells and spacers.

[0113] As mentioned above, for the 3D transistor 2000 used in the page buffer 304 of the memory device 200, the device dimensions are an important characteristic. On the other hand, the off-state leakage current (I off) to reduce current leakage, which is difficult to achieve with planar transistors. Furthermore, as the LV circuit 904 operates at a voltage of, for example, 2V to 3.3V (e.g., 3V), the size reduction of the 3D transistor 2000 cannot be relied upon for voltage reduction, which is difficult to achieve with 3D transistors used in logic devices using advanced CMOS technology nodes (e.g., below 22 nm). It is understood that the page buffer 304 can include both the HV circuit 906 and the LV circuit 904. In one example, the LV circuit 904 of the page buffer 304 can include the 3D transistor 2000, while the HV circuit 906 of the page buffer 304 can include a planar transistor (e.g., the planar transistor 400). In another example, one of the LV circuits 904 in the page buffer 304 can include a 3D transistor having a structure as in FIG. 11A and FIG. 11B. One of the HV circuits 906 in the page buffer can include a 3D transistor having a structure as in FIG. 21A and FIG. 21B. The two 3D transistors in the page buffer have different structures and different sizes. The size of the 3D transistor in the HV circuit 906 is larger than the size of the 3D transistor in the LV circuit 904. The size of the 3D transistor includes at least one of the channel length of the 3D transistor, the height of the 3D semiconductor body of the 3D transistor, the width of the 3D semiconductor body of the 3D transistor, and the area of ​​the 3D transistor. In some implementations, in the peripheral circuits, the page buffer and other circuits all include 3D transistors, and the 3D transistor in the page buffer includes a single fin and the 3D transistor in the other peripheral circuits includes two or more fins.

[0114] In some implementations, the thickness (T) of the gate dielectric 2007 is between 1.8 nm and 10 nm, as shown in Figure 20B. For example, the thickness of the gate dielectric 2007 can be between 2 nm and 8 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The thickness of the gate dielectric 2007 may be larger (e.g., 1x or more) than that of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm) and may be commensurate with the LV voltage range applied to the page buffer 304, as described in detail above, such as 2V to 3.3V (e.g., 3.3V). Also, compared to the 3D transistor 1100 in the LLV circuit 902, such as an I / O circuit, in some implementations, the thickness of the gate dielectric 2007 of the 3D transistor 2000 is thicker, such as 4nm to 8nm, 5nm to 8nm, etc., due to the higher operating voltage.

[0115] In some implementations, the width (W) of the 3D semiconductor body 2004 is between 10 nm and 180 nm, as shown in FIG. 20B. The width of the 3D semiconductor body 2004 can refer to the width of the top end (e.g., top end CD) of the 3D semiconductor body 2004, as shown in FIG. 20B. For example, the width of the 3D semiconductor body 1104 may be between 30 nm and 100 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The width of the 3D transistor 2000 may be larger (e.g., by a factor of 1 or more) than the width of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm). On the other hand, as mentioned above, the width of the 3D transistor 2000 may be smaller than planar transistors used in page buffers of existing memory devices, for example, larger than 180 nm. It is understood that in some examples, the 3D semiconductor body 2004 may have a "dumbbell" shape, in which the width of the 3D semiconductor body 2004 at the two sides where the source and drain 2006 are formed is larger than the width of the 3D semiconductor body 2004 between the source and drain 2006 due to the relatively small width of the 3D semiconductor body 2004 not being sufficient to form the source and drain 2006. For example, as shown in FIG. 18, the width (W2') of the source / drain of the 3D transistor may be larger than the channel width (W2, i.e., the width of the 3D semiconductor body / active area between the source and drain) of the 3D transistor.

[0116] In some implementations, the channel length of the 3D transistor 2000 between the source and drain 2006 is between 30 nm and 180 nm. The channel length of the 3D transistor 2000 can refer to the distance between the source and drain 2006, i.e., the dimension of the gate structure 2008 that contacts the top surface of the channel. For example, the channel length of the 3D transistor 2000 can be between 50 nm and 120 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The channel length of the 3D transistor 2000 can be greater (e.g., by a factor of 1 or more) than the channel length of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm). On the other hand, the channel length of the 3D transistor 2000 may be shorter than the planar transistors used in the page buffers of existing memory devices, for example, greater than 180 nm.

[0117] In some implementations, as shown in FIG. 20B, the height (H) of the 3D semiconductor body 2004 is between 40 nm and 300 nm. For example, the height of the 3D semiconductor body 2004 may be between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The height of the 3D semiconductor body 2004 may be higher (e.g., by a factor of 1 or more) than the height of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm).

[0118] In some implementations, as shown in FIG. 20B, the thickness (t) of the trench isolation 2003 is the same as the height of the 3D semiconductor body 2004. For example, the thickness of the trench isolation 2003 may be 50 nm to 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The thickness of the trench isolation 2003 may be greater (e.g., by a factor of 1 or more) than the thickness of a 3D transistor (e.g., FinFET) used in logic devices using advanced technology nodes (e.g., less than 22 nm).

[0119] The manufacturing yield and cost of the 3D transistor 2000 can also be improved, for example, by changing materials and / or simplifying structures and processes, as compared to 3D transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., below 22 nm). In some implementations, instead of using HKMG, the gate electrode 2009 of the 3D transistor 2000 in the page buffer 304 of the memory device 200 includes polysilicon, e.g., polysilicon doped with nitride (N). In some implementations, the gate dielectric 2007 of the 3D transistor 2000 includes silicon oxide. That is, gate poly and gate oxide can be used as the gate structure 2008 to reduce manufacturing complexity and cost. In some implementations, the 3D transistor 2000 does not include stressors in the source and drain 2006 and / or does not use strained semiconductor materials in the 3D semiconductor body 2004 to reduce manufacturing complexity and cost.

[0120] 21A and 21B show perspective and side views, respectively, of a 3D transistor 2100 in the word line driver 308 of FIG. 13 according to some aspects of the disclosure. The 3D transistor 2100 may be an example of the 3D transistor 500 in FIGS. 5, 6A, and 6B, and is designed to meet the specific requirements of the word line driver 308 or any other suitable HV circuit 906. FIG. 21B shows a cross-sectional side view of the 3D transistor 2100 of FIG. 21A in the BB plane. As shown in FIGS. 21A and 21B, the 3D transistor 2100 may include a 3D semiconductor body 2104 above a substrate 2102 and a gate structure 2108 contacting multiple sides (e.g., top and both sides) of the 3D semiconductor body 2104. It is understood that the 3D transistor 2100 may be any suitable multi-gate transistor, for example, as shown in FIGS. 7A-7I. In some implementations, the gate structure 2108 includes a gate dielectric 2107 in contact with multiple sides of the 3D semiconductor body 2104 and a gate electrode 2109 in contact with the gate dielectric 2107.

[0121] As shown in Figures 21A and 21B, the 3D transistor 2100 may also include a pair of source and drain 2106 in the 3D semiconductor body 2104 separated by a gate structure 2108 in a plan view. Since a relatively high voltage is applied to the 3D transistor 2100 used in the HV circuit 906, the 3D transistor 2100 may further include a drift region 2110 in the 3D semiconductor body 2104. The source and drain 2106 may be in contact with the drift region 2110. It is understood that in some examples, the 3D transistors 1100 and 2000 used in the LLV circuit 902 and the LV circuit 904 may not include the drift region 2110 because the voltage applied to the 3D transistors 1100 and 2000 is lower and destruction is less of a concern. The drift region 2110 can be a doped region in the 3D semiconductor body 2104 that is similar to the source and drain 2106, but has a lower doping concentration than the source and drain 2106. That is, the source and drain 2106 can be a heavily doped region formed in a lightly doped region (i.e., drift region 2110) in the 3D transistor 2100. In some implementations, the drift region 2110 and the source and drain 2106 are doped with N-type dopants such that the source and drain 2106 are a heavily N-type doped region (N+) in a lightly N-type doped region (N, i.e., drift region 2110). To sustain the relatively high voltages applied to the 3D transistor 2100 used in the HV circuit 906 and avoid breakdown, in some implementations, the distance (d1) between the source / drain 2106 and the gate structure 2108 is set to 100 V / V. Main unitIt is larger than the distance (d2) from the edge of 2104. For example, d1 may be at least twice d2. As shown in FIG. 21B, trench isolation 2103 (e.g., STI) can be formed in substrate 2102, whereby gate structure 2108 can be formed on trench isolation 2103. In some implementations, trench isolation 2103 is also formed laterally between adjacent 3D transistors 2100 to reduce leakage current. For ease of explanation, it is understood that trench isolation 2103 is shown in FIG. 21B but not in FIG. 21A. It is also understood that 3D transistor 2100 may include additional components not shown in FIGS. 21A and 21B, such as wells and spacers.

[0122] As described above, in the case of 3D transistor 2100 used in word line driver 308 of memory device 200, device dimensions are an important characteristic. On the other hand, it is also impossible to increase the leakage current (I off ) in the off state to reduce current leakage, which was difficult to achieve with planar transistors. Further, for example, as HV circuit 906 operating at a voltage exceeding 3.3V (e.g., 5V to 30V), reducing the size of 3D transistor 2100 cannot rely on voltage reduction that is difficult to achieve by 3D transistors used in logic devices using advanced CMOS technology nodes (e.g., less than 22nm).

[0123] In some implementations, the thickness (T) of the gate dielectric 2107 is greater than 10 nm, as shown in Figure 21B. For example, the thickness of the gate dielectric 2107 can be between 20 nm and 80 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The thickness of the gate dielectric 2107 may be significantly larger (e.g., an order of magnitude or more) than that of 3D transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., less than 22 nm) and may be commensurate with the HV voltage range applied to the word line driver 308, as described in detail above, such as greater than 3.3 V (e.g., 5 V to 30 V). Also, compared to the 3D transistor 1100 in the LLV circuitry 902, such as the I / O circuitry, and the 3D transistor 2000 in the LV circuitry 904, such as the page buffer 304, in some implementations, the thickness of the gate dielectric 2107 of the 3D transistor 2100 is thicker due to the higher operating voltage.

[0124] In some implementations, the width (W) of the 3D semiconductor body 2104 is greater than 100 nm, as shown in FIG. 21B. The width of the 3D semiconductor body 2104 can refer to the width of the top end (e.g., top end CD) of the 3D semiconductor body 2104, as shown in FIG. 21B. For example, the width of the 3D semiconductor body 1104 may be 300 nm to 1,000 nm (e.g., 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1,000 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The width of the 3D transistor 2100 may be significantly greater (e.g., an order of magnitude or more) than the width of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm). Meanwhile, as mentioned above, the width of the 3D transistor 2100 may be smaller than the planar transistor used in the word line driver of the existing memory device, for example, 1,900 nm. Also, compared with the 3D transistor 1100 in the LLV circuit 902 such as the I / O circuit and the 3D transistor 2000 in the LV circuit 904 such as the page buffer 304, in some implementations, the width of the 3D semiconductor body 2104 of the 3D transistor 2100 is larger due to the higher operating voltage. It is understood that in some examples, unlike some examples in which the 3D semiconductor bodies 1104 and 2004 have a dumbbell shape in a plan view, the 3D semiconductor body 1104 can have a relatively large width sufficient to form the source and drain 2106, so that the 3D semiconductor body 2104 does not have a dumbbell shape in a plan view, i.e., has a uniform width.

[0125] In some implementations, the channel length of the 3D transistor 2100 between the source and drain 2106 is greater than 120 nm. The channel length of the 3D transistor 2100 can refer to the distance between the source and drain 2106, i.e., the dimension of the gate structure 2108 that contacts the top surface of the channel. For example, the channel length of the 3D transistor 2100 can be 500 nm to 1,200 nm (e.g., 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1,000 nm, 1,100 nm, 1,200 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The channel length of the 3D transistor 2100 can be significantly greater (e.g., by an order of magnitude or more) than the channel length of a 3D transistor (e.g., FinFET) used in logic devices using advanced technology nodes (e.g., less than 22 nm). Meanwhile, the channel length of the 3D transistor 2100 may be shorter, e.g., 900 nm, than planar transistors used in word line drivers of existing memory devices. Also, in some implementations, the channel length of the 3D transistor 2100 is larger due to a higher operating voltage compared to the 3D transistor 1100 in the LLV circuitry 902, such as the I / O circuitry, and the 3D transistor 2000 in the LV circuitry 904, such as the page buffer 304.

[0126] In some implementations, as shown in FIG. 21B, the height (H) of the 3D semiconductor body 2104 is greater than 50 nm. For example, the height of the 3D semiconductor body 2104 may be 300 nm to 500 nm (e.g., 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The height of the 3D semiconductor body 2104 may be significantly greater (e.g., an order of magnitude or more) than the height of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm). Also, compared to the 3D transistor 1100 in the LLV circuit 902, such as the I / O circuit, as well as the 3D transistor 2000 in the LV circuit 904, such as the page buffer 304, in some implementations, the height of the 3D semiconductor body 2104 of the 3D transistor 2100 is greater due to a higher operating voltage.

[0127] In some implementations, the thickness (t) of the trench isolation 2103 is smaller, such as one-third (1 / 3) or less of the height of the 3D semiconductor body 2104, as shown in FIG. 21B. For example, the thickness of the trench isolation 2103 may be between 100 nm and 200 nm (e.g., 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, any range bounded by a lower limit by any of these values, or any range defined by any two of these values). The thickness of the trench isolation 2103 may be larger (e.g., by a factor of 1 or more) than the thickness of a 3D transistor (e.g., FinFET) used in a logic device using an advanced technology node (e.g., less than 22 nm). Also, in some implementations, the thickness of the trench isolation 2103 of the 3D transistor 2100 is smaller due to the higher operating voltage compared to the 3D transistor 1100 in the LLV circuit 902, such as the I / O circuit, and the 3D transistor 2000 in the LV circuit 904, such as the page buffer 304.

[0128] The manufacturing yield and cost of the 3D transistor 2100 can also be improved, for example, by changing materials and / or simplifying structures and processes, as compared to 3D transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., below 22 nm). In some implementations, instead of using HKMG, the gate electrode 2109 of the 3D transistor 2100 in the word line driver 308 of the memory device 200 includes polysilicon, for example, polysilicon doped with P-type dopants or N-type dopants, and the gate dielectric 2107 of the 3D transistor 2100 includes silicon oxide doped with nitrogen (N2). In some implementations, the gate dielectric 2107 of the 3D transistor 2100 includes silicon oxide. That is, the gate poly and gate oxide can be used as the gate structure 2108 to reduce manufacturing complexity and cost. In some implementations, the 3D transistor 2100 does not include stressors at the source and drain 2106 and / or does not use strained semiconductor materials in the 3D semiconductor body 2104 to reduce manufacturing complexity and costs.

[0129] Consistent with the scope of the present disclosure, the peripheral circuit 202 may include an LLV circuit 902 (e.g., I / O circuitry of the interface 316 and data bus 318) having a 3D transistor 1100, an LV circuit 904 (e.g., part of the page buffer 304) having a 3D transistor 2000, and an HV circuit 906 (e.g., the word line driver 308) having a 3D transistor 2100. The LLV source 901 is coupled to the LLV circuit 902 and may be configured to provide Vdd1 to the 3D transistor 1100, the LV source 903 is coupled to the LV circuit 904 and may be configured to provide Vdd2 to the 3D transistor 2000, and the HV source 905 is coupled to the HV circuit 906 and may be configured to provide Vdd3 to the 3D transistor 2100, where Vdd3>Vdd2>Vdd1. For example, the 3D transistor 2100 in the word line driver 308 can be coupled to the memory cell array 201 via the word line 218, and the 3D transistor 2000 in the page buffer 304 can be coupled to the memory cell array 201 via the bit line 216. Due to the different operating voltages, the gate dielectric thickness (T) of the 3D transistor 2100 can be larger than the gate dielectric thickness of the 3D transistor 2000, which can be larger than the gate dielectric thickness of the 3D transistor 1100. As described in detail above, due to the higher operating voltages applied to the 3D transistor 2100, it is understood that other sizes / dimensions of the 3D transistor 2000, such as the channel length (L), the height (H) of the 3D semiconductor body, the width (W) of the 3D semiconductor body, etc., may be larger than the size / dimensions of the 3D transistor 2100 and / or the 3D transistor 2100. In some implementations, unlike the 3D transistors 1100 and 2000 of the LLV circuit 902 and the LV circuit 904, the 3D transistor 2100 of the HV circuit 906 further includes a drift region 2110 having a doping concentration lower than the doping concentration of the source / drain 2106 to maintain a voltage of Vdd3 higher than Vdd2 and Vdd1.In some implementations, unlike the 3D transistors 2000 and 2100 that have poly-gate and gate oxide gate structures 2008 and 2108, the 3D transistor 1100 has an HKMG gate structure 1108 to achieve faster switching speeds than the 3D transistors 2000 and 2100.

[0130] FIG. 25 illustrates a block diagram of a system 2500 having a memory device according to some aspects of the disclosure. The system 2500 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As illustrated in FIG. 25, the system 2500 can include a host 2508 and a memory system 2502 having one or more memory devices 2504 and a memory controller 2506. The host 2508 can be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 2508 can be configured to transmit and receive data to and from the memory device 2504.

[0131] Memory devices 2504 can be any memory device disclosed herein, such as 3D memory devices 100 and 101, memory device 200, 3D memory devices 800, 801, and 1900. In some implementations, each memory device 2504 includes peripheral circuitry having 3D transistors, as described in detail above.

[0132] The memory controller 2506, according to some implementations, is coupled to the memory device 2504 and the host 2508 and configured to control the memory device 2504. The memory controller 2506 can manage data stored in the memory device 2504 and communicate with the host 2508. In some implementations, the memory controller 2506 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 2506 is designed to operate in high duty cycle environments SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptop computers, and enterprise storage arrays. The memory controller 2506 can be configured to control operations of the memory device 2504, such as read, erase, and program operations. The memory controller 2506 may also be configured to manage various functions related to data stored or to be stored in the memory device 2504, including, but not limited to, bad block management, garbage collection, logical-physical address translation, wear leveling, etc. In some implementations, the memory controller 2506 is further configured to process error correction codes (ECC) on data read from or written to the memory device 2504. Any other suitable functions, such as formatting the memory device 2504, may also be performed by the memory controller 2506. The memory controller 2506 may communicate with an external device (e.g., a host 2508) according to a particular communication protocol.For example, the memory controller 2506 can communicate with external devices via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0133] The memory controller 2506 and one or more memory devices 2504 may be incorporated into various types of storage devices and may be included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 2502 may be implemented and packaged into different types of end electronic products. In one example shown in FIG. 26A, the memory controller 2506 and the single memory device 2504 may be incorporated into a memory card 2602. The memory card 2602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, and the like. The memory card 2602 may further include a memory card connector 2604 that couples the memory card 2602 to a host (e.g., the host 2508 of FIG. 25). 26B, the memory controller 2506 and the multiple memory devices 2504 may be incorporated into an SSD 2606. The SSD 2606 may further include an SSD connector 2608 that couples the SSD 2606 to a host (e.g., the host 2508 of FIG. 25). In some implementations, the storage capacity and / or operating speed of the SSD 2606 is greater than the storage capacity and / or operating speed of the memory card 2602.

[0134] 22A-22J illustrate a manufacturing process for forming a 3D transistor according to some aspects of the present disclosure. FIG. 23 illustrates a flow chart of a method 2300 for forming an exemplary 3D memory device according to some aspects of the present disclosure. FIG. 24A illustrates a flow chart of a method 2400 for forming a 3D transistor according to some aspects of the present disclosure. FIG. 24B illustrates a flow chart of another method 2401 for forming a 3D transistor according to some aspects of the present disclosure. Examples of 3D memory devices illustrated in FIG. 23 include 3D memory devices 800, 801, and 899 depicted in FIGS. 8A-8C. Examples of 3D transistors depicted in FIGS. 22A-22J, 24A, and 24B include 3D transistors 500, 1100, 2000, and 2100 depicted in FIGS. 5, 11A, 11A, 20A, and 21A. 22A-22J, 23, 24A, and 24B are discussed collectively. It is understood that the operations shown in methods 2300, 2400, and 2401 are not exhaustive and that other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a different order than that shown in FIGS. 23, 24A, and 24B.

[0135] 23, the method 2300 begins at step 2302, where a first semiconductor structure including an array of memory cells is formed on a first substrate. In some implementations, an array of 3D NAND memory strings is formed to form the array of memory cells. For example, as shown in FIG. 8B, an array of 3D NAND memory strings 817 is formed on a substrate 809. The method 2300 proceeds to step 2304, as shown in FIG. 23, where a first bonding layer including a plurality of first bonding contacts is formed above the array of NAND memory strings. For example, as shown in FIG. 8B, a bonding layer 829 including bonding contacts 855 is formed above the array of 3D NAND memory strings 817.

[0136] The method 2300 proceeds to step 2306, as shown in Figure 23, where a second semiconductor structure including peripheral circuitry including a 3D transistor is formed on the second substrate. The recessed gate transistor may include a recessed gate structure that protrudes into the second substrate. To form the second semiconductor structure, a 3D semiconductor body is formed from the second substrate and a gate structure is formed in contact with multiple sides of the 3D semiconductor body.

[0137] The 3D semiconductor body can be formed using various manufacturing processes. In some implementations, as shown in FIG. 24A, in step 2402, a trench isolation is formed in a second substrate surrounding a portion of the second substrate to form a 3D semiconductor body. The substrate can be a silicon substrate.

[0138] As shown in FIG. 22A, trench isolation 2204, such as STI, is formed in silicon substrate 2202 using, for example, wet / dry etching and thin film deposition of silicon oxide. The top surface of trench isolation 2204 can be planarized using, for example, chemical mechanical polishing (CMP). Trench isolation 2204 can divide silicon substrate 2202 into multiple regions in which multiple 3D transistors can be formed, respectively. Before forming trench isolation 2204, sacrificial layer 2206 can be formed to cover the region in which 3D semiconductor body of the 3D transistor is to be formed. In some implementations, a layer of sacrificial material different from silicon substrate 2202 and trench isolation 2204, for example silicon nitride, is deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The deposited sacrificial material layer can then be patterned using lithography and wet / dry etching to form sacrificial layer 2206. Thus, trench isolations 2204 cannot be formed in the portions of silicon substrate 2202 covered by sacrificial layer 2206. As a result, as shown in Fig. 22A, trench isolations 2204 surround the portions of silicon substrate 2202 that are covered by sacrificial layer 2206. Although not shown, wells may then be formed in silicon substrate 2202. Lithography may be used to pattern and align the wells between trench isolations 2204, followed by ion implantation of N-type and / or P-type dopants.

[0139] As shown in Figure 24A, in step 2404, the trench isolation is etched back to expose at least a portion of the second substrate portion. As shown in Figure 22B, according to some implementations, a recess is formed in the trench isolation 2204 by etching back the trench isolation 2204 using, for example, wet / dry etching, to expose at least a portion of the portion of the silicon substrate 2202 (e.g., Figure 22A) covered by the sacrificial layer 2206 and surrounded by the trench isolation 2204. As a result, according to some implementations, the exposed portion of the silicon substrate 2202 now becomes a 3D semiconductor body 2208 above the resulting top surface of the silicon substrate 2202 and the trench isolation 2204 after recess formation (etch back).

[0140] Instead of forming the 3D semiconductor body after forming the trench isolation as shown in Figures 22A, 22B, and 24A, the 3D semiconductor body may be formed before forming the trench isolation as shown in Figures 22H, 22I, and 24B. In some implementations, as shown in Figure 24B, in step 2403, a trench is formed in the second substrate to surround a portion of the second substrate to form the 3D semiconductor body. As shown in Figure 22H, a trench 2209 is formed in the silicon substrate 2202 by etching the silicon substrate 2202 using, for example, dry / wet etching. In some implementations, a sacrificial layer 2206 is formed before etching to cover a portion of the silicon substrate 2202 in which the 3D semiconductor body 2208 will be formed. As a result, according to some implementations, a portion of the silicon substrate 2202 is surrounded by the trench 2209.

[0141] As shown in FIG. 24B, in step 2405, an isolation material is deposited to partially fill the trench and expose at least a portion of the second substrate portion. As shown in FIG. 22I, a trench isolation 2204 is formed in the trench 2209 by depositing an isolation material, such as silicon oxide, in the trench 2209 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof (e.g., as shown in FIG. 22H). The deposition rate and / or duration can be controlled to partially fill the trench 2209 and expose at least a portion of the silicon substrate 2202 portion to form a 3D semiconductor body 2208. As a result, according to some implementations, the exposed portion of the silicon substrate 2202 becomes the 3D semiconductor body 2208 above the resulting top surface of the silicon substrate 2202 and the trench isolation 2204 after the formation of the trench isolation 2204.

[0142] Referring again to FIG. 22C, after formation of the 3D semiconductor body 2208, whether formed before or after the formation of the trench isolation 2204, the sacrificial layer 2206 (e.g., as shown in FIG. 22B and FIG. 22I) is removed, for example, by wet / dry etching.

[0143] In some implementations, a gate dielectric layer and a gate electrode layer are subsequently formed on the multiple sides of the 3D semiconductor body in step 2406 to form a gate structure, as shown in Figures 24A and 24B. As shown in Figure 22D, a gate dielectric layer 2210, such as a silicon oxide layer or a high-k dielectric layer, is formed on multiple sides of the 3D semiconductor body 2208. In some implementations, a layer of dielectric material is deposited on all exposed surfaces of the 3D semiconductor body 2208 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations where the gate dielectric layer 2210 is a silicon oxide layer, dry / wet oxidation is used to oxidize a portion of the silicon in the 3D semiconductor body 2208 at the exposed surfaces to form the gate dielectric layer 2210.

[0144] 22E, a gate electrode layer 2212, such as a doped polysilicon layer or a metal layer, is formed on the gate dielectric layer 2210. In some implementations, a layer of a semiconductor or conductive material is deposited on the gate dielectric layer 2210 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations where the gate electrode layer 2212 is a polysilicon layer, in-situ doping is performed to dope the polysilicon layer, or a doping process, such as ion implantation, is performed after deposition to dope the polysilicon layer.

[0145] In some implementations, to form a gate structure, the gate electrode layer is patterned to form a gate electrode in step 2408, as shown in Figures 24A and 24B. As shown in Figure 22F, the gate electrode layer 2212 (e.g., as shown in Figure 22E) is patterned to form a gate electrode 2214, for example, using lithography and wet / dry etching.

[0146] As shown in Figures 24A and 24B, in step 2410, a source and a drain are formed in the 3D semiconductor body. In some implementations, the portions of the 3D semiconductor body that are not covered by the gate structure are doped to form the source and drain. As shown in Figure 22G, a pair of source and drain 2216 is formed in the 3D semiconductor body 2208 by doping the portions of the 3D semiconductor body 2208 that are not covered by the gate electrode 2214, for example, using ion implantation. As a result, according to some implementations, the source and drain 2216 are not formed directly under the gate electrode 2214 so that a channel can be formed between the source and drain 2216. Although not shown, in some implementations, a portion of the gate dielectric layer 2210 covering the source and drain 2216 is removed, for example, by dry etching / we etching, to expose portions of the source and drain 2216 where source and drain contacts (not shown) can be formed.

[0147] According to some implementations, a 3D transistor having a 3D semiconductor body 2208, a gate electrode 2214, a gate dielectric layer 2210, and a source and drain 2216 is thereby formed. It is understood that the above-mentioned manufacturing process for forming a 3D transistor is compatible with the manufacturing process for forming a planar transistor, so that in some examples, a planar transistor having the same trench isolation depth as the 3D transistor or a different trench isolation depth can be formed using the same manufacturing process described above. In one example, the manufacturing process described in FIG. 24A can be used to form a 3D transistor and a planar transistor having the same trench isolation depth. The same trench isolation depth may be determined by the formation of the trench isolation 2204 before the formation of the 3D semiconductor body 2208. In another example, the manufacturing process described in FIG. 24B can be used to form a 3D transistor and a planar transistor having different trench isolation depths.

[0148] As shown in Figures 22A-22G, 3D transistors may be formed in a first region 2201 and planar transistors may be formed in a second region 2203 of the same silicon substrate 2202 to form 3D transistors and planar transistors with the same trench isolation depth. As shown in Figure 22A, trench isolation 2204, such as STI, may be formed in both the first region 2201 and the second region 2203 to form 3D transistors and planar transistors, respectively, in the same fabrication process described in detail above with respect to Figure 22A. Thus, the trench isolation 2204 for the 3D transistors and the trench isolation 2204 for the planar transistors may have the same depth. As shown in Figure 22B, etchback of the trench isolation 2204 may be performed only in the first region 2201 and not in the second region 2203. In other words, according to some implementations, the trench isolation 2204 for the planar transistor in the second region 2203 remains unchanged without recess when forming the recess of the trench isolation 2204 for the 3D transistor in the first region 2201. In some implementations, an etch mask is patterned to cover the second region 2203 and expose only the first region 2201 before etching back the trench isolation 2204 in the first region 2201 to protect the trench isolation 2204 in the second region 2203. As shown in FIG. 22C, the sacrificial layer 2206 in both the first and second regions 2201 and 2203 can be removed in the same fabrication process as described in detail above with respect to FIG. 22C. As shown in Figure 22D, the gate dielectric layer 2211 of the planar transistor in the second region 2203 can be formed in the same fabrication process as forming the gate dielectric layer 2210 of the 3D transistor in the first region 2201, as described in detail above with respect to Figure 22D. As shown in Figure 22E, the gate electrode layer 2212 can be formed over the gate dielectric layers 2210 and 2211 in both the first region 2201 and the second region 2203 in the same fabrication process as described in detail above with respect to Figure 22E.As shown in Figure 22F, the gate electrode 2215 of the planar transistor in the second region 2203 can be patterned from the gate electrode layer 2212 in the same fabrication process for patterning the gate electrode 2214 of the 3D transistor in the first region 2201, as described in detail above with respect to Figure 22F. As shown in Figure 22G, the pair of source and drain 2217 of the planar transistor in the second region 2203 can be formed in the same fabrication process for forming the pair of source and drain 2216 of the 3D transistor in the first region 2201, as described in detail above with respect to Figure 22G. Thereby, according to some implementations, the planar transistor having the gate electrode 2215, the gate dielectric layer 2211, and the source and drain 2217 is formed in the same process flow (except for the etch-back process of Figure 22B) for forming the 3D transistor having the 3D semiconductor body 2208, the gate electrode 2214, the gate dielectric layer 2210, and the source and drain 2216.

[0149] It is further understood that 3D transistors having different isolation trench depths, for example for peripheral circuits with different applied voltages (e.g., LLV circuit 902, LV circuit 904, and HV circuit 906), can be formed by varying the recess depth when etching back the trench isolation 2204. As shown in FIG. 22J, the 3D semiconductor body 2219 in the third region 2205 of the silicon substrate 2202 can have a different recess depth than the 3D semiconductor body 2208 in the first region 2201 of FIG. 22D by etching back the different recess depths of the trench isolation 2204 in the first region 2201 and the third region 2205. In some implementations, the 3D semiconductor body 2219 is part of a 3D transistor in the HV circuit 906, and the 3D semiconductor body 2208 is part of a 3D transistor in the LLV circuit 902 and / or the LV circuit 904, and the first recess depth for forming the 3D semiconductor body 2219 is greater than the second recess depth for forming the 3D semiconductor body 2208. In one example, the first recess depth may be between 300 nm and 400 nm, and the second recess depth may be between 50 nm and 100 nm.

[0150] 23, the method 2300 proceeds to step 2308 where a second bonding layer including a plurality of second bonding contacts is formed above the peripheral circuitry. For example, as shown in FIG. 8B, a bonding layer 851 including bonding contacts 853 is formed above the 3D transistor 839 of the peripheral circuitry 835. As shown in FIG. 23, the method 2300 proceeds to step 2310 where the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the array of memory cells is coupled to the peripheral circuitry across the bond interface. The bonding can be a hybrid bond. In some implementations, the second semiconductor structure is above the first semiconductor structure after bonding. In some implementations, the first semiconductor structure is above the second semiconductor structure after bonding.

[0151] As shown in FIG. 8A, a second semiconductor structure 804 having a 3D NAND memory string 838 is flipped upside down. A downward-facing bonding layer 826 is bonded, i.e., bonded in a face-to-face manner, with an upward-facing bonding layer 822, thereby forming a bonding interface 806. In some implementations, a treatment process, such as a plasma treatment, a wet treatment, and / or a thermal treatment, is applied to the bonding surfaces before bonding. After bonding, the bonding contacts 828 in the bonding layer 826 and the bonding contacts 824 in the bonding layer 822 are aligned and in contact with each other so that the 3D NAND memory string 838 can be coupled to the device layer 810 (e.g., peripheral circuits 812 and 814). Similarly, as shown in FIG. 8B, a first semiconductor structure 805 having peripheral circuits 835, 837 is flipped upside down. A downward-facing bonding layer 851 is bonded, i.e., bonded in a face-to-face manner, with an upward-facing bonding layer 829, thereby forming a bonding interface 807. After bonding, bonding contacts 853 in bonding layer 851 and bonding contacts 855 in bonding layer 829 are aligned and in contact with each other so that 3D NAND memory string 817 can be coupled to device layer 831 (e.g., peripheral circuits 835 and 837).

[0152] The method 2300 proceeds to step 2312, as shown in Figure 23, where one of the first and second substrates above the other of the first and second substrates after bonding is thinned. As shown in Figure 8A, the substrate of the second semiconductor structure 804 having the 3D NAND memory string 838 is above the substrate of the first semiconductor structure 802 having the peripheral circuits 812 and 814, so the substrate of the second semiconductor structure 804 is thinned to form the semiconductor layer 848 using CMP and / or etching processes. Similarly, as shown in Figure 8B, the substrate of the first semiconductor structure 805 having the peripheral circuits 835 and 837 is above the substrate of the second semiconductor structure 803 having the 3D NAND memory string 817, so the substrate of the first semiconductor structure 805 is thinned to form the semiconductor layer 833 using CMP and / or etching processes.

[0153] The method 2300 proceeds to step 2314, as shown in Figure 23, where an interconnect layer is formed on the thinned first or second substrate. As shown in Figure 8A, a padded-out interconnect layer 850 is formed above semiconductor layer 848 (thinned top substrate). Similarly, as shown in Figure 8B, a padded-out interconnect layer 843 is formed above semiconductor layer 833 (thinned top substrate).

[0154] According to one aspect of the present disclosure, a 3D memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including peripheral circuitry, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuitry includes 3D transistors. The array of memory cells is coupled to the peripheral circuitry across the bonding interface.

[0155] In some implementations, the 3D transistor is a multi-gate transistor.

[0156] In some implementations, the multi-gate transistor comprises a FinFET.

[0157] In some implementations, the multi-gate transistor includes a GAAFET.

[0158] In some implementations, the 3D transistor comprises a 3D semiconductor body and a gate structure in contact with multiple sides of the 3D semiconductor body. The gate structure can include a gate dielectric and a gate electrode.

[0159] In some implementations, the peripheral circuit includes a first peripheral circuit and a second peripheral circuit, the 3D transistor includes a first 3D transistor of the first peripheral circuit and a second 3D transistor of the second peripheral circuit, the first 3D transistor of the first peripheral circuit receives a first voltage, and the second 3D transistor of the second peripheral circuit receives a second voltage greater than the first voltage.

[0160] In some implementations, the peripheral circuit further includes a third peripheral circuit, the 3D transistor further includes a third 3D transistor of the third peripheral circuit, and the third 3D transistor of the third peripheral circuit receives a third voltage greater than the second voltage.

[0161] In some implementations, the first peripheral circuit includes an I / O circuit, the second peripheral circuit includes at least a portion of a page buffer, and the third peripheral circuit includes a word line driver.

[0162] In some implementations, the first semiconductor structure further includes a plurality of bit lines and a plurality of word lines coupled to the array of memory cells, the second 3D transistor of the second peripheral circuit being coupled to the array of memory cells via at least one of the bit lines, and the third 3D transistor of the third peripheral circuit being coupled to the array of memory cells via at least one of the word lines.

[0163] In some implementations, the gate dielectric thickness of the third 3D transistor is greater than the gate dielectric thickness of the second 3D transistor, and the gate dielectric thickness of the second 3D transistor is greater than the gate dielectric thickness of the first 3D transistor.

[0164] In some implementations, the third 3D transistor further includes a drift region and a source and a drain, where the doping concentration of the drift region is lower than the doping concentration of the source and drain.

[0165] In some implementations, the gate electrode of the first 3D transistor comprises a metal and the gate dielectric of the first 3D transistor comprises a high-k dielectric.

[0166] In some implementations, the 3D semiconductor body of the first 3D transistor or the second 3D transistor has a dumbbell shape in a plan view.

[0167] In some implementations, the gate electrode comprises polysilicon.

[0168] In some implementations, the gate dielectric comprises silicon oxide.

[0169] In some implementations, the width of the 3D semiconductor body is greater than 10 nm, hi some implementations, the width of the 3D semiconductor body is between 30 nm and 1,000 nm.

[0170] In some implementations, the height of the 3D semiconductor body is greater than 40 nm, hi some implementations, the height of the 3D semiconductor body is between 50 nm and 1,000 nm.

[0171] In some implementations, the 3D semiconductor body has a channel length greater than 30 nm, hi some implementations, the 3D semiconductor body has a channel length between 50 nm and 1,500 nm.

[0172] In some implementations, the gate dielectric has a thickness greater than 1.8 nm, hi some implementations, the gate dielectric has a thickness between 2 nm and 100 nm.

[0173] In some implementations, the 3D transistor does not include a stressor.

[0174] In some implementations, the peripheral circuitry does not include planar transistors.

[0175] In some implementations, the peripheral circuitry further includes planar transistors.

[0176] In some implementations, the peripheral circuitry further includes other 3D transistors, other planar transistors, a first trench isolation between the 3D transistors and the other 3D transistors, and a second trench isolation between the planar transistors and the other planar transistors.

[0177] In some implementations, the first trench isolation and the second trench isolation have the same depth.

[0178] In some implementations, the first trench isolation and the second trench isolation have different depths.

[0179] In some implementations, the second trench isolation is deeper than the first trench isolation.

[0180] In some implementations, the first semiconductor structure further includes a first bonding layer including a plurality of first bonding contacts, and the second semiconductor structure further includes a second bonding layer including a plurality of second bonding contacts, the first bonding contacts in contact with the second bonding contacts at a bonding interface.

[0181] In some implementations, the array of memory cells comprises an array of 3D NAND memory strings.

[0182] According to another aspect of the disclosure, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including a peripheral circuit, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuit includes a 3D transistor. The array of memory cells is coupled to the peripheral circuit across the bonding interface. The system also includes a memory controller coupled to the memory device and configured to control the array of memory cells via the peripheral circuit.

[0183] In some implementations, the system further includes a host coupled to the memory controller and configured to transmit or receive data.

[0184] According to yet another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A first semiconductor structure including an array of memory cells is formed on a first substrate. A second semiconductor structure including peripheral circuitry is formed on a second substrate. The peripheral circuitry includes 3D transistors. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the array of memory cells is coupled to the peripheral circuitry across a bond interface.

[0185] In some implementations, a 3D semiconductor body is formed from a second substrate to form a second semiconductor, and a gate structure is formed in contact with multiple sides of the 3D semiconductor body.

[0186] In some implementations, to form a 3D semiconductor body, a trench isolation is formed in the second substrate surrounding a portion of the second substrate, and the trench isolation is etched back to expose at least a portion of the portion of the second substrate.

[0187] In some implementations, to form a 3D semiconductor body, a trench is formed in the second substrate surrounding a portion of the second substrate, and an isolation material is deposited to partially fill the trench and expose at least a portion of the portion of the second substrate.

[0188] In some implementations, a gate dielectric layer and a gate electrode layer are subsequently formed on multiple sides of the 3D semiconductor body to form a gate structure, and the gate electrode layer is patterned to form a gate electrode.

[0189] In some implementations, the gate dielectric layer comprises silicon oxide and the gate electrode layer comprises polysilicon.

[0190] In some implementations, a source and a drain are formed in the 3D semiconductor body to form a second semiconductor structure.

[0191] In some implementations, portions of the 3D semiconductor body that are not covered by the gate electrode are doped to form sources and drains.

[0192] In some implementations, a plurality of 3D NAND memory strings are formed to form the first semiconductor structure.

[0193] In some implementations, a first bonding layer including a plurality of first bonding contacts is formed over the array of memory cells to form a first semiconductor structure. In some implementations, a second bonding layer including a plurality of second bonding contacts is formed over the peripheral circuitry to form a second semiconductor structure. In some implementations, the first bonding contacts are in contact with the second bonding contacts at a bonding interface after bonding.

[0194] In some implementations, one of the first and second substrates above the other of the first and second substrates is thinned after bonding, and an interconnect layer is formed on the thinned first or second substrate.

[0195] In some implementations, the bond comprises a hybrid bond.

[0196] The foregoing description of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0197] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. a first semiconductor structure including an array of memory cells; a second semiconductor structure including a peripheral circuit, the peripheral circuit including a 3D transistor; a bond interface between the first semiconductor structure and the second semiconductor structure, across which the array of memory cells is coupled to the peripheral circuitry; The 3D transistor comprises a 3D semiconductor body and a gate structure in contact with a plurality of sides of the 3D semiconductor body, the gate structure including a gate dielectric and a gate electrode, and the peripheral circuitry includes a first peripheral circuit, a second peripheral circuit, and a third peripheral circuit; the 3D transistors include a first 3D transistor of the first peripheral circuit, a second 3D transistor of the second peripheral circuit, and a third 3D transistor of the third peripheral circuit; the first 3D transistor of the first peripheral circuit receives a first voltage; the second 3D transistor of the second peripheral circuit receives a second voltage greater than the first voltage; The third 3D transistor of the third peripheral circuit receives a third voltage greater than the second voltage. Three-dimensional (3D) memory devices.

2. The 3D transistor is a multi-gate transistor.

10. The 3D memory device of claim 1 .

3. the first peripheral circuit includes an input / output (I / O) circuit; the second peripheral circuit includes at least a portion of a page buffer; The third peripheral circuit includes a word line driver.

10. The 3D memory device of claim 1 .

4. the first semiconductor structure further includes a plurality of bit lines and a plurality of word lines coupled to the array of memory cells; the second 3D transistor of a second peripheral circuit is coupled to the array of memory cells via at least one of the bit lines; The third 3D transistor of the third peripheral circuit is coupled to the array of memory cells via at least one of the word lines.

10. The 3D memory device of claim 1 .

5. a thickness of the gate dielectric of the third 3D transistor is greater than a thickness of the gate dielectric of the second 3D transistor; The thickness of the gate dielectric of the second 3D transistor is greater than the thickness of the gate dielectric of the first 3D transistor.

10. The 3D memory device of claim 1 .

6. the third 3D transistor further includes a drift region, a source, and a drain; The doping concentration of the drift region is lower than the doping concentration of the source and drain.

10. The 3D memory device of claim 1 .

7. the gate electrode of the first 3D transistor comprises a metal; The gate dielectric of the first 3D transistor comprises a high dielectric constant (high-k) dielectric.

10. The 3D memory device of claim 1 .

8. The 3D semiconductor body of the first 3D transistor or the second 3D transistor has a dumbbell shape in a plan view.

10. The 3D memory device of claim 1 .

9. the width of the 3D semiconductor body is greater than 10 nm; the height of the 3D semiconductor body is greater than 40 nm; The channel length of the 3D semiconductor body is greater than 30 nm.

10. The 3D memory device of claim 1 .

10. The thickness of the gate dielectric is greater than 1.8 nm.

10. The 3D memory device of claim 1 .

11. The peripheral circuit further includes a planar transistor.

10. The 3D memory device of claim 1 .

12. The peripheral circuit includes: With other 3D transistors, With other planar transistors, a first trench isolation between the 3D transistor and the other 3D transistor; a second trench isolation between the planar transistor and the other planar transistor.

12. The 3D memory device of claim 11.

13. The second trench isolation is deeper than the first trench isolation.

13. The 3D memory device of claim 12.

14. 1. A memory device configured to store data, comprising: a first semiconductor structure including an array of memory cells; a second semiconductor structure including a peripheral circuit, the peripheral circuit including a 3D transistor; a memory device having a bond interface between the first semiconductor structure and the second semiconductor structure, the array of memory cells being coupled to the peripheral circuitry across the bond interface; a memory controller coupled to the memory device and configured to control the array of memory cells via the peripheral circuitry; the 3D transistor comprises a 3D semiconductor body; and a gate structure in contact with a plurality of sides of the 3D semiconductor body, the gate structure including a gate dielectric and a gate electrode; the peripheral circuits include a first peripheral circuit, a second peripheral circuit, and a third peripheral circuit; the 3D transistors include a first 3D transistor of the first peripheral circuit, a second 3D transistor of the second peripheral circuit, and a third 3D transistor of the third peripheral circuit; the first 3D transistor of the first peripheral circuit receives a first voltage; the second 3D transistor of the second peripheral circuit receives a second voltage greater than the first voltage; The third 3D transistor of the third peripheral circuit receives a third voltage greater than the second voltage. system.

15. 1. A method for forming a three-dimensional (3D) memory device, comprising: forming a first semiconductor structure on a first substrate, the first semiconductor structure including an array of memory cells; forming a second semiconductor structure on a second substrate, the second semiconductor structure including peripheral circuitry, the peripheral circuitry including 3D transistors; bonding the first semiconductor structure and the second semiconductor structure in a face-to-face manner such that the array of memory cells is coupled to the peripheral circuitry across a bonding interface; the 3D transistor comprises a 3D semiconductor body; and a gate structure in contact with a plurality of sides of the 3D semiconductor body, the gate structure including a gate dielectric and a gate electrode; the peripheral circuits include a first peripheral circuit, a second peripheral circuit, and a third peripheral circuit; the 3D transistors include a first 3D transistor of the first peripheral circuit, a second 3D transistor of the second peripheral circuit, and a third 3D transistor of the third peripheral circuit; the first 3D transistor of the first peripheral circuit receives a first voltage; the second 3D transistor of the second peripheral circuit receives a second voltage greater than the first voltage; The third 3D transistor of the third peripheral circuit receives a third voltage greater than the second voltage. method.

16. The step of forming a second semiconductor structure includes: forming a 3D semiconductor body from the second substrate; forming a gate structure in contact with a plurality of sides of the 3D semiconductor body. The method of claim 15.

17. The step of forming the 3D semiconductor body includes: forming a trench isolation in the second substrate surrounding a portion of the second substrate; and etching back the trench isolation to expose at least a portion of the portion of the second substrate.

17. The method of claim 16.

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