Semiconductor Device

Abstract

To provide a semiconductor device having large storage capacity per unit area.SOLUTION: A semiconductor device includes a first memory cell, and a second memory cell provided over the first memory cell. Each memory cell 10 includes a transistor 11, a second transistor 12, and a capacitive element 14. A gate of the transistor 11 is electrically connected to one of a source and a drain of the transistor 12 and one of electrodes of the capacitive element. One of a source and a drain of the transistor 11 of the first memory cell is electrically connected to one of a source and a drain of the transistor 11 of the second memory cell. The transistor 12 includes an oxide semiconductor. A channel length direction of the transistor 11 is substantially perpendicular to a channel length direction of the transistor 12.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. For example, the present invention relates to a method for manufacturing a transistor and a semiconductor device. The present invention relates to a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. The present invention also relates to a manufacturing method for a display device, a liquid crystal display device, a light emitting device, a storage device, and electronic equipment. The present invention also relates to a display device, a liquid crystal display device, a light emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an object, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition of matter. It concerns the science of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, semiconductor circuits, and The electronic equipment may include a semiconductor device. [Background technology]

[0004] Transistors that use silicon (Si) as the semiconductor layer and transistors that use oxide semiconductors (Oxide S By combining transistors that use OS (semiconductor layer) Semiconductor devices that enable reading and writing of data have been attracting attention (see Patent Document 1). ).

[0005] In recent years, with the increase in the amount of data handled, semiconductor devices with larger storage capacities have become increasingly popular. In order to increase the memory capacity per unit area, memory cells must be stacked. It is effective to form the memory cells in layers (see Patent Document 2). This makes it possible to increase the storage capacity per unit area in proportion to the number of stacked memory cells. do. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication 2011-119674 [Patent Document 2] Patent Publication No. 2011-66417 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device having a large storage capacity per unit area. An object of the present invention is to provide a semiconductor device having a novel structure in which memory cells are stacked. Another object is to provide a method for driving a semiconductor device having a novel structure.

[0008] Another object of the present invention is to provide a module including the semiconductor device. It is another object of the present invention to provide an electronic device including the semiconductor device or the module. Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a novel electronic device. do.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a memory cell including a first memory cell and a second memory cell provided on the first memory cell. a first memory cell including a first transistor and a second transistor; The second memory cell has a third transistor and a fourth transistor. a gate of the first transistor and a second capacitance element, a source of the second transistor electrically connected to one of the source and drain of the first transistor; Or one of the drains is electrically connected to one of the electrodes of the first capacitance element, and the third transistor The gate of the first transistor is electrically connected to one of the source and drain of the fourth transistor. One of the source and drain of the fourth transistor is connected to one of the electrodes of the second capacitor. and one of the source and drain of the first transistor is electrically connected to the third transistor. a second transistor electrically connected to one of the source and drain of the first transistor, The fourth transistor includes an oxide semiconductor. a channel length direction of the second transistor and a channel length direction of the fourth transistor; The semiconductor device is characterized by being substantially vertical.

[0011] Another embodiment of the present invention is a semiconductor memory device including a first memory cell provided over a substrate and a first memory cell. and a second memory cell disposed on the cell, the first memory cell including a first transistor. a first memory cell, a second transistor, and a first capacitance element, a first transistor, a fourth transistor, and a second capacitance element, The gate of the first transistor is electrically connected to one of the source and drain of the second transistor. One of the source and drain of the second transistor is connected to one of the electrodes of the first capacitor. The gate of the third transistor is electrically connected to the source or drain of the fourth transistor. One of the source or drain of the fourth transistor is electrically connected to a source terminal of the first transistor; One of the drains is electrically connected to one of the source and drain of a third transistor. The second transistor and the fourth transistor each include an oxide semiconductor. The first transistor and the second transistor have a channel length direction substantially perpendicular to the upper surface of the substrate. It is a semiconductor device.

[0012] Another embodiment of the present invention is a semiconductor memory device including a first memory cell provided over a substrate and a first memory cell. and a second memory cell disposed on the cell, the first memory cell including a first transistor. a first memory cell, a second transistor, and a first capacitance element, a first transistor, a fourth transistor, and a second capacitance element, The gate of the first transistor is electrically connected to one of the source and drain of the second transistor. One of the source and drain of the second transistor is connected to one of the electrodes of the first capacitor. The gate of the third transistor is electrically connected to the source or drain of the fourth transistor. One of the source or drain of the fourth transistor is electrically connected to a source terminal of the first transistor; One of the drains is electrically connected to one of the source and drain of a third transistor. The second transistor and the fourth transistor each include an oxide semiconductor. The first transistor and the second transistor are parts of a semiconductor extending substantially perpendicularly to the upper surface of the substrate. The semiconductor device is characterized by having:

[0013] In another embodiment of the present invention, a semiconductor device is provided that extends substantially perpendicularly to an upper surface of a substrate. In another embodiment of the present invention, a crystalline silicon film is formed on the upper surface of the substrate. The elongated semiconductor is preferably cylindrical.

[0014] Another aspect of the present invention is a semiconductor memory device including a plurality of memory cell arrays arranged in a first direction. a plurality of first wirings and a plurality of second wirings, The second wiring is provided so as to extend in a second direction substantially perpendicular to the first direction, and the memory cell array has a plurality of memory cell strings arranged in a second direction, The cell string is provided extending in a third direction substantially perpendicular to the first direction and the second direction. The memory cell string includes a plurality of memory cells and a third no. extending in a third direction. to a fifth wiring, and the memory cell includes a first transistor, a second transistor, and a capacitance element; and a channel length direction of the first transistor is substantially parallel to the third direction. The second transistor includes an oxide semiconductor. A second transistor is electrically connected to the source or drain of the first transistor. One of the source and drain is electrically connected to one of the electrodes of the capacitance element. In one of the re-cell strings, the memory cells are connected to each other by the sources of the first transistors. The source or drain of the first transistor is electrically connected to the other of the source or drain of the second transistor. The source or drain of the first transistor of the memory cell at one end of the memory cell string is connected to the One of the drains is electrically connected to the third wiring, and the other end of the memory cell string is electrically connected to the third wiring. The other of the source and the drain of the first transistor of the cell is electrically connected to a fourth wiring. The other of the source and drain of the second transistor of the plurality of memory cells is connected to a fifth wiring and the capacitance of the memory cells in the same row in one of the memory cell arrays is electrically connected to The other electrode of the element is electrically connected to one of the plurality of first wirings, and A gate of the second transistor is electrically connected to one of the plurality of second wirings. The semiconductor device is as follows.

[0015] Another embodiment of the present invention is a semiconductor device comprising: one of the plurality of memory cell arrays is selected and connected to a second transistor via one of the plurality of second wirings. is turned on, a write potential is applied to the plurality of fifth wirings, and a write potential is applied to one of the plurality of second wirings. The second transistor is turned off, data corresponding to the write potential is held, and the read In the operation, one of the plurality of memory cell arrays is selected and a signal is transmitted through one of the plurality of first wirings. A first potential is applied to the other electrode of the capacitance element, and a first wiring in a row different from one of the plurality of first wirings is A second potential different from the first potential is applied to the other electrode of the capacitance element through the line to generate a first transistor. The transistor is turned on, a readout potential is applied to the third wiring, and data is obtained from the change in the readout potential. The present invention relates to a method for driving a semiconductor device, and a method for reading out data from the semiconductor device.

[0016] Another embodiment of the present invention is a memory device including the above-described semiconductor device. Effect of the Invention

[0017] It is possible to provide a semiconductor device having a large memory capacity per unit area. It is possible to provide a semiconductor device having a novel structure in which recells are stacked. It is possible to provide a method for driving the semiconductor device.

[0018] Alternatively, a module having the semiconductor device can be provided. It is possible to provide a semiconductor device having the module. A conductor device may be provided, or a novel module may be provided. Alternatively, a novel electronic device can be provided.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 2] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 3]FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] 1 is a timing chart illustrating a method for driving a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are schematic diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21]1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 22] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Diagram 23] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 24] Cross-sectional TEM image of a-like OS. [Diagram 25] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 26] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details can be made by those skilled in the art. In addition, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used It is used commonly across different drawings. Note that when referring to similar objects, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0022] The configurations shown in the following embodiments may be applied or combined as appropriate with other configurations shown in the embodiments. The above-mentioned elements can be combined or substituted to form one embodiment of the present invention.

[0023] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0024] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do so.

[0025] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. In general, potential (voltage) is relative, and the magnitude is relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." In some cases, the intermediate potential in the circuit may be the "ground potential." In this case, the positive potential and the negative potential are defined based on that potential.

[0026] The ordinal numbers 1 and 2 are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. Therefore, for example, "first" should not be changed to "second" or "third" In addition, the ordinal numbers described in this specification and the like can be appropriately replaced with the ordinal numbers. In some cases, the term may not match the ordinal number used to identify an aspect of the invention.

[0027] In this specification, "A and B are connected" means that A and B are directly connected. In addition to those that are electrically connected, A and B are also included. Being connected means that there is an object between A and B that has some electrical effect. A means a device that enables the transmission and reception of electrical signals between A and B.

[0028] In this specification, the source of a transistor is a semiconductor film that functions as an active layer. The source region is a part of the semiconductor film, or the source electrode is connected to the semiconductor film. The drain of the transistor refers to a drain region that is a part of the semiconductor film, or The term "gate" refers to a gate electrode connected to a semiconductor film.

[0029] The source and drain of a transistor are determined by the conductivity type of the transistor and the terminals. The name is changed depending on the level of the potential. Generally, n-channel transistors In a capacitor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called the drive. The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. Explain the connection relationship of a transistor, assuming that the source and drain are fixed. However, in reality, the names of source and drain are interchangeable according to the above potential relationship. Bad.

[0030] Unless otherwise specified, in this specification, the off-state current refers to the current flowing when a transistor is in an off state. The off-state refers to the drain current when the transistor is in an n-channel state, unless otherwise specified. In a transistor, the potential difference between the gate and source (V GS ) is lower than the threshold voltage (Vth) In the case of a p-channel transistor, V GS is higher than Vth. For example, , the off-state current of an n-channel transistor is V GS When Vth is lower than The off-state current of a transistor is V GS It may depend on. So the off-state current of the transistor is 10 -21A or less means that the off-state current of the transistor is Flow is 10 -21 V below A GS Sometimes it is said that there exists a value of

[0031] The off-state current of a transistor is determined by the potential difference between the drain and source (V DS ) depends on In this specification, the off-state current is V DS The absolute value of is 0 .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 It may represent the off-state current at 2 V, 16 V, or 20 V. The reliability of semiconductor devices that contain V DS , or the transistor V used in semiconductor devices, etc. DS The term "off-state current" may also refer to the off-state current at

[0032] Even if a material is described as a "semiconductor," if its electrical conductivity is sufficiently low, it may be considered an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. In some cases, the distinction cannot be made precisely. Therefore, the term "semiconductor" as used herein means "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." In some cases, this can be rephrased as "body."

[0033] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and not strictly defined. In some cases, the distinction may not be clear. Therefore, the term "semiconductor" as used herein means "conductor" or "electroconductor". Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor In some cases, this can be rephrased as "body."

[0034] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements present at less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the conductor and carrier movement The degree of conductivity may decrease, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group 1 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can cause In addition, when the semiconductor is silicon, the characteristics of the semiconductor Examples of impurities that change the value of the valence number include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and These include Group 3 elements and Group 15 elements.

[0035] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source region or the channel region This refers to the distance between the drain (drain region or drain electrode) and the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0036] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the electrode (the area where the current flows) forms a channel. This refers to the length of the part of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. That is, The channel width of a transistor may not be determined to a single value. In the fine print, the channel width is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0037] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the lateral surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be large. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0038] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0039] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the source and drain facing each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used simply, it may refer to the effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0040] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0041] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0042] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0043] (Embodiment 1) In this embodiment, a circuit configuration and an operation of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS. 1 to 7.

[0044] <Memory Cell> First, the circuit configuration and operation of a memory cell of a semiconductor device, which will be described later, will be described with reference to FIG. The following description will be given with reference to FIG. 1(A) and FIG. 1(B). FIG. 1(A) shows the circuit of a memory cell 10. FIG. 1(B) is an example of a circuit diagram showing a configuration in a plan view, and FIG. 1(B) is a three-dimensional view of a semiconductor device to be described later. 1 is an example of a circuit diagram showing a three-dimensional representation of the circuit configuration of a memory cell 10 in accordance with a configuration of the memory cell 10.

[0045] In the memory cell 10 shown in FIG. 1A and FIG. 1B, the wiring SL and the transistor 1 The source electrode (or drain electrode) of 1 is electrically connected to the wiring RBL. The drain electrode (or source electrode) of 11 is electrically connected. and the source electrode (or drain electrode) of the transistor 12 are electrically connected to each other, and the wiring WW L and the gate electrode of the transistor 12 are electrically connected. The gate electrode of the transistor 11 and the drain electrode (or source electrode) of the transistor 12 form a capacitance element 1 The wiring RWL and the other electrode of the capacitance element 14 are electrically connected to each other. is connected.

[0046] Here, the transistor 12 is, for example, a transistor including an oxide semiconductor. As will be described later in detail, a transistor including an oxide semiconductor has a low off-state current Therefore, when the transistor 12 is turned off, This makes it possible to hold the potential of the gate electrode of the transistor 11 for an extremely long period of time. It is possible. By having the capacitance element 14, the gate electrode of the transistor 11 This makes it easier to hold the charge applied to the layer and to read out the held information.

[0047] The transistor 11 is not particularly limited. From the viewpoint of this, for example, a transformer using polycrystalline silicon or single crystal silicon is It is preferable to use a transistor having a high switching speed, such as a MOSFET.

[0048] In the memory cell 10 shown in FIGS. 1A and 1B, the gate electrode of the transistor 11 By taking advantage of the feature that the potential can be maintained, information can be written, retained, and read as follows: It is possible to put out.

[0049] First, writing and holding of information will be described. First, the potential of the wiring WWL is set as follows: The transistor 12 is turned on by applying a potential to the transistor 12. As a result, the potential of the wiring WBL is The gate electrode of the transistor 11 and one electrode of the capacitor 14 are electrically connected to each other. Node (also referred to as node FN) is applied to the gate of transistor 11. A given charge is applied to the electrodes (writing). Here, two different potentials are applied. Charge (hereinafter, the charge that gives the low potential is called charge Q L , the charge that gives the high potential is charge Q H (That is, Either one of them is given. Note that three or more different electric potentials are given to the charge Then, the potential of the wiring WWL is changed to the potential of the transistor By setting the potential at which the transistor 12 is turned off, the transistor The charge applied to the gate electrode of the transistor 11 is held (retained).

[0050] Since the off-state current of the transistor 12 is extremely small, the voltage of the gate electrode of the transistor 11 is The load is held for a long period of time.

[0051] Next, reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring SL, In this state, when an appropriate potential (read potential) is applied to the wiring RWL, Depending on the amount of charge held in the electrode, the wiring RBL takes on different potentials. If the transistor 11 is an n-channel type, then the gate electrode of the transistor 11 is connected to Q H is given The apparent threshold voltage V th_H is connected to the gate electrode of transistor 11. L Given The apparent threshold voltage V th_L This is because the temperature is lower than that of the The threshold voltage of the switch is the voltage at which the transistor 11 changes from the "off state" to the "on state" or This refers to the potential of the wiring RWL required to change the state from the "on" state to the "off" state. Therefore, the potential of the wiring RWL is Vth_H and V th_L By setting the potential between these two as V0, The charge applied to the gate electrode of the transistor 11 can be determined. For example, TeQ H When the potential of the wiring RWL is V0 (> V th_H ) Then, Tiger Transistor 11 is in the "ON" state. Q L When is given, the potential of the wiring RWL is V 0( <V th_L ), the transistor 11 remains in the "off state." If transistor 11 is a p-channel type, then Q L If is given, it is "on state" Next, Q H If the wiring RBL By observing the potential, the stored information can be read out.

[0052] When memory cells are arranged in a matrix, information on a desired memory cell is In this way, it is necessary to read only the information of a specific memory cell. To prevent other memory cells from reading information, transistors are placed between each memory cell. When the memory cells 11 are connected in series, the memory cells that are not the object of reading For the wiring RWL, the transistor 11 is in the "on state" regardless of the state of the gate electrode. That is, V th_L In this case, the wiring R WL to V th_L When a larger potential is applied, the transistor 11 A potential is applied to the gate electrode of transistor 11 so that transistor 11 is in the "on state." This allows the transistor 11 to be turned on independently of the data stored in the node FN.

[0053] Next, the rewriting of information will be described. That is, the potential of the wiring WWL is changed by turning on the transistor 12. This causes the potential of the wiring WBL ( A potential related to new information is applied to the gate electrode of the transistor 11 and the capacitor element 14. After that, the potential of the wiring WWL is set to a potential at which the transistor 12 is turned off. By turning off the transistor 12, the gate electrode of the transistor 11 is The charge related to the information is given.

[0054] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. This allows the information to be rewritten quickly. This eliminates the need to extract charge from the floating gate using the high voltages required for This makes it possible to suppress a decrease in the operating speed. In other words, high-speed operation of the semiconductor device is realized. do.

[0055] The drain electrode (or source electrode) of the transistor 12 and the The node FN to which the gate electrode and one electrode of the capacitor 14 are electrically connected is a nonvolatile Floating gate of floating gate type transistor used as memory element When the transistor 12 is off, the node FN is in the insulator. The node FN can be considered to be buried, and charge is stored in the node FN. The off-state current of the transistor 12 is 100,000 times that of a transistor made of a silicon semiconductor. Because the charge stored in node FN is less than one-fifth of the In other words, the transistor 12 using an oxide semiconductor can store information without power supply. It is possible to realize a storage device capable of long-term retention.

[0056] For example, the off-state current of the transistor 12 at room temperature (25° C.) is 10 zA (1 zA Ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 14 is about 10 fF. If so, at least 10 4 It is possible to hold data for more than 1000 seconds. It goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0057] In addition, in the memory cell 10 shown in this embodiment, a conventional floating gate type The problem of deterioration of the gate insulating film (tunnel insulating film) that has been pointed out in transistors In other words, there is no problem with injecting electrons into the floating gate, which was previously considered a problem. This solves the problem of deterioration of the gate insulating film during writing. This means that there is no limit to the number of times that the floating gate The high voltage required for writing and erasing data in the conventional transistor is also unnecessary.

[0058] In the memory cell 10, the node FN is connected to a floating gate of a flash memory or the like. The function is the same as that of a floating gate of a gate-type transistor, but the node FN has characteristics that are fundamentally different from floating gates such as flash memory. In flash memory, the potential applied to the control gate is high, so In order not to affect the floating gates of adjacent cells, the spacing between cells is This is one of the factors that hinders the high integration of semiconductor devices. The cause of this is the flash tunneling effect, which is achieved by applying a high electric field to generate a tunnel current. This is due to the fundamental principles of memory.

[0059] On the other hand, the semiconductor device according to the present embodiment has a transistor switch using an oxide semiconductor. It operates by switching and does not use the principle of charge injection by tunnel current as described above. In other words, a high electric field for injecting charges, as in the case of flash memory, is not required. Therefore, there is no need to consider the effect of high electric fields due to the control gate on adjacent cells. This makes it easier to achieve high integration.

[0060] In order to increase the memory capacity of a semiconductor device, in addition to increasing the integration density, a method for multi-level data storage is also required. For example, it is possible to write three or more levels of information into one memory cell. This allows for a larger memory capacity than when writing binary (1-bit) information. For example, the charge Q L , charge Q giving high potential H In addition By applying a charge Q that gives another potential to the gate electrode of the transistor 11, multi-values ​​are realized. Multi-value data can be expressed as, for example, 4 values ​​(2 bits), 8 values ​​(3 bits), It would be good if it could hold data such as 16 values ​​(4 bits), 16 values ​​(4 values), etc.

[0061] The above explanation is for n-type transistors (n-channel transistors) that use electrons as carriers. This is about using a MOSFET (transistor) instead of an n-type transistor. Alternatively, a p-type transistor may be used.

[0062] In a memory cell array described later, the memory cell 10 has a transistor as shown in FIG. The channel length direction of the transistor 11, the channel length direction of the transistor 12, the wiring SL, the wiring R It is preferable that the wiring BL, the wiring WBL, the wiring RWL and the wiring WWL are provided so as to intersect three-dimensionally. It is nice.

[0063] The channel length direction of the transistor 11 and the channel length direction of the transistor 12 are approximately perpendicular to each other. It is also preferable that the transistor is disposed on the upper surface of the substrate on which the memory cell 10 is provided. The channel length direction of the transistor 11 is approximately vertical, and the channel length direction of the transistor 12 is approximately parallel. It is preferable that there is.

[0064] In addition, for the wiring RBL, wiring SL, and wiring WBL, the wiring WWL and wiring RWL are approximately It is preferable that the wiring is perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. RBL, wiring SL and wiring WBL are approximately perpendicular, and wiring WWL and wiring RWL are approximately parallel. It is preferable that there is.

[0065] By configuring the memory cell 10 in this manner, a plurality of memory cells 1 0 can be stacked in series with each transistor 11. This allows the memory capacity per unit area to be increased according to the number of stacked memory cells 10. It is possible to provide a semiconductor device capable of achieving this.

[0066] As described above, the transistor 11 is arranged so that the channel length direction is perpendicular to the upper surface of the substrate. By configuring the circuit so that the gate electrode surrounds the semiconductor, and the source and drain are A vertical transistor (SGT) with a structure in which the transistor is placed above and below The minimum processing size is F, the area occupied by a standard planar transistor is 8F. 2 whereas, SGT occupies 4 floors 2 This further increases the memory capacity per unit area. The amount can be increased.

[0067] Memory Cell Array Next, the more specific circuit configuration and operation of the circuit shown in Figure 1 will be described in Figure 2. The description will be given with reference to FIG.

[0068] A three-dimensional memory cell array 40, a selection transistor array 50, a drive circuit 51, and a read A block circuit of a semiconductor device having a read circuit 52, a drive circuit 53, and a drive circuit 54. An example of the path diagram is shown in Fig. 2. In the following, as shown in Fig. 2, the x-axis, y-axis, and z-axis For convenience, an orthogonal coordinate system consisting of

[0069] In addition, since the diagram in Fig. 2 is somewhat complicated, the 3D memory cell array is shown in Fig. 3. FIG. 4 shows an example of a block circuit diagram of only the three-dimensional memory cell array 40. 1 shows an example of a block circuit diagram of a two-dimensional memory cell array 30[1] included in the memory cell array 30. 4 shows an example of a block circuit diagram of a two-dimensional memory cell array 30[1] in a plan view. Some of the z-axis configurations are represented on the xy plane. A transistor array 50, a drive circuit 51, a read circuit 52, a drive circuit 53, and a drive circuit 5 shows an example of a block circuit diagram of the circuit 54.

[0070] A selection transistor array 50, a drive circuit 51, a read circuit 52, a drive circuit 53, and The drive circuit 54 is formed on a substrate surface that is approximately parallel to the xz plane. A three-dimensional memory cell array 40 is formed on the substrate 50 .

[0071] The three-dimensional memory cell array 40 has m1×m2×m3 (m1, m2, and m3 are natural numbers) It has memory cells 10, m1 in the x-axis direction, m2 in the y-axis direction, and m3 in the z-axis direction. The memory cells 10 are arranged in a rectangular parallelepiped shape. Coordinates are added to the memory cells 10, such as (1,1,1) to (m1,m2,m3). There are cases.

[0072] As shown in FIG. 3, the three-dimensional memory cell array 40 is extended in the y-axis direction. The wirings SL, RBL and WBL are arranged in the x-axis direction. The wiring RWL and the wiring WWL are m2 × m3 in number. The wiring SL is assigned coordinates in the x-axis direction and the z-axis direction, and wirings SL[1,1] to [m1,m3 Similarly, the wiring RBL[1,1] to [m1,m3], the wiring W It may be represented as BL[1,1] to [m1,m3]. Also, as shown in FIG. The line RWL is assigned coordinates in the y-axis and z-axis directions, and the wiring RWL[1,1] to [m2,m3 Similarly, wiring WWL[1,1] to [m2,m3] may be indicated.

[0073] The three-dimensional memory cell array 40 is made up of m3 two-dimensional memories arranged in the z-axis direction. As shown in FIG. 2, the two-dimensional memory cell array 30 The z-axis coordinates are added to the two-dimensional memory cell arrays 30[1] to [m3]. This may happen.

[0074] Each two-dimensional memory cell array 30 is made up of m1 memory cells arranged in the x-axis direction. As shown in FIG. 2, the memory cell string 20 is The memory cell strings 20[1,1] to [m1, Each memory cell string 20 is arranged in the y-axis direction. Each of the two-dimensional memory cell arrays 3 has m2 memory cells 10. Since the memory cell array 30 is composed of m1 memory cell strings 20, the two-dimensional memory cell array 3 In FIG. 0, m1 memory cells 10 are arranged in a matrix in the x-axis direction and m2 memory cells 10 in the y-axis direction. This means that...

[0075] As shown in FIG. 1B, the memory cell 10 includes a transistor 11, a transistor 12, and a and a capacitance element 14, and a wiring SL, a wiring RBL, a wiring WBL, a wiring RWL, and a wiring WWL However, as shown in FIGS. 2 to 4, each memory cell string 20 is electrically connected to The constituent memory cells 10 are connected in series in the y-axis direction by transistors 11. Therefore, memory cell (i1,1,i3) (i1 is a natural number between 1 and m1, and i3 is a natural number between 1 and m1) ) is connected to the wiring RBL[ In addition, only the memory cell (i1, m2, i3) is connected to other memory cells. The other memory cells 10 are connected to the wiring SL[i1, i3] without going through the memory cell 10. The wiring RBL and the wiring SL and electrically connected to the

[0076] Here, the two-dimensional memory cell array 30[1] shown in FIG. 4 is taken as an example. The structure of the two-dimensional memory cell array 30 [1] shown in FIG. 1 wiring SL[1,1] to [m1,1] and m1 wirings RBL[1,1] to [m1 ,1], m1 wirings WBL[1,1] to [m1,1], and m2 wirings RWL[1 ,1] to [m2,1], m2 wires WWL[1,1] to [m2,1], and m1× The memory cells 10 (1,1,1) to (m1,m2,1) are arranged in a matrix of m2. ) and.

[0077] In the following description, the matrix wiring and memory cells of the two-dimensional memory cell array 30 are For example, the same two-dimensional memory cell array 30 may be expressed as a matrix. In this case, a plurality of memory cells 10 having the same y coordinate are expressed as memory cells 10 in the same row. In the same two-dimensional memory cell array 30, the x coordinates are the same. A plurality of memory cells 10 (which may be said to constitute the same memory cell string 20) can be expressed as the memory cells 10 in the same column. In the following, the two-dimensional memory cell shown in FIG. In the 30-row array, the rows are called the 1st row, the 2nd row, ... the 2nd row, and the rows are called the 30th row, starting from the left. These are called the 1st row, 2nd row, ... m1st row.

[0078] The wiring SL[i1,1] is connected to the corresponding transistor of the memory cell 10 (i1,m2,1). The wiring RBL[i1,1] is electrically connected to the source electrode of the transistor 11. The drain electrode of the corresponding transistor 11 of the memory cell 10 (i1,1,1) is electrically connected to the drain electrode of the corresponding transistor 11 of the memory cell 10 (i1,1,1). To be continued.

[0079] The wiring WBL[i1,1] corresponds to the memory cells 10(i1,1,1) to 10(i 1, m2, 1) are electrically connected to the source electrodes of the corresponding transistors 12. In other words, In other words, the source electrodes of the transistors 12 of the memory cells 10 in the same column are connected to the wiring WB Electrically connected to L.

[0080] The wiring RWL[i2,1] (i2 is a natural number between 1 and m2) is In addition to the electrodes of the corresponding capacitance elements 14 of the resiliency cells 10(1,i2,1) to (m1,i2,1), In other words, the electrodes of the capacitors 14 of the memory cells 10 in the same row are electrically connected to each other. The other one is electrically connected to the wiring RWL in the same row.

[0081] The wiring WWL[i2,1] is connected to the memory cells 10(1,i2,1) to (m i1, i2, i2) are electrically connected to the gate electrodes of the corresponding transistors 12. In other words, In other words, the gate electrodes of the transistors 12 of the memory cells 10 in the same row are connected to the wiring WW Electrically connected to L.

[0082] Memory cell 10 (i1,i 2A ,1)(i 2A indicates a natural number between 1 and m2-1. The source electrode of the transistor 11 of the memory cell 10 (i1, i 2A +1,1) Tiger In other words, in the same column, The memory cells 10 are connected to each other by the source electrode of the transistor 11 and the drain electrode of the transistor 11. The in-electrode is electrically connected to the in-electrode.

[0083] In this way, between the wiring SL[i1,1] and the wiring RBL[i1,1], the transistor 1 The memory cells 10 (i1,1,1) to (i1,m2,1) connected in series in Thus, the memory cell string 20[i1,1] is formed.

[0084] In this manner, the memory cell string 20 includes a plurality of memory cells 10. The transistors 11 can be stacked so that they are connected in series. The ring 20 has a storage capacity of the memory cell string 20 according to the number of stacked memory cells 10. Therefore, the number of memory cells in a three-cell array can be increased by 3. The multi-dimensional memory cell array 40 has a memory capacity per unit area that varies depending on the number of stacked memory cells 10. The capacity can be increased.

[0085] Here, the structure of the selection transistor array 50 shown in FIG. The transistor array 50 is made up of m1×m3 select transistor cells 6 arranged in a matrix. 0, m1 wirings RBL and WBL extending in the z-axis direction, and The wiring SG1 and wiring SG2 are provided so as to extend in the direction of the selection line. The transistor cell 60 is assigned coordinates in the xz plane, and the selection transistor cell 60(1,1) In addition, the wiring RBL and wiring WBL are in the x-axis direction. The coordinates of the wiring RBL[1] to [m1], the wiring WBL[1] to [m1], etc. In addition, the wiring SG1 and wiring SG2 are given coordinates in the z-axis direction, and the wiring S The wirings may be referred to as wirings G1[1] to [m3], and wirings SG2[1] to [m3].

[0086] Each selection transistor cell 60 includes a transistor 61 and a transistor 62 . In the selection transistor cell 60 (i1, i3), the wiring RBL[i1] and the transistor The drain electrodes (or source electrodes) of the memory cell strings [ The wiring RBL[i1,i3] and the source electrode (or drain) of the transistor 61 The gate electrode of the transistor 61 is electrically connected to the wiring SG1[i3]. In addition, in the selection transistor cells 60 (i1, i3), The line WBL[i1] and the drain electrode (or source electrode) of the transistor 62 are electrically connected. The wiring WBL[i1,i3] of the memory cell string [i1,i3] and the transistor The source electrode (or drain electrode) of the transistor 62 is electrically connected to the wiring SG2[i3]. The gate electrodes of the transistors 62 are electrically connected.

[0087] In this manner, each selection transistor cell 60 is set corresponding to each memory cell string 20. The wiring RBL[i1] and the wiring RBL[i1,1] to [i1,m3] are connected The on state is selected by the transistor 61 of each selection transistor cell 60, and the wiring WBL[i1] The conduction state between the wiring WBL[i1,1] to [i1,m3] is determined for each selection transistor cell 6 0 can be selected by transistor 62.

[0088] As shown in FIG. 5, a driving circuit 51 and a read circuit 52 are arranged around the selection transistor array 50. The drive circuit 51 is provided with a wiring RBL[1] to [m1] are connected to wirings WBL[1] to [m1]. The wirings RBL[1] to [m1] are also connected to the read circuit 52. Although not shown, the driving circuit 53 includes wirings RWL[1,1] to [m2,m3] and wirings WW L[1,1] to [m2,m3] are connected to the driving circuit 54. 1[1] to [m3] are connected to wiring SG2[1] to [m3].

[0089] An example of a read circuit that can be used for the read circuit 52 will be described below with reference to FIG. FIG. 6(A) shows a schematic diagram of the readout circuit. The memory cell has a transistor and a sense amplifier circuit.

[0090] When reading, terminal A is connected to the wiring RBL to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and The potential of the electrode is controlled.

[0091] The memory cell 10 exhibits different electrical resistances depending on the data stored therein. When the transistor 11 of the selected memory cell 10 is in an on state, the resistance is low. When the transistor 11 of the selected memory cell 10 is in an off state, the memory cell 10 is in a high resistance state.

[0092] When the memory cell is in a high resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sensor The amplifier outputs a potential (data "0") corresponding to the potential of terminal A. When the resistance of the terminal A is low, the potential of the terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data “1”) corresponding to the potential of terminal A.

[0093] In this way, by using the read circuit, data can be read from the memory cell. Note that the read circuit shown in this embodiment is an example. Other known circuits may be used. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref, it may be configured to be connected to a reference memory cell.

[0094] FIG. 6(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output. becomes.

[0095] FIG. 6(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, the potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal Sn is set to High to supply the power supply potential (Vdd), if the comparison potentials V1in and V2in are in the relationship of V1in > V2in, the output of V1 is High and the output of V2 is Low. If V1in < V2in, the output of V1 is Low and the output of V2 is High. Using such a relationship, the difference between V1in and V2in can be amplified. .

[0096] Note that in the above, the drive circuit 51, the read circuit 52, the drive circuit 53, and the drive circuit 54 are provided independently for each function, but the semiconductor device shown in this embodiment The driving circuit is not limited to the above, and a plurality of circuits may be integrated into one circuit. A circuit 51, a read circuit 52, a driving circuit 53, a driving circuit 54, and circuits connected to each circuit. The layout of the wiring is not limited to the configuration shown in FIG. 5, and may be appropriately set according to the semiconductor device. stomach.

[0097] In addition, the wirings SL[1,1] to [m1,m3] are each provided separately in FIG. However, the present invention is not limited to this configuration. For example, a plurality of wirings SL may be electrically connected. Alternatively, all the wirings SL may be electrically connected. 1,m3] should be connected to a low power supply potential that supplies, for example, ground potential GND or 0V. Just put it there.

[0098] In the semiconductor device shown in FIG. 2, a three-dimensional memory cell is provided on the selection transistor array 50. The semiconductor device shown in this embodiment is configured to include a memory cell array 40. For example, a selection transistor array is provided on the three-dimensional memory cell array 40. In this case, the transistor of the selection transistor cell 60 may be The transistor 61 and the transistor 62 are made of an oxide semiconductor, for example, like the transistor 12. It would be sufficient to set it up accordingly.

[0099] In addition, peripheral circuits such as a driving circuit 51, a read circuit 52, a driving circuit 53, and a driving circuit 54 are A part of the path may be provided under the three-dimensional memory cell array 40. For example, A readout circuit may be provided in a matrix corresponding to the rings 20. In this case, In this case, the readout circuit and the selection transistor cell 60 arranged in a matrix are stacked. That's good.

[0100] Data writing, storage, and reading are basically the same as in Figure 1. In the three-dimensional memory cell array 40, first, the two-dimensional memory cell array 30[1] After selecting one of [m1] to [m2], data is written or read. , writing and reading data in the two-dimensional memory cell arrays 30[1] to [m3] Write operations are at least row-wise. That is, the specific write operations are as follows: In this example, the node FN is set to a potential V2 (a potential lower than the power supply potential VDD). This section explains the case where either the reference potential GND (sometimes expressed as 0V) is applied. However, the relationship of the potential applied to the node FN is not limited to this. When the reference potential GND is applied to the node FN, the data held is data “1”. When the data is “0”, the data held is “0”. Also, the reference potential GND is applied to the wiring SL. This shall be the case.

[0101] In writing data, first, one of the two-dimensional memory cell arrays 30 is selected. In selecting the two-dimensional memory cell array 30, the potential of the corresponding wiring SG2 is set to V1 (for example, For example, a transistor 62 electrically connected to the wiring is turned on as a power supply voltage Vdd. Lines WBL[1] to [m1] and the wiring WB included in the selected two-dimensional memory cell array 30 At this time, the potential of the unselected wiring SG2 is set to GND (0V), and the Lines WBL[1] to [m1] and wiring WB included in the unselected two-dimensional memory cell array 30 L is in a non-conductive state.

[0102] Next, in the selected two-dimensional memory cell array 30, the memory cell in the row to be written The potential of the wiring WWL connected to 10 is set to V3 (a potential higher than V2, for example, VDD). The transistor 12 of the memory cell 10 is turned on. The data "0" is written to the memory cell 10. When writing, GND is applied to the wiring WBL as a write potential, and When data "1" is written, a potential V2 is applied to the wiring WBL as a write potential. Here, the potential of the wiring WWL is V3, so the potential V2 can be applied to the node FN. It is possible.

[0103] The data is retained by setting the potential of the wiring WWL connected to the memory cell 10 to be retained to GND. This is done by turning off the transistor 12 of the memory cell 10. When the potential of WWL is fixed to GND, the potential of node FN is fixed to the potential at the time of writing. In other words, when a potential V2, which is data "1", is applied to the node FN, If GND, which is data "0", is applied to node FN, the potential of The potential of the FN terminal is GND.

[0104] In addition, since the wire WWL is connected to GND, data "1" and data "0" are Even if a deviation is written, the transistor 12 is in an off state. Since the off-state current is extremely small, the charge in the gate electrode of the transistor 11 remains constant for a long time. In this way, the node FN of the memory cell 10 to be held is set to the write potential. The corresponding data can be held.

[0105] In reading data, first, one of the two-dimensional memory cell arrays 30 is selected. In selecting the two-dimensional memory cell array 30, the potential of the corresponding wiring SG1 is set to V1 (for example, For example, a transistor 61 electrically connected to the wiring is turned on as a power supply voltage Vdd. Lines RBL[1] to [m1] and wiring RB included in the selected two-dimensional memory cell array 30 At this time, the potential of the unselected wiring SG1 is set to GND (0V), and the Lines RBL[1] to [m1] and wiring RB included in the unselected two-dimensional memory cell array 30 L is in a non-conductive state.

[0106] Next, in the selected two-dimensional memory cell array 30, the memory cell in the row to be read is The potential of the wiring RWL connected to 10 is set to GND, and the other electrode of the capacitance element 14 connected to The potential of the line connected to the memory cell 10 in the row that is not the object of reading is set to GND. The potential of the line RWL is V5 (for example, VDD), and the other potential of the electrode of the capacitance element 14 to which it is connected is The place is V5.

[0107] If the potential of the wiring RWL connected to the memory cell 10 in the row to be read is GND, A potential V2 representing data "1" is applied to the node FN of the memory cell 10 to be read. On the other hand, when the data "0" is applied to the node FN, the transistor 11 is turned on. If the GND is applied, the transistor 11 is turned off.

[0108] In addition, the potential of the wiring RWL connected to the memory cells 10 in the row that is not the target for reading is set to V5 In this case, if data "1" is written to the memory cell 10 that is not the target for reading, In both cases where data “0” is written, the transistor 11 is in the on state.

[0109] A read potential (for example, VDD) is applied to the wiring RBL. When the transistor 11 of the cell 10 is in an on state, the wiring RBL and the wiring SL are electrically connected. In response to this, the potential of the wiring RBL drops. When switch 11 is in the off state, there is no continuity between wires RBL and SL. In this way, the read potential of the line RBL is changed. The data in the target memory cell can then be read out.

[0110] As a driving method, it is preferable to provide a batch erase operation for data on a block basis. For example, the two-dimensional memory cell array 30 may be one block. The two-dimensional memory cell array 30 to be erased is selected in the same manner as in the data write. The wiring WWL connected to the two-dimensional memory cell array 30 is turned on. This allows one block of data to be erased at once.

[0111] FIG. 7 shows an example of a timing chart relating to the detailed operation of the semiconductor device shown in FIG. The timing chart shown in FIG. 7 shows a batch erase of the two-dimensional memory cell array 30[1], Writing the first row of the two-dimensional memory cell array 30[1] and the two-dimensional memory cell array 30 This shows the relationship between the potentials of each wiring when reading the first row of [1]. The batch erase of the two-dimensional memory cell array 30[1] is performed by This is an operation to erase the data written in modules 10 (1,1,1) through (m1,m2,1). The first row of the two-dimensional memory cell array 30[1] is written in the two-dimensional memory cell array 30 [1] writes data “1” into the memory cell in the first row and first column of the This is an operation to write data "0" to the memory cells in the second column to the m1th column. The first row of the cell array 30[1] is read from the first row of the two-dimensional memory cell array 30[1]. This is an operation to read out the data written in the first row, first column. The data "1" is stored in the memory cell of the first row, and the data "2" is stored in the memory cells of the other columns (the second column to the m1th column) of the first row. The data "0" is stored.

[0112] It is assumed that the read circuit 52 is provided with the read circuit shown in FIG. do.

[0113] In the case of erasing the two-dimensional memory cell array 30[1] all at once, first, A potential V1 is applied to the select transistor cells 60(1,1) to (m1,1) to turn on the transistors. The switch 62 is turned on, and the wirings WBL[1] to [m1] are connected to the corresponding wirings WBL[1, ] to [m1,1]. Also, wires SG2[2] to [m3] are connected to GND. Then, the transistors 62 of the selection transistor cells 60(1,2) to (m1,m3) are turned on. and the wirings WBL[1] to [m1] are switched to the corresponding wirings WBL[1,2] to [m In this way, the two-dimensional memory cell is set as the target for the batch erase operation. Select memory cell array 30[1].

[0114] In the two-dimensional memory cell array 30[1], the wirings WWL[1,1] to WWL[ m2,1] to turn on the transistors 12 in the first row to the m2-th row. At the same time, the wirings WBL[1] to [m1] are connected to GND, and the nodes F Set the N potential to GND.

[0115] In addition, wiring WW electrically connected to the two-dimensional memory cell arrays 30[2] to [m3] L[1,2] to [m2,m3] are grounded, and memory cells 10(1,1,2) to ( m1, m2, m3) maintains the potential of node FN.

[0116] In writing the first row of the two-dimensional memory cell array 30[1], first, The 2D memory cell is used as the target for the write operation in the same manner as the bulk erase of the array 30[1]. Select channel array 30[1].

[0117] In the two-dimensional memory cell array 30[1], a potential V3 is applied to the wiring WWL[1,1]. The transistors 12 in the first row are turned on, and the wirings WWL[2,1] to [m2,1] are The transistors 12 in the second row to the m2th row are turned off as GND. A potential V2 is applied to WBL[1], and the wirings WBL[2] to [m1] are set to GND. The wiring RWL[1,1] to [m2,1] can be set as GND.

[0118] As a result, the node of the memory cell 10 in the first row and first column of the two-dimensional memory cell array 30[1] The potential V2 is applied to the node FN, which means that the data "1" is written. , 0V is applied to the nodes FN in the first row, second column to the m1th column of the two-dimensional memory cell array 30[1]. is given, that is, data "0" is written.

[0119] In addition, similar to the collective erasure of the two-dimensional memory cell array 30[1], Wiring WWL[1,2] to [m2,m3] electrically connected to I30[2] to [m3] ] is GND, and the nodes F of the memory cells 10 (1,1,2) to (m1,m2,m3) The potential of N is maintained.

[0120] In reading the first row of the two-dimensional memory cell array 30[1], first, the wiring SG1[ 1] is applied with a potential V1 to turn on the transistors of the selection transistor cells 60(1,1) to (m1,1). The transistor 61 is turned on, and the wirings RBL[1] to [m1] are connected to the corresponding wirings RBL[ 1,1] to [m1,1]. Also, the wiring SG1[2] to [m3] are connected to As ND, the transistors 60(1,2) to (m1,m3) of the selection transistor cells 1 is turned off, and the wirings RBL[1] to [m1] are turned on by the corresponding wirings RBL[1,2] In this way, the two read operations are performed. Then, select the first-dimensional memory cell array 30[1].

[0121] In the two-dimensional memory cell array 30[1], the memory cell 10 in the first row to be read The wiring RWL[1,1] connected to is set to GND. A potential V4 is applied to the wirings RWL[2,1] to [m2,1] connected to the cell 10. The transistor 11 of the memory cell 10 is turned on.

[0122] Here, the bias potential Vbias of the read circuit shown in FIG. 6A is changed from the potential Vdd to G A wiring to which a power supply potential Vdd is supplied as ND is connected to the wiring RBL.

[0123] As a result, the data “1” is written to the memory cell 10 (1,1,1 ) is connected to the wiring RBL[1], which is electrically connected to the wiring SL[1,1] and the potential drops. , the memory cells 10(2,1,1) to (m The wirings RBL[2] to [m1] connected to the wirings SL[2,1] to [ m1,1], the potential is Vdd.

[0124] The wirings WWL[1,1] to [m2,m3] are connected to GND, and the memory cell 10 (1 The potentials of the nodes FN of (m1, m2, m3) through (m1, m2, m3) are maintained.

[0125] The above explanation is for the case where an n-type transistor using electrons as carriers is used. However, instead of n-type transistors, p-type transistors that use holes as carriers are used. In this case, the operation of the transistor is inverted, so the applied potential should be set appropriately. That's good.

[0126] In the above-described method for driving a semiconductor device, binary (1-bit) data is stored in a memory cell. The above describes the case where data is written, but it is also possible to write three or more levels of information to one memory cell. A multi-value method may be used. For example, a memory cell may be configured to store four values ​​(2 bits) or eight values ​​(3 bits). ), 16-value (4-bit) data, etc. may be held.

[0127] In the semiconductor device described in this embodiment, the off-state current of a transistor including an oxide semiconductor is Because it is so small, it can be used to retain memory contents for a very long period of time. In other words, the refresh operation is unnecessary or the refresh operation is shortened. Since the frequency can be made extremely low, power consumption can be reduced sufficiently. In addition, when there is no power supply (however, it is preferable that the potential is fixed), It is possible to retain the stored contents for a long period of time.

[0128] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating layer due to electron extraction does not occur. In the semiconductor device according to the present invention, the rewritable circuit which is a problem in the conventional non-volatile memory is eliminated. There is no limit to the number of transistors, and reliability is improved dramatically. Since information is written depending on the state, high speed operation can be easily achieved.

[0129] In addition, a transistor using a material other than an oxide semiconductor can operate at sufficiently high speed. Therefore, by combining this with a transistor including an oxide semiconductor, It is possible to sufficiently ensure high speed operation of the semiconductor device (for example, information read operation). In addition, transistors using materials other than oxide semiconductors can be used in various applications where high speed operation is required. It is possible to realize various circuits (logic circuits, driver circuits, etc.) in an appropriate manner.

[0130] In this way, transistors using materials other than oxide semiconductors (or, more broadly, transistors using sufficiently high transistors that can operate at high speeds and transistors that use oxide semiconductors (or, in a broader sense, By integrating a transistor with a sufficiently low off-state current, It is possible to realize a semiconductor device having the above structure.

[0131] Furthermore, in the semiconductor device shown in this embodiment, memory cells are stacked. The memory capacity per unit area can be increased according to the number of layers. The memory cell can achieve the above-mentioned excellent characteristics, and furthermore, it has the same characteristics as a conventional memory. It is possible to provide a semiconductor device having a storage capacity per unit area as large as or even larger than that of the conventional semiconductor device. In addition, in the semiconductor device described in this embodiment, memory cells are stacked in this manner to form a unit. By increasing the memory capacity per area, it is possible to achieve 1TB or more, 5TB or more, It will also be possible to provide storage devices with storage capacities of 10TB or more.

[0132] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0133] (Embodiment 2) In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using:

[0134] <Memory cell configuration> First, the configuration of the memory cell 10 shown in the above embodiment will be described with reference to FIGS. I will explain it below.

[0135] The memory cell 10 shown in FIG. 8A to FIG. 8C includes a transistor 11, a transistor 12 and a capacitance element 14. FIG. 8(A) is a top view of the memory cell 10. FIG. 8(A) is a cross-sectional view corresponding to the dashed line A1-A2 in FIG. 8(A), and FIG. 8(C) is a cross-sectional view corresponding to the dashed line A1-A2 in FIG. This is a cross-sectional view corresponding to the dashed line A3-A4 in the area indicated by the dashed line A1-A2. The figure includes the structure of the transistor 12 in the channel length direction, and the dashed line A3 In the region indicated by -A4, the structure of the transistor 12 in the channel width direction is shown. The channel length direction of the transistor 12 is the direction of the source (source region or source electrode) The direction in which carriers move between the drain and the drain (drain region or drain electrode) The channel width direction of the transistor 12 is the channel It means the direction perpendicular to the longitudinal direction.

[0136] Here, the semiconductor material of the transistor 11 and the semiconductor material of the transistor 12 are different materials. For example, the semiconductor material of the transistor 11 may be a material other than an oxide semiconductor. The semiconductor material is a semiconductor material (such as silicon), and the semiconductor material of the transistor 12 is an oxide semiconductor. A transistor using a material other than an oxide semiconductor, such as polycrystalline silicon, can be On the other hand, transistors using oxide semiconductors have the following characteristics: This allows the charge to be retained for a long period of time.

[0137] Note that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can be used. The technical essence of the present invention is to provide a semiconductor device that can sufficiently suppress the off-state current, such as an oxide semiconductor, in order to retain data. The advantage of using semiconductor materials for the transistor 12 is that they can be reduced to a small amount. The specific configuration of the semiconductor device, such as the materials used in the device and the structure of the semiconductor device, is shown here. There is no need to limit it to anything.

[0138] The transistor 11 includes a conductor 108b, an insulator 132, a semiconductor 134, and an insulator 135. The insulator 132, the semiconductor 134 and the insulator 136 are insulator 104, conductive material 136, and the insulator 132, conductive material 134 and ... The conductive body 108b, the insulator 116, and the insulator 118 are formed in cylindrical openings. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening, and the semiconductor 134 is The insulator 136 is formed in a cylindrical shape inside the semiconductor 134. The insulator 132, the semiconductor 134, and the insulator 136 form the memory cell 10. The semiconductor 134 is formed to extend substantially perpendicularly to the upper surface of the substrate on which the semiconductor 134 is provided. The insulator 136 is not provided on the inside of the insulator 132, and the columnar semiconductor 134 is provided on the inside of the insulator 132. It is also possible to use the following.

[0139] Here, the conductor 108b functions as the gate of the transistor 11, and the insulator 13 2 functions as a gate insulating film of the transistor 11, and the semiconductor 134 is a transistor The semiconductor 134 has a function as an active layer, a source and a drain of the semiconductor 134. The region 134a overlapping with the body 108b functions as a channel forming region of the transistor 11. The region 134b that does not overlap with the conductor 108b serves as the source or drain of the transistor 11. It works like this.

[0140] In this manner, the transistor 11 is configured such that the insulator 132 surrounds the region 134a of the semiconductor 134. The SGT has a conductor 108b that functions as a gate electrode formed to surround the gate electrode. In the semiconductor 134 of the transistor 11, the channel is at the same height as the conductor 108b. Region 134a, which functions as a forming region, is located above and below conductor 108b. The region 134b that functions as the drain is located in the region 134b. The length of the transistor 11 is approximately the same as the thickness of the conductor 108b. The direction is approximately perpendicular to the upper surface of the substrate on which the memory cells 10 are provided. As shown in FIG. 8(B), the channel length direction of the transistor 11 is the same as that of the transistor 12. The channel width of the transistor 11 is approximately perpendicular to the longitudinal direction of the cylindrical semiconductor 13. It is roughly the same length as the circumference of 4.

[0141] In a standard planar transistor, the gate electrode, source electrode, and The drain electrode is formed and the area occupied is 8F 2 On the other hand, the SGT type In the transistor 11, when viewed from above, another structure is formed inside the gate electrode. The area is 4F 2 Thus, the area occupied by the transistor 11 is very small. This reduces the area occupied by the memory cell 10 and reduces the number of The storage capacity per unit area of ​​the semiconductor device can be increased.

[0142] In addition, as in the case of the transistor 11 in FIG. 8, the source electrode and the drain electrode are not explicitly provided. However, for convenience, such a state may be included in the term "transistor." .

[0143] In addition, the opening in which the transistor 11 is provided has a circular upper surface in FIG. However, the present invention is not limited to this. For example, the upper surface may be elliptical, triangular, or quadrilateral. The shape may be a polygon, such as a square. In the case of a polygon, the corners are rounded. In addition, the insulator 132 and the semiconductor 134 may be formed in a shape that matches the shape of the upper surface of the opening. The shape of the upper surface of the insulator 136 may also change. 70 side) of the opening perpendicular to the y axis, the y The cross-sectional area perpendicular to the axis may be narrowed.

[0144] The transistor 12 includes an insulator 106a formed on the insulator 104 and an insulator 106. a semiconductor 106b formed in contact with at least a portion of the upper surface of a; and an insulator 106c formed in contact with at least a portion of the semiconductor 106b and electrically connected to the semiconductor 106b. The conductor 108a and the conductor 108b are formed on the insulating material 106c. 12 and an insulator 112, and at least a portion of the conductor 108a and the conductor 108b are formed on the insulator 112. and a conductor 114 formed between the insulators 106a and 106b. An insulator 116 is formed on the semiconductor 106b, the conductor 108a, and the conductor 108b. An insulator 118 is formed over the edge 116 .

[0145] The transistor 12 has an opening in the insulator 118 that reaches the semiconductor 106b. The insulator 106c, the insulator 112, and the conductor 114 are embedded in the mouth. In addition, the opening separates the conductor 108a and the conductor 108b. The transistor 12 has a conductor 114 that functions as a gate electrode and is surrounded by an insulator 118 or the like. The hole is formed in a self-aligned manner to fill the opening. So, TGSA s-channel FET (Trench Gate Self A It can also be called a linear s-channel FET.

[0146] In the transistor 12, the insulator 118, the insulator 106c, the insulator 112, and the conductor 11 The upper surfaces of the insulator 117 and the insulator 14 are generally flush with each other. 06c, the upper surfaces of the insulator 112 and the conductor 114 are planarized by a CMP method or the like. As a result, the area where the conductor 114 overlaps with the conductors 108a and 108b is almost Therefore, the gate-source and gate-drain of the transistor 24 are almost completely formed. This can reduce the parasitic capacitance that occurs between the two.

[0147] As shown in FIG. 8C, the insulator 106c is a semiconductor 106 It is preferable that the semiconductor 10 is provided so as to cover the side surface of the semiconductor 10 b in the channel width direction. In the vicinity of the side end of 6b in the channel width direction, the insulator 106a or the insulator 106c A continuous junction is formed between the low resistance region 109a and the low resistance region 109b, and the defect level density is reduced. Even if the on-current flows more easily due to the provision of the low-resistance region 109b, the semiconductor 106b The side edge of the channel in the width direction does not become a parasitic channel, and stable electrical characteristics can be obtained. Cut.

[0148] Here, the conductor 108a functions as either the source or the drain of the transistor 12. The conductor 108b functions as the other of the source and drain of the transistor 12. The insulator 112 functions as a gate insulating film of the transistor 12, and the conductor 11 4 functions as the gate of a transistor 12 .

[0149] In addition, in FIG. 8(B) and (C), the ends of the insulator 106a and the semiconductor 106b are roughly The insulator 106a and the semiconductor 106b are formed to coincide with each other. The configuration of the semiconductor device shown is not limited to this.

[0150] In addition, the circles provided on the insulator 104, the conductor 108a, the insulator 116, and the insulator 118 A cylindrical conductor 120 is formed in the cylindrical opening. The conductor 120 is electrically connected to the substrate 108a on which the memory cell 10 is provided. The conductor 120 is formed in a cylindrical shape and extends substantially perpendicular to the upper surface of the conductor 120. Alternatively, the opening of the conductor 120 may be filled with an insulator.

[0151] In addition, the opening in which the conductor 120 is provided has a circular upper surface in FIG. However, the present invention is not limited to this. For example, the upper surface may be elliptical, triangular, or rectangular. In the case of a polygonal shape, the corners are preferably rounded. In addition, the shape of the upper surface of the conductor 120 may be changed in accordance with the shape of the upper surface of the opening. In addition, the cross-sectional area of ​​the opening may be smaller than that of the opening on the upper side (the insulator 170 side). The cross-sectional area of ​​the opening on one side (the semiconductor substrate 150 side) may be narrower.

[0152] The capacitance element 14 includes a conductor 108b, an insulator 116, and a conductor 122. The conductor 108b serves as one of the electrodes of the capacitor 14, and the conductor 122 serves as one of the electrodes of the capacitor 14. The insulator 116 functions as a dielectric of the capacitor element 14. It is sufficient that the conductive material 108b and the conductive material 122 are formed in the overlapping area. That's good.

[0153] As described above, the conductor 108b functions as the gate of the transistor 11 and In the transistor 12, it functions as either the source or the drain, and in the capacitor element 14, it functions as one of the electrodes. That is, the conductor 108b functions as the node FN shown in FIGS. In addition, the wiring WBL shown in FIG. 1(A) and (B) is a conductor 120, and the wiring WWL is a conductor. The body 114 and the wiring RWL correspond to the conductor 122. Also, the semiconductor 134 is provided in an elongated manner. and is electrically connected to a conductor corresponding to the wiring SL and a conductor corresponding to the wiring RBL. .

[0154] Here, the insulator 104, the insulator 106a, the insulator 106c, the insulator 112, the insulator 11 6, the insulator 118, the insulator 132 and the insulator 136 may be referred to as insulating films or insulating layers. In addition, the conductor 108a, the conductor 108b, the conductor 114, the conductor 120, and the conductor The semiconductor 106b and the semiconductor 13 can also be referred to as a conductive film or a conductive layer. 4 can also be called a semiconductor film or a semiconductor layer.

[0155] As will be described in detail later, when the insulator 106a and the insulator 106c are used alone, In some cases, materials may be used that can function as conductors, semiconductors, or insulators. However, when a transistor is formed by stacking the semiconductor 106b, electrons 106b, the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106a 106a and 106c flow near the interface of the transistor. The insulator 1 has a region that does not function as a channel. The semiconductor 106a and the insulator 106c are not described as a conductor and a semiconductor, but as an insulator. do.

[0156] <Transistor 11 Semiconductor> The detailed configuration of the semiconductor 134 will be described below.

[0157] The semiconductor 134 may be, for example, crystalline silicon such as polycrystalline silicon or single crystal silicon. However, it is not limited to this, and microcrystalline silicon and amorphous silicon can also be used. The material is not limited to silicon, and may be germanium, silicon carbide, silicon dioxide, etc. Indium germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. In addition, a semiconductor that can be used for the semiconductor 106b described later may be used.

[0158] When polycrystalline silicon is used as the semiconductor 134, the thickness of the semiconductor 134 is reduced. For example, it is preferably 20 nm or less, more preferably 10 nm or less. This makes it possible to suppress the variation in characteristics of the transistor 11.

[0159] In addition, when polycrystalline silicon or the like is used as the semiconductor 134, hydrogen is supplied to the semiconductor 134. Alternatively, a configuration may be adopted in which a dangling bond in the semiconductor 134 is terminated by supplying a terminating agent.

[0160] In addition, an impurity that imparts p-type conductivity to the semiconductor 134 or an impurity that imparts n-type conductivity to the semiconductor 134 is added. Impurities that impart p-type conductivity include, for example, boron. The impurities that give the n-type conductivity are boron (B) and aluminum (Al). For example, phosphorus or arsenic may be used.

[0161] <Transistor 11 insulator> The detailed configurations of the insulators 132 and 136 will be described below.

[0162] The insulator 132 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used. For example, the insulator 112 may be made of aluminum oxide, Magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide For example, tantalum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used. In the above, silicon nitride oxide is a material that contains more nitrogen than oxygen. Silicon oxynitride is a material that contains more oxygen than nitrogen in its composition. Point.

[0163] The insulator 132 has the effect of blocking hydrogen, water, alkali metals, alkaline earth metals, etc. As such an insulator, for example, a nitride insulating film is preferably used. The nitride insulating film can be made of silicon nitride, silicon oxynitride, aluminum nitride, or the like. The nitride insulating film may be replaced with an insulating film that contains oxygen, hydrogen, water, etc. As the oxide insulating film, an oxide insulating film having a blocking effect may be provided. Aluminum, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide Examples of suitable oxides include yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

[0164] In particular, when the dangling bonds of the semiconductor 134 are terminated with hydrogen, the insulator 132 is hydrogen, If the semiconductor 106 has a water blocking effect, the hydrogen will diffuse and be taken up by the semiconductor 106b. As will be described later in detail, the oxide used in the semiconductor 106b can be suppressed. If hydrogen is absorbed into the semiconductor, the electrical characteristics of the transistor 12 may deteriorate. In other words, the insulator 132 has the effect of blocking hydrogen and water. This allows the electrical characteristics of the transistor 12 to be stable.

[0165] As the insulator 136, an insulator that can basically be used as the insulator 132 is used. However, when the dangling bonds of the semiconductor 134 are terminated with hydrogen, the insulator In this case, hydrogen can be supplied to the semiconductor 134 by making the insulator 136 contain hydrogen. For example, silicon nitride containing hydrogen may be used as the insulating film.

[0166] <Transistor 12 Semiconductor> The detailed configuration of the semiconductor 106b will be described below. The detailed configurations of the insulator 106a and the insulator 106c as well as the insulator 106b will also be described.

[0167] The semiconductor 106b is, for example, an oxide semiconductor containing indium. For example, when indium is contained, the carrier mobility (electron mobility) increases. The body 106b preferably contains the element M. The element M is preferably Ti, Ga, Y, Zr , La, Ce, Nd, Sn or Hf, where M is the element In some cases, a combination of multiple elements may be used. For example, the bond energy with oxygen is For example, the bond energy between oxygen and indium is higher than that between indium and oxygen. Alternatively, the element M may have a function of increasing the energy gap of the oxide semiconductor. The semiconductor 106b preferably contains zinc. If lead is included, it may be prone to crystallization.

[0168] However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. 06b does not contain indium, such as zinc tin oxide, gallium tin oxide, etc. Oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay if there is.

[0169] For example, the insulators 106a and 106c are made of oxygen other than the semiconductor 106b. The semiconductor 106b is an oxide semiconductor including one or more of the elements other than oxygen. Since the insulators 106a and 106c are composed of one or more of the elements, the insulators 10 At the interface between 6a and semiconductor 106b, and at the interface between semiconductor 106b and insulator 106c Therefore, defect levels are less likely to be formed.

[0170] The insulator 106a, the semiconductor 106b, and the insulator 106c each contain at least indium. When the insulator 106a is an In-M-Zn oxide, the sum of In and M is preferably When 100 atomic %, In is preferably less than 50 atomic % and M is preferably less than 50 atomic %. atomic %, and more preferably In is less than 25 atomic % and M is 75 atomic %. When the semiconductor 106b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. %, M is less than 75 atomic %, and more preferably In is 34 atomic % The insulator 106c is In-M-Zn In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as that of the insulator 106a may be used. In some cases, the insulator 106c does not need to contain indium. For example, 106a and / or the insulator 106c is gallium oxide or Ga-Zn oxide. In addition, each of the insulators 106a, the semiconductor 106b, and the insulator 106c may be The atomic numbers of elements do not have to be in a simple integer ratio.

[0171] For example, when the insulator 106a or the insulator 106 A typical example of the atomic ratio of the metal elements in the target used in c is In:M:Zn=1:2. :4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1 :3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn =1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M: Zn=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In: M:Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, I n:M:Zn=1:6:9, In:M:Zn=1:10:1, etc. The atomic ratio of the metal elements in the target used for 6a or the insulator 106c is M:Zn=10: It can also be set to 1.

[0172] In addition, for example, when a film is formed by a sputtering method, the ternary Representative examples of atomic ratios of metal elements in the get are In:M:Zn=1:1:1, In:M :Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1: 2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn= Examples include 4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, etc. In particular, the atomic ratio of In:Ga:Zn=4:2:4.1 is used as a sputtering target. When using this, the atomic ratio of the semiconductor 106b to be formed is In:Ga:Zn=4:2:3. It may be nearby.

[0173] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the insulator 106c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 100% or more. More preferably, it is 90% or more.

[0174] The semiconductor 106b is made of, for example, an oxide having a large energy gap. The energy gap of 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. The value is preferably 8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. The energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b. The energy gap of the insulator 106c is larger than that of the semiconductor 106b. Bigger than a cup.

[0175] The semiconductor 106b is an oxide having a larger electron affinity than the insulator 106a or the insulator 106c. For example, the semiconductor 106b is made of a material selected from the insulators 106a and 106c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. V or less, more preferably, an oxide having a larger energy than the above by 0.15 eV to 0.4 eV is used. , electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. In other words, The energy level of the conduction band minimum of the body 106a or the insulator 106c is equal to that of the conduction band minimum of the semiconductor 106b. It is closer to the vacuum level than the energy level of the lower band.

[0176] At this time, when a gate voltage is applied, the insulator 106a, the semiconductor 106b and the insulator 10 A channel is formed in the semiconductor 106b having a large electron affinity among the semiconductors 106a and 106b. When a voltage is applied to the insulator 106a, the semiconductor 106b and the insulator 106b are electrically connected to each other. Current may also flow near the interface of 6c with semiconductor 106b.

[0177] As described above, when the insulators 106a and 106c are used alone, they are not conductive or semi-conductive. It consists of a material that can function as either a conductor or an insulator. When a transistor is formed by stacking the semiconductor 106b and the semiconductor 106, electrons flow through the semiconductor 106b and the semiconductor 106. The flow passes through the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c. The insulators 106a and 106c do not function as the channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 10 The insulator 106a and the insulator 6c are not described as semiconductors but as insulators. The insulator 106c is described as an insulator because it is a transistor compared to the semiconductor 106b. Since the function of the insulating material is similar to that of an insulator, the insulating material 106a or the insulator 106c is In addition, a material that can be used for the semiconductor 106b may be used.

[0178] Here, between the insulator 106a and the semiconductor 106b, In addition, the semiconductor 106b and the insulator 106c may have a mixed region. In some cases, the semiconductor 106b and the insulator 106c may have a mixed region. Therefore, the level density of the insulator 106a, the semiconductor 106b, and the insulator 106c is In the laminate, the energy changes continuously near each interface (also called continuous junction). The band diagram is a band diagram of the insulator 106a and the semiconductor 106b, or the insulator 106 In some cases, the interface between the semiconductor 106c and the semiconductor 106b cannot be clearly distinguished.

[0179] At this time, the electrons flow into the semiconductor 106b, not into the insulator 106a and the insulator 106c. As described above, the electrons move mainly through the interface between the insulator 106a and the semiconductor 106b. The defect density at the interface between the semiconductor 106b and the insulator 106c is By lowering the concentration, the movement of electrons in the semiconductor 106b is less hindered, The on-state current of the transistor can be increased.

[0180] In addition, the on-current of a transistor can be increased by reducing the factors that inhibit the movement of electrons. For example, if there is no factor that inhibits the movement of electrons, the electrons can move efficiently. It is estimated that the electron movement is slower when the physical unevenness of the channel formation region is large, for example. is also inhibited.

[0181] In order to increase the on-current of the transistor, for example, The square of the surface (the surface to be formed, here the upper surface of the insulator 106a) in the range of 1 μm×1 μm Root Mean Square (RMS) roughness less than 1 nm, preferably is less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in the range of 1 μm × 1 μm is 1n m, preferably less than 0.6 nm, even more preferably less than 0.5 nm, The maximum height difference (PV ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, More preferably, it is less than 7 nm. RMS roughness, Ra and PV are - Scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0182] In addition, in order to increase the on-state current of the transistor, the thickness of the insulator 106c is preferably as small as possible. The thickness of the insulator 106c is preferably smaller than the thickness of the insulator 106a. For example, the thickness is less than 10 nm, preferably 5 nm or less, and More preferably, the insulator 106c has a region of 3 nm or less. 06c is a semiconductor 106b in which a channel is formed, and is formed by introducing oxygen other than oxygen constituting the adjacent insulator. It has the function of blocking elements (hydrogen, silicon, etc.) from entering. It is preferable that the insulator 106c has a certain thickness. For example, the thickness is 0.3 nm or more. , preferably 1 nm or more, more preferably 2 nm or more insulator 10 Just use 6c.

[0183] In order to increase reliability, it is preferable that the insulator 106a is thick. 0 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and more preferably The insulator 106a may have a region with a thickness of 60 nm or more. By thickening the insulator 106a, a channel is formed from the interface between the insulator 106a and the adjacent insulator. The distance to the semiconductor 106b can be increased. However, the productivity of the semiconductor device decreases. Therefore, for example, it is set to 200 nm or less, preferably 120 nm or less, and more preferably The insulating layer 106a may have a region with a thickness of 80 nm or less.

[0184] Silicon in an oxide semiconductor can serve as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the more preferable. b and the insulator 106a, for example, by secondary ion mass spectrometry (SIMS). 1×10 16 ato ms / cm 3 More than 1×10 19 atoms / cm 3 Less than or equal to 1×10 16 ato ms / cm 3 5×10 or more 18 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 The region with the following silicon concentration In addition, a 1×1 0 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, preferably 1×1 0 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 More preferably, 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 Silicon concentration below It has a range of degrees.

[0185] In order to reduce the hydrogen concentration in the semiconductor 106b, the insulator 106a and the insulator 10 It is preferable to reduce the hydrogen concentration in the insulator 106a and the insulator 106c. In S, 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 below , preferably 1 x 10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3 below , more preferably 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 The hydrogen concentration in the semiconductor 106b is reduced. To prevent this, it is preferable to reduce the nitrogen concentration in the insulators 106a and 106c. The thickness of the insulator 106a and the insulator 106c is 1×10 15 atoms / cm 3 5×10 or more 19 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 5×10 or more 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / c m 3 More than 1×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atom s / cm 3 5×10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0186] Insulator 106a, semiconductor 106b, and insulator 106c shown in this embodiment, particularly semiconductor 106b is an oxide semiconductor having a low impurity concentration and a low density of defect states (few oxygen vacancies). and can be called a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source; The carrier density can be reduced. Therefore, a channel region is formed in the oxide semiconductor. The transistors used in this study have electrical characteristics in which the threshold voltage is negative (also called normally-on). In addition, oxide semiconductors that are high purity intrinsic or substantially high purity intrinsic are rarely The low defect density of the material may also result in a low trap density. Intrinsic or substantially highly purified intrinsic oxide semiconductors have a significantly small off-state current and a high channel density. The width W is 1×10 6Even if the device has a channel length L of 10 μm, the source and drain electrodes When the voltage between the drain electrodes (drain voltage) is in the range of 1 V to 10 V, the off-state current is Below the measurement limit of the body parameter analyzer, i.e., 1 × 10 -13 Achieved a characteristic of A or lower It is possible.

[0187] Therefore, the high purity intrinsic or substantially high purity intrinsic oxide semiconductor has a channel region. The transistors in which this region is formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor do not disappear until It takes a long time to charge up and can behave like a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor with a high density of drop states has high electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkali metals. These include lithium-earth metals.

[0188] The hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c bonds with metal atoms. The oxygen reacts with the water to form water, and the lattice from which the oxygen is removed (or the part from which the oxygen is removed) When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms, forming a carrier. In particular, hydrogen trapped in oxygen vacancies can cause the band structure of semiconductors to change. Therefore, the hydrogen-containing oxide semiconductor A transistor using a conductor tends to have a normally-on characteristic. It is preferable that the semiconductor 106b and the insulator 106c have as little hydrogen as possible. Specifically, the insulator 106a, the semiconductor 106b, and the insulator 106c are SIM The hydrogen concentration obtained by S analysis is 2×10 20 atoms / cm 3 Less than or equal to 5, preferably ×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below Bottom, 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 The following applies.

[0189] In addition, in the insulator 106a, the semiconductor 106b, and the insulator 106c, SIMS analysis The concentration of the alkali metal or alkaline earth metal obtained by 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 The following are the alkali metals and When alkaline earth metals combine with oxide semiconductors, they can generate carriers. Therefore, the insulator 106a and the semiconductor 10 6b and the insulator 106c. preferable.

[0190] Furthermore, when nitrogen is contained in the insulator 106a, the semiconductor 106b, and the insulator 106c, This generates electrons as carriers, increases the carrier density, and makes it easier to make the material n-type. A transistor using an oxide semiconductor film including such a semiconductor tends to be normally-on. Therefore, it is preferable that the nitrogen content in the oxide semiconductor film be reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is 5×10 18 atoms / cm 3 below It is preferable to set

[0191] Here, as shown in FIG. 8B, the conductor 108a such as the semiconductor 106b or the conductor 1 In the region adjacent to 08b (shown by the dotted line in FIG. 8B), a low resistance region 109a and a low resistance region The low resistance region 109a and the low resistance region 109b are mainly The oxygen is extracted by the conductor 108a or the conductor 108b in contact with the semiconductor 106b. Alternatively, the conductive material contained in the conductor 108a or the conductor 108b may be mixed with an element in the semiconductor 106b. Such low resistance regions 109a and 109b are formed by bonding. As a result, the conductor 108a or the conductor 108b comes into contact with the semiconductor 106b. Since the resistance can be reduced, the on-current of the transistor 12 can be increased. Cut.

[0192] As shown in FIG. 8B, the semiconductor 106b is made of a conductor 108a and a conductor 108b. There is a region between the conductors 108a and 108b that is thinner than the region where the conductors 108a and 108b overlap. This is because when the conductor 108a and the conductor 108b are formed, the semiconductor 106b The upper surface of the semiconductor 106b is formed by removing a part of the upper surface of the conductor 10 When the conductor that becomes the low resistance region 109a and the conductor 108b is formed, In this way, a region of low resistance similar to the region 109b may be formed. b, by removing the region located between the conductors 108a and 108b. It is possible to prevent a channel from being formed in a low resistance region on the top surface of the semiconductor 106b. In the following drawings, even if thin film regions are not shown in enlarged views, the same There may be cases where thin film regions are formed.

[0193] The above-mentioned three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c is just an example. For example, a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be used. Alternatively, a single-layer structure may be used in which neither the insulator 106a nor the insulator 106c is provided. Alternatively, the insulator 106a, the semiconductor 106b, or the insulator 106c may be used. As an n-layer structure (n is an integer of 4 or more) having either an insulating material, a semiconductor material, or a conductor material. That's fine.

[0194] <Insulators and conductors of transistor 12> Each of the non-semiconductor components of transistor 12 will be described in detail below.

[0195] It is preferable that the insulator 104 contains a small amount of water or hydrogen in the film. The insulator 104 is preferably an insulator having excess oxygen. Examples of the elements include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, and silicon. Copper, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, Insulators containing lanthanum, neodymium, hafnium or tantalum, either in single or multilayered configurations. For example, the insulator 104 may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Hafnium oxide or tantalum oxide may be used. Preferably, silicon oxide or oxide is used. Silicon nitride is used.

[0196] The insulator 104 is preferably an insulator having excess oxygen. By providing the semiconductor 104, the insulator 104 is connected to the insulator 106a, the semiconductor 106b, and the insulator 10 Oxygen can be supplied to the oxide semiconductor insulator 106. a) It is possible to reduce oxygen vacancies that cause defects in the semiconductor 106b and the insulator 106c. As a result, the insulator 106a, the semiconductor 106b, and the insulator 106c have a low defect level density and are stable. It is possible to provide an oxide semiconductor having stable characteristics.

[0197] In this specification and the like, the term "excess oxygen" refers to oxygen contained in excess of the stoichiometric composition. Or, the excess oxygen refers to oxygen that is contained in the solution by heating, for example. This refers to oxygen released from a film or layer. Excess oxygen can, for example, move inside a film or layer. The movement of excess oxygen can occur between atoms in a film or layer, or between oxygen atoms that compose the film or layer. In some cases, the two move in a domino effect, replacing each other.

[0198] The insulator 104 having excess oxygen has a temperature programmed desorption spectroscopy (TDS) analysis of 10 In the surface temperature range of 0°C to 700°C or 100°C to 500°C, the oxygen The amount of desorption is 1.0×10 14 molecules / cm 2 Above 1.0×10 16 Molec ules / cm 2 It is preferable that the value is less than 1.0×10 15 Molecules / c m 2 Above 5.0×10 15 molecules / cm 2 It is more preferable that:

[0199] The method for measuring the amount of released molecules using TDS analysis is as follows, taking the amount of released oxygen as an example. will explain.

[0200] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated by the integral value of the ion intensity of the released gas. and by comparison with a standard sample the total amount of gas released can be calculated.

[0201] For example, the results of a TDS analysis of a silicon substrate containing a standard sample of hydrogen with a given density, From the results of the TDS analysis of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is shown below Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis is Assume that all of the charge is from oxygen molecules. For example, the mass-to-charge ratio of CH3OH is 32, The possibility of their existence is low, so they are not considered here. Oxygen molecules containing oxygen atoms with mass numbers 17 and 18 also occur in nature. Not taken into consideration since its presence ratio is extremely small.

[0202] N O2 =N H2 / S H2 ×S O2 ×α

[0203] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is the standard This is the integral value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let us assume that S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. Details of the above formula For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. Measurements are performed using a silicon substrate containing a fixed amount of hydrogen atoms.

[0204] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of atoms can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, the amount of released oxygen molecules can be evaluated to determine the amount of released oxygen atoms. It is also possible to estimate.

[0205] In addition, N O2 is the amount of oxygen molecules released. The amount of oxygen released when converted to oxygen atoms is This is twice the amount of offspring released.

[0206] Alternatively, insulators that release oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to the peroxide radical is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (E In SR (Electron Spin Resonance), the g value is around 2.01. It is also possible to have asymmetric signals.

[0207] It is preferable that the amount of water or hydrogen contained in the insulator 104 is small. The body 104 has a temperature of 100°C to 700°C or 100°C to 500°C by TDS analysis. In the range of surface temperatures below, the amount of water molecules desorbed is 1.0×10 13 molecules / cm 2 More than 1.4×10 16 molecules / cm 2 Below, 1.0×10 13 Mol ecules / cm 2 Above 4.0×10 15 molecules / cm 2 Below, one more .0×10 13 molecules / cm 2 Above 2.0×10 15 Molecules / cm 2 In addition, it is preferable that the temperature is within the range of 100°C to 700°C by TDS analysis. or in the range of surface temperatures from 100°C to 500°C, the amount of desorption of hydrogen molecules is 1.0×10 1 3 molecules / cm 2 More than 1.2 x 10 15 molecules / cm 2 below, Furthermore, 1.0×10 13 molecules / cm 2 Above 9.0×10 14 molecu les / cm 2 It is preferable that the following is true:

[0208] As described above, it is preferable that the upper or lower surface of the semiconductor 106b is highly flat. Therefore, the upper surface of the insulator 104 is subjected to chemical mechanical polishing (CMP). The planarization process is carried out using methods such as cal polishing to improve the flatness. Good too.

[0209] The conductor 108a and the conductor 108b are the source electrode or It functions as either a drain electrode or a drain electrode.

[0210] The conductor 108a and the conductor 108b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, an alloy or a compound may be used, and a conductor containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0211] The insulator 112 functions as a gate insulating film of the transistor 12. The insulator 112 may be an insulator having excess oxygen, similar to the insulator 104. By providing the insulating material 112, the insulating material 106a, the semiconductor 106b, and the insulating material 106c are can supply oxygen to

[0212] The insulator 112 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used. For example, the insulator 112 may be made of aluminum oxide, Magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide For example, tantalum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0213] The conductor 114 functions as a gate electrode of the transistor 12. Any conductor that can be used for the conductor 108a and the conductor 108b may be used.

[0214] Here, as shown in FIG. 8C, the semiconductor 106b (The electric field generated by the conductor can electrically surround the semiconductor.) The structure of the transistor that surrounds it is called the surrounded channel (s-channel). Therefore, the entire semiconductor 106b (upper surface, lower surface, and side surface) is covered with a chuck. In the s-channel structure, a transistor has a source-drain A large current can be passed through it, and the current when it is conductive (on-state current) can be increased.

[0215] In addition, when the transistor has an s-channel structure, the side surface of the semiconductor 106b is Therefore, the thicker the semiconductor 106b, the larger the channel region. That is, the thicker the semiconductor 106b, the higher the on-state current of the transistor. In addition, the thicker the semiconductor 106b, the greater the proportion of the region with high carrier controllability. Therefore, the subthreshold swing value can be reduced. For example, it is preferably 10 nm or more. Preferably, the thickness is 20 nm or more, more preferably, 30 nm or more, and even more preferably, 50 nm or more. However, the productivity of the semiconductor device may be reduced. Therefore, for example, it is 300 nm or less, preferably 200 nm or less, and more preferably In this case, the semiconductor 106b may have a region with a thickness of 150 nm or less.

[0216] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. For example, The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. More preferably, the transistor has a channel width of 20 nm or less. or less than 40 nm, more preferably less than 30 nm, and even more preferably less than 20 nm. It has a range.

[0217] The insulator 116 serves not only as a dielectric for the capacitive element 14 but also as a protective insulator for the transistor 12. It is preferable that the insulator 116 also functions as an insulating film. The thickness of the insulator 116 may be at least 20 nm or at least 200 nm. It is preferably formed in contact with the upper surface of the insulator 104 .

[0218] The insulator 116 may be, for example, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in The insulator 116 is made of oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, or the like. It is preferable that the insulating material has an effect of blocking metals, etc. Examples of such insulating materials include As the nitride insulating film, a silicon nitride, a nitride oxide, etc. can be used. Examples of the nitride insulating film include silicon nitride, aluminum nitride, and aluminum oxide nitride. Instead, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, and oxide. Gallium nitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Examples include Funium.

[0219] Here, the insulator 116 is preferably formed by sputtering. It is more preferable to carry out the sputtering method in an atmosphere containing By forming the insulator 116, the surface of the insulator 104 (insulator 1 After the film 16 is formed, oxygen is added to the vicinity of the interface between the insulator 104 and the insulator 116 .

[0220] The insulator 116 is an insulator that is less permeable to oxygen than the insulator 104, and serves to block oxygen. By providing such an insulator 116, When oxygen is supplied from the body 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c, Therefore, the oxygen can be prevented from being released to the outside above the insulator 116.

[0221] Aluminum oxide is resistant to both impurities such as hydrogen and moisture, and oxygen. It is preferable to use it for the insulator 116 because it has a high blocking effect of preventing transmission.

[0222] The insulator 118 functions as an interlayer insulating film. Any insulator that can be used as the insulating material may be used.

[0223] The conductor 120 is electrically connected to the source or drain electrode of the transistor 12. The conductor 120 functions as a wiring. The conductor 120 may be a conductor such as phosphorus. A semiconductor such as polycrystalline silicon doped with impurities may also be used.

[0224] The conductor 122 functions as the other electrode of the capacitor. Any conductor that can be used for the conductor 108a and the conductor 108b may be used.

[0225] The above-described structure provides the transistor 12 with stable electrical characteristics. Alternatively, a transistor 12 having a small leakage current when not conducting can be provided. Alternatively, it is possible to provide a transistor 12 having high frequency characteristics. Alternatively, the transistor 12 can have normally-off electrical characteristics. Alternatively, a transistor 12 having a small subthreshold swing value can be provided. It is possible to provide a highly reliable transistor. By using the transistor 12 in the memory cell 10, the memory contents can be retained for a longer period of time. It is possible to provide a semiconductor device that can

[0226] <Memory cell array configuration> Next, an example of the configuration of the three-dimensional memory cell array shown in the above embodiment will be described with reference to FIGS. This will be explained using 11.

[0227] As part of a three-dimensional memory cell array, a two-dimensional memory cell array 30[1] is The structures of modules 10 (1,1,1) to (1,4,4) are shown in Figs. 9 to 11 as examples. 9 is a three-dimensional schematic diagram of memory cells 10 (1,1,1) to (1,4,4). In FIG. 9, a rectangular coordinate system consisting of x-axis, y-axis, and z-axis is set for convenience, as in FIG. 2. Here, the upper surface of the substrate on which the three-dimensional memory cell array is provided is approximately in the xz plane. The y-axis is parallel to the upper surface of the substrate, and the y-axis is approximately perpendicular to the upper surface of the substrate. 10 (e.g., insulator 106c, insulator 112, etc.) are omitted. do.

[0228] FIG. 10 is a top view of memory cells 10(1,4,1) through (1,4,4). 10A is a cross-sectional view corresponding to the dashed line B1-B2 of FIG. FIG. 11(B) corresponds to the dashed line B3-B4 in FIG. 1 is a corresponding cross-sectional view of memory cells 10(1,4,1) through (1,4,4). In the region indicated by the dashed line B1-B2, In the region indicated by the dashed line B3-B4, the memory cell 10 (1 1, 4, 1) to (1, 4, 4) show the structure of the transistor 12 in the channel width direction. is.

[0229] The structure of each memory cell 10 is similar, and please refer to the description of the structure of the memory cell 10 above. However, the memory cells 10 (e.g., FIG. 2) formed on the same plane may be used. In the memory cells 10 (1,1,1) to (m1,1,m3), etc., shown in FIG. , the insulator 116 and the insulator 118 may be integral with each other.

[0230] As shown in FIG. 11A, the insulator 132, the semiconductor 134, and the insulator 136 are arranged in a y-axis direction. The memory cells 10 (1,1,1) to (1,4, 1) is shared. That is, in the memory cells 10 arranged in the y-axis direction, The insulator 132, the semiconductor 134, and the insulator 136 are shared. The region 134b that functions as the source or drain of the transistor 11 in the y-axis direction In other words, the memory cells 10 are adjacent to each other in the y-axis direction. In the memory cell 10, the transistors 11 are electrically connected in series. There are.

[0231] In this manner, the insulator 132, the semiconductor 134, and the insulator 136 form one memory cell. The transistors 11 included in the transistor string 20 are formed together. For example, If the transistor 11 were a standard planar transistor, However, the structure required the formation of plugs and wiring. By using SGT as 11, the sources of the multiple transistors 11 can be self-aligned. and the drain are connected in series.

[0232] In addition, in the semiconductor 134 of the uppermost memory cell 10, the upper surface of the semiconductor 134 and A conductor electrically connected to the low power supply potential line is formed so as to contact the wiring SL. Also, the transistor 6 in the semiconductor 134 of the memory cell 10 at the bottom The connection to 1 will be described later.

[0233] As shown in FIG. 11A, the conductor 120 is elongated in a direction substantially parallel to the y-axis. The memory cells 10(1,1,1) to 10(1,4,1) share the same data. In other words, the conductor 120 is shared among the memory cells 10 arranged in the y-axis direction. The conductor 120 is connected to the source or drain of the transistor 12 in the memory cell 10. It is electrically connected to the other and functions as the wiring WBL shown in FIG.

[0234] In addition, in the conductor 120 of the uppermost memory cell 10, the upper surface of the conductor 120 is a wiring. It is preferable to cover the SL with an insulator so that it does not come into contact with the conductor or other objects that function as SL. In addition, the connection between the conductor 120 of the memory cell 10 at the bottom and the transistor 62 is More details will be provided later.

[0235] As shown in FIG. 10 and FIG. 11B, the conductor 114 is arranged in a direction substantially parallel to the x-axis. The memory cells 10(1,4,1) to 10(1,4,4) are formed in an elongated manner. That is, in the memory cells 10 arranged in the x-axis direction, the conductors 114 are The conductor 114 is provided as the gate of the transistor 11 in the memory cell 10. It also functions as the wiring WWL shown in FIG. 2. In the three-dimensional memory cell array 40 shown in FIG. 11, the insulator 106c and the insulator 112 are also The memory cells arranged in the x-axis direction are patterned in the same manner as the conductor 114. In 10, the insulator 106c and the insulator 112 are also shared. For example, the conductors 114 and the insulators 112 are arranged in the memory cells 10 arranged in the x-axis direction. The insulator 106c is shared by the memory cells 10 arranged in the x-axis direction. Alternatively, each memory cell 10 may be patterned in an island shape.

[0236] As shown in FIG. 10, the conductor 122 is formed to extend in a direction substantially parallel to the x-axis. This is shared by memory cells 10(1,4,1) to (1,4,4). That is, the conductor 122 is shared by the memory cells 10 arranged in the x-axis direction. The electrode 122 also functions as the other electrode of the capacitor element 14 in the memory cell 10. , and functions as the wiring RWL shown in FIG. 2 and the like.

[0237] With the above-mentioned configuration, the memory cells 10 are stacked in a direction perpendicular to the upper surface of the substrate. In this way, a three-dimensional memory cell array can be provided. By providing the layers in this way, the memory capacity per unit area can be increased according to the number of layers. The memory cell includes two transistors and one capacitance element. Because there are a relatively large number of elements, the memory capacity per unit area is smaller than that of conventional memories. In contrast, by using the semiconductor device described in this embodiment mode, In addition to these excellent characteristics, the memory capacity per unit area is equal to or better than that of conventional memory. A semiconductor device having a large storage capacity can be provided. In such a device, memory cells can be stacked to increase the memory capacity per unit area. This allows for the creation of storage capacities of 1TB or more, 5TB or more, or 10TB or more. It is also possible to provide a storage device.

[0238] <Configuration of selection transistor array> Next, one of the configurations of the transistors included in the selection transistor array shown in the above embodiment will be described. An example will be described with reference to FIGS.

[0239] 12(A) and 12(B) show the transistors provided in the selection transistor array 50 shown in FIG. 12A is a cross-sectional view of the transistor 61. The cross-section C1-C2 shown in FIG. 12B is a cross-sectional view of the transistor 61. The figure shows a cross section in the channel width direction.

[0240] The transistor 61 shown in FIGS. 12A and 12B is a transistor using a semiconductor substrate 150. The transistor 61 is a region 172a in the semiconductor substrate 150 and a region 172b in the semiconductor substrate 150. 1, the insulating material 162a and the conductor 154a are disposed in the region 172b. Although not shown, a sidewall insulator may be provided in contact with the side surface of the conductor 154a. In addition, when a sidewall insulator is provided in contact with the side surface of the conductor 154a, the region In the region 172a and the region 172b, the sidewall insulator is overlapped with the sidewall insulator. This can result in regions with lower impurity concentrations than regions that do not overlap with the side-wall insulator. .

[0241] In transistor 61, regions 172a and 172b are the source and drain regions. The insulator 162a functions as a gate insulator. The conductor 154a also functions as a gate electrode. The resistance of the channel formation region can be controlled by the potential applied to the conductive body 154a. That is, the potential applied to the conductor 154a causes a current between the region 172a and the region 172b. Conduction / non-conduction can be controlled.

[0242] The semiconductor substrate 150 may be, for example, a single semiconductor substrate such as silicon or germanium. Or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, nitrogen oxide A semiconductor substrate made of lead, gallium oxide, or the like may be used. Preferably, the semiconductor substrate 150 A single crystal silicon substrate is used as the substrate.

[0243] The semiconductor substrate 150 is a semiconductor substrate having impurities that impart p-type conductivity. However, a semiconductor substrate having impurities that impart n-type conductivity is used as the semiconductor substrate 150. In that case, the region that will become the transistor 61 is given a p-type conductivity. A well having an impurity may be disposed. Alternatively, the semiconductor substrate 150 may be an i-type. I don't.

[0244] Note that a substrate used for the semiconductor device shown in this embodiment mode is not limited to a semiconductor substrate. For example, when forming an active layer such as a transistor 61 by film formation, an insulating substrate Alternatively, a conductive substrate or the like can be used. An example of an insulating substrate is a glass substrate. , quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate In addition, there are semiconductor substrates that have an insulating region inside the semiconductor substrate. Even if a substrate such as an SOI (Silicon On Insulator) substrate is used, Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. , a substrate in which a conductor or semiconductor is provided on an insulator substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate and a substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have elements mounted thereon. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, and a memory element.

[0245] In addition, a flexible substrate that can withstand the heat treatment during transistor fabrication can be used as the substrate. As a method for forming a transistor on a flexible substrate, Another method is to fabricate a transistor on a substrate, peel it off, and transfer it to a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. The substrate may be a sheet, film, or foil having woven fibers. The substrate may be stretchable. Also, the substrate may be designed to retain its original shape when bending or pulling is stopped. The substrate may have a property of returning to its original shape. Alternatively, the substrate may have a property of not returning to its original shape. The thickness is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the thickness is set to 15 μm or more and 300 μm or less. The weight can be reduced. Also, by making the substrate thinner, it is possible to reduce the extension even when glass is used. If the material has shrinkage or the property of returning to its original shape when bending or pulling is stopped, Therefore, in order to reduce the shock applied to the semiconductor device on the board due to dropping, etc. That is, a robust semiconductor device can be provided.

[0246] Regions 172a and 172b are regions having impurities that impart n-type conductivity. In this manner, the transistor 61 constitutes an n-channel transistor.

[0247] Note that transistor 61 is isolated from adjacent transistors by region 160, etc. The region 160 is an insulating region.

[0248] The semiconductor device shown in FIGS. 12A and 12B includes an insulator 132, a semiconductor 134, and an insulator 135. 36, insulator 164, insulator 166, insulator 168, insulator 170, and conductor 1 80a, conductor 180b, conductor 178a, conductor 178b, conductor 176a, , and a conductor 174a. Here, the insulator 132, the semiconductor 134, and the insulator 136 are formed in the above-mentioned three-dimensional memory cell array 40.

[0249] The insulator 164 is formed on the transistor 61. The insulator 166 is formed on the insulator 1 64. Insulator 168 is formed on insulator 166. Insulator A body 170 is formed on the insulator 168 .

[0250] Insulators 164, 166, 168 and 170 reach region 172a. The opening has a cylindrical shape, and the opening contains an insulator 132, a semiconductor 134, and an insulator 135. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening. The insulator 134 is formed cylindrically inside the insulator 132, and the insulator 136 is the semiconductor 134. The insulator 132, the semiconductor 134, and the insulator 136 are formed in a cylindrical shape on the inside. The insulating film 154 is formed to extend substantially perpendicular to the upper surface of the substrate 150 .

[0251] An opening is formed in at least a part of the bottom surface of the insulator 132, and the semiconductor The semiconductor body 134 is in contact with the region 172a. corresponds to any one of the wirings RBL[1,1] to [m1,m3] shown in FIG. The region 172a functions as a source region or a drain region of the transistor 61. By adopting the above-mentioned configuration, the wiring RBL The source region or drain region of the transistor 61 of the selected transistor cell 60 is electrically connected to can be effectively connected.

[0252] Additionally, the insulator 164 has an opening extending to the region 172b and an opening extending to the conductor 154a. The openings are filled with a conductor 180a and a conductor 180b. Additionally, the insulator 166 has an opening that reaches the conductor 180a and an opening that reaches the conductor 180b. The openings are provided with conductors 178a and 178b. The insulator 168 has an opening that reaches the conductor 178a. A conductor 176a is embedded in the opening. 6a, and a conductor 174a is embedded in the opening.

[0253] Here, the conductor 174a functions as a source region or a drain region of the transistor 61. 5 and the like. ]. The conductor 178b functions as the gate of the transistor 61. The conductor 154a is electrically connected to the conductor 154a and functions as the wiring SG1 shown in FIG. The data can be read out through the wiring SG1 and the transistor 61 thus formed. In this case, any one of the two-dimensional memory cell arrays 30[1] to [m3] can be selected. Cut.

[0254] The insulators 164, 166, 168 and 170 may be, for example, boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0255] One or more of the insulators 164, 166, 168, and 170 may be an insulator such as hydrogen. It is preferable to have an insulator that has the function of blocking impurities and oxygen. Impurities such as hydrogen and acids are present below the transistors 12 included in the memory cell array 40. By disposing an insulator that has the function of blocking the element, the electrical The characteristics can be stabilized.

[0256] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include HO. Uranium, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators including titanium, hafnium, or tantalum may be used in single or multilayer configurations.

[0257] Conductor 180a, Conductor 180b, Conductor 178a, Conductor 178b, Conductor 176a The conductor 174a may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, Yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum A conductor containing one or more of zinc and tungsten may be used in a single layer or a multilayer structure. For example, the conductor may be an alloy or a compound, such as an aluminum-containing conductor, a copper- and titanium-containing conductor, Conductors, conductors containing copper and manganese, conductors containing indium, tin and oxygen, Conductors containing titanium and nitrogen may also be used.

[0258] 12C and 12D show transistors provided in the selection transistor array 50 shown in FIG. 12C is a cross-sectional view of the transistor 62. The cross section C5-C6 shown in FIG. 12(D) is a cross-sectional view of the transistor 6 in the channel length direction. 2 shows a cross section in the channel width direction.

[0259] The configuration of the semiconductor device shown in FIG. 12C and FIG. 12D includes an insulator 132, a semiconductor 134, and an insulating layer. 12 except that instead of the body 136, the conductor 120 is formed. The configuration of the semiconductor device shown in (A) and (B) is the same as that of the semiconductor device shown in (A) and (B). 50, region 172d in semiconductor substrate 150, insulator 162b, and conductor The region 172c and the region 172d are the same as the region 172a and the region 172b. The insulator 162b has the structure of the insulator 162a, and the conductor 154b has the structure of the conductor 154b. The configuration of the electric body 154a can be taken into consideration.

[0260] In addition, the conductor 180c, the conductor 180d, the conductor 178c, the conductor 178d, and the conductor 1 76b and conductor 174b are conductors 180a, 180b, 178a, and The structures of conductor 178b, conductor 176a, and conductor 174a can be taken into consideration.

[0261] Insulator 164, insulator 166, insulator 168 and insulator 170 reach region 172c. The conductive material 120 is a conductive material having a cylindrical opening. The conductor 120 is formed in a cylindrical shape in contact with the inner wall of the opening. The conductor shown in FIG. 12(C) and (D) is formed to extend substantially perpendicular to the surface. 120 corresponds to any one of the wirings WBL[1,1] to [m1,m3] shown in FIG. Region 172c functions as a source or drain region of transistor 62. With the above-mentioned configuration, the transistor 1 of the memory cell 10 The wiring WBL electrically connected to the transistor 62 of the selection transistor cell 60 is The source region or the drain region can be electrically connected.

[0262] Also, the conductor 174b functions as a source region or a drain region of the transistor 62. 5 and the like. Conductor 178d also functions as the gate of transistor 62. The conductor 154b is electrically connected to the conductor 154b, and functions as the wiring SG2 shown in FIG. In the data write, the transistor 62 is turned on through the wiring SG2 formed in this manner. In this case, any one of the two-dimensional memory cell arrays 30[1] to [m3] can be selected. do.

[0263] The semiconductor device shown in FIGS. 13(A)(B) and 13(C)(D) is The transistor 61 of the semiconductor device shown in FIG. The only difference is the structure of the motor 62. The semiconductor device shown in FIG. 12(A)(B) and FIG. 12(C)(D) The description of the body device can be taken into consideration. Specifically, FIG. 13(A)(B) and FIG. 13(C) In the semiconductor device shown in FIG. 1(D), the transistor 61 or the transistor 62 is a fin type. The transistor 61 or the transistor 62 is a Fin type. As a result, the effective channel width of the transistor 61 or the transistor 6 In addition, the on-characteristics of the gate electrode can be improved by increasing the contribution of the electric field of the gate electrode. Therefore, the off-state characteristics of the transistor 61 or the transistor 62 can be improved. can.

[0264] <Modification of memory cell> A modification of the transistor 12 will be described below with reference to FIG. Similar to FIG. 8B and FIG. 8C, a cross-sectional view of the transistor 12 in the channel length direction and a 1 is a cross-sectional view of the transistor 12 in the channel width direction.

[0265] The memory cell 10a shown in FIGS. 14A and 14B is mainly a transistor 12a. The transistor 12a is different from the transistor 12 in that the transistor 12a has an insulator 119 under the insulator 104, an insulator An edge 101, an insulator 107, a conductor 102, an insulator 103 and an insulator 105 are formed. The transistor 101 is formed on the insulator 119. An insulator 107 is formed on the insulator 101, and a conductor 102 is formed in the opening of the insulator 107. The insulator 105 is formed on the insulator 107 and the conductor 102. Then, the insulator 103 is formed on the insulator 105, and the insulator 104 is formed on the insulator 103. has been formed.

[0266] As the insulator 119, an insulator that can be used as the insulator 104 may be used. .

[0267] The insulator 101 is an insulator having a function of blocking hydrogen or water. Hydrogen and water in the insulator provided near 6a, semiconductor 106b, and insulator 106c are converted into oxides. Carriers are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c, which also function as semiconductors. This may result in a decrease in the reliability of the transistor 12. In particular, the memory cell 10(1,1,1) provided at the bottom of the three-dimensional memory cell array 40 1 through (m1,1, m3) are the closest to the selection transistor array 50 and therefore are isolated. It is more effective to provide an insulating body 101. When a semiconductor element is provided, hydrogen is used to terminate the dangling bonds of the semiconductor element. In this case, hydrogen may diffuse to the transistor 12. By providing an insulator 101 having a function of blocking water, the transistor 12 is The diffusion of hydrogen or water from the layer can be suppressed, thereby improving the reliability of the transistor 12. can.

[0268] In addition, the insulator 101 preferably has a function of blocking oxygen. By blocking oxygen diffusing from the insulator 104, the insulator 1 As a result, oxygen can be effectively supplied to the semiconductor 106a, the insulator 106b, and the insulator 106c.

[0269] The insulator 101 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride and the like can be used. By using these as the insulator 101, As a result, it can function as an insulating film that has the effect of blocking the diffusion of oxygen, hydrogen, or water. The insulator 101 may be made of, for example, silicon nitride or silicon oxide nitride. By using these as the insulator 101, the diffusion of hydrogen and water can be blocked. It can function as an insulating film that exhibits a blocking effect.

[0270] At least a portion of the conductor 102 is in a region sandwiched between the conductor 108a and the conductor 108b. The conductor 102 preferably overlaps with the semiconductor 106b in the junction region 104 of the transistor 12. By providing such a conductor 102, the transistor By controlling the threshold voltage, When the voltage applied to the gate (conductor 114) of transistor 12 is low, e.g. When the applied voltage is equal to or lower than 0 V, the transistor 12 can be prevented from being turned on. In other words, the electrical characteristics of the transistor 12 are shifted more toward normally-off. The conductor 102 can be used as the conductor 114. A conductor may be used.

[0271] The length of the conductor 102 in the channel length direction is the length of the semiconductor 106b in the channel length direction. It is preferable that the conductive material 102 is larger than the lower surface of the semiconductor 106b and covers the lower surface of the semiconductor 106b. By providing the conductor 102, the electric field generated in the memory cell provided below is 102, the electric field is prevented from affecting the semiconductor 106b. .

[0272] As the insulator 107, an insulator that can be used as the insulator 104 may be used. The upper surfaces of the insulator 107 and the conductor 102 are planarized by a CMP method or the like. It is preferable to improve the flatness by forming a conductive layer that functions as a back gate. Even if the body 102 is provided, the flatness of the surface on which the semiconductor 106b is formed is not impaired. This improves the mobility of the ions and increases the on-state current of the transistor 12. The step on the surface of the insulator 104 caused by the shape of the conductor 102 is eliminated, so that the conductor 1 Between the drain of the drain electrode 108a or 108b and the conductor 102, an insulator 108 is provided. This reduces the leakage current that occurs through the step portion of the transistor. The off-current of the transistor 12 can be reduced.

[0273] As the insulator 105, an insulator that can be used as the insulator 104 may be used. .

[0274] The insulator 103 preferably has a function of blocking oxygen. By providing 103, the conductor 102 is prevented from extracting oxygen from the insulator 104. As a result, the insulator 104 is divided into the insulator 106a, the semiconductor 106b, and the insulator 106b. In addition, the insulator 103 can effectively supply oxygen to the electrode 06c. This reduces the amount of oxygen drawn out of the insulator 104, and the amount of oxygen drawn out of the insulator 104 is reduced. The insulator 106a, the semiconductor 106b, and the insulator 106c can be supplied with oxygen more effectively. can.

[0275] The insulator 103 may be boron, aluminum, silicon, scandium, titanium, or gallium. Sodium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, halide An oxide or nitride containing hafnium or thallium is used. Preferably, hafnium oxide is used. Aluminum or aluminum oxide is used.

[0276] In the insulators 105, 103, and 104, the insulator 103 traps electrons. It is preferable that the insulator 105 and the insulator 104 have a function of suppressing the emission of electrons. When the insulator 103 has the function of trapping electrons, the electrons trapped in the insulator 103 behave like negative fixed charges. Therefore, the insulator 103 functions as a floating gate.

[0277] However, the memory cell 10a is not limited to the configuration shown in FIGS. For example, the insulators 107, 105, and 104 are not provided, and the insulator 104 is a conductor. It may be configured so that it protrudes according to the shape of 102, or a configuration in which no insulator 101 is provided may be used. It may also be composed of.

[0278] The memory cell 10b shown in FIG. 14C and FIG. 14D is mainly characterized by the configuration of the transistor 12b. The transistor 12b is different from the transistor 12 in that the insulators 106c and 112 are semiconductor The insulating layer 11 is formed so as to cover the conductive body 106b, the conductive body 108a, and the conductive body 108b. 117 is formed on the insulator 112 and the conductor 114, and the like, and the insulator 117 is formed on the insulator 117. The transistor 12 differs from the transistor 12 in that a transistor 8 is formed.

[0279] In addition, the capacitance element 14b uses an insulator 112 and an insulator 106c as a dielectric. The capacitance element 14 differs from the capacitance element 14 in that.

[0280] The insulator 117 may be an insulator that can be used for the insulator 116. Here, the insulator 117 is preferably formed by a sputtering method. It is more preferable to perform the sputtering method under an insulating atmosphere. By forming the insulator 117, the surface of the insulator 112 (insulator 117) is simultaneously After the film formation, oxygen is added near the interface between the insulator 112 and the insulator 117 .

[0281] The insulator 117 is an insulator that is less permeable to oxygen than the insulator 112, and serves to block oxygen. By providing such an insulator 117, When oxygen is supplied from the body 112 to the insulator 106a, the semiconductor 106b, and the insulator 106c, Therefore, it is possible to prevent the oxygen from being discharged to the outside above the insulator 112. Aluminum oxide is permeable to both impurities such as hydrogen and moisture, and oxygen. Since the insulating effect is high, it is preferable to use it for the insulator 117.

[0282] However, the memory cell 10b is not limited to the configuration shown in FIGS. 14(C) and 14(D). For example, a portion of the insulator 106 or the insulator 112 may be patterned.

[0283] The memory cell 10c shown in FIG. 14(E) and (F) is mainly a transistor 12c. The transistor 12c is different from the transistor 12 in that the conductor 108a and the conductor 108b are insulated from each other. The insulating layer 118 is formed on the semiconductor 106b and is in contact with the semiconductor 106b through an opening formed in the insulating layer 118. In this respect, an insulator 137 is formed on the conductor 108a and the conductor 108b, and an insulator 13 7, and an insulator 138 is formed on the insulator 137 and the conductor 122. The insulator 117 is formed to cover the insulator 106c and the like, and the conductive The side edges of the body 114 and the insulator 112 are generally aligned. The transistor 12 is different from the transistor 12. The low resistance regions 109a and 109b functioning as source and drain regions are used as gates. This is a gate last method in which the gate is formed before the formation of the functional conductor 114. In the transistor manufacturing process, the source region or the drain region of the transistor 12c is The low resistance regions 109a and 109b functioning as a gate are formed in the shape of a conductor 114 functioning as a gate. This is a gate first method, where the gate is formed after growth.

[0284] In the transistor 12c, the low resistance region 109a and the low resistance region 109b are made of an insulator. The low resistance region 109a and the low resistance region 117 include at least one of the elements included in the low resistance region 109a and the low resistance region 117. A part of the semiconductor 106b overlaps with the conductor 114 (channel formation region). It is preferable that the area is approximately in contact with or overlaps with a part of the area.

[0285] In addition, the low resistance region 109a and the low resistance region 109b are formed by using an element contained in the insulator 117. Since the semiconductor 106b is doped with ZnO, the low resistance regions 109a and 109b of the semiconductor 106b are not SIMS analysis is more sensitive to the area of ​​the semiconductor 106b than the area of ​​the semiconductor 106c that overlaps the conductor 114. This results in a higher concentration of the element.

[0286] The element added to the low resistance region 109a and the low resistance region 109b is, for example, boron. Elements, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, Zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, Indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum or tungsten These elements are relatively easy to form oxides, and the oxides are semiconductors. Therefore, the insulator 106a, the semiconductor 106b, or the insulator 106c can function as a semiconductor or an insulator. For example, the low resistance region 109a and the low resistance region 109c are preferably used as an additive element. b contains 1×10 14 / cm 2 More than 2×10 16 / cm 2 The following should preferably be included: In addition, the low resistance region 109a and the low resistance region 109b in the insulator 106c are preferably In the region of the insulator 106c other than the low resistance region 109a and the low resistance region 109b (for example, an insulating The concentration of the above-mentioned elements is higher in the region of the conductive material 106c (the region overlapping the conductive material 114).

[0287] The low resistance regions 109a and 109b contain nitrogen to form n-type Therefore, the low resistance region 109a and the low resistance region 109b of the semiconductor 106b can be b (for example, the area of ​​the semiconductor 106b overlapping with the conductor 114). The nitrogen concentration obtained by analysis is higher.

[0288] By forming such low resistance regions 109a and 109b, a conductive The semiconductor 108a or the conductor 108b and the insulator 106a, the semiconductor 106b or the insulator 106c Since the contact resistance of the transistor 12c can be reduced, the on-current of the transistor 12c can be increased. It is possible.

[0289] In the transistor 12c, the semiconductor 106b is connected to the insulator 106a and the insulator 106c. Therefore, the side end of the semiconductor 106b, in particular The vicinity of the side end in the channel width direction is provided in contact with the insulator 106a and the insulator 106c. As a result, the insulator 106a or the insulator 106b is in contact with the semiconductor 106b in the vicinity of the side end portion. A continuous junction is formed between the substrate 106c and the low-resistance region 106, and the defect density is reduced. Even if the on-current becomes easy to flow by providing the low-resistance region 109a and the low-resistance region 109b, The side edge of the semiconductor 106b in the channel width direction does not become a parasitic channel, and stable electrical characteristics are obtained. can be obtained.

[0290] The capacitance element 14c is a capacitance element in that an insulator 137 is used as a dielectric. The insulator 137 and the insulator 138 are different from the insulator 118. Any insulator that can be used may be used.

[0291] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0292] (Embodiment 3) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using Figure 20.

[0293] In the following, the A1-A2 cross section of the memory cell 10 constituting the three-dimensional memory cell array 40 will be described. A method for fabricating the three-dimensional memory cell array 40 will be described with attention to the plane and the A3-A4 cross section. Although only one memory cell 10 is shown in the figure, memory cells formed on the same plane 10 (for example, memory cells 10(1,1,1) to (m1,1,m3) shown in FIG. 2) can be made simultaneously.

[0294] First, a substrate on which the selection transistor array 50 is formed is prepared. The transistor array 50 is formed by forming an insulator 1 shown in FIGS. 32, the semiconductor 134, the insulator 136, and the conductor 120 before being formed. The selection transistor array 50 may be fabricated by any known method.

[0295] First, a film is formed as the insulator 104. As the insulator 104, any of the above insulators may be used.

[0296] The insulator 104 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. Vapor Deposition, Molecular Beam Epitaxy (MBE) Laser Beam Epitaxy (PLD) or Pulsed Laser Deposition (PLD) Laser Deposition) method, Atomic Layer Deposition (ALD) This can be done using a photo-reactive deposition method or the like.

[0297] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) These methods are further classified into the VD method, which uses light, and the Photo CVD method, which uses light. Depending on the source gas, metal CVD (MCVD: Metal CVD) method, metal organic CVD method (MOCVD: Metal Organic CVD) method.

[0298] In order to reduce the amount of water or hydrogen contained in the insulator 104, the substrate is heated. It is preferable to perform film formation.

[0299] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later has a high flatness. Therefore, a planarization process such as a CMP process is performed on the top surface of the insulator 104 to improve the planarization. This is also fine.

[0300] Next, it is preferable to perform heat treatment. By performing heat treatment, water in the insulator 104, Alternatively, hydrogen can be further reduced. Also, by making the insulator 104 have excess oxygen, The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 450° C. The heating temperature is preferably from 520° C. to 570° C. The treatment is in an inert gas atmosphere or an oxidizing gas atmosphere of 10 ppm or more, 1% or more, or 10% The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under an inert atmosphere. After heat treatment in an oxidizing gas atmosphere, oxidizing gas is added at a concentration of 10 ppm or less to replenish the oxygen that has been removed. The heat treatment may be carried out in an atmosphere containing 1% or more or 10% or more of the above. In order to improve the crystallinity of the insulator 126a and the semiconductor 126b, impurities such as hydrogen and water can be removed. Heat treatment can be performed using an RTA device that uses lamp heating. Heat treatment with an RTA device takes less time than with a furnace, so it is suitable for increasing productivity. is effective for.

[0301] In addition, in accordance with the configuration of the selection transistor array 50, a relatively low temperature range (for example For example, it may be preferable to heat the material at a temperature in the range of about 350° C. or more and 445° C. or less.

[0302] Next, an insulator that will become the insulator 106a in a later step is formed. Any insulator or semiconductor that can be used as the insulating body 106a may be used. The film formation of the substrate is performed by sputtering, CVD, MBE, PLD, ALD, etc. This can be done using

[0303] Next, a semiconductor film that will become the semiconductor 106b in a later step is formed. Any semiconductor that can be used as the semiconductor 106b may be used. The semiconductor may be formed as follows: This is done using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. In addition, the formation of the insulator that will become the insulator 106a and the formation of the semiconductor that will become the semiconductor 106b can be performed. By performing the deposition and deposition in succession without exposing the film to the atmosphere, impurities are prevented from being mixed into the film or at the interface. can be reduced.

[0304] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 106a and the semiconductor In some cases, the hydrogen concentration in the insulator 106a and the insulator 106b can be reduced. The oxygen vacancies in the semiconductor 106b may be reduced. 450°C or more and 600°C or less, more preferably 520°C or more. The heat treatment is carried out at a temperature of 570°C or less. ppm or more, 1% or more, or 10% or more. Heat treatment is performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere, followed by removing the desorbed oxygen. To compensate for this, heat treatment is performed in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The crystallinity of the insulator 106a and the semiconductor 106b can be improved by heat treatment. Heat treatment can be used to remove impurities such as hydrogen and water. A thermal RTA device can also be used. Heat treatment with an RTA device is shorter than that with a furnace. This is effective for increasing productivity since it only takes a short time. When CAAC-OS is used as a sintered body, the peak intensity increases by heat treatment. The full width of the value is narrowed. That is, the crystallinity of the CAAC-OS is increased by the heat treatment.

[0305] In addition, in accordance with the configuration of the selection transistor array 50, a relatively low temperature range (for example For example, it may be preferable to heat the material at a temperature in the range of about 350° C. or more and 445° C. or less.

[0306] The heat treatment converts the insulator 104 into an insulator 106a and the semiconductor 106 In this way, oxygen can be supplied to the semiconductor that becomes the insulator 106a. By supplying oxygen to the semiconductor that will become the semiconductor 106b and reducing oxygen vacancies, It is possible to obtain a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor having a low density of recess states. Cut.

[0307] In addition, a high-density plasma treatment may be performed. High-density plasma is generated by using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide is generated. Alternatively, a mixture of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used. A mixed gas may be used. In the high density plasma treatment, a bias may be applied to the substrate. This allows oxygen ions in the plasma to be attracted to the substrate. The plasma treatment may be performed while heating the substrate. When performing plasma treatment at high temperature, the same effect can be obtained at a temperature lower than that of the heat treatment described above. The high-density plasma treatment may be performed before forming the insulator that will become the insulator 106a, or after forming the insulator. This may be performed before deposition of the insulator 116, or before deposition of the insulator 106c, etc.

[0308] Next, a resist or the like is applied to the insulator that will become the insulator 106a and the semiconductor that will become the semiconductor 106b. Then, the resist is used to process the insulating layer 106a and the semiconductor layer 106b. (See Fig. 15(A)(B).) When simply saying that a resist is formed, This also includes the case where an anti-reflection layer is formed underneath.

[0309] The resist is removed after the object is processed by etching or the like. For this purpose, plasma treatment and / or wet etching are used. Plasma ashing is suitable for this purpose. If removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% or more by volume and up to 1% by volume. Residual resist may be removed by using aqueous solution or the like.

[0310] Next, it is preferable to perform heat treatment. By performing heat treatment, water in the insulator 104, Alternatively, hydrogen can be further reduced. The heat treatment is performed at a temperature of 250°C to 650°C. The temperature is preferably 450° C. to 600° C., and more preferably 520° C. to 570° C. The heat treatment is preferably carried out in an inert gas atmosphere. The heat treatment may be carried out in an atmosphere containing the fluorine atomizer. The heat treatment may be carried out under reduced pressure. After heat treatment in an active gas atmosphere, oxidizing gas is added at 10 ppm to compensate for the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 1% or more or 10% or more of lanthanide. An RTA device using a lamp heating system can also be used. Heating with an RTA device is much faster than with a furnace. This is effective in increasing productivity because it takes only a short time.

[0311] In addition, in accordance with the configuration of the selection transistor array 50, a relatively low temperature range (for example For example, it may be preferable to heat the material at a temperature in the range of about 350° C. or more and 445° C. or less.

[0312] Next, a conductor is formed as a film, a resist or the like is formed on the conductor, and the resist or the like is used to The conductive material 108 is formed by processing the conductive material 108 (see FIG. 15(C) and (D)). The conductors that can be used as the conductors 108a and 108b described above are The conductive material used for the conductive material 108 can be formed by a sputtering method, a CVD method, or the like. The deposition can be performed by using a deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0313] Next, the insulator 116 is formed. As the insulator 116, any of the above insulators may be used. The insulator 116 is formed by sputtering, CVD, MBE, PLD, or ALD. This can be done using the method.

[0314] Note that the insulator 116 is preferably formed by using plasma, and is preferably formed by sputtering. It is more preferable to carry out the deposition by a sputtering method in an atmosphere containing oxygen. It is even more preferable to do so.

[0315] The sputtering method uses a direct current (DC) power supply for the sputtering power source. Current sputtering method, and pulsed DC sputtering method, which applies a bias in a pulsed manner. RF (Radio Frequency) sputtering method, which uses a high-frequency power source for sputtering A sputtering method may also be used. A magnetron having a magnet mechanism inside the chamber may also be used. The bias sputtering method, which applies a voltage to the substrate during film formation, and the reactive A reactive sputtering method performed in a gas atmosphere may also be used. The oxygen gas flow rate and the film formation power for sputtering may be adjusted according to the amount of oxygen. It may be appropriately determined depending on the amount to be added, etc.

[0316] By forming the insulator 116 by the sputtering method, the insulator 116 is formed at the same time. Oxygen is added near the surface of 04 (the interface between insulator 104 and insulator 116 after insulator 116 is formed). Here, oxygen is added to the insulator 104 as, for example, oxygen radicals. The state in which oxygen is added is not limited thereto. The oxygen may be an oxygen atom or an oxygen ion. In addition, oxygen may be added to the insulator 104 in such a state. In some cases, oxygen is contained in the mixture in excess of the stoichiometric composition, and this oxygen is called excess oxygen. You can also do this.

[0317] Next, a conductor is formed as a film, a resist or the like is formed on the conductor, and the resist or the like is used to The conductive material 122 is formed by processing the conductive material 122 (see FIG. 15(E)(F)). As the conductor, any conductor that can be used as the conductor 122 described above may be used. The conductive material used for the conductive material 122 is deposited by sputtering, CVD, MBE or P This can be done using the LD method, the ALD method, or the like.

[0318] Next, a resist or the like is formed on the conductor 128, and the conductor is processed using the resist or the like. The conductive body 108a and the conductive body 108b are formed.

[0319] Next, an insulator that will become the insulator 118 is formed. The insulator to be the insulator 118 can be formed by a sputtering method, a CV method, or the like. This can be carried out by using a deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0320] Next, a resist or the like is formed on the insulator that will become the insulator 118, and the resist or the like is used to The insulating material 118a, the conductor 108a, and the conductor 108b are formed (FIG. 16(A) )(B). ).

[0321] In addition, in a region of the semiconductor 106b in contact with the conductor 108a and the conductor 108b, Resistance regions 109a and low resistance regions 109b may be formed. b is a portion between the conductor 108a and the conductor 108b that overlaps the conductor 108a and the conductor 108b. This is because the conductor 108a and the conductor 108b may have a region with a thinner thickness than the region with a thinner thickness. When forming 08b, it is formed by removing a part of the upper surface of semiconductor 106b.

[0322] Here, a capacitance element 14 having the conductor 108b, the insulator 116, and the conductor 122 is formed. will be done.

[0323] Next, the insulator 106d that will become the insulator 106c in a later step is formed. As the insulating material, an insulator or a semiconductor that can be used as the insulator 106c described above can be used. The insulator 106d may be formed by sputtering, CVD, MBE or PLD. Before the insulator 106d is formed, the semiconductor 10 The surfaces of the electrodes 6b and 6c may be etched. For example, the surfaces of the electrodes 6b and 6c may be etched using a plasma containing a rare gas. After that, the insulator 106d is formed continuously without being exposed to the atmosphere. By forming a film, the inclusion of impurities in the interface between the semiconductor 106b and the insulator 106c is reduced. Impurities present at the interface between films tend to diffuse more easily than impurities within the film. Therefore, by reducing the inclusion of such impurities, the transistor can be made stable. It is possible to impart the desired electrical properties.

[0324] Next, an insulator 112a that will become the insulator 112 in a later step is formed. For the insulator 112, any insulator that can be used as the insulator 112 may be used. The film of a is formed by sputtering, CVD, MBE, PLD, ALD, etc. The deposition of the insulator 106d and the deposition of the insulator 112a can be performed simultaneously. By performing this process continuously without exposing the film to air, it is possible to reduce the inclusion of impurities in the film and at the interface. This can be done.

[0325] Next, a conductor 114a that will become the conductor 114 in a later step is formed (FIGS. 16(C) and 16(D)). The conductor 114a may be any of the conductors that can be used as the conductor 114 described above. The conductor 114a can be formed by a sputtering method, a CVD method, an MBE method, or the like. Alternatively, the PLD method, the ALD method, or the like may be used. The deposition of the conductive material 114a and the deposition of the conductive material 114b are performed continuously without exposure to the atmosphere. This can reduce the inclusion of impurities on the surface.

[0326] Next, the conductor 114a is polished until the insulator 118a is exposed. 114, insulator 112, insulator 106c and insulator 118 are formed (FIG. 16(E)( The conductor 114 and the insulator 112 are the gate of the transistor 12. The conductor 114 and the gate insulator are formed by the above-mentioned method. and the insulator 112 can be formed in a self-aligned manner.

[0327] The insulator 118, the insulator 106c, and the insulator 11 are the same as the insulator 116. 2 and the conductor 114 to add oxygen to the insulator 118.

[0328] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 104 (or The oxygen added to the insulator 106a, the semiconductor 106b, and the insulator 118 is diffused to form the insulator 106a, the semiconductor 106b, and the insulator 118. The heat treatment can be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably The heat treatment may be performed at a temperature of 350° C. to 450° C. The heat treatment may be performed in an inert gas atmosphere or in an oxidizing atmosphere. The heat treatment is carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of reactive gas. Heat treatment may be performed under pressure. Heat treatment may also be performed using an RTA device with lamp heating. .

[0329] In addition, the temperature of this heat treatment is preferably lower than that of the heat treatment performed after the formation of the semiconductor film 126b. The temperature difference between the heat treatment after the formation of the semiconductor 126b and the heat treatment after the formation of the semiconductor 126b is 20° C. or more and 150° C. or less, and preferably 4 The temperature is set to 0° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 104 and the like. The heat treatment after the formation of the insulator 118 can be performed in the same manner. In the case where the heat treatment for the insulating layer 118 can be performed by the heat treatment for the insulating layer 118 during the deposition of each layer, In some cases, this may not be necessary (when equivalent heating is performed in the deposition of the film).

[0330] The heat treatment converts the oxygen added to the insulator 104 (or the insulator 118) into an insulating material. The oxygen diffuses into the insulator 104 or the insulator 112. The insulator 116 is more permeable to oxygen than the insulator 104. It is an insulator that does not easily allow oxygen to pass through, and functions as a barrier film that blocks oxygen. Since the insulator 116 is formed on the insulator 104, oxygen diffusing through the insulator 104 is prevented from being absorbed by the insulator 116. The metal does not diffuse upward through the insulator 104, but diffuses mainly laterally or downward through the insulator 104.

[0331] The oxygen diffusing through the insulator 104 is transferred to the insulators 106a, 106c, and the semiconductor 106. At this time, an insulator having a function of blocking oxygen is provided under the insulator 104. By providing the insulating layer 104 at the upper surface of the insulating layer 104, oxygen diffused into the insulating layer 104 is prevented from reaching a lower layer than the insulating layer 104. In addition, the insulator 118 may be provided with an insulator similar to the insulator 116. In the case of forming a film of the insulator 118, oxygen is also contained in the insulators 106a, 106c, and and the semiconductor 106b.

[0332] In this manner, the insulator 106a, the insulator 106c and the semiconductor 106b, particularly the semiconductor 106b, In this way, oxygen can be effectively supplied to the region where the channel is to be formed. Oxygen is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, and oxygen vacancies are reduced. By this, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with a low density of defect states can be obtained. It may be a conductor.

[0333] In this manner, the transistor 12 and the capacitor element 14 of the memory cell 10 are formed. By repeating the above steps, a memory cell having a transistor 12 and a capacitor element 14 is formed. The memory cell 10 can be formed by stacking the transistor 12 and the capacitance element 14. After stacking the memory cells 10, the conductors 120 and the transistors of the three-dimensional memory cell array 40 are The transistors 11 are formed collectively.

[0334] A method for manufacturing the conductor 120 and the transistor 11 will be described below with reference to FIGS. In the following description, the memory cells 10 are stacked in two stages, and a cross section taken along line D1-D2 of FIG. 12(A) and 12(B), a cross section of the conductor 120 shown in FIG. Attention will be paid to the D5-D6 cross section corresponding to the vicinity of the transistor 11.

[0335] First, a method for forming the conductor 120 will be described with reference to FIG.

[0336] First, a resist or the like is formed on the uppermost memory cell 10, and the resist or the like is used to An opening 17 extending from the top memory cell 10 to the region 172c of the select transistor cell 60 1 (see FIGS. 17(A) and 17(B)). The opening 171 is a 3D memory cell array 4 In the embodiment shown in FIG. 1, at least the insulator 104, the conductor 108a, the insulator 116 and the insulator 11 are included. 8, and in the selection transistor array 50, at least the semiconductor substrate 150 Region 172a is formed in insulator 164, insulator 166, insulator 168 and insulator 170. do.

[0337] The opening 171 is formed to extend in a direction substantially perpendicular to the upper surface of the substrate, and has a very small aspect ratio. Therefore, the opening 171 is formed by etching in a direction substantially perpendicular to the upper surface of the substrate. It is preferable to use anisotropic etching, which has a high etching rate. For example, dry etching When the opening 171 is formed, the region 172 of the semiconductor substrate 150 is A part of c may be over-etched, forming a recess on the surface of the semiconductor substrate 150. .

[0338] Next, the conductor 120 is formed in the opening 171 (see FIGS. 17(C) and (D)). The body 120 may be any conductor that can be used as the conductor 120 described above. As described above, the opening 171 has a very high aspect ratio, and therefore can be formed by ALD or CVD. It is preferable to form the conductor 120 by using a CVD method. It is preferable to form the film by using the OCVD method or the MCVD method.

[0339] In addition, in the uppermost memory cell 10, the upper surface of the conductor 120 is insulated so as not to be exposed. It is preferable to cover it with your body.

[0340] Next, a method for forming the transistor 11 will be described with reference to FIGS. .

[0341] First, a resist or the like is formed on the uppermost memory cell 10, and the resist or the like is used to An opening 18 extending from the topmost memory cell 10 to the region 172a of the select transistor cell 60 1a is formed (see FIG. 18(A)(B)). The opening 181a is also formed in the same manner as the opening 171. In the two-dimensional memory cell array 40, at least an insulator 104, a conductor 108a, an insulating The selection transistor array 50 includes at least one In each case, the region 172a of the semiconductor substrate 150, the insulators 164, 166, 168, and It is formed in an insulator 170 .

[0342] The opening 181a is formed to extend in a direction substantially perpendicular to the upper surface of the substrate, and has a very narrow aspect ratio. For this reason, the opening 181a is also formed on the upper surface of the substrate in the same manner as the opening 171. It is preferable to use anisotropic etching in which the etching proceeds quickly in a direction approximately perpendicular to the substrate. For example, dry etching or the like may be used. In addition, a portion of the region 172a of the semiconductor substrate 150 is over-etched to expose the surface of the semiconductor substrate 150. A depression may form on the surface.

[0343] Next, the insulator 132 is formed in contact with the inner wall of the opening 181a (see FIGS. 18(C) and 18(D)). As the insulator 132, the insulator that can be used as the insulator 132 described above is used. As described above, the opening 181a has a very high aspect ratio, and therefore can be formed by the ALD method or It is preferable to form the insulator 132 by using a CVD method or the like. Since it functions as a gate insulating film for the transistor 11, it is preferable that the thickness of the film is highly uniform. Therefore, the ALD method is preferable in terms of high film thickness controllability.

[0344] Next, an opening 181b is formed in the bottom of the insulator 132, reaching the region 172a (FIG. 19( The opening 181b is formed in at least a part of the bottom surface of the insulator 132. Therefore, the diameter of the opening 181b is often smaller than that of the opening 181a.

[0345] Here, the formation of the opening 181b is achieved by removing the insulator 132 formed on the sidewall of the opening 181a. It is necessary to remove at least a portion of the bottom surface of the insulator 132 without removing the opening. The opening 181b is also formed in the same manner as the opening 181a, by forming an aperture in a direction substantially perpendicular to the upper surface of the substrate. It is preferable to use anisotropic etching, which has a fast etching rate. For example, dry etching is used. In addition, when the opening 181b is formed, the area of ​​the semiconductor substrate 150 A portion of the region 172a is over-etched to form a further recess in the surface of the semiconductor substrate 150. This may be the case.

[0346] Next, a semiconductor 134 is formed inside the insulator 132 (see FIGS. 19(C) and (D)). As the semiconductor 134, the semiconductor that can be used as the semiconductor 134 described above may be used. Here, the semiconductor 134 is provided in contact with the region 172a.

[0347] As described above, the opening 181a has a very high aspect ratio, and therefore can be formed by ALD, CVD, or the like. It is preferable to form the semiconductor 134 by using an epitaxial method or the like. The method can be used to form a semiconductor 134, such as single crystal silicon or polycrystalline silicon. After the amorphous silicon film is formed, it can be annealed to form a thin film. Alternatively, the semiconductor 134 may be made of polycrystalline silicon by crystallizing the silicon.

[0348] When the semiconductor 134 is made of polycrystalline silicon, it is preferable to make the film thickness of the semiconductor 134 thin. For example, it is preferable that the thickness is 20 nm or less, and more preferably 10 nm or less. By making the semiconductor 134 have such a thickness, the characteristics of the transistor 11 can be prevented from fluctuating. This can reduce the amount of noise.

[0349] In addition, when the semiconductor 134 is formed, impurities that impart p-type conductivity or n-type conductivity are added. The semiconductor 134 may be deposited so that it contains impurities that impart a type.

[0350] Next, an insulator 136 is formed inside the semiconductor 134 (see FIGS. 20(A) and (B)). As the insulator 136, the above-mentioned semiconductor that can be used as the insulator 136 may be used. The insulator 136 is preferably formed by ALD or CVD. .

[0351] In addition, when polycrystalline silicon is used for the semiconductor 134, hydrogen is contained in the insulator 136. Then, a heat treatment or the like may be performed to terminate the dangling bonds in the semiconductor 134. At this time, an insulator having a blocking effect against hydrogen, water, etc. is used as the insulator 132. This prevents hydrogen from diffusing out during heat treatment and more effectively bonds the semiconductor 134 to the dummy layer. Gring bonds can be terminated.

[0352] After the process shown in FIG. 19(A) and (B), a cylindrical A semiconductor 134 having a rectangular shape may be formed (see FIGS. 20C and 20D).

[0353] In the uppermost memory cell 10, a conductor is provided so as to contact the upper surface of the semiconductor 134. It is preferable to form a film so that the conductor is electrically connected to a low power supply potential.

[0354] In this manner, the conductor 108b, the insulator 132, the semiconductor 134, and the insulator 136 are formed. A vertical transistor 11 can be formed by using the above method. By fabricating the transistor 11, a plurality of transistors included in the three-dimensional memory cell array 40 Therefore, the transistor 11 can be manufactured in a very simple process. This allows shortening of the tact time and improving productivity.

[0355] Through the above steps, a semiconductor device according to one embodiment of the present invention can be manufactured.

[0356] By using the above manufacturing method, a semiconductor device with a large memory capacity per unit area can be manufactured. Alternatively, a semiconductor device having a novel structure in which memory cells are stacked can be provided. It is possible.

[0357] As described above, the configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0358] (Embodiment 4) In this embodiment, the oxide semiconductor included in the semiconductor device of one embodiment of the present invention will be described in detail. The following explains this.

[0359] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0360] Oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Nanocrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconducting ductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor. be.

[0361] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductors, and nc-OS.

[0362] Amorphous structures are generally isotropic and have no inhomogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0363] That is, a stable oxide semiconductor is transformed into a completely amorphous s) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, it has a periodic structure in a small area). An oxide semiconductor having an Al structure cannot be called a completely amorphous oxide semiconductor. ike OS is not isotropic, but has an unstable structure with voids. In terms of instability, the a-like OS is physically similar to an amorphous oxide semiconductor. stomach.

[0364] <caac-os> First, let me explain about CAAC-OS.

[0365] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0366] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals was analyzed by the out-of-plane method. As shown in FIG. 21(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the upper surface. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferred that the C-OS does not exhibit such a peak.

[0367] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS in a direction parallel to the surface on which the X-ray is to be formed. When structural analysis was performed using the ane method, a peak appeared at 2θ of approximately 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. Then, the sample is rotated around the normal vector of the sample surface as an axis (φ axis) while analyzing (φ scan). Even if this is done, no clear peak appears as shown in FIG. When 2θ is fixed at around 56° and φ is scanned for ZnO4, the results shown in Figure 21(C) As shown in the figure, six peaks attributable to crystal planes equivalent to the (110) plane are observed. XRD structural analysis revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0368] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was parallel to the CAAC-OS surface. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This is also called a selected area electron diffraction pattern.) may appear. This diffraction pattern includes I The spots are due to the (009) plane of the nGaZnO4 crystal. Diffraction also confirmed that the pellets contained in the CAAC-OS have a c-axis orientation and that the c-axis is the unformed On the other hand, for the same sample, the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident perpendicularly to the ) is shown. From FIG. 21(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the PEG-1000 nanometers in the CAAC-OS It can be seen that the a-axis and b-axis of the slits have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Fig. 21(E) is thought to be due to the (110) plane. It is thought that.

[0369] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope. When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. (also called underly.) may not be clearly identified. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0370] Figure 22(A) shows a high-resolution cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. A spherical aberration correction (SCA) was used for high-resolution TEM imaging. The spherical aberration corrector function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0371] From FIG. 22(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with no crystals. It reflects the unevenness of the surface on which the C-OS is formed or the top surface, and the unevenness of the surface on which the CAAC-OS is formed or It is parallel to the top surface.

[0372] In addition, Fig. 22(B) and Fig. 22(C) show CAA images observed from a direction approximately perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the C-OS surface. 22(B) and 22(C), respectively. First, the method of processing is explained. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the acquired FFT image, the origin is used as the reference point, and the -1 From 5.0 nm -1 The range between Next, the masked FFT image is transformed by inverse fast Fourier transform (IFFT : Inverse Fast Fourier Transform) processing is used to The image obtained in this way is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. This indicates a child array.

[0373] In FIG. 22(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the dashed line is the connection between the pellets. The broken line shows the hexagonal shape, so we can see that the pellet is hexagonal. The shape of the let is not limited to a regular hexagon, and is often a non-regular hexagon.

[0374] In FIG. 22(E), a dot is drawn between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The lattice arrangement direction is shown by a dotted line. If you connect the lattice points around the dotted line, you will get a distorted hexagon. Shapes such as pentagons and / or heptagons can be formed. That is, by distorting the lattice arrangement, This indicates that the formation of grain boundaries is suppressed. The atomic arrangement is not dense in the plane direction, and the bond distance between atoms is reduced by the substitution of metal elements. This is thought to be because the change in the distance allows distortion to be tolerated.

[0375] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor having lane-anchored crystals. Cut.

[0376] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is determined by the presence of impurities. CAAC-OS is designed to prevent impurities and defects from causing degradation. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0377] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0378] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the ZnO traps hydrogen and becomes a carrier generation source.

[0379] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than , and more preferably 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be obtained by using a high-purity pure oxide semiconductor. CAAC-OS is a highly pure or substantially intrinsic oxide semiconductor with low impurity concentration. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0380] <nc-os> Next, we will explain nc-OS.

[0381] The following describes the case where nc-OS is analyzed by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0382] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the result shown in Fig. 2 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in 3(A) was observed. In addition, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample ( The nanobeam electron diffraction pattern is shown in Figure 23(B). Therefore, the nc-OS has a probe diameter of 50 nm. No order was observed when an electron beam with a probe diameter of 1 nm was incident. When light is incident on it, order is confirmed.

[0383] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 23(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is considered that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals are highly ordered. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0384] FIG. 23(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image as the area indicated by the auxiliary lines. How to identify the crystals and the areas where no clear crystals can be identified The crystal parts in the nc-OS have a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. An oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called ocrystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be called a pellet.

[0385] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, particularly The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the Cr-Al-Al-Fe-Al-Fe-O-Pb-Al-Zn ... Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0386] In addition, since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is , oxidation with RANC (Random Aligned nanocrystals) Semiconductors or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor has a conductivity of 1000.

[0387] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0388] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0389] FIG. 24 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 Electrons (e - ) A-like OS after irradiation High-resolution cross-sectional TEM images. Figures 24(A) and 24(B) show that a-like O It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is suspected to be a density region.

[0390] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0391] As samples, a-like OS, nc-OS and CAAC-OS are prepared. Both samples are In-Ga-Zn oxides.

[0392] First, high-resolution cross-sectional TEM images of each sample are obtained. All of the materials have crystalline parts.

[0393] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers in the c-axis direction. The distance between these adjacent layers is the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is called InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0394] Figure 25 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes is the size of the crystal part. e. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 25, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that grew up (also called the initial nucleus) absorbs electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of 100 to 150 mm. Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is , and 1.3 nm and 1.8 nm, respectively. The Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0395] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0396] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0397] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 Less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0398] If single crystals of the same composition do not exist, single crystals of different compositions may be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions. However, the density can be estimated by using as few types of single crystals as possible. A combined estimate is preferred.

[0399] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0400] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0401] (Embodiment 5) In this embodiment mode, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is used in, for example, various electronic devices (e.g., Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (e.g., D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 26 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a format and used in various storage devices and removable memory.

[0402] FIG. 26A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0403] FIG. 26(B) is a schematic diagram of the external appearance of an SD card, and FIG. 26(C) is a schematic diagram of the inside of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, the substrate 11 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, The capacity can be increased. In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the host device and the SD card 1110 to wirelessly communicate with each other. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0404] FIG. 26(D) is a schematic diagram of the external appearance of the SSD, and FIG. 26(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153. By providing the memory chip 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like. [Explanation of symbols]

[0405] 10 Memory Cells 10a Memory Cell 10b Memory Cell 10c Memory Cell 11 Transistor 12 Transistor 12a Transistor 12b Transistor 12c transistor 14 Capacitive element 14b Capacitive element 14c Capacitive element 20 Memory Cell String 24 Transistor 30 Two-dimensional memory cell array 40 3D Memory Cell Array 50 Select transistor array 51 Drive circuit 52 Circuit 53 Drive circuit 54 Drive circuit 60 Select Transistor Cell 61 Transistor 62 Transistor 101 Insulators 102 Conductor 103 Insulators 104 Insulators 105 Insulators 106 Insulators 106a Insulator 106b Semiconductors 106c Insulator 106d Insulators 107 Insulators 108 Conductor 108a Conductor 108b Conductor 109a Low resistance area 109b Low resistance region 112 Insulators 112a Insulator 114 Conductors 114a Conductor 116 Insulators 117 Insulators 118 Insulators 118a Insulator 119 Insulators 120 Conductor 122 Conductors 126a Insulator 126b Semiconductors 128 Conductors 132 Insulators 134 Semiconductors 134a area 134b area 136 Insulators 137 Insulators 138 Insulators 150 Semiconductor Substrate 154a Conductor 154b Conductors 160 areas 162a Insulator 162b Insulator 164 Insulators 166 Insulators 168 Insulators 170 Insulators 171 Aperture 172a area 172b area 172c area 172d area 174a Conductors 174b Conductors 176a Conductors 176b Conductors 178a Electric conductor 178b Conductor 178c conductor 178d conductor 180a Conductor 180b conductor 180c conductor 180d Conductor 181a aperture 181b aperture 1100 USB memory 1101 Case 1102 Cap 1103 USB connector 1104 Substrate 1105 Memory Chip 1106 Controller Chip 1110 SD card 1111 Case 1112 Connector 1113 Substrate 1114 Memory Chip 1115 Controller Chip 1150 SSD 1151 Case 1152 Connector 1153 PCB 1154 memory chip 1155 memory chip 1156 controller chip

Claims

1. A memory cell is disposed above a substrate; The memory cell includes a first transistor, a second transistor, and a capacitance element, the first transistor has a channel formation region in a part of a cylindrical semiconductor having a height in a direction perpendicular to an upper surface of the substrate; a first conductive layer having a region functioning as a gate electrode of the first transistor has a region functioning as one of electrodes of the capacitor and a region functioning as one of a source electrode and a drain electrode of the second transistor; the second transistor includes an oxide semiconductor layer having a channel formation region, an insulating layer having a region disposed above the oxide semiconductor layer has a region that functions as a gate insulating layer of the second transistor; a second conductive layer disposed above the insulating layer has a region that functions as a gate electrode of the second transistor; The insulating layer and the second conductive layer are disposed so as to be embedded in an insulator.

2. In claim 1, A semiconductor device, wherein an upper surface of the insulating layer and an upper surface of the second conductive layer have regions that are flush with an upper surface of the insulator.

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