Circuit Board

Abstract

A circuit board according to an embodiment includes a first insulating layer, a first circuit pattern disposed on one side of the first insulating layer and including a pad, and a second insulating layer disposed on one side of the first insulating layer and including a cavity exposing the pad, wherein the first circuit pattern includes a 1-1 metal layer disposed on one side of the first insulating layer and a 1-2 metal layer disposed on one side of the 1-1 metal layer, wherein the area of ​​the 1-1 metal layer is larger than the area of ​​the 1-2 metal layer, and at least a portion of the side of the 1-1 metal layer is exposed through the cavity.

Description

[Technical field]

[0001] The embodiments relate to a circuit board and a package substrate including the same. [Background technology]

[0002] A circuit board has a structure in which the mounting positions of various types of devices are determined and a circuit pattern that connects the devices is printed and fixed on the surface of the flat plate in order to densely mount various types of devices on the flat plate. Such a circuit board may have an embedded structure in which devices are embedded inside.

[0003] Recently, in order to realize miniaturization and multi-function of electronic components, circuit boards are used in multi-layer structures that enable high density integration.

[0004] In general, in conventional embedded circuit boards, cavities for mounting elements are formed using a drill bit, a secondary material such as a release film is used to seat the elements, or a cavity for mounting elements is formed using sand blasting.

[0005] However, the cavity included in the conventional circuit board has an inner wall with an inclination angle of 150° or more based on the bottom surface of the cavity, and therefore, in order to provide a mounting space for an element in the cavity, the space required for forming the cavity is relatively large due to the inclination angle of the inner wall. As a result, the conventional circuit board has a problem that the integration density of the circuit is reduced and the overall volume of the circuit board is increased due to the increase in the space for forming the cavity. Summary of the Invention [Problem to be solved by the invention]

[0006] The embodiments relate to a circuit board, a package substrate, and a manufacturing method thereof that can improve the inclination angle of the inner wall of the cavity.

[0007] In addition, the embodiments provide a circuit board, a package substrate, and a manufacturing method thereof, which can form a cavity of a desired depth in a desired area in the cavity formation process without having to separately form a stop layer required on the bottom surface of the cavity.

[0008] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the embodiments pertain from the description below. [Means for solving the problem]

[0009] A circuit board according to an embodiment includes a first insulating layer, a first circuit pattern arranged on one side of the first insulating layer and including a pad, and a second insulating layer arranged on one side of the first insulating layer and including a cavity exposing the pad, wherein the first circuit pattern includes a 1-1 metal layer arranged on one side of the first insulating layer and a 1-2 metal layer arranged on one side of the 1-1 metal layer, an area of ​​the 1-1 metal layer is larger than an area of ​​the 1-2 metal layer, and at least a portion of a side of the 1-1 metal layer is exposed through the cavity.

[0010] Moreover, the 1-1 metal layer includes a first portion vertically overlapping the 1-1 metal layer and a second portion other than the first portion, and a side surface of the second portion is exposed through the cavity.

[0011] Moreover, the second portion of the 1-1 metal layer has a closed loop shape surrounding the outside of the cavity, and is disposed between the first insulating layer and the second insulating layer.

[0012] Moreover, the 1-1 metal layer is a seed layer for the 1-2 metal layer.

[0013] Additionally, an upper surface of the first portion of the 1-1 metal layer is in direct contact with a lower surface of the 1-2 metal layer, and an upper surface of the second portion of the 1-1 metal layer is in direct contact with the second insulating layer.

[0014] In addition, the second portion of the 1-1 metal layer is spaced apart from the 1-2 metal layer at a constant distance.

[0015] Moreover, the first circuit pattern includes a 1-1 circuit pattern arranged in an area adjacent to the cavity, and a 1-2 circuit pattern other than the 1-1 circuit pattern, the 1-1 metal layer of the 1-2 circuit pattern and the 1-2 metal layer of the 1-2 circuit pattern have the same area, and the 1-1 metal layer of the 1-1 circuit pattern has an area larger than the 1-2 metal layer of the 1-1 circuit pattern.

[0016] In addition, the 1-1 metal layer of the 1-1 circuit pattern includes a first portion vertically overlapping the 1-2 metal layer of the 1-1 circuit pattern and a second portion other than the first portion, and the second portion of the 1-1 metal layer of the 1-1 circuit pattern surrounds the outside of the cavity and is disposed between the first insulating layer and the second insulating layer.

[0017] Moreover, the second insulating layer includes a 2-1 insulating layer and a 2-2 insulating layer, and the cavity commonly penetrates the 2-1 insulating layer and the 2-2 insulating layer.

[0018] Further, the second insulating layer includes a 2-1 insulating layer and a 2-2 insulating layer, and includes a second circuit pattern arranged between the 2-1 insulating layer and the 2-2 insulating layer, the cavity includes a first cavity formed in the 2-1 insulating layer and a second cavity formed in the 2-2 insulating layer and having a size different from the first cavity, at least a portion of a side surface of the 1-1 metal layer is exposed through the first cavity, the second circuit pattern includes a 2-1 metal layer arranged on one side of the 2-1 insulating layer and a 2-2 metal layer arranged on one side of the 2-1 metal layer, an area of ​​the 2-1 metal layer is larger than an area of ​​the 2-2 metal layer, and at least a portion of a side surface of the 2-1 metal layer is exposed through the second cavity.

[0019] The second insulating layer has a thickness in the range of 5 μm to 20 μm.

[0020] The second insulating layer includes RCC (Resin Coated Copper).

[0021] On the other hand, a package substrate according to an embodiment includes a first insulating layer, a first circuit pattern disposed on one side of the first insulating layer and including a pad, a second insulating layer disposed on one side of the first insulating layer and including a cavity exposing the pad, a connection portion disposed on the pad, and an electronic element disposed on the connection portion, wherein the first circuit pattern includes a 1-1 metal layer disposed on one side of the first insulating layer and a 1-2 metal layer disposed on one side of the 1-1 metal layer, the area of ​​the 1-1 metal layer being larger than the area of ​​the 1-2 metal layer, the 1-1 metal layer including a first portion vertically overlapping the 1-1 metal layer and a second portion other than the first portion, and a side of the second portion is exposed through the cavity.

[0022] Moreover, the second portion of the 1-1 metal layer has a closed loop shape surrounding the outside of the cavity, and is disposed between the first insulating layer and the second insulating layer.

[0023] Further, the first circuit pattern includes a 1-1 circuit pattern arranged in an area adjacent to the cavity and a 1-2 circuit pattern other than the 1-1 circuit pattern, the 1-1 metal layer of the 1-2 circuit pattern and the 1-2 metal layer of the 1-2 circuit pattern have the same area, and the 1-1 metal layer of the 1-1 circuit pattern has an area larger than the 1-2 metal layer of the 1-1 circuit pattern.

[0024] In addition, the 1-1 metal layer of the 1-1 circuit pattern includes a first portion vertically overlapping the 1-2 metal layer of the 1-1 circuit pattern and a second portion other than the first portion, and the second portion of the 1-1 metal layer of the 1-1 circuit pattern surrounds the outside of the cavity and is disposed between the first insulating layer and the second insulating layer.

[0025] The second insulating layer includes RCC (Resin Coated Copper) having a thickness in the range of 5 μm to 20 μm.

[0026] In addition, a circuit board according to an embodiment includes a first insulating layer, a first circuit pattern including a pad and disposed on one surface of the first insulating layer, and a second insulating layer including a cavity exposing the pad, wherein an inclination angle of an inner wall of the cavity is in the range of 90.1 degrees to 100 degrees with respect to an upper surface of the first insulating layer, the second insulating layer includes a prepreg having glass fibers disposed in a resin, and the glass fibers of the insulating layer do not protrude into the inside of the cavity.

[0027] Also, the vertical cross section of the cavity has a rectangular or square shape.

[0028] Additionally, the horizontal cross section of the cavity includes a curved surface.

[0029] Additionally, a horizontal cross section of the cavity includes an edge portion having a constant curvature.

[0030] Moreover, the curvature of the edge portion of the cavity corresponds to the curvature of a circle in the range of 20 μm to 80 μm.

[0031] A circuit board according to the embodiment includes a first insulating layer and a second insulating layer disposed on the first insulating layer and including the cavity, the cavity being formed through the second insulating layer, and an inner wall of the cavity includes a first portion in contact with an upper surface of the first insulating layer and having a first inclination angle, a second portion extending from the first portion and having a second inclination angle different from the first inclination angle, and a third portion extending from the second portion and having a third inclination angle different from the second inclination angle.

[0032] The first tilt angle is smaller than the second and third tilt angles, the second tilt angle is larger than the first and third tilt angles, and the third tilt angle is larger than the first tilt angle and smaller than the second tilt angle.

[0033] The first tilt angle has a range of 89 degrees to 91 degrees, the second tilt angle has a range of 130 degrees to 160 degrees, and the third tilt angle has a range of 92 degrees to 130 degrees.

[0034] The cavity also includes a first inflection point between the first and second portions of the inner wall and a second inflection point between the second and third portions of the inner wall.

[0035] The semiconductor device also includes a pad disposed on an upper surface of the first insulating layer and exposed through the cavity, and the second inflection point is located lower than an upper surface of the pad.

[0036] The pad also includes a first metal layer disposed on an upper surface of the first insulating layer and a second metal layer disposed on an upper surface of the first metal layer, and the first inflection point has the same height as the first metal layer.

[0037] The second insulating layer has a thickness in the range of 5 μm to 20 μm.

[0038] The second insulating layer includes RCC (Resin Coated Copper).

[0039] Additionally, the surface roughness of the first portion of the inner wall of the cavity is different from the surface roughness of the second portion or the third portion of the inner wall of the cavity. Effect of the Invention

[0040] In the embodiment, the first circuit pattern is disposed on the upper surface of the first insulating layer. The first circuit pattern may include a 1-1 metal layer that is a seed layer, and a 1-2 metal layer that is a plating layer disposed on the 1-1 metal layer. In the embodiment, the 1-1 metal layer that is a seed layer of the 1-2 metal layer is used as a stop layer of a cavity C formed in the second insulating layer. As a result, the area of ​​the 1-1 metal layer in the embodiment may be larger than the area of ​​the 1-2 metal layer. In addition, the 1-1 metal layer in the embodiment may include a first portion that overlaps with the 1-2 metal layer in the vertical direction, and a second portion that does not overlap with the 1-2 metal layer. A side surface of the second portion of the 1-1 metal layer may be exposed through a cavity C formed in the second insulating layer. The second portion of the 1-1 metal layer may be disposed between the first insulating layer and the second insulating layer, surrounding the outside of the cavity C.

[0041] According to this, in the embodiment, it is not necessary to form a separate stop layer that is required when forming a cavity in the second insulating layer using a laser process, thereby achieving a reduction in manufacturing costs and a simplification of the manufacturing process.

[0042] In addition, in the embodiment, a cavity is formed by performing two processing steps. For example, in the embodiment, a primary processing is performed by a carbon dioxide (CO2) laser, and a secondary processing is performed by an ultraviolet (UV) laser to form a cavity. That is, when a cavity is formed by a carbon dioxide (CO2) laser, a step-like step is generated on the inner wall of the cavity so as to correspond to the moving distance of the laser source performed during the laser processing. As a result, in the embodiment, the cavity formed through the carbon dioxide (CO2) laser can be further processed using an ultraviolet (UV) laser. As a result, the inner wall of the cavity in the embodiment may be approximately perpendicular to the bottom surface of the cavity or the surface of the insulating layer. For example, the inner wall of the cavity may have an inclination angle of 90.01° to 100° with respect to the bottom surface of the cavity or the surface of the insulating layer. For example, the inner wall of the cavity may have an inclination angle of 90.1° to 95° with respect to the bottom surface of the cavity or the surface of the insulating layer. For example, the inner wall of the cavity may have an inclination angle of 91° to 93° with respect to the bottom surface of the cavity or the surface of the insulating layer. In this manner, the vertical cross-sectional shape of the cavity in embodiments may approximate a rectangle or a square, which in turn may allow embodiments to reduce the space that the cavity occupies within the insulating layer, thereby improving circuit integration.

[0043] That is, the size of the cavity C may be determined such that the width of the lower region corresponds to the size of the electronic element disposed therein. In this case, in the comparative example, the width of the upper region of the cavity C is greater than that of the lower region, and a space is wasted by a space corresponding to the difference in width between the upper and lower regions. For example, when a carbon dioxide (CO2) laser is used as in the comparative example, the inclination angle of the inner wall of the cavity is 110° or more. In the comparative example, the size of the cavity may be significantly larger than the size of the electronic element due to the inclination angle of the inner wall of the cavity. In contrast, in the embodiment, the inclination angle of the inner wall of the cavity is made almost vertical, thereby reducing the size of the cavity and thereby solving the wasted space.

[0044] Also, at least a part of the cavity C in the embodiment may include a rounded portion. For example, the shape of the cavity may have a shape including a rounded portion. For example, the cavity C in the embodiment may have at least a part of a curved surface. For example, the cavity C in the embodiment may have an edge portion with a curved shape. Thereby, in the embodiment, it is possible to solve a problem that may occur when the edge portion of the cavity has a vertical straight line. For example, when the edge portion of the cavity has a vertical straight line, stress is concentrated on the edge portion, and thus, it is possible to solve a structural reliability problem such as the collapse of the cavity. In contrast, in the embodiment, the edge portion of the cavity is made to include a curved surface, thereby solving the structural reliability problem, and thereby improving product satisfaction.

[0045] In addition, in the embodiment, the insulating layer in which the cavity is formed may be formed of a prepreg. The prepreg contains glass fibers in a resin to ensure rigidity. In the process of forming the cavity C, a part of the glass fibers may be exposed to the outside through the cavity C. When the glass fibers are exposed through the cavity C, various reliability problems may occur. For example, the glass fibers may cause a problem in the flatness of the electronic element disposed in the cavity C. For example, the glass fibers may cause an electrical shot of the electronic element disposed in the cavity C. Therefore, in the embodiment, a primary cavity processing is performed using a carbon dioxide (CO2) laser, and then a secondary cavity processing is performed using an ultraviolet (UV) laser. At this time, the ultraviolet (UV) laser may make the inclination angle of the inner wall of the cavity C almost vertical, and further remove the glass fibers exposed through the cavity that has been primarily processed. That is, in the embodiment, in order to improve the reliability of the cavity C, a cavity processing is further performed using an ultraviolet (UV) laser. At this time, an ultraviolet (UV) laser can remove glass fibers that may be exposed through the cavity, thereby improving the structural reliability of the cavity in the embodiment, and thus improving product reliability.

[0046] The circuit board of the embodiment includes a first insulating layer and a second insulating layer disposed on the first insulating layer. A cavity is formed in the second insulating layer. At this time, an inner wall of the cavity extends from an upper surface of the first insulating layer and includes a first portion having a first inclination angle, a second portion having a second inclination angle, and a third portion having a third inclination angle. At this time, the first to third inclination angles are different from each other. For example, a first inflection portion is formed between the first and second portions of the inner wall of the cavity, and a second inflection portion is formed between the second and third portions. The first inclination angle of the first portion may be smaller than the second inclination angle of the second portion. The second inclination angle of the second portion may be larger than the third inclination angle of the third portion. The third inclination angle of the third portion may be larger than the first inclination angle of the first portion and smaller than the second inclination angle of the second portion. In the above embodiment, the inclination angle of the first and third portions can be smaller than that of the comparative example, and therefore the space required to form the cavity can be minimized compared to the comparative example. Furthermore, in the embodiment, the circuit integration can be improved within the same space. Furthermore, in the embodiment, the average inclination angle of the inner wall of the cavity can be reduced compared to the comparative example, and therefore more circuits can be formed within the same area compared to the comparative example, and therefore the overall volume of the circuit board can be reduced.

[0047] Also, the package substrate in the embodiment includes a molding layer disposed in the cavity. In this case, a first portion, a second portion, and a third portion of the inner wall of the cavity are disposed in contact with each other. In this case, the first portion, the second portion, and the third portion of the inner wall of the cavity may have different inclination angles based on a first inflection portion and a second inflection portion, rather than a single inclination angle. The structure of the cavity in the above embodiment may increase a surface area in contact with the molding layer, thereby improving the bonding strength between the molding layer and the circuit board.

[0048] In the embodiment, a cavity is formed using a mask pattern. At this time, the mask pattern includes a first mask pattern that determines the depth of the cavity in a lower region of the cavity, and a second mask pattern that is disposed surrounding the periphery of the cavity in an upper region of the cavity and determines the upper width of the cavity. At this time, in the comparative example, the first mask pattern and the second mask pattern are formed using different metal layers. Differently from this, in the embodiment, the seed layer used to form the circuit pattern can be used as the first mask pattern and the second mask pattern. At this time, the first mask pattern and the second mask pattern at least partially overlap in the vertical direction. That is, the first mask pattern and the second mask pattern in the comparative example are disposed so as not to overlap in the vertical direction. As a result, in the comparative example, due to process deviation during laser processing, laser processing is performed on an area outside the second mask pattern, which may cause a problem that a part of the first insulating layer is processed. In contrast to this, in the embodiment, the first mask pattern and the second mask pattern are arranged so as to overlap partially as described above, so that a cavity can be accurately machined in the cavity processing area, thereby improving reliability. [Brief description of the drawings]

[0049] [Figure 1] FIG. 2 is a diagram showing a circuit board according to the first embodiment. [Diagram 2] FIG. 2 is a plan view of a portion of the configuration of FIG. [Diagram 3] FIG. 2 is a diagram showing a package substrate according to the first embodiment. [Figure 4] FIG. 11 is a diagram showing a package substrate according to a second embodiment. [Diagram 5] 2A to 2C are diagrams showing a method for manufacturing the circuit board shown in FIG. 1 in the order of steps. [Figure 6] 2A to 2C are diagrams showing a method for manufacturing the circuit board shown in FIG. 1 in the order of steps. [Figure 7] 2A to 2C are diagrams showing a method for manufacturing the circuit board shown in FIG. 1 in the order of steps. [Figure 8]2A to 2C are diagrams showing a method for manufacturing the circuit board shown in FIG. 1 in the order of steps. [Figure 9] 2A to 2C are diagrams showing a method for manufacturing the circuit board shown in FIG. 1 in the order of steps. [Figure 10] 2A to 2C are diagrams showing a method for manufacturing the circuit board shown in FIG. 1 in the order of steps. [Figure 11] 1. FIG. 4 is a diagram showing a modified example of the circuit board in FIG. [Figure 12] 1. FIG. 4 is a diagram showing a modified example of the circuit board in FIG. [Figure 13] 1. FIG. 4 is a diagram showing a modified example of the circuit board in FIG. [Figure 14] FIG. 11 is a diagram showing a circuit board according to a second embodiment. [Figure 15] 15 is a plan view of a partial configuration of the circuit board of FIG. 14. [Figure 16] 15A to 15C are diagrams showing a method for manufacturing the circuit board shown in FIG. 14 in order of steps. [Figure 17] 15A to 15C are diagrams showing a method for manufacturing the circuit board shown in FIG. 14 in order of steps. [Figure 18] 15A to 15C are diagrams showing a method for manufacturing the circuit board shown in FIG. 14 in order of steps. [Figure 19] 15A to 15C are diagrams showing a method for manufacturing the circuit board shown in FIG. 14 in order of steps. [Figure 20] 15A to 15C are diagrams showing a method for manufacturing the circuit board shown in FIG. 14 in order of steps. [Figure 21] 15A to 15C are diagrams showing a method for manufacturing the circuit board shown in FIG. 14 in order of steps. [Figure 22] 15A to 15C are diagrams showing a method for manufacturing the circuit board shown in FIG. 14 in order of steps. [Figure 23a] FIG. 11 is a diagram specifically illustrating the structure of a cavity according to the third embodiment. [Figure 23b] FIG. 11 is a diagram specifically illustrating the structure of a cavity according to the third embodiment. [Figure 24] 13A to 13C are diagrams for explaining a cavity processing method according to a third embodiment. [Diagram 25] 11A to 11C are diagrams for explaining a cavity processing method according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0051] However, the technical concept of the present invention is not limited to the embodiments described, but may be realized in various different forms, and one or more of the components between the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0052] In addition, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings commonly understood by those having ordinary knowledge in the technical field to which the present invention belongs, unless otherwise clearly and specifically defined, and commonly used terms such as predefined terms may be interpreted in consideration of the contextual meaning of the related art. In addition, the terms used in the embodiments of the present invention are intended to describe the embodiments, and do not limit the present invention.

[0053] In this specification, unless otherwise specified in the phrase, the singular form includes the plural form, and when described as "A and (and) at least one (or more) of B and C," it includes one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. can be used to describe components of the present invention.

[0054] Such terms are used merely to distinguish a component from other components, and are not intended to limit the essence, order, or sequence of the components. Furthermore, when a component is described as being "coupled," "bonded," or "connected" to another component, it includes not only the case where the component is directly coupled, bonded, or connected to the other component, but also the case where the component is "coupled," "bonded," or "connected" between the other component or by the other component.

[0055] In addition, when it is described that something is formed or placed "above or below" each component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or placed between the two components. In addition, when it is expressed as "above or below," it can include not only the upward direction based on one component, but also the downward direction.

[0056] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0057] FIG. 1 is a diagram showing a circuit board according to a first embodiment, and FIG. 2 is a plan view of a portion of the configuration of FIG.

[0058] Referring to FIG. 1, the circuit board 100 according to the first embodiment includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, circuit patterns 140, 150, 160, 170, vias V1, V2, V3, and protective layers 180, 185.

[0059] The first insulating layer 110 may be an insulating layer located in the center of the circuit board 100 .

[0060] The second insulating layer 120 is disposed on the first insulating layer 110 .

[0061] In addition, a third insulating layer 130 is disposed under the first insulating layer 110 .

[0062] In this case, in the drawings, the first insulating layer 110 is shown to be disposed in the center layer in the entire laminated structure of the circuit board 100, but is not limited thereto. That is, the first insulating layer 110 may be disposed in a position biased toward the upper side in the entire laminated structure of the circuit board 100, or conversely, may be disposed in a position biased toward the lower side.

[0063] Referring to FIG. 1, a second insulating layer 120 may be disposed on the first insulating layer 110. The second insulating layer 120 may be configured as a single layer. However, the embodiment is not limited thereto. For example, the second insulating layer 120 may have a multi-layer structure. However, a cavity C may be formed in the second insulating layer 120 in the embodiment. In addition, when the second insulating layer 120 has a multi-layer structure, the single second insulating layer shown in FIG. 1 may represent an insulating layer in which the cavity C is formed.

[0064] In addition, a third insulating layer 130 is disposed under the first insulating layer 110. In this case, the third insulating layer 130 may be configured as a single layer. However, the embodiment is not limited thereto. For example, the third insulating layer 130 may have a multi-layer structure.

[0065] In addition, although the circuit board 100 is shown in the drawings as having a three-layer structure based on the number of insulating layers, the present invention is not limited thereto. For example, the circuit board 100 may have fewer than three insulating layers, or may have more than three insulating layers.

[0066] The first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 are substrates on which electrical circuits that can be rewired are arranged, and may include any of printed circuit boards, wiring boards, and insulating substrates made of insulating materials on which circuit patterns can be formed.

[0067] For example, the first insulating layer 110 may be rigid or flexible. For example, the first insulating layer 110 may include glass or plastic. In particular, the first insulating layer 110 may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass, or may include reinforced or ductile plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

[0068] Also, the first insulating layer 110 may include an optical isotropic film. For example, the first insulating layer 110 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optical isotropic polycarbonate (PC), an optical isotropic polymethyl methacrylate (PMMA), or the like.

[0069] In addition, the first insulating layer 110 may be partially curved. That is, the first insulating layer 110 may be partially flat and partially curved. In particular, the first insulating layer 110 may be curved with an end having a curved surface, or may be curved with a surface including a random curvature.

[0070] In addition, the first insulating layer 110 may be a flexible substrate having a flexible characteristic, and may be a curved or bent substrate.

[0071] Meanwhile, the second insulating layer 120 and the third insulating layer 130 may be made of RCC (Resin Coated Copper).

[0072] That is, when the second insulating layer 120 and the third insulating layer 130 are each configured as a single layer, the single second insulating layer 120 and the single third insulating layer 130 may each be configured as RCC. Also, when the second insulating layer 120 and the single third insulating layer 130 have a multi-layer structure, each layer of the multi-layer structure of the second insulating layer 120 and each layer of the multi-layer structure of the third insulating layer 130 may all be configured as RCC.

[0073] Thus, each of the second insulating layer 120 and the third insulating layer 130 may have a thickness of 5 μm to 20 μm. For example, each of the second insulating layer 120 and the third insulating layer 130 may have a thickness of 6 μm to 18 μm. Each of the second insulating layer 120 and the third insulating layer 130 may have a thickness of 7 μm to 15 μm.

[0074] In this case, when the second insulating layer 120 is formed in a plurality of layers, the thickness range may refer to the range of thickness of each of the plurality of layers.

[0075] That is, the insulating layer constituting the circuit board in the comparative example was composed of the prepreg (PPG) containing glass fiber. In this case, it is difficult to reduce the thickness of the glass fiber in the circuit board in the comparative example based on the PPG. This is because, when the thickness of the PPG is reduced, the glass fiber contained in the PPG can be electrically connected to the circuit pattern arranged on the surface of the PPG, which induces cracks. Therefore, when the thickness of the PPG is reduced in the circuit board in the comparative example, dielectric breakdown or damage to the circuit pattern may occur. Therefore, the circuit board in the comparative example has a limit in reducing the overall thickness due to the thickness of the glass fiber constituting the PPG.

[0076] In addition, the circuit board in the comparative example has a high dielectric constant because it is composed of an insulating layer made only of PPG containing glass fiber. However, there is a problem that it is difficult to use a dielectric material with a high dielectric constant as a high-frequency substitute. That is, the circuit board in the comparative example has a phenomenon in which the dielectric constant is destroyed in the high-frequency band because the dielectric constant of the glass fiber is high.

[0077] Therefore, in the embodiment, the insulating layer is formed using RCC having a low dielectric constant, and thus, it is possible to provide a highly reliable circuit board in which the thickness of the circuit board is reduced and signal loss is minimized even in the high frequency band.

[0078] Meanwhile, by forming the second insulating layer 120 of the embodiment from RCC, the thickness of the circuit board can be significantly reduced compared to the comparative example formed from PPG. As a result, in the embodiment, the thickness of the circuit board can be reduced by at least 5 μm compared to the comparative example by using RCC made of a low dielectric constant material.

[0079] However, even if an RCC with a low dielectric constant of 2.7, which is 10% better than the dielectric constant of PPG at 3.0 level, is used, the thickness reduction rate is only 10% compared to the comparative example. Therefore, in the embodiment, a cavity is formed by laser processing in the part where a chip such as an electronic element is mounted, thereby providing an optimal circuit board.

[0080] In this case, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can express the electrical wiring that connects the circuit components based on the circuit design as a wiring diagram, and reproduce the electrical conductor on the insulator. Also, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can mount electrical components and form wiring that connects them in a circuit manner, and can mechanically fix components other than those that have an electrical connection function.

[0081] For example, a first circuit pattern 140 may be disposed on an upper surface of the first insulating layer 110. For example, a second circuit pattern 150 may be disposed on a lower surface of the first insulating layer 110. For example, a third circuit pattern 160 may be disposed on an upper surface of the second insulating layer 120. For example, a fourth circuit pattern 170 may be disposed on a lower surface of the third insulating layer 130.

[0082] Each of the first to fourth circuit patterns 140, 150, 160, and 170 may be formed in a plurality on the surface of each insulating layer while being spaced apart from each other at regular intervals.

[0083] In addition, when the second insulating layer 120 has a multi-layer structure, the third circuit pattern 160 may be disposed on the surface of each of the second insulating layers, and when the third insulating layer 130 has a multi-layer structure, the fourth circuit pattern 170 may be disposed on the surface of each of the third insulating layers.

[0084] Meanwhile, the first to fourth circuit patterns 140, 150, 160, 170 are wirings that transmit electrical signals and may be formed of metal materials with high electrical conductivity. To this end, the first to fourth circuit patterns 140, 150, 160, 170 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Also, the first to fourth circuit patterns 140, 150, 160, 170 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) that has excellent bonding strength. Preferably, the first to fourth circuit patterns 140, 150, 160, and 170 are made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0085] The first to fourth circuit patterns 40, 150, 160, and 170 can be formed by a typical printed circuit board manufacturing process such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), and a detailed description thereof will be omitted here.

[0086] Meanwhile, the first circuit pattern 140 may include a pad 140P disposed on the upper surface of the first insulating layer 110 and exposed through the cavity C. The pad 140P may be electrically connected to an electronic device (described below) mounted in the cavity C. For example, the pad 140P may be a wire bonding pad connected to the electronic device mounted in the cavity C via a wire. Alternatively, the pad 140P may be a flip chip bonding pad directly connected to a terminal of the electronic device mounted in the cavity C.

[0087] Meanwhile, the first to fourth circuit patterns 40, 150, 160, and 170 may each include a via pad connected to a via for interlayer conduction, a trace for signal transmission, and a mounting pad connected to an electronic element or the like.

[0088] Here, the first to fourth circuit patterns 140, 150, 160, and 170 can have a multi-layer structure.

[0089] For example, the first circuit pattern 140 may include a 1-1 metal layer 141 and a 1-2 metal layer 142. The 1-1 metal layer 141 may be disposed on the upper surface of the first insulating layer 110. For example, a lower surface of the 1-1 metal layer 141 may directly contact an upper surface of the first insulating layer 110. The 1-1 metal layer 141 may be a chemical copper plating layer. For example, the 1-1 metal layer 141 may be an electroless plating layer. The 1-1 metal layer 141 may be a seed layer for electrolytic plating of the 1-2 metal layer 142. The 1-2 metal layer 142 may be an electrolytic plating layer formed by electrolytic plating using the 1-1 metal layer 141 as a seed layer. The 1-2 metal layer 142 may have a thickness greater than that of the 1-1 metal layer 141. For example, the 1-1 metal layer 141 may have a first thickness. The first thickness of the 1-1 metal layer 141 may vary depending on the plating method of the 1-1 metal layer 141. For example, the chemical copper plating layer may be classified into heavy copper plating (heavy copper, 2 μm or more), medium copper plating (medium copper, 1 to 2 μm), and light copper plating (light copper, 1 μm or less) according to the thickness. In this case, the 1-1 metal layer 141 in the embodiment may have a first thickness of 0.5 μm to 1.5 μm in the medium copper plating or light copper plating. The first and second metal layers 142 may have a thickness in the range of 8.5 μm to 13.5 μm. Thus, the total thickness of the first circuit pattern 140 including the 1-1 metal layer 141 and the 1-2 metal layer 142 may have a thickness in the range of 10 μm to 14 μm.

[0090] For example, the second circuit pattern 150 may include a 2-1 metal layer 151 and a 2-2 metal layer 152. The 2-1 metal layer 151 may be disposed on the lower surface of the first insulating layer 110. For example, the upper surface of the 2-1 metal layer 151 may directly contact the lower surface of the first insulating layer 110. The 2-1 metal layer 151 may be a chemical copper plating layer. For example, the 2-1 metal layer 151 may be an electroless plating layer. The 2-1 metal layer 151 may be a seed layer for electroplating the 2-2 metal layer 152. The 2-2 metal layer 152 may be an electroplating layer formed by electroplating using the 2-1 metal layer 151 as a seed layer. The 2-2 metal layer 152 may be thicker than the 2-1 metal layer 151.

[0091] For example, the third circuit pattern 160 may include a 3-1 metal layer 161 and a 3-2 metal layer 162. The 3-1 metal layer 161 may be disposed on the upper surface of the second insulating layer 120. For example, a lower surface of the 3-1 metal layer 161 may directly contact an upper surface of the second insulating layer 120. The 3-1 metal layer 161 may be a chemical copper plating layer. For example, the 3-1 metal layer 161 may be an electroless plating layer. The 3-1 metal layer 161 may be a seed layer for electroplating the 3-2 metal layer 162. The 3-2 metal layer 162 may be an electroplating layer formed by electroplating using the 3-1 metal layer 161 as a seed layer. The 3-2 metal layer 162 may be thicker than the 3-1 metal layer 161.

[0092] For example, the fourth circuit pattern 170 may include a 4-1 metal layer 171 and a 4-2 metal layer 172. The 4-1 metal layer 171 may be disposed on the lower surface of the third insulating layer 130. For example, the upper surface of the 4-1 metal layer 171 may directly contact the lower surface of the third insulating layer 130. The 4-1 metal layer 171 may be a chemical copper plating layer. For example, the 4-1 metal layer 171 may be an electroless plating layer. The 4-1 metal layer 171 may be a seed layer for electroplating the 4-2 metal layer 172. The 4-2 metal layer 172 may be an electroplating layer formed by electroplating using the 4-1 metal layer 171 as a seed layer. The 4-2 metal layer 172 may be thicker than the 4-1 metal layer 171.

[0093] Vias V1, V2, and V3 electrically connecting circuit patterns arranged in different layers may be arranged in the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. The vias V1, V2, and V3 may be arranged to penetrate at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. Both ends of the vias V1, V2, and V3 are respectively connected to circuit patterns arranged in different insulating layers, thereby transmitting electrical signals.

[0094] A first via V1 may be disposed in the first insulating layer 110. The first via V1 may be disposed penetrating an upper surface and a lower surface of the first insulating layer 110. The first via V1 may electrically connect a first circuit pattern 140 disposed on the upper surface of the first insulating layer 110 to a second circuit pattern 142 disposed on the lower surface of the first insulating layer 110.

[0095] A second via V2 may be disposed in the second insulating layer 120. The second via V2 may be disposed to penetrate the upper and lower surfaces of the second insulating layer 120. The second via V2 may electrically connect a first circuit pattern 140 disposed on the upper surface of the first insulating layer 110 and a third circuit pattern 160 disposed on the upper surface of the second insulating layer 120.

[0096] In addition, a third via V3 may be disposed in the third insulating layer 130. The third via V3 may be disposed to penetrate the upper and lower surfaces of the third insulating layer 130. The third via V3 may electrically connect the second circuit pattern 150 disposed on the lower surface of the first insulating layer 110 and the fourth circuit pattern 170 disposed on the lower surface of the third insulating layer 130.

[0097] Meanwhile, the vias V1, V2, and V3 may penetrate only one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130, or may be disposed to penetrate a plurality of insulating layers in common. Thus, the vias V1, V2, and V3 may connect circuit patterns disposed on the surfaces of insulating layers that are at least two layers apart, rather than adjacent insulating layers.

[0098] Meanwhile, the vias V1, V2, and V3 may be formed by filling the inside of a through hole (not shown) penetrating at least one of the insulating layers with a conductive material.

[0099] The through hole may be formed by any one of mechanical, laser, and chemical processing. When the through hole is formed by mechanical processing, milling, drilling, routing, etc. may be used, when the through hole is formed by laser processing, UV or CO2 laser may be used, and when the through hole is formed by chemical processing, at least one of the insulating layers may be opened using a chemical containing aminosilane, ketones, etc.

[0100] On the other hand, laser processing is a cutting method that focuses optical energy on a surface to melt and evaporate part of a material to create a desired shape, and can easily process complex shapes created by computer programs, as well as composite materials that are difficult to cut with other methods.

[0101] In addition, the laser processing has the advantage that the cutting diameter can be as small as 0.005 mm, and the range of processable thicknesses is wide.

[0102] As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, while the CO2 laser is a laser that can process only the insulating layer.

[0103] When the through holes are formed, the insides of the through holes may be filled with a conductive material to form the vias V1, V2, and V3. The metal material forming the vias V1, V2, and V3 may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material may be filled by any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink jetting, and dispensing, or a combination thereof.

[0104] Meanwhile, protective layers 180, 185 may be disposed on the surfaces of the uppermost and lowermost insulating layers among the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. For example, the first protective layer 180 may be disposed on the upper surface of the insulating layer disposed at the top of the plurality of insulating layers. For example, the first protective layer 180 may be disposed on the upper surface of the second insulating layer 120. In addition, the second protective layer 185 may be disposed on the lower surface of the insulating layer disposed at the bottom of the plurality of insulating layers. For example, the second protective layer 185 may be disposed on the lower surface of the third insulating layer 130.

[0105] The first protective layer 180 and the second protective layer 185 may each have an opening. For example, the first protective layer 180 may have an opening exposing a surface of the third circuit pattern 160 disposed on the upper surface of the second insulating layer 120 that should be exposed.

[0106] In addition, the second protective layer 185 may have an opening that exposes a surface of the fourth circuit pattern 170 that is to be exposed out of the fourth circuit pattern 170 disposed on the lower surface of the third insulating layer 130 .

[0107] The first protective layer 180 and the second protective layer 185 may include an insulating material. The first protective layer 180 and the second protective layer 185 may include various materials that can be applied to protect the surface of the circuit pattern and then cured by heating. The first protective layer 180 and the second protective layer 185 may be a resist layer. For example, the first protective layer 180 and the second protective layer 185 may be a solder resist layer including an organic polymer material. As an example, the first protective layer 180 and the second protective layer 185 may include an epoxy acrylate resin. In detail, the first protective layer 180 and the second protective layer 185 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and it goes without saying that the first protective layer 180 and the second protective layer 185 may be any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0108] The first protective layer 180 and the second protective layer 185 may have a thickness of 1 μm to 20 μm. The first protective layer 180 and the second protective layer 185 may have a thickness of 1 μm to 15 μm. For example, the first protective layer 180 and the second protective layer 185 may have a thickness of 5 μm to 20 μm. If the thickness of the first protective layer 180 and the second protective layer 185 exceeds 20 μm, the thickness of the circuit board 100 may increase. If the thickness of the first protective layer 180 and the second protective layer 185 is less than 1 μm, the reliability of the circuit pattern included in the circuit board 100 may decrease.

[0109] Meanwhile, a cavity C may be formed in the second insulating layer 120. In this case, the cavity C may be formed in the second insulating layer 120 configured in a plurality of layers, or may be formed penetrating the second insulating layer 120 configured in a single layer.

[0110] Accordingly, in the embodiment, the pads 140P of the first circuit pattern 140 disposed on the upper surface of the first insulating layer 110 may be exposed through the cavity C. The cavity C may provide a space for mounting an electronic element. In addition, the pads 140P may be exposed through the cavity C and electrically connected to the electronic element mounted in the cavity C.

[0111] The cavity C in the embodiment may be formed through a laser process. At this time, in order to form the cavity C through the laser process, a stop layer is necessary to process the insulating layer to a desired depth. The stop layer may be made of a metal material that cannot be processed by the laser. For example, the laser may be a laser that can process only the insulating layer. And, the laser may not be able to process the metal layer made of a metal material. Therefore, a general circuit board has a stop layer that prevents the laser from passing further through the cavity formation area. At this time, the stop layer of the general circuit board may be formed by a process separate from the circuit pattern. Therefore, in the conventional method, a process of forming the stop layer and a process of removing the stop layer after the cavity is formed must be further performed, which causes problems such as an increase in manufacturing cost and a complicated manufacturing process.

[0112] Differently from this, in the embodiment, a separate stop layer is not formed in the region where the cavity C is formed, and a part of the circuit pattern can be used as the stop layer.

[0113] In the embodiment, a part of the first circuit pattern 140 is used as a stop layer. Preferably, in the embodiment, the 1-1 metal layer 141 constituting the first circuit pattern 140 is used as a stop layer for forming the cavity C.

[0114] That is, the 1-1 metal layer 141 may be removed after forming the 1-2 metal layer 142. In other words, the 1-1 metal layer 141 before being removed may be formed entirely on the upper surface of the first insulating layer 110.

[0115] In a general circuit board, after the 1-2 metal layer is formed, the 1-1 metal layer formed in the area not overlapping the 1-2 metal layer in the vertical direction is entirely removed.

[0116] Differently, in the embodiment, after the 1-2 metal layer 142 is formed, the 1-1 metal layer 141 is not entirely removed, but the 1-1 metal layer 141 present in the region where the cavity C is to be formed is left.

[0117] Then, in the embodiment, when the cavity C is formed, a process of further removing the 1-1 metal layer 141 is performed in the area exposed through the cavity C. That is, in the embodiment, the 1-1 metal layer 141, which is a seed layer of the 1-2 metal layer 142, can be used as a stop layer for forming the cavity C. As a result, in the embodiment, a process of further forming a stop layer necessary for forming the cavity C can be omitted, thereby achieving a reduction in manufacturing cost and a simplification of the manufacturing process.

[0118] In this embodiment, after the 1-2 metal layer 142 is formed, it is difficult to leave the 1-1 metal layer 141 exactly only in the area where the cavity C is to be formed. That is, due to the existence of tolerances in the laser process and product design, it is practically impossible to leave the 1-1 metal layer 141 only in the area where the cavity C is to be formed. Therefore, the area where the 1-1 metal layer 141 remains without being removed may be larger than the actual area where the cavity C is to be formed.

[0119] As a result, in the embodiment, the side surface of the 1-1 metal layer 141 used as a stop layer may be exposed through the side wall of the cavity C.

[0120] That is, in the embodiment, the 1-1 metal layer 141 may include a first portion disposed in a region vertically overlapping with the 1-2 metal layer 142 .

[0121] In addition, the 1-1 metal layer 141 in the embodiment may include a second portion 141a disposed in a region that does not vertically overlap with the 1-2 metal layer 142. As shown in FIG 2, the second portion 141a of the 1-1 metal layer 141 may have a structure disposed to surround the outside of the cavity C.

[0122] At this time, the second portion 141a of the 1-1 metal layer 141 in the first embodiment may be separated from the 1-2 metal layer 142. In other words, the second portion 141a of the 1-1 metal layer 141 in the first embodiment may be electrically insulated from the 1-2 metal layer 142 constituting the first circuit pattern 140. In other words, the second portion 141a of the 1-1 metal layer 141 in the first embodiment may be disposed at a constant distance from the 1-2 metal layer 142 constituting the first circuit pattern 140. And, the second portion 141a of the 1-1 metal layer 141 in the first embodiment may be disposed in a region adjacent to the cavity C, surrounding the outside of the cavity C.

[0123] Therefore, in the first embodiment, the 1-1 metal layer 141 may have a different area from the 1-2 metal layer 142. That is, in a general circuit board, the seed layer and the plating layer disposed on the seed layer may have the same area. This is because, after the plating layer is formed, the seed layer is entirely removed from the area where the plating layer is not disposed. As a result, the seed layer and plating layer of the general circuit board may have the same area.

[0124] Alternatively, in the embodiment, the 1-1 metal layer 141 may have an area larger than the 1-2 metal layer 142. For example, the 1-1 metal layer 141 may have an area larger than the 1-2 metal layer 142 by the second portion 141a.

[0125] Meanwhile, in the embodiment, the cavity C may be formed using a Gaussian beam. At this time, the outermost portion of the cavity C may be processed using the center point of the Gaussian beam. That is, the center point of the Gaussian beam generates a laser with the highest intensity, and therefore, the inclination angle of the inner wall of the cavity C at the outermost portion may be smaller than that of the comparative example.

[0126] As described above, the embodiment includes a first circuit pattern 140 disposed on the upper surface of the first insulating layer 110. The first circuit pattern 140 may include a 1-1 metal layer 141 that is a seed layer and a 1-2 metal layer 142 that is a plating layer disposed on the 1-1 metal layer 141. In the embodiment, the 1-1 metal layer 141 that is a seed layer of the 1-2 metal layer 142 is used as a stop layer of the cavity C formed in the second insulating layer 120. As a result, the area of ​​the 1-1 metal layer 141 in the embodiment may be larger than the area of ​​the 1-2 metal layer 142. In addition, the 1-1 metal layer 141 in the embodiment may include a first portion that overlaps with the 1-2 metal layer 142 in the vertical direction and a second portion 141a that does not overlap with the 1-2 metal layer 142. In addition, a side surface of the second portion 141a of the 1-1 metal layer 141 may be exposed through the cavity C formed in the second insulating layer 120. The second portion 141a of the 1-1 metal layer 141 may surround the outside of the cavity C and be disposed between the first insulating layer 110 and the second insulating layer 120. As a result, in the embodiment, it is not necessary to form a separate stop layer that is required when forming a cavity in the second insulating layer using a laser process, thereby achieving a reduction in manufacturing cost and a simplification of the manufacturing process.

[0127] The following mainly describes the structure of the circuit board in the first embodiment, as well as a package substrate including the circuit board and a method for manufacturing the same.

[0128] FIG. 3 is a diagram showing a package substrate according to the first embodiment.

[0129] 3, a package substrate 200AA in the embodiment includes the circuit board 100 shown in FIG.

[0130] The circuit board 100 described with reference to FIGS. 1 and 2 can be used as a package substrate 200A for mounting an electronic element 190 thereon.

[0131] At this time, since the circuit board 100 has already been described in detail above, the description thereof will be omitted.

[0132] The circuit board 100 includes a cavity C, and a pad 140P that is a part of the first circuit pattern 140 may be exposed in the cavity C. A 1-1 metal layer 141a having a closed loop shape surrounding the outside of the cavity C may be disposed in the cavity C. In this case, although the closed loop shape of the 1-1 metal layer 141a is shown to be a square shape in FIG. 2, the closed loop shape of the 1-1 metal layer 141a is not limited thereto. For example, the closed loop shape of the 1-1 metal layer 141 may be a circle, and may be various other shapes such as a triangle, a polygon, or an ellipse.

[0133] At this time, the electronic element 190 may be an electronic component disposed in the cavity C of the circuit board 100, which may be divided into an active element and a passive element. The active element is an element that actively uses a nonlinear portion, and the passive element means an element that does not use a nonlinear characteristic even if both linear characteristics and nonlinear characteristics exist. The passive element may include a transistor, an IC semiconductor chip, etc., and the passive element may include a capacitor, a resistor, an inductor, etc. The passive element is mounted on a normal circuit board to increase the signal processing speed of the semiconductor chip, which is an active element, or to perform a filtering function, etc.

[0134] Meanwhile, a connection part 195 may be disposed on the pad 140P. The planar shape of the connection part 195 may be a rectangle. The connection part 195 is disposed on the pad 140P to fix the electronic component 190 and electrically connect the electronic component 190 and the pad 140P. To this end, the connection part 195 may be formed of a conductive material. As an example, the connection part 195 may be a solder ball. The connection part 195 may include a material having a different component in a solder. The solder may be at least one of SnCu, SnPb, and SnAgCu. The material having a different component may include any one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

[0135] Meanwhile, the upper surface of the electronic component 190 may be located higher than the surface of the top layer of the circuit board 100. However, the embodiment is not limited thereto, and depending on the type of the electronic component 190, the upper surface of the electronic component 190 may be located at the same height as the surface of the top layer of the circuit board 100, or may be located lower than the above.

[0136] FIG. 4 is a diagram showing a package substrate according to the second embodiment.

[0137] Referring to FIG. 4, a package substrate 200B in the embodiment includes a circuit board 100 and an electronic component 190a mounted in a cavity C of the circuit board 100. As shown in FIG.

[0138] In addition, the package substrate 200B further includes a molding layer M disposed in the cavity C and covering the electronic element 190a.

[0139] The molding layer M can be selectively disposed in the cavity C to protect the electronic element 190a mounted in the cavity C.

[0140] The molding layer M may be made of a molding resin, for example, EMC (Epoxy molding compound). However, the embodiment is not limited thereto, and the molding layer M may be made of various other molding resins other than EMC.

[0141] The circuit board 100 can be used as a package substrate 200B for mounting an electronic element 190a.

[0142] As described above, the connection portion 195a may be disposed between the electronic element 190a and the pad 140P.

[0143] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described with reference to the accompanying drawings.

[0144] 5 to 10 are diagrams showing a method for manufacturing the circuit board shown in FIG. 1 in the order of steps.

[0145] Referring to FIG. 5, the first insulating layer 110 may be prepared, and first and second circuit patterns 140, 150 may be formed on the surface of the first insulating layer 110. A first via V1 may be formed to penetrate the first insulating layer 110 and electrically connect the first and second circuit patterns 140, 150.

[0146] The first insulating layer 110 may be a prepreg. The prepreg (PPG) has good fluidity and adhesion in a semi-cured state and is used as an intermediate substrate for fiber-reinforced composite materials used as adhesive layers and insulating layers. It is a molding material in which reinforcing fibers are pre-impregnated with a matrix resin. Such prepregs are laminated and heated / pressurized to harden the resin, forming a molded product. That is, prepreg refers to a material in which glass fiber is impregnated with resin (BT / Epoxy, FR4, FR5, etc.) and hardened to B-stage.

[0147] That is, the first insulating layer 110 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic / inorganic composite substrate, or a glass fiber impregnated substrate, and when it contains a polymer resin, it may contain an epoxy-based insulating resin, or alternatively, it may contain a polyimide-based resin.

[0148] In this case, the first circuit pattern 140 and the second circuit pattern 150 may be configured in a plurality of layers.

[0149] For example, the first circuit pattern 140 may include a 1-1 metal layer 141 and a 1-2 metal layer 142. For example, the second circuit pattern 150 may include a 2-1 metal layer 151 and a 2-2 metal layer 152.

[0150] Briefly, the process of forming the first circuit pattern 140 may be performed by forming the 1-1 metal layer 141 on the surface of the first insulating layer 110 by electroless plating in an embodiment. Then, in an embodiment, a process of forming a mask on the 1-1 metal layer 141 may be performed. Then, in an embodiment, the mask may be exposed and developed to form an opening exposing an area where the 1-2 metal layer 142 is to be formed. Then, in an embodiment, the 1-1 metal layer 141 may be electrolytically plated on a seed layer to form the 1-2 metal layer 142 filling the opening. Meanwhile, the first circuit pattern 140 may include a pad 140P that is later electrically connected to an electronic element and exposed through a cavity C.

[0151] Next, referring to FIG. 6, in an embodiment, after the 1-2 metal layer 142 and the 2-2 metal layer 152 are formed, a process can be performed to remove the 1-1 metal layer 141 and the 2-1 metal layer 151 used as seed layers.

[0152] At this time, in this embodiment, the metal layer used as the seed layer is not entirely removed, and the metal layer arranged in the region where the cavity C is to be formed is left unremoved.

[0153] Specifically, the cavity C may be formed in the second insulating layer 120 disposed on the 1-1 metal layer 141. Thus, in the embodiment, a portion of the 1-1 metal layer 141 corresponding to the region CR where the cavity C is to be formed is left without being removed.

[0154] That is, generally, all of the 1-1 metal layer 141 that does not vertically overlap with the 1-2 metal layer 142 is removed. At this time, in the embodiment, among the parts of the 1-1 metal layer 141 that do not vertically overlap with the 1-2 metal layer 142, the parts located in the region where the cavity C is to be formed are left without being removed.

[0155] At this time, the remaining portion of the 1-1 metal layer 141 may be larger than the actually formed cavity C. This solves the problem in the embodiment that a part of the surface of the first insulating layer 110 is removed due to a process error occurring in the process of forming the cavity C.

[0156] 7, in the embodiment, a second insulating layer 120 is formed on an upper surface of the first insulating layer 110. In addition, in the embodiment, a third insulating layer 130 is formed under a lower surface of the first insulating layer 110. At this time, the second insulating layer 120 and the third insulating layer 130 may each be made of RCC.

[0157] In addition, a process of forming a circuit pattern on the surface of the second insulating layer 120 may be performed. For example, a process of forming a third circuit pattern 160 on the upper surface of the second insulating layer 120 may be performed.

[0158] In addition, a process of forming a circuit pattern on the surface of the third insulating layer 130 may be performed. For example, a process of forming a fourth circuit pattern 170 on the lower surface of the third insulating layer 130 may be performed.

[0159] The third circuit pattern 160 and the fourth circuit pattern 170 may each have a multi-layer structure.

[0160] For example, the third circuit pattern 160 may include a 3-1 metal layer 161 and a 3-2 metal layer 162. For example, the fourth circuit pattern 170 may include a 4-1 metal layer 171 and a 4-2 metal layer 172.

[0161] In addition, in the embodiment, a step of forming a second via V2 in the second insulating layer 120 can be performed. In the embodiment, a step of forming a third via V3 in the third insulating layer 130 can be performed.

[0162] Next, referring to FIG. 8, in an embodiment, a process of opening the second insulating layer 120 using a laser to form a cavity C may be performed.

[0163] At this time, the 1-1st metal layer 141 remains without being removed on the upper surface of the first insulating layer 110 in the region where the cavity C is to be formed.

[0164] In the embodiment, in the laser process, the 1-1 metal layer 141 remaining in the area where the cavity C is formed can be used as a stop layer to remove the insulating layer up to the area where the 1-1 metal layer 141 is formed.

[0165] At this time, in the embodiment, a step of forming the cavity C can be performed using the center line of a Gaussian beam. That is, in the embodiment, the beam of the center line of a Gaussian beam is used to process the outermost region of the cavity C. Then, in the embodiment, the entire region of the cavity C is processed while moving the Gaussian beam by a certain distance.

[0166] 9, in an embodiment, a process may be performed to remove the 1-1 metal layer 141 whose upper surface is exposed through the cavity C. For example, in an embodiment, a process may be performed to remove the 1-1 metal layer 141 exposed through the cavity C by etching.

[0167] Next, referring to FIG. 10, in an embodiment, a process of forming protective layers 180 and 185 on an upper surface of the second insulating layer 120 and a lower surface of the third insulating layer 130, respectively, may be performed.

[0168] The first protective layer 180 and the second protective layer 185 may each have an opening. For example, the first protective layer 180 may have an opening exposing a surface of a fifth circuit pattern that is to be exposed among the third circuit pattern 160 disposed on the upper surface of the second insulating layer 120.

[0169] In addition, the second protective layer 185 may have an opening that exposes a surface of the fourth circuit pattern 170 that is to be exposed out of the fourth circuit pattern 170 disposed on the lower surface of the third insulating layer 130 .

[0170] 11 to 13 are diagrams showing modified examples of the circuit board of FIG.

[0171] 11, the circuit board 100A differs from the circuit board according to the first embodiment of FIG. 1 only in the structure of the first circuit pattern 140, and therefore the following description will focus on this feature.

[0172] In the first embodiment, the 1-1 metal layer 141 disposed around the cavity C has a structure separated from the 1-2 metal layer 142 .

[0173] Alternatively, the first circuit pattern may include a 1-1 circuit pattern 140b disposed adjacent to the cavity C. Also, the first circuit pattern may include a 1-2 circuit pattern other than the 1-1 circuit pattern 140b. And, the 1-1 metal layer and the 1-2 metal layer of the 1-2 circuit pattern may have the same area or width. Alternatively, the 1-1 metal layer and the 1-2 metal layer of the 1-1 circuit pattern may have different areas or widths.

[0174] That is, the 1-1 circuit pattern 140b may include a 1-1 metal layer 141b and a 1-2 metal layer 142b. At this time, the 1-1 metal layer 141b may be formed on the first insulating layer 110 with a first width. Also, the 1-2 metal layer 142b may be disposed on the 1-1 metal layer 141b with a second width. At this time, the first width may be greater than the second width. Thus, the 1-1 metal layer 141b may include a first portion that vertically overlaps with the 1-2 metal layer 141b and a second portion that does not vertically overlap with the 1-2 metal layer 142b. At this time, an upper surface of the first portion of the 1-1 metal layer 141b may be in direct contact with the 1-2 metal layer 142b. Also, an upper surface of the second portion of the 1-1 metal layer 141b may be disposed in direct contact with the second insulating layer 120, unlike the first portion.

[0175] The second portion of the 1-1 metal layer 141b may be located closer to the cavity C than the first portion of the 1-1 metal layer 141b.

[0176] In addition, a side surface of the second portion of the 1-1 metal layer 141b may be exposed through the cavity C. In contrast, the 1-2 metal layer 142b may have a width smaller than that of the 1-1 metal layer 141b and may be disposed at a position away from the cavity C on the 1-1 metal layer 141b, and may not be exposed through the cavity C.

[0177] 12, the circuit board may have a different layer structure of insulating layers compared to the circuit board of FIG.

[0178] That is, in FIG. 1, the second insulating layer 120 and the third insulating layer 130 are each configured as a single layer, but in the circuit board in FIG. 12, the second insulating layer 120 and the third insulating layer 130 can each have a multi-layer structure.

[0179] For example, the second insulating layer may include a 2-1 insulating layer 120-1 and a 2-2 insulating layer 120-2. Also, the 2-1 insulating layer 120-1 and the 2-2 insulating layer 120-2 may each be made of RCC.

[0180] Also, the third insulating layer may include a 3-1 insulating layer 130-1 and a 3-2 insulating layer 130-2. Also, the 3-1 insulating layer 130-1 and the 3-2 insulating layer 130-2 may each be made of RCC.

[0181] In addition, in an embodiment, the third circuit pattern may include a 3-1 circuit pattern 160-1 arranged on the upper surface of the 2-1 insulating layer 120-1 and a 3-2 circuit pattern 160-2 arranged on the upper surface of the 2-2 insulating layer 120-2.

[0182] In addition, in an embodiment, the fourth circuit pattern may include a 4-1 circuit pattern 170-1 arranged under the lower surface of the 3-1 insulating layer 130-1 and a 4-2 circuit pattern 170-2 arranged under the lower surface of the 3-2 insulating layer 130-2.

[0183] In addition, the cavity C in the embodiment may be formed penetrating the second insulating layer 120 having the multi-layer structure.

[0184] At this time, the cavity C may form one cavity by commonly penetrating the second insulating layer 120. For example, the cavity C may include a first cavity part C-1 formed in the 2-1 insulating layer 120-1 and a second cavity part C-2 formed in the 2-2 insulating layer 120-2. The first cavity part C-1 and the second cavity part C-2 may have the same width.

[0185] As a result, the 3-2 circuit pattern 160-2 arranged on the upper surface of the 2-2 insulating layer 120-2 is not exposed through the cavity C, and only the pads corresponding to the 3-1 circuit pattern 160-1 arranged on the upper surface of the 2-1 insulating layer 120-1 can be exposed.

[0186] In this case, the metal layer corresponding to the stop layer used to form the cavity C in the embodiment may be located only on the first insulating layer 110 and the 2-1 insulating layer 120-1. That is, the metal layer corresponding to the stop layer may have the same structure as the metal layer shown in any one of FIGS. 1 and 11 and may include the second portion 141a of the 1-1 metal layer 141 surrounding the outside of the cavity C.

[0187] 13, the second insulating layer may include a 2-1 insulating layer 120-1 and a 2-2 insulating layer 120-2, and the 2-1 insulating layer 120-1 and the 2-2 insulating layer 120-2 may each be made of RCC.

[0188] Also, the third insulating layer may include a 3-1 insulating layer 130-1 and a 3-2 insulating layer 130-2, and the 3-1 insulating layer 130-1 and the 3-2 insulating layer 130-2 may each be made of RCC.

[0189] In addition, in an embodiment, the third circuit pattern may include a 3-1 circuit pattern 160-1 arranged on the upper surface of the 2-1 insulating layer 120-1 and a 3-2 circuit pattern 160-2 arranged on the upper surface of the 2-2 insulating layer 120-2.

[0190] In addition, in an embodiment, the fourth circuit pattern may include a 4-1 circuit pattern 170-1 arranged under the lower surface of the 3-1 insulating layer 130-1 and a 4-2 circuit pattern 170-2 arranged under the lower surface of the 3-2 insulating layer 130-2.

[0191] In addition, the cavity C in the embodiment may be formed penetrating the second insulating layer 120 having the multi-layer structure.

[0192] In this case, the cavity C may include two cavities each penetrating a plurality of second insulating layers 120. For example, the cavity C may include a first cavity C1 formed in the 2-1 insulating layer 120-1 and a second cavity C2 formed in the 2-2 insulating layer 120-2.

[0193] The first cavity C1 and the second cavity C2 may have different widths. For example, in the embodiment, the package substrate may mount a first electronic component in the first cavity C1 formed in the 2-1 insulating layer 120-1 and mount a second electronic component in the second cavity C2 formed in the 2-2 insulating layer 120-2.

[0194] As a result, a portion of the first circuit pattern (a pad connected to the first electronic element) may be exposed in the first cavity C1 formed in the 2-1 insulating layer 120-1, and a portion of the 3-1 circuit pattern 160-1 may be exposed in the second cavity C2 formed in the 2-2 insulating layer 120-2.

[0195] The first cavity C1 and the second cavity C2 may have different widths, so that in the embodiment, the process of forming each cavity may be performed separately.

[0196] In such a case, the metal layer corresponding to the stop layer used for forming the cavity C in the embodiment may be located not only between the first insulating layer 110 and the 2-1 insulating layer 120-1, but also between the 2-1 insulating layer 120-1 and the 2-2 insulating layer 120-2.

[0197] That is, a plating layer 160-1a, which is a part of the 3-1 circuit pattern 160-1 used to form the second cavity C2, may be disposed on the upper surface of the 2-1 insulating layer 120-1 to surround the periphery of the second cavity C2.

[0198] FIG. 14 is a diagram showing a circuit board according to the second embodiment, and FIG. 15 is a plan view of a portion of the circuit board of FIG.

[0199] 1, the circuit board in the second embodiment may not include the second portion 141a of the 1-1 metal layer 141. This can be achieved by forming a cavity in the circuit board in the second embodiment by performing multiple processing steps different from those in the first embodiment.

[0200] However, the circuit board of the second embodiment in Fig. 14 may also include the second portion 141a of the 1-1 metal layer 141 shown in Fig. 1, Fig. 11, Fig. 12, and Fig. 13. However, the following description will be given assuming that the circuit board of the second embodiment does not include the second portion 141a of the 1-1 metal layer 141.

[0201] Referring to FIG. 14, a circuit board 1000 includes a first insulating layer 1100, a second insulating layer 1200, a third insulating layer 1300, circuit patterns 1400, 1500, 1600, 1700, vias V1, V2, V3, and protective layers 1800, 1850.

[0202] At this time, the second insulating layer 120 of the first embodiment is formed of RCC. Differently, the second insulating layer 1200 of the second embodiment may be formed of the same prepreg as the first insulating layer 1100. At this time, the prepreg contains glass fiber inside. When a cavity is formed in the prepreg, at least a part of the glass fiber contained in the prepreg may be exposed in the cavity. The exposed glass fiber may cause various reliability problems as described above. Therefore, in the second embodiment, even if the second insulating layer 1200 is made of a prepreg containing glass fiber, the glass fiber exposed through the cavity can be completely removed. However, the embodiment is not limited thereto, and the second insulating layer 1200 in the second embodiment may also be formed of RCC like the second insulating layer 120 of the first embodiment.

[0203] However, in the following description, it is assumed that second insulating layer 1200 of the second embodiment is made of prepreg.

[0204] At this time, a cavity C, which will be described later, may be formed in the second insulating layer 1200. The cavity C may be formed penetrating the second insulating layer 1200. In the embodiment, the second insulating layer 1200 is formed of a prepreg. Here, the prepreg may have a structure in which glass fibers and fillers are dispersed in a resin. When the cavity C is formed in the second insulating layer 1200 made of the prepreg, a problem may occur in that the glass fibers dispersed in the second insulating layer 1200 are exposed through the cavity C. Therefore, in the embodiment, an attempt is made to provide a cavity forming method capable of efficiently removing the glass fibers exposed through the cavity C among the glass fibers disposed in the second insulating layer 1200, and a cavity structure resulting therefrom.

[0205] This can be achieved by features appearing in the process of forming cavity C, which will be described later. For example, in the embodiment, cavity C is formed by performing a plurality of processing steps. That is, when a laser is used to form cavity C, the cavity shape and processing time vary depending on the laser source. In this case, in the embodiment, a cavity in which glass fibers are not exposed through cavity C can be formed within the process time for forming the optimal cavity while having an optimal cavity shape.

[0206] A first circuit pattern 1400 may be disposed on an upper surface of the first insulating layer 1100. For example, a second circuit pattern 1500 may be disposed on a lower surface of the first insulating layer 1100. For example, a third circuit pattern 1600 may be disposed on an upper surface of the second insulating layer 1200. For example, a fourth circuit pattern 1700 may be disposed on a lower surface of the third insulating layer 1300.

[0207] Meanwhile, the first circuit pattern 1400 may be disposed on the upper surface of the first insulating layer 1100 and may include a pad 1400P exposed through the cavity C.

[0208] Also, similar to the first embodiment, the circuit pattern in the second embodiment may have a two-layer structure. For example, the first circuit pattern 1400 may include a 1-1 metal layer 1410 and a 1-2 metal layer 1420. For example, the second circuit pattern 1500 may include a 2-1 metal layer 1510 and a 2-2 metal layer 1520. For example, the third circuit pattern 1600 may include a 3-1 metal layer 1610 and a 3-2 metal layer 1620. For example, the fourth circuit pattern 1700 may include a 4-1 metal layer 1710 and a 4-2 metal layer 1720.

[0209] Vias V1, V2, and V3 may be disposed in the first insulating layer 1100, the second insulating layer 1200, and the third insulating layer 1300 to electrically connect circuit patterns disposed in different layers to each other.

[0210] Meanwhile, a cavity C may be formed in the second insulating layer 1200. In this case, the cavity C may be formed in the second insulating layer 1200 configured in a plurality of layers, or may be formed penetrating the second insulating layer 1200 configured in a single layer.

[0211] As a result, the pads 1400P of the first circuit pattern 1400 disposed on the upper surface of the first insulating layer 1100 in the embodiment may be exposed through the cavity C.

[0212] In the embodiment, a part of the first circuit pattern 1400 is used as a stop layer in the cavity forming process. Preferably, in the embodiment, the 1-1st metal layer 1410 constituting the first circuit pattern 1400 can be used as a stop layer for forming the cavity C.

[0213] Meanwhile, in the embodiment, a mask (not shown) is required to perform laser processing precisely only in the area where the cavity C is to be formed. The mask can determine the size of the area to be processed by the laser. In other words, the mask can determine the size of the cavity C. The mask is formed in an area corresponding to the upper area of ​​the cavity C and can determine the size of the upper area. For example, the mask can have a shape that surrounds the periphery of the upper area of ​​the cavity. Therefore, the mask can determine the size of the upper area of ​​the cavity, and can further determine the overall size of the cavity C.

[0214] Furthermore, the stop layer can determine the depth of the cavity C. That is, the stop layer can be disposed in a region corresponding to the lower region of the cavity C. Therefore, the stop layer can allow the laser to process the insulating layer only up to a position corresponding to the lower region of the cavity C.

[0215] In this case, the mask in the embodiment may use the circuit pattern disposed on the upper surface of the second insulating layer 1200. Preferably, the mask in the embodiment may use a seed layer of the circuit pattern disposed on the upper surface of the second insulating layer 1200. More preferably, the mask in the embodiment may use the 3-1 metal layer 1610 constituting the third circuit pattern 1600 disposed on the upper surface of the second insulating layer 1200.

[0216] That is, in an embodiment, after the first circuit pattern 1400 and the third circuit pattern 1600 are formed, a cavity C can be formed in the second insulating layer 1200 using the 1-1 metal layer 1410 of the first circuit pattern 1400 and the 3-1 metal layer 1610 of the third circuit pattern 1400 in the area where the cavity C is to be formed.

[0217] On the other hand, in this embodiment, the cavity C can be formed in the second insulating layer 1200 by performing laser processing in two steps.

[0218] Preferably, in the embodiment, the cavity may be formed primarily in the second insulating layer 1200 using a carbon dioxide (CO2) laser. The carbon dioxide (CO2) laser has an advantage that a cavity of a desired size can be quickly formed in the second insulating layer 1200 compared to other lasers, but has a disadvantage that the inclination angle of the inner wall of the cavity C forms an obtuse angle based on the bottom surface of the cavity. That is, the inner wall of the cavity formed using the carbon dioxide laser has an angle of 110 degrees or more. And, when the inclination angle of the inner wall of the cavity C forms an obtuse angle, a lot of space is required to form the cavity C of a desired size. That is, the size of the cavity C may be determined by the size of the lower region where the electronic element is disposed. However, when the inner wall of the cavity C has an obtuse angle, the size of the upper region of the cavity C is larger than the size of the lower region of the cavity C. Therefore, the space required to form the cavity C may be larger by the size of the upper region, not the size of the lower region.

[0219] As a result, in an embodiment, a cavity formed by a carbon dioxide (CO2) laser can be subjected to secondary processing using an ultraviolet (UV) laser. That is, when a cavity is formed by a carbon dioxide (CO2) laser, a step-shaped step is generated on the inner wall of the cavity so as to correspond to the moving distance of the laser source performed during the laser processing. As a result, in an embodiment, a cavity formed through the carbon dioxide (CO2) laser can be subjected to secondary processing using an ultraviolet (UV) laser. Specifically, the secondary processing of the cavity using the ultraviolet (UV) laser can be performed only on the inner wall of the cavity that has been primarily processed.

[0220] Thus, in the embodiment, the inner wall of the secondary processed final cavity C may have an inclination angle of 90.01° to 100° with respect to the bottom surface of the cavity or the surface of the insulating layer. For example, the inner wall of the secondary processed final cavity may have an inclination angle of 90.1° to 95° with respect to the bottom surface of the cavity or the surface of the insulating layer. For example, the inner wall of the cavity may have an inclination angle of 91° to 93° with respect to the bottom surface of the cavity or the surface of the insulating layer. That is, the cavity in the embodiment may be substantially perpendicular (or close to perpendicular) with respect to the bottom surface of the cavity or the top surface of the first insulating layer.

[0221] For example, in the embodiment, the vertical cross-sectional shape of the cavity C formed in the second insulating layer 1200 may be close to a rectangle or a square. Thus, in the embodiment, the vertical cross-sectional shape of the cavity C formed in the second insulating layer 1200 has a shape corresponding to a rectangle or a square, so that the space required to form the cavity C can be reduced. This can improve the circuit integration degree.

[0222] Specifically, an upper region of the cavity C in the embodiment may have a first width W1. And, a lower region of the cavity C in the embodiment may have a second width W2 that is equal to the first width W1. As a result, the space required to form the cavity C in the embodiment may be significantly reduced.

[0223] The size of the cavity C may be determined such that the width of the lower region corresponds to the size of the electronic element disposed therein. In the comparative example, the width of the upper region of the cavity C is greater than the width of the lower region, and a space is wasted corresponding to the difference in width between the upper and lower regions. In contrast, in the embodiment, the widths of the lower and upper regions of the cavity C are the same, and this can solve the space wastage.

[0224] On the other hand, the horizontal cross section of the cavity C in the embodiment may have at least a partially rounded shape. For example, the cavity C in the embodiment may have at least a curved surface. For example, the cavity C in the embodiment may have a shape in which the edge portion has a curved surface.

[0225] Referring to FIG. 15, a horizontal cross section of cavity C in an embodiment includes at least four straight line segments.

[0226] For example, the horizontal cross section of the cavity C in the embodiment may include a linear first portion S1. Also, the horizontal cross section of the cavity C in the embodiment may include a linear second portion S2 that is substantially perpendicular to the first portion S1. Also, the horizontal cross section of the cavity C in the embodiment may include a linear third portion S3 that is substantially perpendicular to the second portion S2 and parallel to the first portion S1. Also, the horizontal cross section of the cavity C in the embodiment may include a linear fourth portion S4 that is substantially perpendicular to the third portion S3 and parallel to the second portion S2.

[0227] In addition, the horizontal cross section of the cavity C may include a first edge E1 between the first portion S1 and the second portion S2. In this case, the first edge E1 may have a curved line rather than a straight line. For example, the first edge E1 may be a rounded region. That is, the first edge E1 may include a curved surface.

[0228] In addition, the horizontal cross section of the cavity C may include a second edge E2 between the second portion S2 and the third portion S3. In this case, the second edge E2 may have a curved line rather than a straight line. For example, the second edge E2 may be a rounded region. That is, the second edge E2 may include a curved surface.

[0229] In addition, the horizontal cross section of the cavity C may include a third edge E3 between the third portion S3 and the fourth portion S4. In this case, the third edge E3 may have a curved line rather than a straight line. For example, the third edge E3 may be a rounded region. That is, the third edge E3 may include a curved surface.

[0230] In addition, the horizontal cross section of the cavity C may include a fourth edge E4 between the first portion S1 and the fourth portion S4. In this case, the fourth edge E4 may have a curved line rather than a straight line. For example, the fourth edge E4 may be a rounded region. That is, the fourth edge E4 may include a curved surface.

[0231] In this case, the curved surfaces of the first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 in the embodiment may correspond to the beam size of the ultraviolet (UV) laser in the embodiment. For example, the beam size of the ultraviolet (UV) laser may be a circle having a diameter of 20 μm to 80 μm. The first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 may have curved surfaces corresponding to the beam size of the ultraviolet (UV) laser. For example, the curvature of the curved surfaces of the first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 may correspond to the curvature of a circle having a diameter of 20 μm to 80 μm.

[0232] As a result, in the embodiment, the first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 have vertical straight lines, which can solve structural reliability problems such as cavity collapse that may occur at the corresponding edge portions, thereby improving product satisfaction.

[0233] Meanwhile, in the embodiment, the second insulating layer 1200 may be formed of a prepreg. The prepreg contains glass fiber in resin to ensure rigidity. In the process of forming the cavity C, a part of the glass fiber may be exposed to the outside through the cavity C. When the glass fiber is exposed through the cavity C, various reliability problems may occur. For example, the glass fiber may cause a problem in the flatness of the electronic element disposed in the cavity C. For example, the glass fiber may cause an electrical shot of the electronic element disposed in the cavity C.

[0234] At this time, the carbon dioxide (CO2) laser cannot remove the glass fibers contained in the second insulating layer 1200. Therefore, when the cavity C is formed only using the carbon dioxide (CO2) laser, the glass fibers contained in the second insulating layer 1200 may be exposed to the outside through the cavity C.

[0235] However, in the embodiment, the primary cavity is processed using a carbon dioxide (CO2) laser, and then the secondary cavity is processed using an ultraviolet (UV) laser. At this time, the ultraviolet (UV) laser can remove the glass fibers exposed through the primary processed cavity while making the inclination angle of the inner wall of the cavity C almost vertical.

[0236] That is, in the embodiment, the ultraviolet (UV) laser can be used to remove all glass fibers of the second insulating layer 1200 that may protrude into the inside of the cavity C. As a result, the glass fibers of the second insulating layer 1200 may not protrude from the inner wall of the cavity C toward the inside of the cavity C.

[0237] 16 to 22 are diagrams showing the process steps of a method for manufacturing the circuit board shown in FIG.

[0238] Referring to FIG. 16, the first insulating layer 1100 may be prepared, and first and second circuit patterns 1400, 1500 may be formed on the surface of the first insulating layer 1100. A first via V1 may be formed through the layer 1100 to electrically connect the first and second circuit patterns 1400, 1500.

[0239] Next, referring to FIG. 17, in an embodiment, after the 1-2 metal layer 1420 and the 2-2 metal layer 1520 are formed, a process can be performed to remove the 1-1 metal layer 1410 and the 2-1 metal layer 1510 used as seed layers.

[0240] At this time, in this embodiment, the metal layer used as the seed layer is not entirely removed, and the metal layer disposed in the region where the cavity C is to be formed is left unremoved.

[0241] At this time, the 1-1 metal layer 1410 may include a 1-1 portion P1-1 that vertically overlaps with the 1-2 metal layer 1420 in a region where the cavity is not formed. The 1-1 metal layer 1410 may include a 1-2 portion P1-2 that does not vertically overlap with the 1-2 metal layer 1420 in a region where the cavity is not formed. The 1-1 metal layer 1410 may also include a 1-3 portion P1-3, 1410a, disposed in the cavity forming region.

[0242] In an embodiment, when the manufacture of the first circuit pattern 1400 is completed by plating the 1-2 metal layer 1420, the 1-2 portion P1-2 of the 1-1 metal layer 1410 is removed, while the 1-3 portion P1-3 of the 1-1 metal layer 1410 is left unremoved.

[0243] 18, in an embodiment, a second insulating layer 1200 is formed on an upper surface of the first insulating layer 1100. In addition, in an embodiment, a third insulating layer 1300 is formed under a lower surface of the first insulating layer 1100. At this time, the second insulating layer 1200 and the third insulating layer 1300 may be made of RCC, or may be made of prepreg.

[0244] Also, a process of forming a circuit pattern on the surface of the second insulating layer 1200 may be performed. For example, a process of forming a third circuit pattern 1600 on the upper surface of the second insulating layer 1200 may be performed.

[0245] In addition, in an embodiment, a step of forming a second via V2 in the second insulating layer 1200 can be performed. In addition, in an embodiment, a step of forming a third via V3 in the third insulating layer 1300 can be performed.

[0246] Meanwhile, in this embodiment, a third circuit pattern 1600 disposed on the upper surface of the second insulating layer 1200 includes a 3-1 metal layer 1610 and a 3-2 metal layer 1620 .

[0247] At this time, in the manufacturing process of the third circuit pattern 1600, when plating of the 3-2 metal layer 1620 is completed, the 3-1 metal layer 1610 used as a plating seed layer of the 3-2 metal layer 1620 is removed. At this time, in this embodiment, the entire 3-1 metal layer 1610 used as a seed layer of the 3-2 metal layer 1620 is not removed, and the metal layer arranged in the region where the cavity C is to be formed is left unremoved.

[0248] Specifically, in the embodiment, a portion of the 3-1 metal layer 1610 disposed in an outer region of the cavity surrounding the region where the cavity C is to be formed is left without being removed. That is, generally, the 3-1 metal layer 1610 is entirely removed in a portion that does not vertically overlap with the 3-2 metal layer 1620 after the third circuit pattern 1600 is formed. At this time, in the embodiment, of the 3-1 metal layer 1610, a portion that is located around the region where the cavity C is to be formed among the portions that do not vertically overlap with the 3-2 metal layer 1620 is left without being removed.

[0249] Specifically, the 3-1 metal layer 1610 may be formed entirely on the top surface of the second insulating layer 1200 .

[0250] At this time, the 3-1 metal layer 1610 may include a 2-1 portion P2-1 that vertically overlaps with the 3-2 metal layer 1620. And, the 3-1 metal layer 1610 may include a portion that does not vertically overlap with the 3-2 metal layer 1620 in a region where the cavity is not formed. At this time, the portion of the 3-1 metal layer 1610 that does not vertically overlap with the 3-2 metal layer 1620 may include a 2-2 portion P2-2 that overlaps with a region where the cavity C is formed or is separated from the region where the cavity is formed. And, the portion of the 3-1 metal layer 1610 that does not vertically overlap with the 3-2 metal layer 1620 may include a 2-3 portion P2-3 adjacent to the cavity region where the cavity C is formed.

[0251] Here, in a typical circuit board manufacturing process, when the third circuit pattern 1600 is completed by plating the 3-2 metal layer 1620, the 3-1 metal layer 1610 including the 2-2 portion P2-2 and the 2-3 portion P2-3 is removed.

[0252] In contrast, in an embodiment, in a typical circuit board manufacturing process, when the 3-2 metal layer 1620 is plated to complete the manufacture of the second circuit pattern 1600, the 2-2 portion P2-2 of the 3-1 metal layer 1610 is removed, while the 2-3 portion P2-3 of the 3-1 metal layer 1410 is left unremoved.

[0253] The 2-3 portion P2-3 of the 3-1 metal layer 1610 may be located in a boundary region between a region where the cavity C is formed and other regions on the upper surface of the second insulating layer 1200. For example, the 2-3 portion P2-3 of the 3-1 metal layer 1610 may be formed in the remaining region excluding the region where the cavity C is formed on the upper surface of the second insulating layer 1200. For example, the 2-3 portion P2-3 of the 3-1 metal layer 1610 may be disposed to surround the periphery of the region where the cavity C is formed on the upper surface of the second insulating layer 1200.

[0254] At this time, the 2-3 portion P2-3 of the 3-1 metal layer 1610 may have a constant width. At this time, the width of the 2-3 portion P2-3 of the 3-1 metal layer 1610 may be larger than the radius of the beam size in a subsequent laser process. That is, in an embodiment, a cavity processing process may be performed using a Gaussian beam corresponding to the center portion of the beam in a carbon dioxide (CO2) laser process. As a result, the center portion of the Gaussian beam is located at the edge region of the cavity C. And, when the width of the 2-3 portion P2-3 of the 3-1 metal layer 1610 is smaller than the radius of the beam size, a region other than the cavity forming region in the second insulating layer 1200 may be processed by the Gaussian beam. Therefore, in an embodiment, the 2-3 portion P2-3 of the 3-1 metal layer 1610 may have a width larger than the radius of the Gaussian beam.

[0255] 19, a primary cavity may be formed in the second insulating layer 1200 with the 2-3 portion P2-3 of the 3-1 metal layer 1610 as a boundary line. The primary cavity may be formed using a carbon dioxide (CO2) laser. The primary processed cavity Ca may have a trapezoidal horizontal cross section. For example, the primary processed cavity Ca may have a gradually decreasing width from the top to the bottom. Also, the glass fiber GF contained in the second insulating layer 1200 may be exposed to the outside of the cavity through the primary processed cavity Ca.

[0256] As a result, in this embodiment, similarly to FIG. 20, a secondary cavity processing can be performed on the primarily processed cavity by using an ultraviolet (UV) laser.

[0257] That is, in the embodiment, a secondary processing can be performed using an ultraviolet (UV) laser on a cavity that has been primarily processed using a carbon dioxide (CO2) laser. That is, when a cavity is formed using the carbon dioxide (CO2) laser, a step-shaped step is generated on the inner wall of the cavity so as to correspond to the moving distance of the laser source performed during the laser processing. Thus, in the embodiment, a secondary processing can be performed on the cavity formed through the carbon dioxide (CO2) laser using an ultraviolet (UV) laser. Specifically, the secondary processing of the cavity using an ultraviolet (UV) laser can be performed only on the inner wall of the primarily processed cavity.

[0258] Next, referring to FIG. 21, when the processing of the cavity C is completed, a part of the 1-1 metal layer 1410 and the 3-1 metal layer 1610 remaining for processing the cavity C may be removed.

[0259] That is, in the embodiment, the 1-3 portion P1-3 of the 1-1 metal layer 1410 and the 2-3 portion P2-3 of the 3-1 metal layer 1610, which are the seed layers, are left without being removed for the cavity processing. Then, when the processing of the cavity C is completed, in the embodiment, a process of removing the 1-3 portion P1-3 of the 1-1 metal layer 1410 and the 2-3 portion P2-3 of the 3-1 metal layer 1610 can be performed. At this time, as in the first embodiment, at least a part of the 1-3 portion P1-3 of the 1-1 metal layer 1410 and the 2-3 portion P2-3 of the 3-1 metal layer 1610 may remain without being removed.

[0260] Next, referring to FIG. 22, in this embodiment, a process of forming protective layers 1800 and 1850 on an upper surface of the second insulating layer 1200 and a lower surface of the third insulating layer 1300, respectively, may be performed.

[0261] Also, it is possible to embody the structure shown in Figs. 11 to 13, which has a structure corresponding to the second embodiment and corresponds to a modification of the first embodiment.

[0262] 23a and 23b are diagrams specifically illustrating the structure of a cavity according to the third embodiment.

[0263] Fig. 23a shows a circuit board in which the second insulating layer described in the first and second embodiments is configured in multiple layers, and Fig. 23b shows a circuit board in which the second insulating layer is configured in a single layer.

[0264] 23a and 23b, the second insulating layer 2120 may have a cavity formed therein.

[0265] The cavity may be formed by opening a plurality of second insulating layers 2120 (see FIG. 23a) or a single second insulating layer 2120 (see FIG. 23b). When the cavity is formed in a plurality of second insulating layers (e.g., insulating layers 2-1 to 2-3), the cavity may include a first part formed in the 2-1 insulating layer, a second part formed in the 2-2 insulating layer, and a third part formed in the 2-3 insulating layer.

[0266] Here, the cavity includes inner walls S1, S2, and S3. The inner walls S1, S2, and S3 of the cavity may have a certain surface roughness. In this embodiment, the surface roughness may be formed during a laser process for forming the cavity, rather than performing an additional process so that the inner walls S1, S2, and S3 of the cavity have a certain surface roughness.

[0267] Meanwhile, the inner wall of the cavity may be divided into a plurality of parts. For example, the inner wall of the cavity may be divided into a first part S3, the second part S2, and a third part S1 from the bottom. In this case, the inclination angles of the first part S3, the second part S2, and the third part S1 may be different from each other. Also, the surface roughness of at least one of the first part S3, the second part S2, and the third part S1 may be different from the surface roughness of the other part. For example, the surface roughness of the second part S2 may be the same as the surface roughness of the third part S1. However, the surface roughness of the second part S2 and the third part S1 may be different from the surface roughness of the first part S3. This is because at least one of the first part S3, the second part S2, and the third part S1 constituting the inner wall of the cavity is formed by a process different from the other parts. For example, the second part S2 and the third part S1 are parts formed through a laser process and a desmear process. In contrast, the first portion S3 is a portion formed by removing a portion of the circuit pattern, and therefore the second portion S2 and the third portion S1 may have surface roughness corresponding to the laser process and desmear process conditions, and the first portion S3 may have a surface roughness corresponding to the surface roughness of a side surface of the circuit pattern.

[0268] Meanwhile, in the embodiment, the cavity is formed using a Gaussian beam. At this time, the outermost portion of the cavity is processed using the center point of the Gaussian beam. That is, the center point of the Gaussian beam generates the strongest laser, and therefore, the inclination angle of the inner wall of the cavity at the outermost portion may be smaller than that of the comparative example.

[0269] In other words, the inner wall of the cavity may have a form in which a first portion S3, a second portion S2, and a third portion S1 are connected to each other from the lower side. The first portion S3 of the cavity may be connected to an upper surface of the first insulating layer 110. For example, the first portion S3 of the cavity may be in contact with the upper surface of the first insulating layer 110. The first portion S3 of the inner wall of the cavity may have a first inclination angle. For example, the inclination angle of the first portion S3 of the cavity may be approximately perpendicular to the reference plane BS.

[0270] The second portion S2 of the cavity may have a second inclination angle θ2. For example, the second inclination angle θ2 of the second portion S2 of the cavity may refer to an inclination angle of a virtual straight line connecting one end E1 and the other end E3 of the second portion S2 with respect to a reference plane BS. The reference plane BS may be, but is not limited to, an upper surface of the first insulating layer 110, for example.

[0271] Furthermore, the third portion S1 of the cavity may have a third inclination angle θ1. For example, the third inclination angle θ1 of the third portion S1 of the cavity may be smaller than the second inclination angle θ2 of the second portion S2. The third inclination angle θ1 of the third portion S1 refers to the inclination angle of a virtual line connecting one end E2 and the other end E1 of the third portion S1.

[0272] That is, the third portion S1 of the inner wall of the cavity is a portion processed using the center point of a Gaussian beam, thereby allowing it to have a third inclination angle θ1 that is smaller than the second inclination angle θ2 of the second portion S2.

[0273] The inclination angle θ2 of the second portion S2 of the inner wall of the cavity may be in the range of 130 degrees to 160 degrees. Also, the third inclination angle θ1 of the third portion S1 of the inner wall of the cavity may be in the range of 92 degrees to 130 degrees, which is smaller than the second inclination angle θ2 of the second portion S2.

[0274] In other words, the inner wall of the cavity in the embodiment may have a plurality of inflection points, which may also be expressed as inflection sections or portions where an angle changes.

[0275] For example, the inner wall of the cavity in the embodiment may have a first inflection point E3 and a second inflection point E2.

[0276] The cavity in the embodiment may be divided into a first portion S3 having a first inclination angle centered on the first inflection point E3 and a second portion S2 having a second inclination angle θ2. Also, in the embodiment, the cavity may be divided into a second portion S2 having a second inclination angle θ2 and a third portion S1 having a third inclination angle centered on the second inflection point E2.

[0277] The first inflection point E3 may be a point where the first portion S3 and the second portion S2 of the inner wall of the cavity meet each other, and the second inflection point E2 may be a point where the second portion S2 and the third portion S1 of the inner wall of the cavity meet each other.

[0278] The height of the first inflection point E3 may correspond to the height of the circuit pattern 140. Preferably, the height of the first inflection point E3 may be the same as the height of a portion of the first circuit pattern 141 disposed on the upper surface of the first insulating layer 110. More preferably, the height of the first inflection point E3 may be the same as the height of a seed layer constituting the first circuit pattern 141.

[0279] In addition, the height of the second inflection point E2 may be located higher than the upper surface of the pad 141a.

[0280] As described above, in the embodiment, when forming the cavity, the third portion S1 of the outermost portion of the cavity has a third inclination angle θ1, the second portion S2 meeting the third portion S1 has a second inclination angle θ2, and the first portion S3 meeting the second portion S2 has a first inclination angle.

[0281] This can be achieved by laser processing the first metal layer 140a, which is a seed layer that constitutes the circuit pattern, as a stop layer to form the cavity, and then processing the outermost portion of the cavity using the center point of a Gaussian beam, thereby reducing the inclination angle of the outermost portion of the cavity compared to the comparative example, thereby significantly reducing the space required to form the cavity.

[0282] As a result, the cavity in the embodiment can include a first region including the third portion S1, a second region including the second portion S2, and a third region other than the first region.

[0283] A second portion S2 of the inner wall of the cavity corresponding to the second region may extend upward from the first portion S3 that terminates in the third region R3 of the cavity at a second inclination angle θ2.

[0284] The third portion S1 corresponding to the first region R1 may extend upward from the second portion S2 at a third inclination angle θ1.

[0285] FIG. 24 is a diagram for explaining the cavity processing method according to the third embodiment, and FIG. 25 is a diagram for explaining the cavity processing method according to the comparative example.

[0286] 24, in the embodiment, the center line of the Gaussian beam is used to process the outermost region of the cavity, and the entire region of the cavity is processed while moving the Gaussian beam a certain distance.

[0287] In this embodiment, the center line of the first Gaussian beam is used to process the outermost region of the cavity. Then, when the cavity processing using the first Gaussian beam is completed, a second Gaussian beam is provided at a position spaced a certain distance from the first Gaussian beam. In this case, by spaced apart the first Gaussian beam and the second Gaussian beam at a certain distance, the cavity in the embodiment includes a third portion S1 having a third inclination angle θ1 in the outermost region, and a second portion S2 extending from the third portion S1 and having a second inclination angle θ2.

[0288] Meanwhile, referring to FIG. 25, in the comparative example, the cavity processing process is performed such that the outer edge of the laser beam is positioned at the outermost corner of the cavity.

[0289] As a result, the inner wall of the outermost portion of the cavity in the comparative example has an inclination angle of 160 degrees or more, whereas the inner wall of the outermost portion of the cavity in the example has a third inclination angle in the range of 92 degrees to 130 degrees.

[0290] For example, in the process of the comparative example, when a cavity is processed in an area of ​​600 μm, a cavity of 500 μm is formed, which is smaller than 600 μm, due to the inclination angle of the inner wall of the cavity. This is because the lower region of the cavity is actually used as the cavity in which the element is mounted, but a space of about 100 μm is not used due to the inclination angle of the inner wall.

[0291] In contrast, in the embodiment, when a cavity is processed in an area of ​​600 μm, a cavity of 550 μm is formed compared to the comparative example due to the improvement in the inclination angle of the inner wall of the cavity. As a result, in the embodiment, the space required for cavity formation can be reduced, thereby increasing the circuit integration density.

Claims

1. A first insulating layer; a second insulating layer disposed on the first insulating layer, the second insulating layer including a cavity; a circuit pattern layer disposed between the first insulating layer and the second insulating layer; the circuit pattern layer includes an adjacent circuit pattern that is disposed adjacent to the cavity in a vertical direction without overlapping the cavity and has a stepped upper surface; The adjacent circuit pattern is a first-1 metal layer disposed on the first insulating layer and having a first width; a first-second metal layer disposed on the first-first metal layer and having a second width smaller than the first width; A part of a surface of the 1-1 metal layer perpendicular to a surface on the 1-2 metal layer side is covered with the second insulating layer, and another part of the perpendicular surface is not covered with the second insulating layer, A circuit board, wherein all of the surfaces of the 1-2 metal layer that are perpendicular to the surface on the 1-1 metal layer side are covered with the second insulating layer.

2. The 1-1 metal layer is a first portion vertically overlapping the first-second metal layer; a second portion other than the first portion, 2. The circuit board according to claim 1, wherein a surface of said second portion that is perpendicular to the surface on said first-2 metal layer side is exposed through said cavity.

3. 3. The circuit board of claim 2, wherein the second portion of the first-1 metal layer has a closed loop shape surrounding the outside of the cavity and is disposed between the first insulating layer and the second insulating layer.

4. the first-1 metal layer is a seed layer for the first-2 metal layer; 2. The circuit board according to claim 1, wherein the first-2 metal layer is an electrolytic plating layer formed using the first-1 metal layer as a seed layer.

5. an upper surface of the first portion of the first-1 metal layer directly contacts a lower surface of the first-2 metal layer; The circuit board of claim 2 , wherein an upper surface of the second portion of the first-1 metal layer is in direct contact with the second insulating layer.

6. 3. The circuit board of claim 2, wherein the second portion of the first-1 metal layer is spaced apart from the first-2 metal layer by a fixed distance.

7. The circuit pattern layer is a circuit pattern that does not vertically overlap the cavity and is spaced farther from the cavity than the adjacent circuit patterns; The circuit board according to claim 1 , wherein the upper surface of the circuit pattern has no steps.

8. 2. The circuit board according to claim 1, wherein the first-1 metal layer of the adjacent circuit pattern is disposed closer to the inner wall of the cavity than the first-2 metal layer.

9. the second insulating layer includes a 2-1 insulating layer disposed on the first insulating layer and a 2-2 insulating layer disposed on the 2-1 insulating layer; 2. The circuit board of claim 1, wherein the cavities include a first cavity penetrating the 2-1 insulating layer and a second cavity penetrating the 2-2 insulating layer.

10. The circuit board of claim 9 , wherein the first cavity and the second cavity vertically overlap and have the same width as each other.

11. The circuit board according to claim 9 , wherein an inner wall of the first cavity and an inner wall of the second cavity have a step with each other.

12. 12. The circuit board of claim 11, wherein the width of the first cavity is smaller than the width of the second cavity.

13. a second circuit pattern disposed between the 2-1 insulating layer and the 2-2 insulating layer; At least a part of a surface of the 1-1 metal layer that is perpendicular to a surface on the 1-2 metal layer side is exposed through the first cavity, The second circuit pattern is a second-1 metal layer disposed on one surface of the second-1 insulating layer; A second-2 metal layer is disposed on one surface of the second-1 metal layer, 13. The circuit board according to claim 12, wherein the width of the 2-1 metal layer is greater than the width of the 2-2 metal layer.

14. A portion of a surface of the 2-1 metal layer perpendicular to a surface on the 2-2 metal layer side is covered with the 2-2 insulating layer; Another part of the surface of the 2-1 metal layer perpendicular to the surface on the 2-2 metal layer side is not covered with the 2-2 insulating layer, 14. The circuit board according to claim 13, wherein a surface of the 2-2 metal layer perpendicular to a surface on the 2-1 metal layer side is covered with the 2-2 insulating layer.

15. The circuit board of claim 1 , wherein an inner wall of the cavity is perpendicular to an upper surface of the first insulating layer.

16. The circuit board according to claim 15 , wherein the periphery of the bottom surface of the cavity includes a plurality of straight portions and curved portions provided between the straight portions.

17. The circuit board according to claim 16 , wherein the curved portion has a constant curvature and is provided at an edge portion of the cavity.

18. 18. The circuit board according to claim 17, wherein a curvature of the edge portion of the cavity corresponds to a curvature of a circle in a range of 20 μm to 80 μm.

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