Configurable input and output blocks and physical layout for analog neural memories in deep learning artificial neural networks

Abstract

To provide an analog neural memory system and method that has an input block and an output block which are configurable and a physical layout and that uses a nonvolatile memory cell.SOLUTION: In a vector matrix multiplication (VMM) system 3400, an input circuit block 3409 (3410) supports different numbers of arrays 3401, 3402 (3403, 3404) arranged in a horizontal direction, and an output circuit block 3411 (3412) supports different numbers of arrays 3401, 3403 (3402, 3404) arranged in a vertical direction.SELECTED DRAWING: Figure 34

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 62 / 842,279, filed May 2, 2019, entitled “CONFIGURABLE INPUT BLOCKS AND OUTPUT BLOCKS AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK,” and U.S. Patent Application No. 16 / 449,201, filed June 21, 2019, entitled “CONFIGURABLE INPUT BLOCKS AND OUTPUT BLOCKS AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK.”

[0002] FIELD OF THEINVENTION Configurable input and output blocks and associated physical layouts for analog neural memory systems utilizing non-volatile memory cells are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain), and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There is typically one or more intermediate layers of neurons, and an output layer of neurons that provides the output of the neural network. At each level, the neurons make decisions, either individually or together, based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technologies. In practice, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated GPU (Graphics Processing Unit) clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses required.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application Serial No. 15 / 594,439, published as U.S. Patent Publication No. 2017 / 0337466, which is incorporated by reference. The non-volatile memory array operates as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs.

[0007] Each non-volatile memory cell used in an analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge, or number of electrons, in its floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0008] One challenge in a vector matrix multiplication (VMM) system is the ability to quickly and accurately deliver output from a VMM as input to another VMM, and to do so while efficiently utilizing physical space within a semiconductor die.

[0009] What is needed is a configurable input and output block and physical layout for an analog neural memory system that utilizes non-volatile memory cells. Summary of the Invention

[0010] Configurable input and output blocks and associated physical layouts for analog neural memory systems utilizing non-volatile memory cells are disclosed.

[0011] One embodiment of an analog neural memory system comprises a plurality of vector matrix multiplication arrays, each array including non-volatile memory cells organized into rows and columns, and an input block capable of providing inputs to a configurable number N of the vector matrix multiplication arrays, where N can range between 1 and a total number of arrays in the plurality of vector matrix multiplication arrays, the arrays receiving the inputs providing outputs in response to the inputs.

[0012] Another embodiment of an analog neural memory system comprises a plurality of vector matrix multiplication arrays, each of the plurality of vector matrix multiplication arrays including non-volatile memory cells organized into rows and columns; and an output block capable of providing outputs from a configurable number N of the plurality of vector matrix multiplication arrays, where N can range between 1 and a total number of arrays in the plurality of vector matrix multiplication arrays, the outputs being provided in response to received inputs.

[0013] Another embodiment of an analog neural memory system comprises a plurality of vector matrix multiplication arrays, each array including non-volatile memory cells organized into rows and columns, and an output block for performing a verify operation after a programming operation on a configurable number N of the vector matrix multiplication arrays, where N can range between 1 and a total number of arrays in the plurality of vector matrix multiplication arrays.

[0014] Another embodiment of an analog neural memory system comprises a plurality of vector matrix multiplication arrays, each array including non-volatile memory cells organized into rows and columns; an input block capable of providing inputs to a first configurable number N of the vector matrix multiplication arrays, where N may range between 1 and a total number of arrays in the plurality of vector matrix multiplication arrays; and an output block capable of providing outputs from a second configurable number M of the vector matrix multiplication arrays, where M may range between 1 and a total number of arrays in the plurality of vector matrix multiplication arrays, where the output block generates the outputs in response to the inputs.

[0015] Another embodiment of an analog neural memory system comprises a plurality of vector matrix multiplication arrays, each vector matrix multiplication array including non-volatile memory cells organized into rows and columns, and an output block capable of receiving output neuron currents from one or more of the vector matrix multiplication arrays and generating digital output bits using a ramp type analog-to-digital converter.

[0016] Another embodiment of an analog neural memory system comprises a plurality of vector matrix multiplication arrays, each vector matrix multiplication array including non-volatile memory cells, and an input block capable of converting a plurality of digital input bits into a binary indexed time sum signal as a timing input to at least one of the vector matrix multiplication arrays.

[0017] An embodiment of a method for performing an output conversion on an analog neural memory including a plurality of vector matrix multiplication arrays, each vector matrix multiplication array including non-volatile memory cells, includes receiving output neuron currents from one or more of the plurality of vector matrix multiplication arrays, and generating digital output bits using the output neuron currents and a ramp type analog-to-digital converter, the converter operating in a coarse comparison mode and a fine comparison mode.

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[0078] [Brief description of the drawings]

[0079] [Figure 1] FIG. 1 illustrates a prior art artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 9] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 10] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more vector-matrix multiplication systems. [Figure 11] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 14] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 15] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 16] 1 shows a prior art long-short-term memory system. [Figure 17] An exemplary cell for use in the long- and short-term memory system is shown. [Figure 18] 18 illustrates an embodiment of the exemplary cell of FIG. 17. [Figure 19] 18 illustrates an alternative embodiment of the exemplary cell of FIG. 17. [Figure 20] 1 shows a prior art gated recurrent unit system. [Figure 21]1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 22] 22 illustrates an embodiment of the exemplary cell of FIG. 21. [Diagram 23] 22 illustrates an alternative embodiment of the exemplary cell of FIG. 21. [Figure 24] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 25] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 26] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 27] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 28] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 29] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 30] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 31] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 32] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 33] 1 illustrates an example block diagram of a vector matrix multiplication system. [Diagram 34] 1 illustrates an example block diagram of a vector matrix multiplication system, where vertically adjacent arrays share an output block. [Figure 35A] 1 illustrates an example block diagram of a vector matrix multiplication system, where horizontally adjacent arrays share an input block. [Figure 35B] 1 illustrates an example block diagram of a vector matrix multiplication system, where horizontally adjacent arrays share an input block. [Diagram 36] 1 illustrates an example block diagram of a vector matrix multiplication system. [Figure 37A] 1 illustrates an embodiment of an integrated analog-to-digital converter. [Figure 37B] 37B shows an example output waveform for the system of FIG. 37A. [Figure 38] 37B illustrates an exemplary input that may be provided to the integrated analog-to-digital converter of FIG. 37A. [Figure 39] 1 illustrates an embodiment of a current-to-voltage converter. [Diagram 40] 1 shows a digital data to voltage converter. [Diagram 41] 1 illustrates a configurable analog-to-digital converter. [Diagram 42] A configurable current-voltage input circuit is shown. [Figure 43A] 1 shows a digital-to-pulse line converter. [Figure 43B] 43B shows exemplary waveforms of the digital-to-pulse row converter of FIG. 43A. [Figure 44A] 1 shows a digital-to-pulse line converter. [Figure 44B] 44B shows exemplary waveforms of the digital-to-pulse row converter of FIG. 44A. [Figure 44C] 44B shows a row digital pulse generator for use with the digital-to-pulse row converter of FIG. 44A. [Figure 45A] 1 shows a ramp type analog-to-digital converter output converter. [Figure 45B] 45B illustrates an exemplary reference voltage for use with the ramp-type analog-to-digital converter output converter of FIG. 45A. [Figure 45C] 45B illustrates an exemplary reference voltage for use with the ramp-type analog-to-digital converter output converter of FIG. 45A. [Diagram 46] An algorithmic analog-to-digital converter output converter 4600 is shown. [Figure 47A] Shows SAR ADC. [Figure 47B] 47B shows an algorithm for generating digital output bits for the SAR ADC of FIG. [Figure 48] 1 shows a sigma-delta analog-to-digital converter. [Figure 49] The calibration method is shown. [Figure 50A] A real-time calibration method is presented. [Figure 50B]1 shows a background calibration method. [Figure 51A] The calibration and conversion methods are shown. [Figure 51B] 2 illustrates another calibration and conversion method. [Figure 52] 37A-37B and 45A-45C show a comparator for optional use with the embodiments of FIGS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0080] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. Non-volatile Memory Cell

[0081] Digital non-volatile memories are well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A wordline terminal 22 (typically coupled to a wordline) has a first portion disposed above and insulated from (and controls the conductivity of) the second portion of the channel region 18, and a second portion extending upwardly over the floating gate 20. The floating gate 20 and wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0082] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0083] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electronic current flows from the source region 14 towards the drain region 16. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0084] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is detected as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is detected as the programmed or "0" state.

[0085] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. 2 [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line.

[0086] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2 with the addition of a control gate (CG) 28. The control gate 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0v / -8V) during erasure, and a low or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are biased similarly to the terminals of Figure 2.

[0087] FIG. 4 shows a four-gate memory cell 410 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0088] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of Flash Memory Cell 410 of FIG. [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line.

[0089] Figure 5 shows a memory cell 510 similar to memory cell 410 of Figure 4, except that memory cell 510 does not include an erase gate (EG). Erasing is accomplished by biasing substrate 18 to a high voltage and control gate CG28 to a low or negative voltage. Alternatively, erasure is accomplished by biasing word line 22 to a positive voltage and control gate 28 to a negative voltage. Programming and reading are similar to those of Figure 4.

[0090] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate. Erase and read operations (where erasure occurs through the use of an erase gate) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line during a program operation to compensate for the lack of control gate bias.

[0091] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 610 of FIG. [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line.

[0092] Figure 7 shows another type of flash memory cell, a stacked gate memory cell 710. Memory cell 710 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (coupled to a wordline) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, programming, and read operations operate in a similar manner as described above for memory cell 210.

[0093] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. Table 4. Operation of Flash Memory Cell 710 of FIG. [Table 4]

[0094] "Read 1" is a read mode in which the cell current is output to a bit line. "Read 2" is a read mode in which the cell current is output to a source line. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, a source line can be shared by adjacent rows of memory cells.

[0095] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0096] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog, or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), making every cell in the memory array very precisely and individually adjustable, and making the memory array ideal for storing and fine-tuning the weights of the synapses of a neural network.

[0097] The methods and means described herein can be applied to other non-volatile memory technologies, such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive RAM), PCM (phase change RAM), MRAM (magnetoresistive RAM), FeRAM (ferroelectric RAM), OTP (bi-level or multi-level one-time programmable) and CeRAM (strongly correlated electron RAM). The methods and means described herein can be applied to, but not limited to, SRAM, DRAM, and volatile memory technologies used in neural networks, such as volatile synapse cells. Neural network using non-volatile memory cell arrays

[0098] 8 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses the non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using the non-volatile memory array-based neural network.

[0099] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel being 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters of 3x3 pixels (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., called filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in the input layer S0 (i.e., add a column of 3 pixels to the right and drop a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of C1, until all feature maps of layer C1 have been calculated.

[0100] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, relationships, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify square edges, or the aspect ratio of a particular feature, etc.

[0101] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function is to average nearby positions (or a max function can be used), e.g. to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e. 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from consecutive non-overlapping 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. every neuron in layer C3 connects to every neuron in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0102] Each layer of synapses is implemented using an array or part of an array of non-volatile memory cells.

[0103] 9 is a block diagram of an array that can be used for that purpose. A vector matrix multiplication (VMM) system 32 includes non-volatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM system 32 includes an array 33 including non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37 that decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0104] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, it effectively multiplies the inputs by the weights stored in the VMM array 33 and adds them for each output line (source line or bit line) to produce an output that becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient with on-the-fly memory computations.

[0105] The outputs of the VMM array 33 are fed to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0106] The summed output values ​​of the differential summer 38 are then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other non-linear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 8) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the VMM array 33 constitutes a number of synapses (receiving input from a previous layer of neurons or from an input layer such as an image database), and the summer 38 and activation function circuit 39 constitute a number of neurons.

[0107] The inputs to the VMM system 32 of FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0108] FIG. 10 is a block diagram illustrating the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be done by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s) to the input VMM system 32a.

[0109] The output generated by the input VMM system 32a is provided as input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as input to the next VMM system (hidden level 2) 32c, and so on. The various layers of the VMM systems 32 function as various layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM systems 32a, 32b, 32c, 32d, and 32e may be a standalone physical non-volatile memory array, or the multiple VMM systems may utilize different portions of the same physical non-volatile memory array, or the multiple VMM systems may utilize overlapping portions of the same physical non-volatile memory system. Each VMM system 32a, 32b, 32c, 32d, and 32e may also be time multiplexed to various portions of its array or neurons. The example shown in FIG. 10 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may instead include more than two hidden layers and more than two fully connected layers. Furthermore, different layers may use different combinations of n-bit memory cells (different cells supporting different levels), including two-level memory cells (meaning there are only two levels, "0" and "1"). VMM Array

[0110] Figure 11 shows a neuron VMM array 1100 that is particularly suited for memory cells 310 shown in Figure 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array could be located at the bottom.

[0111] In the VMM array 1100, control gate lines such as control gate line 1103 run vertically (so that row-wise reference array 1102 is orthogonal to control gate line 1103) and erase gate lines such as erase gate line 1104 run horizontally. Here, inputs to the VMM array 1100 are provided on the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0, SL1, respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0112] As described herein for neural networks, the non-volatile memory cells of VMM array 1100, ie, the flash memory of VMM array 1100, are preferably configured to operate in the sub-threshold region.

[0113] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt where Vg is the gate voltage to the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope coefficient = 1 + (Cdep / Cox), where Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; and Io is the memory cell current at a gate voltage equal to the threshold voltage. Io is (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0114] When using an IV-log converter that uses memory cells (such as reference or peripheral memory cells) or transistors to convert the input current to an input voltage: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or periphery memory cell.

[0115] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout = (wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt where wa=w for each memory cell in the memory array.

[0116] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0117] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta * (Vgs-Vth) * Vds, beta=u * Cox * Wt / L, where Wt and L are the width and length, respectively, of the transistor. W = α(Vgs-Vth), That is, the weight W is proportional to (Vgs-Vth).

[0118] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0119] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0120] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * beta * (Vgs-Vth) 2 , beta=u * Cox * Wt / L W = α(Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0121] The word lines, control gates, or erase gates can be used as inputs for memory cells operating in the saturation region, and the bit lines or source lines can be used as outputs for output neurons.

[0122] Alternatively, the flash memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation).

[0123] Other embodiments for the VMM array 32 of Figure 9 are described in U.S. Patent Application Serial No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0124] FIG. 12 shows a neuron VMM array 1200 that is particularly suitable for the memory cells 210 shown in FIG. 2 and used as synapses between an input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 arranged in the columns of the array serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (only some of which are shown) with current inputs flowing into them. The reference cells are adjusted (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0125] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200 in each memory cell. Second, it effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which are the inputs to the next layer or the last layer. With the memory array 1203 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on bit lines BL0-BLN, respectively, during read (inference) operations. The current placed on each bit line BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0126] Table 5 shows the operating voltages for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations. Table 5. Operation of VMM Array 1200 in Figure 12 [Table 5]

[0127] FIG. 13 illustrates a neuron VMM array 1300 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of synapses and neurons between an input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 run in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1100, except that the word lines run vertically in the VMM array 1300. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current applied to each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0128] Table 6 shows the operating voltages for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1300 in FIG. 13 [Table 6]

[0129] 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of a first non-volatile reference memory cell, and a reference array 1402 of a second non-volatile reference memory cell. The reference arrays 1401 and 1402 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 to voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexers 1412 each include a respective multiplexer 1405 and cascoding transistor 1404 to ensure a constant voltage on the bit line (e.g., BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are adjusted to a target reference level.

[0130] The memory array 1403 serves two purposes. First, it stores the weights used by the VMM array 1400. Second, it effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1401 and 1402 convert to input voltages and provide to control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory cell array, and then adds all the results (cell currents) to produce an output that appears on BL0-BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient, where the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current applied to each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0131] The VMM array 1400 performs one-way conditioning of the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the precision programming techniques described below. If too much charge is added to the floating gate (such as an incorrect value being stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0132] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1400 in FIG. 14 [Table 7]

[0133] FIG. 15 shows a neuron VMM array 1500 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of synapses and neurons between an input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 or a first non-volatile reference memory cell, and a reference array 1502 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1501 and 1502 convert the input currents in terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1514) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0134] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1500 in FIG. 15 [Table 8]

[0135] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cell 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2400, the input INPUT 0 , ... , INPUT N is the bit line BL 0 , ...BL N are received and output 1 , OUTPUT 2 , OUTPUT 3 , and OUTPUT 4 is the source line SL 0 , S.L. 1 , S.L. 2 , and S.L. 3 are generated respectively.

[0136] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , INPUT 1 , INPUT 2 , and INPUT 3 is the source line SL 0 , S.L. 1 , S.L. 2 , and S.L. 3 are received and output 0 , ...OUTPUT N is the bit line BL 0 , ..., B.L. N is generated.

[0137] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the word line WL 0 , ..., W.L. M are received and output 0 , ...OUTPUT N is the bit line BL0 , ..., B.L. N is generated.

[0138] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the word line WL 0 , ..., W.L. M are received and output 0 , ...OUTPUT N is the bit line BL 0 , ..., B.L. N is generated.

[0139] 28 shows a neuron VMM array 2800 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT n are the vertical control gate lines CG 0 , ..., C.G. N Received and output OUTPUT 1 and OUTPUT 2 is the source line SL 0 and S.L. 1 is generated.

[0140] 29 shows a neuron VMM array 2900 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT N is the bit line BL 0 , ..., B.L. N , 2901-(N-1), and 2901-N, which are respectively coupled to the bit line control gates 2901-1, 2901-2, ..., 2901-(N-1), and 2901-N. 1 and OUTPUT 2 But the source line SL 0and S.L. 1 is generated.

[0141] 30 shows a neuron VMM array 3000 that is particularly suitable for the memory cells 310 shown in FIG. 3, the memory cells 510 shown in FIG. 5, and the memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the word line WL 0 , ..., W.L. M Received and output OUTPUT 0 , ..., OUTPUT N is the bit line BL 0 , ..., B.L. N are generated respectively.

[0142] 31 shows a neuron VMM array 3100 that is particularly suitable for the memory cells 310 shown in FIG. 3, the memory cells 510 shown in FIG. 5, and the memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the control gate line CG 0 , ..., C.G. M OUTPUT 0 , ..., OUTPUT N is the vertical source line SL 0 , ..., S.L. N and each source line SL i is coupled to the source line terminals of all memory cells in column i.

[0143] 32 shows a neuron VMM array 3200 that is particularly suitable for the memory cells 310 shown in FIG. 3, the memory cells 510 shown in FIG. 5, and the memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the control gate line CG 0 , ..., C.G.M OUTPUT 0 , ..., OUTPUT N is the vertical bit line BL 0 , ..., B.L. N and each bit line BL i is coupled to the bit line terminals of all memory cells in column i. Long and short term memory

[0144] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any predefined period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0145] 16 illustrates an example LSTM 1600. The LSTM 1600 in this example includes cells 1601, 1602, 1603, and 1604. Cell 1601 receives an input vector x 0 It receives the output vector h 0 and the cell state vector c 0 Cell 1602 generates the input vector x 1 and the output vector (hidden state) h from cell 1601 0 and cell state c from cell 1601 0 and outputs vector h 1 and the cell state vector c 1 Cell 1603 generates the input vector x 2 and the output vector (hidden state) h from cell 1602 1 and the cell state c from cell 1602 1 and outputs vector h 2 and the cell state vector c 2 Cell 1604 generates the input vector x3 and the output vector (hidden state) h from cell 1603 2 and cell state c from cell 1603 2 and outputs vector h 3 Additional cells can be used, the LSTM with four cells is just an example.

[0146] Figure 17 shows an example implementation of an LSTM cell 1700 that can be used for cells 1601, 1602, 1603, and 1604 in Figure 16. The LSTM cell 1700 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0147] LSTM cell 1700 includes sigmoid function devices 1701, 1702, and 1703, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1700 also includes tanh devices 1704 and 1705 for applying a hyperbolic tangent function to the input vector, multiplier devices 1706, 1707, and 1708 for multiplying two vectors, and adder device 1709 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0148] FIG. 18 shows an example of an implementation of the LSTM cell 1700, the LSTM cell 1800. For the convenience of the reader, the same numbering scheme from the LSTM cell 1700 is used in the LSTM cell 1800. The sigmoid function devices 1701, 1702, and 1703, and the tanh device 1704 each include a plurality of VMM arrays 1801 and activation circuit blocks 1802. It can therefore be seen that the VMM array is particularly useful in the LSTM cell used in certain neural network systems. The multiplier devices 1706, 1707, and 1708, and the adder device 1709 are implemented in a digital or analog manner. The activation function block 1802 can be implemented in a digital or analog manner.

[0149] An alternative example of LSTM cell 1800 (and another example of an implementation of LSTM cell 1700) is shown in Figure 19. In Figure 19, sigmoid function devices 1701, 1702, and 1703, and tanh device 1704 share the same physical hardware (VMM array 1901 and activation function block 1902) in a time-multiplexed manner. LSTM cell 1900 also includes a multiplier device 1903 for multiplying two vectors, an adder device 1908 for adding two vectors, a tanh device 1705 (which includes activation circuit block 1902), a register 1907 for storing the value i(t) output from sigmoid function block 1902, and a value f(t) output from multiplier device 1903 via multiplexer 1910. * A register 1904 stores c(t-1), and a value i(t) output from the multiplier device 1903 via a multiplexer 1910. * A register 1905 for storing u(t) and a value o(t) output from the multiplier device 1903 via a multiplexer 1910 * It includes a register 1906 and a multiplexer 1909 for storing {tilde over (c)}(t).

[0150] Whereas LSTM cell 1800 includes multiple sets of VMM arrays 1801 and respective activation function blocks 1802, LSTM cell 1900 includes only one VMM array 1901 and one set of activation function blocks 1902 that are used to represent multiple layers in embodiments of LSTM cell 1900. LSTM cell 1900 requires less space than LSTM 1800 because it requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 1800.

[0151] It can further be appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as an adder and activation circuit block and a high voltage generation block. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Gated Recurrent Unit

[0152] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0153] 20 illustrates an example GRU 2000. The GRU 2000 in this example includes cells 2001, 2002, 2003, and 2004. Cell 2001 receives an input vector x 0 It receives the output vector h 0 Cell 2002 generates the input vector x 1 and the output vector h from cell 2001 0 and outputs vector h 1 Cell 2003 generates the input vector x 2 and the output vector (hidden state) h from cell 2002 1 and outputs vector h 2Cell 2004 generates the input vector x 3 and the output vector (hidden state) h from cell 2003 2 and outputs vector h 3 Additional cells are possible, the GRU with four cells is just an example.

[0154] FIG. 21 illustrates an exemplary implementation of a GRU cell 2100 that can be used for cells 2001, 2002, 2003, and 2004 of FIG. 20. The GRU cell 2100 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). The GRU cell 2100 includes sigmoid function devices 2101 and 2102, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). The GRU cell 2100 also includes a tanh device 2103 for applying a hyperbolic tangent function to the input vector, a number of multiplier devices 2104, 2105, and 2106 for multiplying two vectors together, an adder device 2107 for adding the two vectors together, and a complementary device 2108 for subtracting the input from 1 to generate an output.

[0155] FIG. 22 shows a GRU cell 2200, which is an implementation example of the GRU cell 2100. For the convenience of the reader, the same numbering method from the GRU cell 2100 is used in the GRU cell 2200. As can be seen from FIG. 22, the sigmoid function devices 2101 and 2102 and the tanh device 2103 each include a plurality of VMM arrays 2201 and activation function blocks 2202. Therefore, it can be understood that the VMM array is particularly used in the GRU cell used in a specific neural network system. The multiplier devices 2104, 2105, 2106, the adder device 2107, and the complementary device 2108 are implemented in a digital or analog manner. The activation function block 2202 can be implemented in a digital or analog manner.

[0156] An alternative example of GRU cell 2200 (and another example implementation of GRU cell 2300) is shown in Figure 23. In Figure 23, GRU cell 2300 uses a VMM array 2301 and activation function block 2302, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In Figure 23, sigmoid function devices 2101 and 2102 and tanh device 2103 share the same physical hardware (VMM array 2301 and activation function block 2302) in a time-multiplexed manner. The GRU cell 2300 also includes a multiplier device 2303 for multiplying two vectors together, an adder device 2305 for adding the two vectors together, a complementary device 2309 for subtracting an input from one to generate an output, a multiplexer 2304, and a value h(t-1) output from the multiplier device 2303 via the multiplexer 2304. * A register 2306 holds r(t) and a value h(t-1) output from the multiplier device 2303 via a multiplexer 2304. * A register 2307 holds z(t), and a value h^(t) output from the multiplier device 2303 via a multiplexer 2304. * and a register 2308 that holds (1-z((t)).

[0157] Whereas GRU cell 2200 includes multiple sets of VMM arrays 2201 and activation function blocks 2202, GRU cell 2300 includes only one set of VMM arrays 2301 and activation function blocks 2302 that are used to represent multiple tiers in embodiments of GRU cell 2300. GRU cell 2300 requires less space than GRU cell 2200 because it requires one-third the space for the VMM and activation function blocks compared to GRU cell 2200.

[0158] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient.

[0159] The input to the VMM array can be analog levels, binary levels, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the output can be analog levels, binary levels, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0160] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, or by a differential cell, or by two blended memory cells (average of two cells). In the case of differential cells, two memory cells are required to implement weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to implement weight W as an average of two cells. A configurable I / O system for VMM arrays.

[0161] 33 shows a VMM system 3300. The VMM system 3300 includes a VMM array 3301 (which may be based on any of the VMM array designs previously described, such as VMM arrays 1100, 1200, 1300, 1400, 1500, 2400, 2500, 2600, 2700, 2800, 2900, 3000 3100, and 3200, or other VMM array designs), a low voltage row decoder 3302, a high voltage row decoder 3303, a column decoder 3304, a column driver 3305, control logic 3306, bias circuits 3307, a neuron output circuit block 3308, an input VMM circuit block 3309, an algorithm controller 3310, a high voltage generator block 3311, an analog circuit block 3315, and control logic 3316.

[0162] The input circuit block 3309 serves as an interface from an external input to the input terminal of the memory array 3301. The input circuit block 3309 may include, without limitation, a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an APC (analog-to-pulse converter), an IVC (current-to-voltage converter), an AAC (analog-to-analog converter such as a voltage-to-voltage scaler), or an FAC (frequency-to-analog converter). The neuron output block 3308 serves as an interface from the memory array output to an external interface (not shown). The neuron output block 3308 may include, without limitation, an ADC (analog-to-digital converter), an APC (analog-to-pulse converter), a DPC (digital-to-pulse converter), an IVC (current-to-voltage converter), or an IFC (current-to-frequency converter). The neuron output block 3308 may include, without limitation, an activation function, a normalization circuit, and / or a rescaling circuit.

[0163] Figure 34 shows a VMM system 3400 that includes VMM arrays 3401, 3402, 3403, and 3404, high voltage row decoders 3405 and 3406, low voltage row decoders 3407 and 3408, input blocks 3409 and 3410 (each similar to input block 3309 of Figure 33), and output blocks 3411 and 3412. In this configuration, VMM arrays 3401 and 3403 share a set of bit lines and output block 3411, and VMM arrays 3402 and 3404 share a set of bit lines and output block 3412. VMM arrays 3401 and 3403 can be read simultaneously (which can effectively be combined into a single larger array) or can be read at different times. Output blocks 3411 and 3412 (similar to output block 3308 in FIG. 33) are configurable to be able to process read operations from one array at a time (such as reading from only array 3401 or 3403) or from multiple arrays at a time (such as reading from both arrays 3401 and 3403).

[0164] FIG. 35A illustrates a VMM system 3500 that includes VMM arrays 3503, 3504, and 3505, a shared global high voltage row decoder 3506, local high voltage row decoders 3507 and 3508, a shared low voltage row decoder 3509, and an input block 3510. In this configuration, VMM arrays 3503, 3504, and 3505 share input block 3510. VMM arrays 3503, 3504, and 3505 can receive inputs (e.g., voltages or pulses on word lines, control gate lines, erase gate lines, or source lines) via input block 3510 simultaneously (effectively combining into a single larger VMM array) or can receive inputs via input block 3510 at different times (effectively operating as three separate VMM arrays with the same input block). Input block 3510 is configurable so that it can provide inputs to one array at a time or to multiple arrays at a time.

[0165] 35B illustrates a VMM system 3550 that includes VMM arrays 3511, 3512, 3513, and 3514, a global high voltage decoder 3515, local high voltage row decoders 3516, 3517, and 3518, a shared low voltage row decoder 3519, and an input block 3520. In this configuration, VMM arrays 3511, 3512, 3513, and 3514 share an input block 3520. VMM arrays 3511, 3512, 3513, and 3514 can receive inputs (e.g., voltages or pulses on word lines, control gate lines, erase gate lines, or source lines) via input block 3520 simultaneously (effectively combining into a single larger array) or can receive inputs via input block 3520 at different times (effectively operating as three separate VMM arrays with the same input block 3520). Input block 3520 is configurable to provide input to one array at a time or to multiple arrays at a time, for example, input block 3510 in Figure 35A is configured to provide input to three arrays, while input block 3520 is configured to provide input to four arrays.

[0166] 36 shows VMM system 3600, which includes horizontal set 3601 and horizontal set 3611. Horizontal set 3601 includes VMM arrays 3602 and 3603, a shared global high voltage row decoder 3604, a local high voltage row decoder 3605, a shared low voltage row decoder 3606, and an input block 3607. VMM arrays 3602 and 3603 share input block 3607. Input block 3607 is configurable so that it can provide input to one array at a time or to multiple arrays at a time.

[0167] Horizontal set 3611 includes VMM arrays 3612 and 3613, a shared global high voltage decoder 3614, a local high voltage row decoder 3615, a shared low voltage row decoder 3616, and an input block 3617. VMM arrays 3612 and 3613 share input block 3617. Input block 3617 is configurable such that it can provide input to one array at a time or to multiple arrays at a time.

[0168] In a first configuration, horizontal set 3601 utilizes output blocks 3608 and 3609, and horizontal set 3611 utilizes output blocks 3618 and 3619. Output blocks 3608, 3609, 3618, and 3619 can output a current, a digital pulse, or a digital bit as an output. In one embodiment where digital bits are output, output blocks 3608, 3609, 3618, and 3619 each output eight digital output bits.

[0169] In a second configuration, output blocks 3608 and 3609 are disabled, VMM arrays 3602 and 3612 share output block 3618, and VMM arrays 3603 and 3613 share output block 3619. VMM arrays 3602 and 3612 can be read out simultaneously, which effectively combines them into a single larger vertical array (i.e., more rows per bit line), or they can be read out at different times. When VMM arrays 3602 and 3612 are read out simultaneously, output blocks 3608 and 3609 each output a 9-bit range value, in an embodiment where each output block outputs an 8-bit range value when combined with only one array. This is due to the dynamic range of the output neurons being doubled by using the two arrays as a single larger array. In this case, the output may need to be rescaled or normalized (e.g., scaled down from 9 bits to 8 bits) if the next array only requires 8 bits of dynamic range. In another embodiment, the number of output bits can remain the same when increasing the number of vertical arrays.

[0170] Similarly, VMM arrays 3603 and 3613 may be read simultaneously (effectively combining them into a single larger array) or may be read at different times. Output blocks 3618 and 3619 are configurable so that they can handle read operations from one array at a time or from multiple arrays at once.

[0171] In VMM systems 3400, 3500, 3550, and 3600, if the system is configurable to utilize a different number of arrays with each input block and / or output block, the input or output blocks themselves must also be configurable. For example, in VMM system 3600, if output blocks 3608, 3609, 3612, and 3619 each output an 8-bit output when combined into a single array, then output blocks 3618 and 3619 each need to be configured to output a 9-bit output when combined into two arrays (e.g., arrays 3602 and 3612, and arrays 3603 and 3609, respectively). If those outputs are then provided to an input block of another VMM system, the outputs must first be normalized if the input block expects an 8-bit input rather than a 9-bit input. Numerous analog and digital techniques are known for converting an N-bit value to an M-bit value. In the above example, N would be 9 and M would be 8, but one skilled in the art would understand that N and M could be any positive integer.

[0172] Additional arrays may be coupled to the input and output blocks in VMM systems 3400, 3500, 3550, and 3600. For example, in VMM system 3400, three or more arrays may be coupled to input block 3409, three or more arrays may be coupled to input block 3410, in VMM system 3500, four or more arrays may be coupled to input block 3510, in VMM system 3550, five or more arrays may be coupled to input block 3520, and in VMM system 3600, three or more arrays may be coupled to input block 3607, three or more arrays may be coupled to input block 3617, three or more arrays may be coupled to output block 3618, and three or more arrays may be coupled to output block 3619. In these situations, the associated input and output blocks need to be further configured to accommodate the additional arrays.

[0173] The output blocks 3411 and 3412 of the VMM system 3400, as well as the output blocks 3618 and 3619, need to be configurable for a verify operation after a programming operation, and the verify operation is affected by the number of arrays connected to the output block. Furthermore, for program / erase verify (used to calibrate, meaning to generate a specific charge on the floating gate of the memory to generate a desired cell current), the precision of the output block circuitry (e.g., 10 bits) needs to be greater than the precision required for speculative read (e.g., 8 bits). For example, the verify precision is one or more bits, e.g., 1-5 bits, greater than the speculative precision. This is necessary to ensure sufficient margin between one level and the next level for, without limitation, verify result distribution, data retention drift, temperature or variation, etc.

[0174] In addition, input blocks 3409, 3410, 3510, 3520, 3607, and 3617 and output blocks 3411, 3412, 3608, 3609, 3618, and 3619 in Figures 34, 35A, 35B, and 36 need to be configurable for a calibration process since the number of arrays connected to the output blocks affects the calibration. Examples of calibration processes include processes that compensate for changes due to offsets, leakage, manufacturing processes, and temperature changes.

[0175] The next section discloses various tunable components used in the input and output blocks to allow the input and output blocks to be configured based on the number of arrays coupled to the input or output block. Input and Output Block Components

[0176] FIG. 37A shows an integrating dual mixed slope analog-to-digital converter (ADC) 3700 that can be used in output blocks such as output blocks 3411, 3412, 3608, 3609, 3618, and 3619 in FIGS. 34 and 36, and outputs an output neuron, I NEU 3706 is the output current from the VMM array received by the output block. The integrating dual mixed slope analog-to-digital converter (ADC) 3700 outputs I NEU 3706 into a series of digital to analog pulses or digital output bits. Figure 37B shows the operating waveforms of the integrating ADC 3700 of Figure 37A. Output waveforms 3710, 3711, and 3714 are for one current level. Output waveforms 3712, 3713, and 3715 are for another, higher current level. Waveforms 3710 and 3712 have pulse widths proportional to the value of the output current. Waveforms 3711 and 3713 have a number of pulses proportional to the value of the output current. Waveforms 3714 and 3715 have digital output bits proportional to the value of the output current.

[0177] In one embodiment, the ADC 3700 is NEU3706 (the analog output current received by the output block from the VMM array) into digital pulses whose width varies in proportion to the magnitude of the analog output current in the neuron output block, as shown in the example shown in Figure 38. The ADC 3700 converts I NEU 3706. Optionally, IREF 3707 has a zero temperature coefficient or NEU The initialization phase may include a bandgap filter with a temperature coefficient that tracks Vref 3706. The latter may be obtained, if desired, from a reference array containing values ​​determined during the test phase. During the initialization phase, switch 3708 is closed. Vout 3703 and the input to the negative terminal of the operational amplifier 3701 are then equal to the VREF value. Then, switch 3708 is opened and for a fixed time tref, switch S1 is closed, causing the neuron current I NEU 3706 is integrated upwards. For a fixed time tref, Vout rises and its slope changes as the neuron current changes. Then, by opening switch S1 and closing switch S2 for a period tmeas, the fixed reference current IREF is integrated downwards over a time tmeas (during which Vout falls), where tmeas is the time required to integrate Vout downwards to VREF.

[0178] The output EC 3705 is high when VOUT>VREFV and low otherwise. Thus, EC 3705 generates a pulse whose width reflects the period tmeas, and this width in turn reflects the current I NEU 3706 (pulses 3710 and 3712 in FIG. 37B).

[0179] Optionally, the output pulse EC 3705 can be converted to a train of pulses of uniform duration for transmission to a next stage circuit, such as an input block of another VMM array. At the beginning of the period tmeas, the output EC 3705 is input to an AND gate 3740 along with a reference clock 3741. The output is a pulse series 3742 (the frequency of the pulses in pulse series 3742 is the same as the frequency of clock 3741) for the period when VOUT>VREF. The number of pulses is proportional to the period tmeas, which in turn is proportional to the current I NEU 3706 (waveforms 3711 and 3713 in FIG. 37B).

[0180] Optionally, the pulse sequence 3743 can be input to a counter 3720, which counts the number of pulses in the pulse sequence 3742 and calculates the neuronal current I NEU 3706. The pulse train 3742 generates a count value 3721 that is a digital count of the number of pulses in the pulse sequence 3742 that is directly proportional to 3706. The count value 3721 comprises a set of digital bits (waveforms 3714 and 3715 in FIG. 37B).

[0181] In another embodiment, the integrating dual-slope ADC 3700 detects the neuron current I NEU 3706 can be converted into a pulse, and the width of the pulse is the neuron current I NEU 3706. This inversion can be done in digital or analog fashion and can be converted into a series of pulses or digital bits for output to subsequent circuitry.

[0182] The adjustable integrating capacitor 3702 and the adjustable reference current IREF 3707 are adjusted according to the number N of arrays connected to the integrating dual mixed slope analog-to-digital converter (ADC) 3700. For example, if N arrays are connected to the integrating dual mixed slope analog-to-digital converter (ADC) 3700, then the adjustable integrating capacitor 3702 is adjusted by 1 / N or the adjustable reference current IREF 3707 is adjusted by N.

[0183] Optionally, a calibration step can be performed while the VMM array and ADC 3700 are at or above operating temperature to offset any leakage current present in the VMM array or control circuitry, and then that offset value can be subtracted from Ineu in Figure 37A. A calibration step can also be performed to compensate for process or voltage supply variations in addition to temperature variations.

[0184] The method of operation of the output circuit block includes first performing a calibration for offset and voltage supply variation compensation. Next, an output conversion is performed (such as converting neuron currents to pulses or digital bits), followed by data normalization to match the output range to the input range of the next VMM array. Data normalization may include data compression or output data quantization (such as reducing the number of bits from 10 bits to 8 bits, for example). Activation may be performed after output conversion or after data normalization, compression, or quantization. Examples of calibration algorithms are described below with reference to Figures 49, 50A, 50B, and 51.

[0185] Figure 39 shows a current-to-voltage converter 3900 that can optionally be used to convert neuron output currents to a voltage that can be applied, for example, as an input (e.g., on the WL or CG lines) of a VMM memory array. Thus, the current-to-voltage converter 3900 can be used in input blocks 3409, 3410, 3510, 3520, 3607, and 3617 of Figures 34, 35A, 35B, and 36 when those blocks are receiving analog currents (as opposed to pulses or digital data) as inputs.

[0186] The current-to-voltage converter 3900 includes an operational amplifier 3901, an adjustable capacitor 3902, a switch 3903, a switch 3904, and a current source 3905, which represents the neuron current INEU received by the input block. During current-to-voltage operation, switch 3903 is open and switch 3904 is closed. The output Vout increases in amplitude in proportion to the magnitude of the neuron current INEU 3905.

[0187] FIG. 40 shows a digital data to voltage converter 4000 that can be optionally used to convert digital data received as signal DIN to a voltage that can be applied, for example, as an input (e.g., on a WL or CG line) of a VMM memory array. When switch 4002 is closed, the data input of signal DIN allows IREF_u reference current 4001 to enter capacitor 4003 and generate a voltage at its terminal. Thus, digital data to voltage converter 4000 can be used in input blocks 3409, 3410, 3510, 3520, 3607, and 3617 of FIGS. 34, 35A, 35B, and 36 when those blocks are receiving digital data (as opposed to pulses or analog currents) as input. Additionally, digital data to voltage converter 4000 can be configured to allow digital data received at the input as signal DIN to flow directly to output OUT by opening switches 4002 and 4004 and closing switch 4005. Thus, switches 4002, 4004 and 4005 are configured to allow output OUT to either receive the voltage on capacitor 4003 or directly receive the digital data received as signal DIN, which in the embodiment shown is received as a data pulse.

[0188] The digital data to voltage pulse converter 4000 includes an adjustable reference current 4001, a switch 4002, a variable capacitor 4003, a switch 4004, and a switch 4005. The adjustable reference current 4001 and the variable capacitor 4003 can be configured to have different values ​​to adjust for differences in the size of the array to which the digital data to voltage pulse converter 4000 is attached. In operation, the digital data controls the switch 4002 such that whenever the digital data is high, the switch 4002 closes. When the switch is closed, the adjustable reference current 4001 charges the variable capacitor 4003. The switch 4004 is closed whenever it is desired to provide an output at node OUT, such as when the array is ready to be read. Alternatively, the switch 4004 can be opened and the switch 4005 closed to pass the data input as the output.

[0189] 41 shows a configurable analog-to-digital converter 4100 that can be optionally used to convert analog neuron currents to digital data. The configurable analog-to-digital converter 4100 can be used in output blocks such as output blocks 3411, 3412, 3608, 3609, 3618, and 3619 in FIGS. 34 and 36, and outputs an output neuron, I NEU 4101 is the output current received by the output block.

[0190] The configurable analog-to-digital converter 4100 includes a current source 4101, a variable resistor 4102, and an analog-to-digital converter 4103. A current INEU 4101 drops across a variable resistor Rneu 4102 to produce a voltage Vneu=Ineu * The ADC 4103 (such as, without limitation, an integrating ADC, a SAR ADC, a flash ADC, or a sigma-delta ADC) converts this voltage into digital bits.

[0191] FIG. 42 shows a configurable current-to-voltage converter 4200 that can be optionally used to convert analog neuron currents to voltages that can be applied as inputs (e.g., on WL or CG lines) of a VMM memory array. Thus, the configurable current-to-voltage converter 4200 can be used in input blocks 3409, 3410, 3510, 3520, 3607, and 3617 of FIGS. 34, 35A, 35B, and 36 when those blocks are receiving analog currents (as opposed to pulses or digital data) as inputs. The configurable current-to-voltage converter 4200 includes an adjustable resistor Rin 4202 that receives an input current Iin 4201 (which is the received input current described above) and converts it to Vin 4203 (=Iin * Rin).

[0192] 43A and 43B show a digital bit to pulse width converter 4300 for use in an input block, a row decoder, or an output block. The pulse width output from the digital bit to pulse width converter 4300 is proportional to the value of the digital bit.

[0193] The digital bit-to-pulse width converter includes a binary counter 4301. The state Q[N:0] of the binary counter 4301 can be loaded by serial or parallel data in a load sequence. The row control logic 4310 outputs a voltage pulse WLEN having a pulse width proportional to the value of a digital data input provided from a block such as the integrating ADC of FIG.

[0194] 43B shows a waveform of the output pulse width, which is proportional to the digital bit value. First, the data in the received digital bits is inverted and the inverted digital bits are loaded either serially or in parallel into counter 4301. The row pulse width is then generated by row control logic 4310 as shown in waveform 4320 by counting in a binary manner until a maximum counter value is reached.

[0195] An example of using a 4-bit value for DIN is shown in Table 9. Table 9: Digital Input Bits to Output Pulse Width [Table 9]

[0196] Optionally, a pulse sequence-to-pulse converter can be used to convert the output containing the pulse sequence into a single pulse whose width varies proportionally to the number of pulses in the pulse sequence and used as an input to the VMM array to be applied to a word line or control gate in the VMM array. An example of a pulse sequence-to-pulse converter is a binary counter with control logic.

[0197] Another embodiment utilizes an up binary counter and digital compare logic: the output pulse width is generated by counting using an up binary counter until the digital output of the binary counter is the same as the digital input bit.

[0198] Another embodiment utilizes a down binary counter. The down binary counter is first loaded, either serially or in parallel, with the digital data input pattern. The output pulse width is then generated by counting down the down binary counter until the digital output of the binary counter reaches a minimum value, i.e., a "0" logic state.

[0199] FIG. 44A shows a digital data to pulse row converter 4400 including binary indexed pulse stages 4401-i, where i ranges from 0 to N (i.e., the least significant bit, LSB, to the most significant bit, MSB). The row converter 4400 is used to provide row inputs to the array. Each stage 4401-i includes a latch 4402-i, a switch 4403-i, and a row digital binary indexed pulse input 4404-i (RDIN_Ti). For example, the binary indexed pulse input 4404-0 (RDIN_T0) is latched for one time unit, i.e., 1 *The binary indexed pulse input 4404-1 (RDIN_T1) has a pulse width equal to 2 time units, i.e., 2 * The binary indexed pulse input 4404-2 (RDIN_T2) has a pulse width equal to 4 time units, i.e., 4 * The binary indexed pulse input 4403-3 (RDIN_T3) has a pulse width equal to 8 time units, i.e., 8 * The digital data of the pattern DINi (from the neuron output) of each row is stored in the latch 4402-i. When the output Qi of the latch 4402-i is "1", the binary indexed pulse input 4404-i (RDIN_Ti) is transferred to the time summing converter node 4408 via the switch 4403-i. Each time summing converter node 4408 is connected to a respective input of a NAND gate 4404, the output of which generates the row converter output WLIN / CGIN 4409 via a level shifting inverter 4405. The time summing converter node 4408 sequentially sums the binary indexed pulse inputs 4404-i in time according to a common clocking signal CLK. This is because the binary index pulse inputs 4404-i (RDIN_Ti) are enabled one digital bit at a time sequentially, for example, from LSB to MSB, or from MSB to LSB, or in any random bit pattern.

[0200] 44B illustrates an example waveform 4420, which shows example signals for row digital binary indexing pulse inputs 4404-i, specifically 4404-0, 4404-1, 4404-2, and 4404-3, as well as example outputs from level shifting inverter 4405, labeled as WL0 and WL3, which are generated from the circuitry of row converter 4400. In this example, WL0 is generated by the row decoder's row digital inputs 4403-0 and 4403-3 being asserted (WL0:Q0="1", Q3="1"), and WL3 is generated by the row decoder's row digital inputs 4403-1 and 4403-2 being asserted (WL3:Q1="1", Q2="1"). If none of the row digital inputs 4403-x are asserted, then there is no pulse on WL0 or WL3 (the control logic for this case is not shown in FIG. 44A). The inputs from other rows of the digital-to-pulse row converter 4400, i.e., the other inputs to NAND gate 4404, are assumed high during this period.

[0201] FIG. 44C shows a row digital pulse generator 4410 that generates a row digital binary indexing pulse input 4403-i (RDIN_Ti), the width of the pulse being proportional to the binary value of the digital bit, as described above in connection with FIG. 44A.

[0202] FIG. 45A shows a ramp-type analog-to-digital converter 4400, which includes a current source 4401 (representing the received neuron current Ineu), a switch 4402, a variable configurable capacitor 4403, and a comparator 4404, which receives as a non-inverting input the voltage developed across the variable configurable capacitor 4403, denoted Vneu, and as an inverting input a configurable reference voltage Vreframp, and generates an output Cout. Vreframp is raised by a discrete level every comparison clock cycle. The comparator 4404 compares Vneu with Vreframp, resulting in an output Cout that is "1" if Vneu>Vreframp and "0" otherwise. Thus, the output Cout is a pulse whose width varies according to Ineu. A larger Ineu makes Cout "1" for a longer period, resulting in an increase in the width of the pulse of the output Cout. A digital counter 4420 converts each pulse of the output Cout into a digital output bit as shown in FIG. 45B for two different Ineu currents, denoted OT1A and OT2A, respectively. Alternatively, the ramp voltage Vreframp is a continuous ramp voltage 4455 as shown in graph 4450 of FIG. 45B. A multi-ramp embodiment is shown in FIG. 45C to reduce the conversion time by utilizing a coarse-fine ramp conversion algorithm. First, the coarse reference ramp reference voltage 4471 is rapidly ramped up to find each Ineu sub-range. Then, the fine reference ramp reference voltages 4472, Vreframp1 and Vreframp2, are used for each sub-range to convert the Ineu current in the corresponding sub-range, respectively. As shown, there are two sub-ranges for the fine reference ramp voltage. More than two coarse / fine steps or two sub-ranges are possible.

[0203] FIG. 52 illustrates a comparator 5200 that is optionally used in place of comparators 3704 and 4404 of FIG. 37A and FIG. 45A. Comparator 5200 may be a static comparator (not necessarily utilizing a clock signal) or a dynamic comparator (utilizing a comparison clock signal). If comparator 5200 is a dynamic comparator, it may include a clocked cross-coupled inverter comparator, a StrongARM comparator, or other known dynamic comparators. Comparator 5200 operates as a coarse comparator when coarse enable 5203 is asserted, and comparator 5200 operates as a fine comparator when fine enable 5204 is asserted. Select signal 5206 may be optionally used to indicate a coarse comparator mode or a fine enable mode, or may be optionally used to configure comparator 5200 to operate as a static comparator or a dynamic comparator. When the comparator 5200 functions as a dynamic comparator, the comparator 5200 receives a clock signal 5205. When operating as a dynamic comparator, the comparison clock signal 5205 is a first clock signal with a first frequency when the comparator is a coarse comparator, and the clock signal 5205 is a second clock signal with a second frequency greater than the first frequency when the comparator is a fine comparator. When the comparator 5200 is operated as a coarse comparator, it has lower accuracy and slower speed, but uses less power compared to the situation where the comparator 5200 operates as a fine comparator. Thus, a dynamic comparator used for coarse comparison may utilize a slower comparison clock, while a dynamic comparator used for fine comparison may utilize a faster comparison clock during conversion ramping.

[0204] Comparator 5200, similar to comparators 3704 and 4404 in Figures 37A and 45A, compares array output 5201 against a reference voltage 5202 to generate output 5205. When comparator 5200 is operating as a coarse comparator, reference voltage 5202 can be an offset voltage.

[0205]

[0206] During the conversion period to generate the digital output bits as shown in Figures 37B and 45B / 45C, the comparator 5200 can function as a coarse comparator and a fine comparator during the coarse comparison period and the fine comparison period, respectively. At the start of this digital output bit conversion, a fine comparison period or a hybrid coarse-fine comparison period (coarse comparison in parallel with fine comparison) is performed for a certain period of time. Next, a coarse comparison period is performed, and then finally a fine comparison is performed to complete the conversion.

[0207] 46 shows an algorithmic analog-to-digital output converter 4600 including a switch 4601, a switch 4602, a sample and hold (S / H) circuit 4603, a 1-bit analog-to-digital converter (ADC) 4604, a 1-bit digital-to-analog converter (DAC) 4605, a summer 4606, and a gain of 2 residue opamp (2x opamp) 4607. The algorithmic analog-to-digital output converter 4600 has an analog input Vin, and a switch 4602. 1and generates a converted digital output 4608 in response to a control signal applied to 4602. An input received at an analog input Vin (e.g., Vneu in FIG. 45A) is first sampled by the S / H circuit 4603 via the switch 4602, and then a conversion is performed in N clock cycles for N bits. Every conversion clock cycle, the 1-bit ADC 4604 compares the S / H voltage 4609 with a reference voltage (e.g., VREF / 2, where VREF is the full-scale voltage for the N bits) and outputs a digital bit (e.g., “0” if input<=VREF / 2, and “1” if input>VREF / 2). This digital bit, which is the digital output signal 4608, is then converted to an analog voltage (e.g., either VREF / 2 or 0V) by the 1-bit DAC 4605 and fed to the adder 4606 to be subtracted from the S / H voltage 4609. The 2× residue opamp 4607 then amplifies the summer difference voltage output to a converted residue voltage 4610, which is provided to the S / H circuit 4603 via switch 4601 for the next clock cycle. To reduce the effects of offsets such as from the ADC 4604 and the residue opamp 4607, a 1.5-bit (i.e., 3-level) algorithmic ADC can be used instead of this 1-bit (i.e., 2-level) algorithmic ADC. A 1.5-bit or 2-bit (i.e., 4-level) DAC is required for the 1.5-bit algorithmic ADC.

[0208] FIG. 47A shows a successive approximation (SAR) analog-to-digital converter 4700 applied to an output neuron to convert the cell current representing the output neuron into a digital output bit. The SAR ADC 4700 includes a SAR 4701, a digital-to-analog converter 4702, and a comparator 4703. The cell current can be dropped across a resistor to generate a voltage VCELL, which is applied to the inverting input of the comparator 4703. Alternatively, the cell current can charge a sample-and-hold capacitor to generate a voltage VCELL (such as Vneu as shown in FIG. 45A). A binary search is then used by the SAR 4701 to calculate each bit from the MSB bit (most significant bit) to the LSB bit (least significant bit). A DAC 4702 is used to set the appropriate analog reference voltage to the comparator 4703 based on the digital bits (DN-D0) from the SAR 4701. The output of the comparator 4703 is then fed back to the SAR 4701 to select the next analog level of the analog reference voltage for the comparator 4703. As shown in FIG. 47B, in the example of a four-bit digital output bit, there are four evaluation periods. The first pulse evaluates DOUT3 by setting the analog level of the analog reference voltage for the comparator 4703 to the midpoint of the range, and then the second pulse evaluates DOUT2 by setting the analog level of the analog reference voltage for the comparator 4703 halfway between the midpoint of the range and the maximum point of the range, or halfway between the midpoint of the range and the minimum point of the range. This is followed by further steps, each step further refining the analog reference voltage level for the comparator 4703. The successive outputs of the SAR 4701 are the output digital bits. An alternative SAR ADC circuit is a switched capacitor (SC) circuit with only one reference level and a local SC ratio that continuously generates ratio reference levels for successive comparisons.

[0209] FIG. 48 shows a sigma-delta analog-to-digital converter 4800 applied to an output neuron to convert the cell current 4806 (ICELL or Ineu) to a digital output bit 4807. An integrator including an opamp 4801 and a configurable capacitor 4805 (Cint) integrates the sum of a current from the cell current 4806 and a configurable reference current obtained from a 1-bit current DAC 4804 that converts the digital output 4807 to a current. A comparator 4802 compares the integrated output voltage Vint from the comparator 4801 to a reference voltage VREF2, and the output of the comparator 4802 is fed to a D input of a clocked DFF 4803. The clocked DFF 4803 provides a digital output stream 4807 according to the output of the comparator 4802. The digital output stream 4807 may be fed to a digital filter before being output as a digital output bit 4807. The clock period of the clocked DFF 4803 is configurable for different Ineu ranges.

[0210] Calibration methods 4900, 5010 5020, and 5100 are now described with reference to Fig. 49, Fig. 50A, Fig. 50B, and Fig. 51, respectively. Methods 4900, 5010, 5020, and 5100 compensate for leakage and / or offset. The leakage may include one or more of array leakage and circuit leakage. The array leakage may include one or more of memory cell leakage and leakage from one or more of the decoding circuitry and the column write circuitry. The offset may include one or more of the array offset and the circuit offset. The array offset may include an offset from array variations due to one or more of the memory cell capacitance and the cell junction capacitance. The circuit offset may include an offset from one or more of the decoding circuitry and the column write circuitry.

[0211] FIG. 49 shows a calibration method 4900 for compensating for leakage and / or offset. A leakage and / or offset calibration step is performed (step 4901). The leakage and / or offset is measured and the measured amount is stored as leakage_value and / or offset_value (step 4902). The LSB is determined using the following formula: LSB=leakage_value and / or offset_value+deltaLmin. Optionally, deltaLMin is a current value that compensates for variations between levels due to process, temperature, noise, or use degradation and ensures that the separation between levels is sufficient. deltaLmin can optionally be determined from sample data characterization. (step 4903). The MSB is determined using the following formula: MSB=LSB+(N-1). * deltaL, where N is the number of levels, is a delta level amount equal to the average or ideal difference between two consecutive levels. (Step 4904). In one embodiment, DeltaL is equal to the LSB. In another embodiment, DeltaL is determined from sample data characterization. DeltaL may have uniform or non-uniform values ​​for different pairs of consecutive levels.

[0212] For example, for a 6-bit memory cell, there are 64 levels of current, each associated with a weight in a neural network application, where N = 64. A minimum offset current may be injected at this step during the calibration and measurement steps to create a baseline value.

[0213] Table 10 shows example values ​​for a 4-bit cell. Table 10: Example levels for a 4-bit cell (16 levels): [Table 10]

[0214] 50A and 50B show a calibration method 5000 that includes one or more of a real-time calibration method 5010 and a background calibration method 5020.

[0215] In the real-time calibration method 5010, a leakage and / or offset calibration is performed (step 5011), which includes measuring the leakage and / or offset and storing the measured values ​​as leakage_value and / or offset_value. The LSB is determined using the following formula: LSB level = leakage_value and / or offset_value + deltaLmin. (step 5012). The MSB is determined using the following formula: MSB = LSB + (N-1). * deltaL, where N is the number of levels (step 5013). The explanation of deltaLmin and deltaL with respect to Figure 49 applies equally to Figure 50A. A numerical example is as follows: leakage and offset = 200pA, deltaLmin = 300pA, LSB = 500pA, deltaL = 400pA, MSB = 500pA + (16-1) when N = 16. * 400pA=6500pA.

[0216] In the background calibration method 5020, the offset_value and / or leakage_value plus temperature data are stored in a fuse (e.g., a lookup table of offset and / or leakage vs. temperature) (step 5021). This is done once or periodically in a background calibration step. The offset_value and / or leakage_value plus temperature data are recalled (step 5022). A temperature adjustment to the offset_value and / or leakage_value is performed according to a lookup table or by device transistor equation (step 5023). The LSB is then determined using the following formula: LSB level=offset_value and / or leakage_value+deltaLmin (step 5024). The MSB is determined using the following formula: MSB=LSB+(N-1) *deltaL (step 5025). The discussion of deltaLmin and deltaL with respect to Figure 49 applies equally to Figure 50B. The temperature adjustment can be done by lookup table or extrapolated from the device equations (e.g., subthreshold, linear, or saturation equations).

[0217] 51A shows a calibration and conversion method 5100 with automatic cancellation of leakage and / or offset. Leakage and / or offset calibration is performed (step 5101). The leakage and / or offset is measured, such as by ADC conversion, and the measured digital output is stored in a counter (step 5102). Conversion of the neuron output is enabled, the counter counts down until it reaches zero (thereby compensating for the leakage and / or offset originally stored in the counter), and then the digital output bits are counted up (step 5103).

[0218] 51B shows a calibration and conversion method 5110 with automatic cancellation of leakage and / or offset, which is a variation of method 5100. Leakage and / or offset calibration is performed (step 5111). The leakage and / or offset is measured, such as by ADC conversion, and the measured digital output is stored in a register (step 5112). Conversion of the neuron output is enabled, and a count-up is performed on the digital output bits, and then the stored digital output is subtracted (step 5113).

[0219] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly on" (with no intermediate material, element, or gap disposed between them) and "indirectly on" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached to" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled to" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above a substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. A method for performing an output transform on an analog neural memory including a plurality of vector matrix multiplication arrays, each vector matrix multiplication array including non-volatile memory cells, the method comprising: receiving output neuron currents from one or more of the plurality of vector matrix multiplication arrays; generating digital output bits using the output neuron currents and a ramp type analog-to-digital converter, the converter operating in a coarse comparison mode and a fine comparison mode.

2. The method of claim 1 , wherein the generating step utilizes a dynamic comparator.

3. The method of claim 2 , wherein the dynamic comparator is configured differently for the coarse comparison mode and the fine comparison mode.

4. 4. The method of claim 3, wherein the dynamic comparator receives a first comparison clock for a coarse comparison mode and a second comparison clock for the fine comparison mode, the frequency of the second comparison clock exceeding the frequency of the first comparison clock.

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