Power supply for driving the synchronous rectifier element of a SEPIC converter

Abstract

The present invention stably supplies a power source for driving a DC-DC converter including a synchronous rectification-type SEPIC circuit. A synchronous rectification-type SEPIC circuit 1, including inductors 2, 5, a switch element 3, a capacitor 4, a synchronous rectification element 6, and an output capacitor 7, is provided with a drive voltage switching unit 15 for stably supplying a drive signal voltage of the synchronous rectification element 6 regardless of whether an output voltage Vo is greater or less than a drive power voltage Vdrv of the synchronous rectification element 6. The drive voltage switching unit 15 is characterized by including a means for: switching connection so that power is supplied from the output voltage Vo to a second drive circuit 10 if the output voltage Vo is set higher than the drive power voltage Vdrv; and switching connection so that power is supplied from the drive voltage Vdrv if the output voltage Vo is set lower than the drive voltage Vdrv.

Description

[Technical field]

[0001] The present invention relates to a DC / DC converter configured as a SEPIC circuit. [Background technology]

[0002] A buck-boost converter is used as a means for generating a stable output voltage from an unstable input power source such as an automobile battery. To prevent unnecessary battery consumption, it is necessary to increase the efficiency of the power supply circuit. As shown in Fig. 10, Patent Documents 1 and 2 disclose a DC-DC converter configured with a synchronous rectification type SEPIC circuit that achieves loss reduction by using a P-channel MOSFET as a rectification means. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Publication JP5937442 [Patent Document 2] Publication US7,352,158 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the power supply voltage for the P-channel MOSFET drive circuit is supplied from the drive voltage Vdrv, so that the synchronous rectification P-channel MOSFET can be turned on and off when the output voltage Vo is lower than the drive voltage Vdrv, as shown in FIG. 11(1). However, as shown in FIG. 11(2), when the output voltage Vo is set higher than the drive voltage Vdrv, the first drive signal switches from low to high at the timing of T2b and exceeds the threshold value Vth_Nch of the N-channel MOSFET 3, so that the N-channel MOSFET 3 switches from off to on. On the other hand, the second drive signal switches from low to high, but does not exceed the threshold value Vth_Pch (GND reference) of the P-channel MOSFET 6, so that the P-channel MOSFET 6 does not switch from on to off. As a result, a current flows back from the output voltage Vo terminal to GND via the PchMOSFET 6 and the second inductor 5, and the output voltage Vo cannot rise higher than the drive voltage Vdrv. This causes a problem that the setting of the output voltage Vo must be limited to be lower than the drive voltage Vdrv. Patent Document 2 discloses a configuration in which the drive voltage for a synchronous rectification P-channel MOSFET is supplied between the output voltage and GND, which simplifies the drive circuit for the synchronous rectification P-channel MOSFET and generates an output voltage Vo higher than the drive voltage of the drive circuit. However, since the off drive side of the output stage circuit of the drive means for the synchronous rectification P-channel MOSFET is composed of a resistor, it is difficult to quickly discharge the gate-source capacitance Cgs of the synchronous rectification P-channel MOSFET, and there is a problem that it is difficult to support high-speed switching operations, for example at 2 MHz or higher, required for in-vehicle applications. Moreover, the gate-source capacitance Cgs tends to increase as the on-resistance value of the P-channel MOSFET decreases. Therefore, when a large output current is supplied, the gate-source capacitance Cgs becomes large and the switching loss increases. Even if the gate resistance is reduced to speed up the switching operation, the loss in the gate resistance becomes excessive, making high-speed switching operation difficult.

[0005] Here, even if a general driver IC (with an output stage in a push-pull configuration made up of a combination of a P-channel MOSFET and an N-channel MOSFET) is used as the driving means, a problem occurs in that a sufficient driving voltage cannot be supplied when the output voltage setting value exceeds the power supply voltage value of the driver IC, making it impossible to turn off the P-channel MOSFET.

[0006] In view of the above problems, an object of the present invention is to provide a drive power supply that can control a synchronous rectification P-channel MOSFET in a SEPIC circuit regardless of the output voltage setting range. [Means for solving the problem]

[0007] In order to solve the above problems, according to one aspect of the present invention, a DC-DC converter which is a synchronous rectification type SEPIC is provided with a drive voltage switching means for a drive circuit for driving a synchronous rectification MOS transistor, and the drive voltage switching means is characterized in that when a drive voltage for supplying power to the drive circuit is set lower than an output voltage, the drive voltage switching means switches a connection to the drive circuit so that power is supplied to the drive circuit from the output voltage, and when the drive voltage for supplying power to the drive circuit is set higher than the output voltage, the drive voltage switching means switches a connection to supply power from the drive voltage. Effect of the Invention

[0008] According to the present invention, by switching to and connecting the higher of the drive voltage and the output voltage, it is possible to secure a power supply for driving the synchronous rectification MOS transistor, thereby reliably driving the P-channel MOSFET off. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a DC / DC converter configured with a SEPIC circuit according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing a first drive signal and a second drive signal based on the voltage magnitude relationship between the drive voltage and the output voltage in the first embodiment of the present invention shown in FIG. [Diagram 3] FIG. 3 is a diagram showing a DC / DC converter configured with a SEPIC circuit according to a second embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing a DC / DC converter configured with a SEPIC circuit according to a third embodiment of the present invention. [Diagram 5] FIG. 5 is a diagram showing a DC / DC converter configured with a SEPIC circuit according to a fourth embodiment of the present invention. [Figure 6] FIG. 6 is a diagram showing the first drive signal and the second drive signal when the output voltage Vo is higher than the drive voltage Vdrv in the fourth embodiment of the present invention shown in FIG. [Figure 7] FIG. 7 is a diagram showing operational waveforms of each part when the output voltage Vo is higher than the drive voltage Vdrv in the fourth embodiment of the present invention shown in FIG. [Figure 8] FIG. 8 is a diagram showing a DC / DC converter configured with a SEPIC circuit according to a fifth embodiment of the present invention. [Figure 9] FIG. 9 is a diagram showing a DC / DC converter configured with a SEPIC circuit according to a sixth embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing a prior art SEPIC circuit. [Figure 11] FIG. 11 is a diagram showing a first drive signal and a second drive signal based on the voltage magnitude relationship between the drive voltage and the output voltage in the conventional technology shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Embodiment 1) The first embodiment in FIG. 1 is composed of a first inductor 2, an N-channel MOSFET 3, a coupling capacitor 4, a second inductor 5, a P-channel MOSFET 6, an output capacitor 7, an output load 8, a first driving means 9, a second driving means 10, an AD converter 11, a subtractor 12, a filter calculation means 13, a PWM signal generating means 14, and a driving voltage switching unit 15. Moreover, the drive voltage switching unit 15 is composed of a switch means 16, a switch means 17, and a voltage switching control means 18, and the voltage switching control means 18 compares the output voltage Vo with the drive voltage Vdrv, and when the output voltage Vo is lower than the drive voltage Vdrv, turns on the switch means 16 and turns off the switch means 17. As a result, the second drive means 10 drives the P-channel MOSFET 6 with the drive voltage Vdrv. Moreover, when the output voltage Vo exceeds the drive voltage Vdrv, the switch means 16 is turned off and the switch means 17 is turned on, so that the second drive means 10 drives the P-channel MOSFET 4 with the output voltage Vo. A drive voltage Vdrv is supplied to the power supply terminal of the first drive means 1, and the first drive means 1 drives the N-channel MOSFET 3 based on the first PWM signal output from the PWM signal generation means. Since the source of the N-channel MOSFET 3 is connected to the GND side, the gate threshold voltage Vth_Nch is not affected by the output voltage Vo. A drive voltage Vdrv or an output voltage Vo is supplied to a power supply terminal of the second drive means 10 via a drive voltage switching unit 15, and drives the P-channel MOSFET 6 based on the second PWM signal. During the period when the N-channel MOSFET 3 is on and the P-channel MOSFET 6 is off, energy is excited into the first inductor 2 and the second inductor 5, and during the period when the N-channel MOSFET 3 is off and the P-channel MOSFET 6 is on, the excited energy is supplied to the output capacitor 7 and the output load 8, thereby generating an output voltage Vo. The AD converter 11 detects the output voltage Vo, converts it into a digital value with a predetermined number of bits, and outputs the converted digital value to the subtractor 12 . The subtractor 12 generates a difference value between the output target value and the digitally converted value, and outputs it to the filter calculation means 13. The filter calculation means 13 performs PI or PID calculation based on the difference value, and outputs the calculated value to the PWM signal generation means 14. The PWM signal generating means 14 generates a first PWM signal having a duty corresponding to the calculated value, and a second PWM signal.

[0011] Next, the overall operation will be described in detail with reference to the timing chart of FIG. 2, which shows the first drive signal and the second drive signal according to the voltage magnitude relationship between the drive voltage and the output voltage. Here, it is assumed that approximately the same inductor value is selected for the first inductor 2 and the second inductor 5. When the output voltage Vo is set to be lower than the drive voltage Vdrv, the drive voltage Vdrv is supplied as the power supply voltage for the first drive means 9, and the drive voltage Vdrv is supplied as the power supply voltage for the second drive means 10 via the switch means 16 of the drive voltage switching unit 15. At timing T1a, the first drive signal switches from High to Low, falling below the threshold Vth_Nch of the N-channel MOSFET 2, so that the N-channel MOSFET 2 switches from ON to OFF. Also, the second drive signal switches from High to Low, falling below the threshold Vth_Pch (GND reference) of the P-channel MOSFET 6, so that the P-channel MOSFET 4 switches from OFF to ON. At timing T2a, the first drive signal switches from low to high and exceeds the threshold Vth_Nch of the N-channel MOSFET 3, so that the N-channel MOSFET 3 switches from off to on. Also, the second drive signal switches from low to high and exceeds the threshold Vth_Pch (with respect to GND) of the P-channel MOSFET 6, so that the P-channel MOSFET 6 switches from on to off. On the other hand, when the output voltage Vo is set to a value higher than the drive voltage Vdrv, the power supply voltage of the first drive means is supplied with the drive voltage Vdrv, and the power supply voltage of the second drive means 10 is supplied with the output voltage Vo via the switch means 17 of the drive voltage switching unit 15. At timing T1b, the first drive signal switches from High to Low, falling below the threshold Vth_Nch of the N-channel MOSFET 3, so that the N-channel MOSFET 3 switches from ON to OFF. Also, the second drive signal switches from High to Low, falling below the threshold Vth_Pch (GND reference) of the P-channel MOSFET 6, so that the P-channel MOSFET 6 switches from OFF to ON. At timing T2b, the first drive signal switches from low to high and exceeds the threshold value Vth_Nch of the N-channel MOSFET 2, so that the N-channel MOSFET 2 switches from off to on. Also, the second drive signal switches from low to high and exceeds the threshold value Vth_Pch (with respect to GND) of the P-channel MOSFET 6, so that the P-channel MOSFET 6 switches from on to off. In this way, in comparison with the prior art 1, since an optimum power supply voltage can be supplied to the second driving means regardless of the output voltage value, a highly efficient power supply circuit can be configured over a wide output voltage range. In addition, compared to Prior Art 2, the second driving means can use a general driver IC with a push-pull output in which the output stage circuit is configured with a combination of a P-channel MOSFET and an N-channel MOSFET, making it possible to support high-speed operation and switching operations of 2 MHz or more required for automotive applications. It is also possible to reduce costs by integrating the second driving means 10 and the driving voltage switching means 15 on the same semiconductor substrate. Furthermore, if the inductors 2 and 5 are made of an element made of a single core material, the effects of integration and cost reduction can be further achieved.

[0012] (Embodiment 2) The second embodiment shown in Fig. 3 differs from the first embodiment shown in Fig. 1 in that the driving voltage switching means 15 is changed to 15a. The driving voltage switching means 15a is configured by a common cathode connection of a diode 16a and a diode 17a. The drive voltage switching means 15a is composed of an OR circuit of a diode 16a and a diode 17a, and compares the output voltage Vo with the drive voltage Vdrv, and when the output voltage Vo is lower than the drive voltage Vdrv, the drive voltage Vdrv is supplied from the diode 16a to the power terminal of the second drive means 10. This drives the P-channel MOSFET 6 with the drive voltage Vdrv. Furthermore, when the output voltage Vo exceeds the drive voltage Vdrv, the output voltage Vo is supplied from the diode 17a to the power supply terminal of the second drive means 10. As a result, the P-channel MOSFET 6 is driven by the output voltage Vo. In the second embodiment, the P-channel MOSFET 6 is driven via the diode 16a or 17a. Since a voltage drop occurs due to the forward voltage VF of the diode, it is preferable to use a Schottky diode with a low forward voltage.

[0013] (Embodiment 3) The third embodiment shown in FIG. 4 differs from the second embodiment shown in FIG. 3 in that the driving voltage switching means 15a is changed to 15b, and the anode connection location of the diode 17b configured in the driving voltage switching means 15b is changed. In the third embodiment, the anode of a diode 17b is connected to the connection point between the drain of a P-channel MOSFET 6, the inductor 5, and the capacitor 4, and the cathode is OR-connected to the drive voltage Vdrv, thereby generating a drive voltage higher than that in the second embodiment. Since the voltage drop between the drain and source when the P-channel MOSFET 6 is in an on-operation is added to the output voltage Vo, when the output voltage Vo exceeds the drive voltage Vdrv, the voltage supplied from the diode 17b to the power supply terminal of the second drive means 10 can be higher than in the second embodiment by the on-voltage between the drain and source of the P-channel MOSFET 6. Therefore, the gate terminal voltage of the P-channel MOSFET 6 when it is off is higher than in the third embodiment, and the gate terminal capacitance can be charged more quickly, so that the P-channel MOSFET 6 can be turned off quickly.

[0014] (Embodiment 4) The fourth embodiment shown in Fig. 5 differs from the third embodiment shown in Fig. 4 in that the driving voltage switching means is changed from 15b to 15c, and a third inductor 20c is added between the connection point of the inductor 5, the capacitor 4, and the anode of the diode 17c and the drain terminal of the P-channel MOSFET 6. Here, the third inductor 20c may be an inductor with a small inductance value such as a ferrite bead, and may be replaced by the inductance of the board wiring or the like. In the fourth embodiment, by connecting the inductor 20c in series with the P-channel MOSFET 6, the high-side voltage of the drive output of the second drive means 10 can be set higher than the output voltage Vo, thereby realizing faster switching than in the third embodiment and configuring a more efficient power supply. Fig. 6 shows the first drive signal and the second drive signal when the output voltage Vo is higher than the drive voltage Vdrv, and Fig. 7 is an operational waveform diagram of the N-channel MOSFET 3, the P-channel MOSFET 6, and the diode D17c under the same conditions. At time T1c shown in Fig. 7, the P-channel MOSFET 6 is turned off, and when the P-channel MOSFET 6 is turned on, an electromotive force is generated in the inductor 20c, and a charging current flows to the capacitor 19 via the diode 17c until the period of time T1'c. This has the effect of supplying a higher voltage on the High side of the second drive signal for the P-channel MOSFET 6 by the charging voltage by the third inductor 20c, as shown in Fig. 6. This makes it possible to charge the gate terminal capacitance of the P-channel MOSFET 6 quickly, and turn off the P-channel MOSFET 6 quickly.

[0015] (Embodiment 5) The fifth embodiment shown in Fig. 8 differs from the fourth embodiment shown in Fig. 5 in that the drive voltage switching means 15c is changed to 15d, and the third inductor 20d is inserted between the capacitor 4 and the connection point between the second inductor 5 and the drain terminal of the P-channel MOSFET 6. The anode of the diode 17d of the drive voltage switching means 15d is connected to the connection point between the capacitor 4 and the second inductor 5. Here, similar to the fourth embodiment, the third inductor 20d may be an inductor with a small inductance value such as a ferrite bead, or may be replaced by the inductance of the board wiring or the like. In the fifth embodiment, by connecting the inductor 20d in series with the P-channel MOSFET 6, the High-side voltage of the drive output of the second drive means 10 can be set higher than the output voltage Vo, thereby achieving the same effect as in the fourth embodiment.

[0016] (Embodiment 6) The sixth embodiment shown in FIG. 9 differs from the second embodiment in FIG. 3 in that the drive voltage switching means 15 is changed to 15e, and the anode terminal of the diode 17e of the drive voltage switching means 15e is changed from being connected to the output voltage Vo to being connected to the inductance 3, the capacitor 4, and the drain terminal of the N-channel MOSFET 3. Here, the pulse voltage value of the anode terminal voltage of diode 17e becomes the sum of the input voltage Vi and the output voltage Vo, and the voltage of the second drive signal for the P-channel MOSFET 6 can be supplied higher by the input voltage Vi. As a result, the gate terminal voltage of the P-channel MOSFET 6 when it is off can be made higher than the output voltage VO, and the gate terminal capacitance can be charged quickly, making it possible to turn off the P-channel MOSFET 6 quickly.

[0017] Although the embodiment of the present invention has been described above, the above embodiment is merely an example for embodying the technical idea of ​​the present invention, and the individual configurations, combinations, etc. are not limited to those described above. The present invention can be implemented with various modifications within the scope of the gist of the present invention. [Industrial Applicability]

[0018] As described above, the driving power supply according to the present invention is suitable for use as a driving power supply for a synchronous rectifier element of a SEPIC converter, etc. Therefore, it can be used as a power supply for in-vehicle devices using this power supply, etc. [Explanation of symbols]

[0019] 1, 1a, 1b, 1c, 1d, 1e SEPIC Converters 2 First inductor 3 N-channel MOSFET 4 Capacitors 5 Second inductor 6 P-channel MOSFETs 7 Output Capacitor 8. Load 9 First driving means 10 Second driving means 11. A / D Converter 12 Subtractor 13 Filter calculation means 14 PWM signal generation means 15, 15a, 15b, 15c, 15d, 15e Drive voltage switching unit 16, 16a, 16b, 16c, 16d, 16e Diodes 17, 17a, 17b, 17c, 17d, 17e Diodes 18 Voltage switching control means 19 Capacitor 20c, 20d Third inductor

Claims

1. a first inductor connected between the input power supply and a first terminal of the coupling capacitor; a first switching element connected between the first terminal of the coupling capacitor and ground; a second inductor connected between the second terminal of the coupling capacitor and the ground; a second switching element connected between the second terminal of the coupling capacitor and an output terminal; a driving means for driving the second switching element; A DC-DC converter including a synchronous rectification type SEPIC circuit having a drive voltage for supplying power to the drive means, a drive voltage switching means for switching a connection so that power is supplied to the drive means from a voltage source higher than the output voltage or the output voltage when the output voltage is set higher than the drive voltage, and for switching a connection so that power is supplied to the drive means from the drive voltage when the output voltage is set lower than the drive voltage; an AD converter that detects the output voltage and converts the output voltage into a digital value; a subtractor that outputs a difference value between an output target value and the digital converted value; A filter calculation means for calculating a calculation value based on the difference value; a PWM signal generating means for generating a PWM signal having a duty corresponding to the calculated value, The DC-DC converter is characterized in that the drive means outputs a drive signal for driving the second switching element based on the voltage supplied from the drive voltage switching means and the PMW signal.

2. 2. The DC-DC converter according to claim 1, wherein the drive voltage switching means comprises a first rectification means connected between the drive voltage and the drive means, and a second rectification means connected between the output voltage and the drive means.

3. the drive voltage switching means includes a first rectifying means connected between the drive voltage and the drive means, and a second rectifying means connected between the output voltage and the drive means; 2. The DC-DC converter according to claim 1, wherein the second rectifying means is connected to a connection point between the second terminal of the coupling capacitor and the second switching element.

4. the DC-DC converter includes a third inductor and a second rectifier; the third inductor is connected between the second switching element and a connection point of the second inductor, the connection point being connected to a second terminal of the coupling capacitor; 2. The DC-DC converter according to claim 1, wherein the second rectifying means is connected to a connection point between the second terminal of the coupling capacitor and the second inductor, and to the driving means.

5. the DC-DC converter includes a third inductor and a second rectifier; one end of the third inductor is connected to the second terminal of the coupling capacitor, and the other end is connected to the second inductor and the second switching element; 2. The DC-DC converter according to claim 1, wherein the second rectifying means is connected to a connection point between the second terminal of the coupling capacitor and the third inductor, and to the driving means.

6. A first inductor connected between an input power supply and a first terminal of a coupling capacitor; a first switching element connected between the first terminal of the coupling capacitor and ground; a second inductor connected between the second terminal of the coupling capacitor and the ground; a second switching element connected between the second terminal of the coupling capacitor and an output terminal; a driving means for driving the second switching element; A DC-DC converter including a synchronous rectification type SEPIC circuit having a drive voltage for supplying power to the drive means, a drive voltage switching means for switching a connection so that power is supplied to the drive means from a source of the voltage or a voltage higher than the voltage when a voltage related to a potential at the first terminal of the coupling capacitor is set higher than the drive voltage, and for switching a connection so that power is supplied to the drive means from the drive voltage when the voltage is set lower than the drive voltage; an AD converter that detects an output voltage and converts the output voltage into a digital converted value; a subtractor that outputs a difference value between an output target value and the digital converted value; A filter calculation means for calculating a calculation value based on the difference value; a PWM signal generating means for generating a PWM signal having a duty corresponding to the calculated value, the driving means outputs a driving signal for driving the second switching element based on the voltage supplied from the driving voltage switching means and the PWM signal; The drive voltage switching means includes a first rectifier means connected between the drive voltage and the drive means; a second rectifier connected between the drive means and a connection point between the first terminal of the coupling capacitor and the first switching element.

Images