Display device and driving method thereof

Abstract

To provide a display device capable of changing the driving mode of a display panel according to resolution or a driving frequency of an image applied thereto.SOLUTION: A display device according to an embodiment comprises a display panel for displaying an image, a gate driver configured to supply gate signals to the display panel, a data driver connected to the display panel, and a timing controller for controlling the gate driver. The timing controller controls the output type of the gate driver so that one gate signal is applied per gate line or per at least two gate lines, based on an externally applied image.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a display device and a driving method thereof. [Background technology]

[0002] As information technology develops, the market for display devices, which are a medium connecting users with information, is expanding, leading to an increase in the use of display devices such as light emitting (DIS)play devices (LEDs), quantum dot (DIS)play devices (QDDs), and liquid crystal (DIS)play devices (LCDs).

[0003] The above-mentioned display device includes a display panel including sub-pixels, a driver that outputs a drive signal for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0004] In such a display device, when driving signals, such as scan signals and data signals, are supplied to sub-pixels formed in a display panel, selected sub-pixels can transmit light or directly emit light to display an image. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a display device capable of switching a driving method of a display panel according to a resolution or driving frequency of an image applied to the display device, and integrating a circuit platform to expand versatility when implementing a device for increasing or decreasing a driving scan rate. The present invention also provides a universal switching circuit capable of changing a driving scan rate in a method requiring sensing and compensation of a display panel or a method not requiring such sensing and compensation. [Means for solving the problem]

[0006] One embodiment of the present invention provides a display device including a display panel for displaying an image, a gate driver for supplying gate signals to the display panel, a data driver connected to the display panel, and a timing controller for controlling the gate driver, wherein the timing controller controls an output mode of the gate driver so that the gate signals are applied one for each gate line, or one for at least two gate lines, in response to an image applied from outside.

[0007] The gate driving unit may include a shift register that outputs the gate signal, a level shifter that outputs a scan clock signal for driving the shift register, and an output switching circuit unit that is activated or deactivated under the control of the timing control unit and controls the output of the shift register or the level shifter.

[0008] The output switching circuit unit is activated under the control of a timing control unit and may control a gate signal output from a shift register or a scan clock signal output from a level shifter.

[0009] The timing control unit may generate an output switching signal for controlling an output mode of the gate driving unit based on at least one of resolution information and frequency information of an externally applied image.

[0010] When the resolution is changed by the externally applied image, the output switching signal may be generated as a high logic signal corresponding to an active period in which an image is displayed, and may be generated as a low logic signal corresponding to a blank period in which no image is displayed.

[0011] When the output switch signal is generated as a low logic corresponding to a blank period in which no image is displayed, the data driver senses the display panel through a sensing line to obtain a sensing value.

[0012] When the resolution is changed by an externally applied image, the display panel includes a resolution switching period for operating the device under changed driving conditions, and no gate signal is output during the resolution switching period.

[0013] The output switching circuit unit may include a first type transistor having a gate electrode connected to an output switching signal line through which the output switching signal is transmitted, a first electrode connected to a first output stage and a first gate line of a shift register included in the gate driver, and a second electrode connected to a second output stage and a second gate line of the shift register, and a second type transistor different from the first type, having a gate electrode connected to the output switching signal line, a first electrode connected to a second output stage of the shift register, and a second electrode connected to the second gate line.

[0014] In another aspect, another embodiment of the present invention provides a method for driving a display device, including the steps of detecting resolution information from an externally applied image, generating an output switching signal when the resolution is changed by the externally applied image, generating a high logic output switching signal corresponding to an active period in which an image is displayed, and generating a low logic output transition signal corresponding to a blank period in which an image is not displayed, and controlling the application of one gate signal for every gate line in response to the high logic output switching signal, or applying one gate signal for every two gate lines in response to the low logic output switching signal.

[0015] The output switch signal may be generated at a high logic level when the resolution is changed from a high resolution to a low resolution. Effect of the Invention

[0016] The present invention has an effect of switching a driving method of a display panel according to a resolution or a driving frequency of an image applied to the display device. In addition, the present invention has an effect of expanding versatility by integrating a circuit platform when implementing a device for increasing or decreasing a driving scan rate of a display device. In addition, the present invention has an effect of providing a universal switching circuit that can change the driving scan rate in a method requiring sensing and compensation of a display panel or in other methods. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram illustrating a display device. [Diagram 2] FIG. 2 is a block diagram illustrating a schematic configuration of the subpixel shown in FIG. [Diagram 3] FIG. 2 is a diagram for explaining the configuration of a gate-in-panel type gate driving unit. [Figure 4] FIG. 2 is a diagram for explaining the configuration of a gate-in-panel type gate driving unit. [Diagram 5] FIG. 13 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver; [Figure 6] 4 is a block diagram showing an output state of gate signals when the display device according to the first embodiment of the present invention is driven in a first mode. FIG. [Figure 7] 5 is a block diagram showing an output manner of a seagate signal when the display device according to the first embodiment of the present invention is driven in a second mode. FIG. [Figure 8] 1 is a diagram showing a main configuration of a display device according to a first embodiment of the present invention. [Figure 9] 9 is a waveform diagram for explaining an output switching signal applied to an output switching circuit unit shown in FIG. 8. [Figure 10] FIG. 2 is an exemplary diagram illustrating an output switching circuit unit according to the first embodiment of the present invention. [Figure 11] FIG. 11 is a diagram illustrating an example of the layout of an output switching circuit section according to a modified example of the first embodiment of the present invention. [Figure 12] FIG. 11 is a diagram illustrating an example of the layout of an output switching circuit section according to a modified example of the first embodiment of the present invention. [Figure 13] FIG. 2 is a detailed configuration diagram of an output switching circuit unit. [Figure 14] 5A and 5B are diagrams illustrating the operation of an output switching circuit unit. [Figure 15] 5A and 5B are diagrams illustrating the operation of an output switching circuit unit. [Figure 16] 6 is a flowchart for explaining an operation of an output switching circuit unit according to a driving state of a display panel. [Figure 17] FIG. 5 is a diagram showing a main configuration of a display device according to a second embodiment of the present invention. [Figure 18] FIG. 11 is an exemplary diagram illustrating an output switching circuit unit according to a second embodiment of the present invention. [Figure 19] 5A and 5B are diagrams illustrating the operation of an output switching circuit unit. [Figure 20] 5A and 5B are diagrams illustrating the operation of an output switching circuit unit. [Figure 21] FIG. 11 is a diagram illustrating an output switching circuit section of a display device according to a third embodiment of the present invention. [Figure 22] FIG. 11 is a diagram illustrating an output switching circuit section of a display device according to a third embodiment of the present invention. [Figure 23] FIG. 11 is a diagram illustrating a configuration example of a display device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The display device according to the present invention may be implemented as a television, an image player, a personal computer (PC), a home theater, an automobile electronic device, a smartphone, etc., but is not limited thereto. The display device according to the present invention may be implemented as a light emitting (DIS)play device (LED), a quantum dot (DIS)play device (QDD), a liquid crystal (DIS)play device (LCD), etc. However, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode will be described as an example below.

[0019] The thin film transistors described below can be configured as n-type thin film transistors, p-type thin film transistors, or a combination of n-type and p-type. A thin film transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a thin film transistor, carriers start to flow from the source. The drain is an electrode in a thin film transistor from which carriers exit to the outside. That is, carriers in a thin film transistor flow from the source to the drain.

[0020] In the case of a p-type thin film transistor, the carriers are holes, so the source voltage is higher than the drain voltage so that holes flow from the source to the drain. In the case of a p-type thin film transistor, the holes flow from the source to the drain, so that the current flows from the source to the drain. In contrast, in the case of an n-type thin film transistor, the carriers are electrons, so the source voltage has a lower voltage than the drain voltage so that electrons flow from the source to the drain. In the case of an n-type thin film transistor, the electrons flow from the source to the drain, so that the current flows from the drain to the source. However, the source and drain of a thin film transistor can be changed depending on the applied voltage. In the following description, either the source or the drain will be described as a first electrode, and the remaining one of the source and the drain will be described as a second electrode.

[0021] FIG. 1 is a block diagram that illustrates a display device, and FIG. 2 is a block diagram that illustrates a subpixel shown in FIG.

[0022] As shown in FIGS. 1 and 2, the display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power provider 180, and the like.

[0023] The image supply unit (set or host system) 110 can output various driving signals together with image data signals supplied from the outside or image data signals stored in an internal memory (image data signals). The image supply unit 110 can supply the data signals and various driving signals to the timing control unit 120.

[0024] The timing controller 120 may output a gate timing control signal (GDC) for controlling the operation timing of the gate driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronous signals (such as a vertical synchronous signal VSYNC and a horizontal synchronous signal HSYNC). The timing controller 120 may supply a data signal DATA supplied from the image supplier 110 to the data driver 140 together with the data timing control signal (DDC). The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0025] The gate driver 130 may output a gate signal (or a gate voltage) in response to a gate timing control signal (GDC) provided from the timing controller 120. The gate driver 130 may provide the gate signals to sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The gate driver 130 may be formed in an IC form and may be directly formed on the display panel 150 in a gate in panel manner, but is not limited thereto.

[0026] The data driver 140 may sample and latch a data signal (DATA) in response to a data timing control signal (DDC) provided from the timing controller 120, convert a digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 may provide data voltages to sub-pixels included in the display panel 150 via data lines (DL1 to DLn). The data driver 140 may be formed in an IC form and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0027] The power supply unit 180 may generate a high potential voltage and a low potential voltage based on an external input voltage supplied from the outside and output the high potential voltage and the low potential voltage via a first power line EVDD and a second power line EVSS. The power supply unit 180 may generate and output not only the high potential voltage and the low potential voltage but also a voltage required to drive the gate driver 130 (e.g., a gate voltage including a gate high voltage and a gate low voltage) and a voltage required to drive the data driver 140 (a drain voltage including a drain voltage and a half drain voltage).

[0028] The display panel 150 can display an image in response to driving signals including gate signals and data voltages, driving voltages including high potential voltages and low potential voltages, etc. The sub-pixels of the display panel 150 directly emit light. The display panel 150 can be fabricated based on a rigid or ductile substrate such as glass, silicon, polyimide, etc. And the light-emitting sub-pixels can be composed of pixels including red, green, and blue, or pixels including red, green, blue, and white.

[0029] For example, one subpixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, etc. The subpixel SP used in the light emitting display device directly emits light, and therefore has a complex circuit configuration. In addition, there are various compensation circuits for compensating for deterioration of not only the organic light emitting diode that emits light, but also the driving transistor that supplies the driving current required to drive the organic light emitting diode, etc. Therefore, the subpixel SP is shown simply in the form of a block.

[0030] Meanwhile, in the above description, the timing controller 120, the gate driver 130, the data driver 140, etc. are described as separate components. However, depending on the configuration of the light emitting display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into one IC.

[0031] 3 and 4 are diagrams for explaining the configuration of a gate-in-panel type gate driver, and FIG. 5 is a diagram showing an example of the arrangement of the gate-in-panel type gate driver.

[0032] 3, the gate-in-panel type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a clock signal (Clks), a start signal (Vst), etc. based on the signal and voltage output from the timing control unit 120 and the power supply unit 180. The shift register 131 operates based on the clock signal (Clks), the start signal Vst, etc. output from the level shifter 135, and may output gate signals (Gout[1] to Gout[m]).

[0033] 3 and 4, the level shifter 135 may be formed independently in an IC form, different from the shift register 131, or may be included inside the power supply unit 180. However, this is merely an example and is not limited thereto.

[0034] 5, first and second shift registers 131a and 131b for outputting gate signals in a gate-in-panel gate driver may be disposed in a non-display area (NA) of a display panel 150. The first and second shift registers 131a and 131b may be formed as thin films on the display panel 150 in a gate-in-panel manner. The first and second shift registers 131a and 131b are disposed in the left and right non-display areas (NA) of the display panel 150, respectively, as an example, but are not limited thereto.

[0035] FIG. 6 is a block diagram showing an output mode of a gate signal when the display device according to the first embodiment of the present invention is driven in a first mode, FIG. 7 is a block diagram showing an output mode of a gate signal when the display device according to the first embodiment of the present invention is driven in a second mode, FIG. 8 is a main configuration diagram of the display device according to the first embodiment of the present invention, and FIG. 9 is a waveform diagram for explaining an output switching signal applied to the output switching circuit section shown in FIG. 8.

[0036] 6, the display device according to the first embodiment of the present invention sequentially divides and outputs gate signals (Gout[1] to Gout[8]) to be supplied to the display panel 150 when driven in the first mode, and may output one for each gate line. Thus, a first gate signal (Gout[1]) may be output through a first gate line, and a second gate signal (Gout[2]) may be output through a second gate line so as to overlap a portion of the first gate signal (Gout[1]).

[0037] As shown in FIG. 7, the display device according to the first embodiment of the present invention sequentially divides and outputs gate signals (Gout[1] to Gout[8]) to be supplied to the display panel 150 when driven in the second mode, and may output one for every two gate lines. Thus, the first gate signal (Gout[1]) may be output through the first and second gate lines, and then the third gate signal (Gout[3]) may be output through the third and 24th gate lines so as to overlap with the first gate signal (Gout[1]) for a certain period. That is, two gate lines adjacent to each other vertically may transmit one gate signal generated at the same time.

[0038] 6 and 7, a configuration has been described in which a signal is output when a gate signal of a high voltage (H) is generated, and a signal is not output when a gate signal of a low voltage (L) is generated. This configuration illustrates an example in which a transistor included in a subpixel of the display panel 150 is turned on by a high voltage (H). That is, when a transistor included in a subpixel of the display panel 150 is turned on by a low voltage (L), it can be described as a configuration in which a gate signal is output when it has a phase opposite to that shown in the figure.

[0039] As shown in FIG. 8, the display device according to the first embodiment of the present invention may include a timing control unit 120, a level shifter 135, a shift register 131, an output switching circuit unit 132, a display panel 150, and the like.

[0040] The timing control section 120 can output a first clock signal necessary for the operation of the level shifter 135. The level shifter 135 can output a second clock signal, etc. necessary for the operation of the shift register 131, based on the first clock signal, etc. The timing control section 120 can output an output switching signal via an output switching signal line (DLG_en).

[0041] The output switching circuit unit 132 may be included in the shift register 131. The output switching circuit unit 132 can change the output mode of the gate signals (Gout[1] to Gout[m]) output from the shift register 131 according to the logical state of the output switching signal output from the timing control unit 120. For example, the output switching circuit unit 132 can change the output mode of the gate signals (Gout[1] to Gout[m]) in the form shown in FIG. 6 or FIG. 7.

[0042] As shown in FIGS. 8 and 9, the output switching signal (DLG_en) can be generated in the form of high logic or low logic. In the output switching signal (DLG_en), the high logic state can be defined as an activation signal (E(NA)) that activates the operation of the output switching circuit unit 132, and the low logic state can be defined as an inactivation signal (DIS) that inactivates the operation of the output switching circuit unit 132.

[0043] The output switching signal (DLG_en) can be generated in the form of an activation signal (E(NA)) corresponding to the driving frequency Dfreq information of the display device or the resolution information of the display panel, or in the form of a deactivation signal (DIS). For example, if the driving frequency Dfreq of the display device is AHz, it can be generated in the form of a deactivation signal (DIS), and when it is changed to BHz, it can be generated in the form of an activation signal (E(NA)). At this time, the relationship between AHz and BHz may be AHz (relatively low frequency or low-speed driving) < BHz (relatively high frequency or high-speed driving), but it is not limited thereto. Note that the output switching signal DLG_en can also be temporarily generated in the form of a deactivation signal (DIS) even when the driving frequency Dfreq of the display device is BHz. An example thereof will be described below.

[0044] FIG. 10 is an exemplary diagram for explaining the output switching circuit unit according to the first embodiment of the present invention, and FIGS. 11 and 12 are layout example diagrams of the output switching circuit unit according to a modification of the first embodiment of the present invention. FIG. 13 is a detailed configuration diagram of the output switching circuit unit, FIGS. 14 and 15 are diagrams for explaining the operation of the output switching circuit unit, and FIG. 16 is a flowchart for explaining the operation of the output switching circuit unit according to the driving state of the display panel.

[0045] As shown in Figures 8 and 10, the output switching signal DLG_en can be generated at high logic during an active period (ACTIVE) in which an image is displayed on the display panel, and at low logic during a blank period BLANK in which an image is not displayed on the display panel.

[0046] When the driving frequency Dfreq of the display device is AHz, the output switching signal DLG_en may be generated as a low logic signal regardless of the active period and the blank period. In this case, since the output switching circuit unit 132 is in an inactive state, the gate signals (Gout[1] to Gout[8]) supplied to the display panel 150 are sequentially divided and output, and each signal may be output for each gate line.

[0047] When the driving frequency Dfreq of the display device is BHz, the output switching signal DLG_en may be generated as a high logic corresponding to the active period ACTIVE. In this case, since the output switching circuit unit 132 is in an activated state, the gate signals Gout[1] to Gout[8] to be supplied to the display panel 150 are sequentially divided and output, and one may be output for every two gate lines.

[0048] When the driving frequency Dfreq of the display device is BHz, the output switching signal DLG_en may be generated as a low logic corresponding to the blank period BLANK. In this case, the output switching circuit unit 132 is in an inactive state, but may output only a gate signal to be supplied to a selected gate line to the display panel 150. In FIG. 10, the first gate signal (Gout[1]) is output in the first blank period BLANK, and the second gate signal (Gout[2]) is output in the second blank period BLANK, but at least one gate signal may be output at various positions.

[0049] As shown in Fig. 11, the output switching circuit unit 132 may be located in the non-display area (NA) of the display panel 150, and may be disposed between the shift register 131 and the display area (AA). As shown in Fig. 12, the output switching circuit unit 132 is located in the non-display area (NA) of the display panel 150, but may be disposed adjacent to the display area (AA). Note that Figs. 8, 11, and 12 show an example in which the timing control unit 120 and the level shifter 135 are mounted in an IC form on the same substrate, but the present invention is not limited thereto.

[0050] 8, 11 or 12 because the circuits constituting the output switching circuit section 132 can be formed by a thin film process like the elements included in the display panel 150. The elements constituting the output switching circuit section 132 will be described below.

[0051] 13, the output switching circuit section 132 may include A transistors TA1, TA2 and B transistors TB1, TB2. The A transistors TA1, TA2 may be selected as n-type, and the B transistors TB1, TB2 may be selected as p-type. The A transistors TA1, TA2 and the B transistors TB1, TB2 have their gate electrodes (control electrodes) commonly connected to the output switching signal line DLG_en. The connection relationship between the first A transistor TA1 and the first B transistor TB1 will be described below.

[0052] The first A transistor TA1 may have a gate electrode connected to the output switching signal line DLG_en, a first electrode connected to the first output stage GO1 and the first gate line GL1 of the shift register 131, and a second electrode connected to the second output stage GO2 and the second gate line GL2 of the shift register 131. The first B transistor TB1 may have a gate electrode connected to the output switching signal line DLG_en, a first electrode connected to the second output stage GO2 of the shift register 131, and a second electrode connected to the second gate line GL2.

[0053] The A transistors TA1, TA2 and the B transistors TB1, TB2 may operate as follows in response to the logic state of the output switching signal supplied via the output switching signal line DLG_en: The A transistors TA1, TA2 may operate to connect two adjacent gate lines, and the B transistors TB1, TB2 may operate to mask (not output) a gate signal output via one selected gate line (odd gate line or even gate line) of the two adjacent gate lines.

[0054] 14, when the output switching signal is in a low state, the B transistors TB1 and TB2 are turned on, but the A transistors TA1 and TA2 are turned off. In this case, gate signals may be output to the first to fourth gate lines GL1 to GL4 in the form shown in FIG.

[0055] 15, when the output switching signal is in a high state, the B transistors TB1 and TB2 may be turned off and the A transistors TA1 and TA2 may be turned on. In this case, gate signals may be output to the first to fourth gate lines GL1 to GL4 in the form as shown in FIG.

[0056] 8 and 16, the timing controller 120 may check the driving state of the display panel 150 (S10) and check whether the display panel 150 is being driven to normally display an image (S20). If the display panel 150 is being driven to normally display an image (Y), the timing controller 120 may check the output switching signal DLG_en (S30) and output a high logic (HIGH) or a low logic (LOW) (S40).

[0057] However, if the driving state is not being performed to normally display an image (N), the driving state may be checked again (S10). Here, the case where the driving state is not being performed to normally display an image may include a sensing operation, a compensation operation, etc. of the display panel 150.

[0058] When the timing control unit 120 outputs a high logic (HIGH) output switching signal DLG_en, the output switching circuit unit 132 is activated (DLG: ON) and can perform an output switching operation (S50). In contrast, when the timing control unit 120 outputs a low logic (LOW) output switching signal DLG_en, the output switching circuit unit 132 is deactivated (DLG: OFF) and does not perform an output switching operation (S60).

[0059] FIG. 17 is a diagram showing the main configuration of a display device according to a second embodiment of the present invention, FIG. 18 is an exemplary diagram for explaining an output switching circuit section according to the second embodiment of the present invention, and FIGS. 19 and 20 are diagrams for explaining the operation of the output switching circuit section.

[0060] As shown in FIG. 17, the display device according to the second embodiment of the present invention may include a timing control unit 120, a level shifter 135, a shift register 131, an output switching circuit unit 132, a display panel 150, and the like.

[0061] The timing control section 120 can output a first clock signal necessary for the operation of the level shifter 135. The level shifter 135 can output a second clock signal, etc. necessary for the operation of the shift register 131, based on the first clock signal, etc. The timing control section 120 can output an output switching signal via an output switching signal line DLG_en.

[0062] The output switching circuit unit 132 may be included in the level shifter 135. The output switching circuit unit 132 may change the output mode of the second clock signal output from the level shifter 135 in accordance with the logic state of the output switching signal output from the timing control unit 120. The change in the output mode of the second clock signal output from the level shifter 135 will be described below.

[0063] As shown in Figures 17 and 18, the output switching signal DLG_en can be generated at high logic during an active period (ACTIVE) in which an image is displayed on the display panel, and at low logic during a blank period BLANK in which an image is not displayed on the display panel.

[0064] When the driving frequency Dfreq of the display device is AHz, the output switching signal DLG_en may be generated as a low logic signal regardless of the active period and the blank period. In this case, since the output switching circuit unit 132 is in an inactive state, the gate signals (Gout[1] to Gout[8]) supplied to the display panel 150 are sequentially divided and output, and each signal may be output for each gate line.

[0065] When the driving frequency Dfreq of the display device is BHz, the output switching signal DLG_en may be generated as a high logic corresponding to the active period (ACTIVE). In this case, since the output switching circuit unit 132 is in an activated state, the gate signals (Gout[1] to Gout[8]) supplied to the display panel 150 are sequentially divided and output, and one may be output for every two gate lines.

[0066] When the driving frequency Dfreq of the display device is BHz, the output switching signal DLG_en may be generated at a low logic level corresponding to the blank period BLANK. In this case, the output switching circuit unit 132 is in an inactive state, but may output only the gate signal to be supplied to the selected gate line to the display panel 150.

[0067] 17, 19, and 20, the level shifter 135 may receive a first clock signal IClks and the like output from the timing control section 120. The first clock signal IClks may include a first driving clock signal Gclk and a second driving clock signal Mclk.

[0068] For example, the first driving clock signal Gclk may be generated as a pulse having a constant period and alternating high and low logics. The second driving clock signal Mclk may also be generated as a pulse having alternating high and low logics, but the time of the high logic may be longer than the time of the low logic. However, this is merely an example, and the present invention is not limited thereto.

[0069] The level shifter 135 may output a second clock signal OClks etc. necessary for the operation of the shift register 131 based on the first clock signal IClks etc. supplied from the timing control unit 120. The second clock signal OClks may include a first scan clock signal Sclk1 to an i-th scan clock signal Sclki (where i is an integer equal to or greater than 4).

[0070] For example, the first scan clock signal Sclk1 may be generated as a high logic signal in synchronization with a first rising edge of the first driving clock signal Gclk and may be generated as a low logic signal in synchronization with a first polling edge of the second driving clock signal Mclk. And, the second scan clock signal Sclk2 may be generated as a high logic signal in synchronization with a second rising edge of the first driving clock signal Gclk and may be generated as a low logic signal in synchronization with a second polling edge of the second driving clock signal Mclk. However, this is merely an example and the present invention is not limited thereto.

[0071] When a low logic output switching signal is output from the timing control unit 120, the level shifter 135 may output a second clock signal OClks including scan clock signals Sclk1 to Sclki that are generated sequentially so that adjacent scan clock signals overlap for a certain period of time, as shown in FIG. 19.

[0072] On the other hand, when a high logic output switching signal is output from the timing control unit 120, the level shifter 135 may output a second clock signal OClks including scan clock signals Sclk1 to Sclki configured in a paired form so that adjacent two scan clock signals are generated simultaneously, although adjacent scan clock signals are sequentially generated to overlap each other for a certain period as shown in Fig. 20. That is, two vertically adjacent scan clock signals may be paired and generated in the same form.

[0073] The level shifter 135 can change the output mode of the second clock signal OClks in response to the logic state of the output switching signal supplied from the timing control unit 120. Then, the shift register 131 can output gate signals (Gout[1] to Gout[8]) in the form as shown in FIG. 18 in response to the change in the output mode of the second clock signal OClks.

[0074] 21 and 22 are diagrams for explaining an output switching circuit section of a display device according to a third embodiment of the present invention, and FIG. 23 is a diagram showing an example of the configuration of the display device according to the third embodiment of the present invention.

[0075] As shown in FIG. 21, the display device according to the third embodiment of the present invention can deactivate (DLG:OFF) or activate (DLG:ON) the output switching circuit section 132 depending on the resolution displayed on the display panel 150.

[0076] For example, when an image of resolution A is displayed on the display panel 150, the output switching circuit unit 132 may be inactivated (DLG: OFF), and when an image of resolution B is displayed, the output switching circuit unit 132 may be activated (DLG: ON). At this time, the relationship between resolution A and resolution B is, but is not limited to, resolution A (relatively high resolution)>resolution B (relatively low resolution).

[0077] 22, the output switch signal DLG_en may be generated as low logic when an image with UHD resolution is applied to the display panel 150, but may be generated as high logic when an image with FHD resolution is applied. Even when an image with FHD resolution is applied, the output switch signal DLG_en may be generated as high logic during an active period (ACTIVE) of the display panel 150, and may be generated as low logic during a blank period (BLANK) of the display panel 150.

[0078] On the other hand, when the resolution of the image applied to the display panel 150 is changed from UHD to FHD, a resolution switching period (TRS) may be included therebetween. The resolution switching period TRS may be defined as a period in which the generation timing of the output switching signal DLG_en and the drive timing of the display panel 150 are synchronized (matched). During the resolution switching period (TRS), devices included in driving the display device may synchronize with the changed drive conditions. This makes it possible to prevent a phenomenon in which the device operates in an abnormal state (e.g., abnormal screen output) when the resolution is switched.

[0079] The output switching signal DLG_en may be generated as a high logic signal at the same time as the application of the UHD image ends and the resolution switching period TRS begins. However, there may be a period of time during which the output switching signal DLG_en is applied to the output switching circuit unit 130 and updated with new driving conditions. Therefore, the output switching circuit unit 130 may be activated (DLG:ON) after a certain delay time has elapsed after the output switching signal DLG_en is generated.

[0080] A period during which a UHD image is applied to the display panel 150 may be defined as a normal driving period (NDRV) (or a first mode driving period). During the normal driving period NDRV, the gate signals Gout are output sequentially, and may be output so as to be applied one by one to each gate line.

[0081] A resolution switching period TRS during which the resolution of an image applied to the display panel 150 is changed can be defined as a non-driving period XDRV. During the non-driving period XDRV, a gate signal (Gout) is not output. Meanwhile, in FIG. 22, after the resolution switching period TRS is generated, a non-driving period XDRV is provided after a predetermined delay time (because there is a time required for the scan driving unit, the data driving unit, etc. to be controlled based on the signal output from the timing control unit).

[0082] The active period ACTIVE may be defined as a double driving period DDRV (or a second mode driving period) even during a period in which an FHD image is applied to the display panel 150. During the double driving period DDRV, the gate signals Gout are output sequentially, but may be output so that one signal is applied to every two gate lines.

[0083] The blank period BLANK may be defined as the sensing driving period SDRV (or the third mode driving period) even during a period in which an FHD image is applied to the display panel 150. During the sensing driving period SDRV, the gate signal Gout may output only the gate signal to be supplied to the selected gate line.

[0084] 22 and 23, the timing control unit 120 may include a resolution detection unit RES, a signal detection unit DED, a signal generation unit GEN, and a compensation unit COMP. The resolution detection unit RES and the signal detection unit DED may detect resolution information and a data enable signal (or including frequency information) that activates the output of the data signal DATA input to the timing control unit 120, and supply this to the signal generation unit GEN. The signal generation unit GEN may generate an output switching signal DLG_en based on the resolution information and the data enable signal, and supply this to the output switching circuit unit 130.

[0085] The data driver 140 may drive the display panel 150 based on a data signal DATA provided from the timing controller 120. The data driver 140 may provide data voltages to the sub-pixels via the data lines DL of the display panel 150 during a normal driving period NDRV or a double driving period DDRV.

[0086] The data driver 140 may sense characteristics (e.g., threshold voltage, mobility, etc.) of elements included in the subpixels through the sensing lines SL of the display panel 150 during the sensing drive period SDRV. The data driver 140 may convert the sensing value SEN corresponding to the element characteristics acquired through the sensing lines SL into a digital format and provide the digital value to the timing controller 140.

[0087] The compensation unit COMP may grasp the characteristics and deterioration of the elements based on the sensing value SEN supplied to the timing control unit 140, and compensate for the deterioration. The compensation unit COMP may generate a compensation data signal CDATA. The compensation unit COMP may generate the compensation data signal CDATA in response to a change in the threshold voltage of the organic light emitting diode or the driving transistor included in the subpixel. Furthermore, the compensation unit COMP may update and store information related to compensation, such as the position of the deteriorated element(s), the compensation value, etc., based on a memory, etc.

[0088] As described above, the present invention has an effect of switching the driving method of a display panel according to the resolution or driving frequency of an image applied to the display device. In addition, the present invention has an effect of expanding versatility by integrating a circuit platform when configuring a device for increasing or decreasing the driving scan rate of a display device. In addition, the present invention has an effect of providing a universal switching circuit that can change the driving scan rate in a method requiring sensing and compensation of a display panel and other methods. [Explanation of symbols]

[0089] 120 Timing control section 135 Level Shifter 131 Shift Register 132 Output switching circuit section 150 Display Panel 130 Gate driver DLG_EN Output switching signal line DLG_en Output switching signal

Claims

1. a display panel for displaying an image; a gate driver for supplying a gate signal to the display panel; a data driver connected to the display panel; a timing controller for controlling the gate driver; the timing control unit controls an output mode of the gate driving unit so that the gate signals are applied to one gate line at a time, or to at least two gate lines at a time, in response to an image applied from an external source; The gate driver includes: A shift register that outputs the gate signal; a level shifter that outputs a scan clock signal for driving the shift register; an output switching circuit section which is activated or deactivated under the control of the timing control section and controls an output of the shift register or the level shifter; The timing control unit is generating an output switching signal for controlling an output mode of the gate driver based on at least one of resolution information and frequency information of the externally applied image; The output switching signal is A display device in which, in response to a change in resolution due to an externally applied image, a high logic level is generated corresponding to an active period in which an image is displayed, and a low logic level is generated corresponding to a blank period in which no image is displayed.

2. A display panel for displaying an image; a gate driver for supplying a gate signal to the display panel; a data driver connected to the display panel; a timing controller for controlling the gate driver; the timing control unit controls an output mode of the gate driving unit so that the gate signals are applied to one gate line at a time, or to at least two gate lines at a time, in response to an image applied from an external source; The gate driver includes: A shift register that outputs the gate signal; a level shifter that outputs a scan clock signal for driving the shift register; an output switching circuit section which is activated or deactivated under the control of the timing control section and controls an output of the shift register or the level shifter; the timing control unit generates an output switching signal for controlling an output mode of the gate driving unit based on at least one of resolution information and frequency information of the image applied from the outside, In response to the output switching signal being generated as a low logic signal corresponding to a blank period in which the image is not displayed, The data driver senses the display panel through a sensing line to obtain a sensing value.

3. A display panel for displaying an image; a gate driver for supplying a gate signal to the display panel; a data driver connected to the display panel; A display device including a timing controller for controlling the gate driver, the timing control unit controls an output mode of the gate driving unit so that the gate signals are applied to one gate line at a time, or to at least two gate lines at a time, in response to an image applied from an external source; The gate driver includes: A shift register that outputs the gate signal; a level shifter that outputs a scan clock signal for driving the shift register; an output switching circuit section which is activated or deactivated under the control of the timing control section and controls an output of the shift register or the level shifter; The timing control unit is generating an output switching signal for controlling an output mode of the gate driver based on at least one of resolution information and frequency information of the externally applied image; the frequency information includes a drive frequency of the display device, When the driving frequency is a first frequency, the output switching signal is generated as a low logic; When the driving frequency is a second frequency, the output switching signal is generated as a high logic signal based on an active period during which an image is displayed, and is generated as a low logic signal based on a blank period during which an image is not displayed; The display device according to claim 1, wherein the first frequency is smaller than the second frequency.

4. The output switching circuit unit includes: A display device according to any one of claims 1 to 3, wherein the timing control unit controls the gate signal that is activated and output from the shift register, or controls the scan clock signal that is output from the level shifter.

5. A display device according to any one of claims 1 to 3, wherein when the resolution is changed by the externally applied image, the gate signal is not output over a resolution switching period for operating the device under changed driving conditions.

6. The output switching circuit unit includes: a first type transistor having a gate electrode connected to an output switching signal line through which the output switching signal is transmitted, a first electrode connected to a first output stage and a first gate line of the shift register included in the gate driver, and a second electrode connected to a second output stage and a second gate line of the shift register; The display device according to any one of claims 1 to 3, comprising a transistor having a gate electrode connected to the output switching signal line, a first electrode connected to the second output stage of the shift register, and a second electrode connected to the second gate line, the transistor being of a second type different from the first type.

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