Multi-protocol support over a common physical layer

Abstract

To provide, e.g., systems including a PHY that includes a logical PHY to support multiple interconnect protocols.SOLUTION: A logical PHY includes a first set of CRC encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer directs data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY includes a first set of ECC encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC / ECC combinations can be used based on the interconnect protocol and the link operational conditions.SELECTED DRAWING: Figure 4

Description

[Background technology]

[0001] When the data rate of a serial link exceeds 32.0 GT / s, Pulse Amplitude Modulation (PAM) with Forward Error Correction (FEC) (e.g., PAM-4) can be used to limit the effective Bit Error Rate (BER) to an acceptable range. Forward Error Correction (FEC) is a technique used to control errors in data transmission over unreliable or noisy communication channels. By using an Error-Correcting Code (ECC), the sender can encode the message in a redundant manner. The redundancy allows the receiver to detect a finite number of errors that may occur anywhere in the message and often correct those errors without retransmission. [Brief description of the drawings]

[0002] [Figure 1] 1 illustrates an embodiment of a block diagram for a computer system including a multi-core processor. [Figure 2A] 1 is a schematic block diagram of an example link including one or more retimers in accordance with an embodiment of the present disclosure. [Figure 2B] 1 is a schematic block diagram of an example link including one or more retimers in accordance with an embodiment of the present disclosure. [Diagram 3] 1 is a schematic diagram of a common physical layer (common PHY) supporting multiple interconnect protocols in accordance with an embodiment of the present disclosure. [Figure 4] FIG. 2 is a schematic diagram of a transmit side logical sub-block of a common PHY according to an embodiment of the present disclosure. [Diagram 5] 2 is a schematic diagram of a receiver logical sub-block of a common PHY according to an embodiment of the present disclosure. [Figure 6] FIG. 1 is a process flow diagram for dynamically changing interconnect operating conditions in a common PHY according to an embodiment of the present disclosure. [Figure 7] 1 illustrates an embodiment of a computer system that includes an interconnect architecture. [Figure 8] 1 illustrates an embodiment of an interconnect architecture that includes a layered stack. [Figure 9] 1 illustrates an embodiment of a request or packet that is generated or received within an interconnect architecture. [Figure 10] 1 illustrates an embodiment of a transmitter and receiver pair for an interconnect architecture. [Figure 11] 3 illustrates another embodiment of a block diagram for a computer system including a processor. [Figure 12] 1 illustrates an embodiment of a block diagram for a computer system including multiple processor sockets. [Figure 13] FIG. 2 is a schematic diagram illustrating an example of a link training state machine according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0003] The drawings are not to scale.

[0004] In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure, such as specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc. However, as will be apparent to one of ordinary skill in the art, such specific details need not be used to practice the present disclosure. In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / code for the algorithms described, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific power-down and gating techniques, and other specific operational details of computer systems, have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0005] Although the following embodiments may be described with reference to energy conservation and efficiency in a particular integrated circuit, such as a computer platform or microprocessor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks, and may also be used in other devices, such as portable devices, tablets, other thin notebooks, System on a Chip (SoC) devices, and embedded applications. Some examples of portable devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and portable PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), SoCs, network computers (NetPCs), set-top boxes, network buses, wide area network (WAN) switches, or any other system capable of performing the functions and operations taught below. Furthermore, the apparatus, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimization for energy conservation and efficiency. As will be readily apparent from the following description, the method, apparatus and system embodiments described herein (whether with reference to hardware, firmware, software, or a combination thereof) are essential to the future of 'green technology' balancing performance concerns.

[0006] As computer systems advance, their components are becoming more and more complex. As a result, the interconnect architectures that couple and communicate between components are also becoming more complex to ensure that bandwidth requirements are met for optimal component operation. Furthermore, different market segments require different aspects of the interconnect architecture to suit the market needs. For example, servers require higher performance, while the mobile ecosystem can sometimes sacrifice overall performance for power savings. Furthermore, the sole objective of most organizations is to provide the highest possible performance with maximum power savings. Below, a number of interconnects are described that may benefit from aspects of the disclosure described herein.

[0007] Referring to Figure 1, an embodiment of a block diagram for a computer system including a multi-core processor is shown. Processor 100 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a SoC, or a device for executing code. Processor 100, in one embodiment, includes at least two cores, here cores 101 and 102, which may include asymmetric cores or symmetric cores (in the illustrated embodiment). It is noted that processor 100 may include any number of processing elements, which may be symmetric or asymmetric.

[0008] In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and / or any other element that can hold a processor state, such as an execution state or an architectural state. In other words, a processing element, in one embodiment, refers to any hardware that can be independently associated with code, such as a software thread, an operating system, an application, or other code. A physical processor (or processor socket) generally refers to an integrated circuit that may contain any number of other processing elements, such as cores or hardware threads.

[0009] A core often refers to logic located on an integrated circuit capable of maintaining independent architectural states, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to a core, a hardware thread usually refers to any logic located on an integrated circuit capable of maintaining independent architectural states, where the independently maintained architectural states share access to the execution resources. As will be apparent, the line between the nomenclature of a hardware thread and a core overlaps when certain resources are shared and other resources are dedicated to an architectural state. Moreover, often, cores and hardware threads are viewed by the operating system as separate logical processors, and the operating system can schedule operations separately for each logical processor.

[0010] The physical processor 100 includes two cores, namely, cores 101 and 102, as depicted in FIG. 1. Here, the cores 101 and 102 are considered to be symmetric cores, i.e., cores with the same configuration, functional units, and / or logic. In other embodiments, the core 101 includes an out-of-order processor core, while the core 102 includes an in-order processor core. However, the cores 101 and 102 may be individually selected from any type of core, such as a native core, a software-managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a transformed Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e., asymmetric cores), some form of translation, such as binary translation, may be utilized to schedule or execute code on one or both cores. More specifically, the functional units depicted in core 101 are described in more detail below, as the units in core 102 operate similarly in the depicted embodiment.

[0011] As depicted, core 101 includes two hardware threads 101a and 101b, which may also be referred to as hardware thread slots 101a and 101b. Thus, a software entity, such as an operating system, in one embodiment, potentially views processor 100 as four separate processors, i.e., four logical processors or processing elements that can simultaneously execute four software threads. As alluded to above, a first thread is associated with architecture state register 101a, a second thread is associated with architecture state register 101b, a third thread is associated with architecture state register 102a, and a fourth thread is associated with architecture state register 102b. Here, each of the architecture state registers (101a, 101b, 102a, and 102b) may be referred to as a processing element, thread slot, or thread unit, as described above. As shown, architecture state register 101a is duplicated in architecture state register 101b so that individual architecture state / context can be stored for logical processor 101a and logical processor 101b. In core 101, other smaller resources such as instruction pointers and renaming logic in allocator and renamer block 130 may also be duplicated for threads 101a and 101b. Some resources such as reorder retirement unit 135, ILTB 120, load / store buffers, and queues may be shared through partitioning. Other resources such as general purpose internal registers, page table base registers, low level data cache and data TLB 115, execution unit 140, and out-of-order unit 135 are potentially fully shared.

[0012] Processor 100 often includes other resources that may be fully shared, shared through partitioning, or dedicated to a processing element. In FIG. 1, a purely exemplary processor embodiment is depicted with the processor's illustrative logical units / resources. Note that the processor may include or omit any of those functional units, as well as any other known functional units, logic, or firmware not depicted. As depicted, core 101 includes a simplified representative out-of-order (OOO) processor core. However, an in-order processor may be used in another embodiment. The OOO core includes a branch target buffer 120 that predicts executed / taken branches, and an instruction translation buffer (I-TLB) 120 that stores address translation entries for instructions.

[0013] Core 101 further includes a decode module 125 coupled to fetch unit 120 to decode fetched elements. The fetch logic, in one embodiment, includes separate sequencers associated with each of thread slots 101a, 101b. Typically, core 101 is associated with a first ISA that defines / specifies instructions executable by processor 100. Often, machine code instructions that are part of the first ISA include portions of the instructions (called opcodes) that refer to / specify the instruction or operation to be performed. Decode logic 125 includes circuitry to recognize such instructions from their opcodes and send the decoded instructions down the pipeline for processing as defined by the first ISA. For example, as described in more detail below, decoder 125, in one embodiment, includes logic designed or adapted to recognize certain instructions, such as transactional instructions. As a result of recognition by decoder 125, the architecture or core 101 takes specific, predefined actions to perform a task associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be executed in response to a single instruction or multiple instructions (some of which may be new or old instructions). Note that the decoder 126, in one embodiment, recognizes the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, the decoder 126 recognizes a second ISA (either a subset of the first ISA or a different ISA).

[0014] In one example, allocator and renamer block 130 includes an allocator that reserves resources such as a register file to store instruction processing results. Note that threads 101a and 101b are potentially capable of out-of-order execution, and allocator and renamer block 130 also reserves other resources such as a reorder buffer to track instruction results. Unit 130 may also include a register renamer that renames program / instruction reference registers to other registers internal to processor 100. Reorder / retirement unit 135 includes components such as the reorder buffer, load buffer, and store buffer described above to support out-of-order execution and, later, in-order retirement of instructions that were executed out-of-order.

[0015] Scheduler and execution units block 140, in one embodiment, includes a scheduler unit that schedules instructions / operations to the execution units. For example, floating point instructions are scheduled to ports of execution units that have an available floating point execution unit. Register files associated with the execution units are also included to store information regarding instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

[0016] A lower level data cache and data translation buffer (D-TLB) 150 is coupled to the execution units 140. The data cache stores recently used / operated elements, such as data operands, potentially held in a memory coherent state. The D-TLB stores recent virtual / linear address to physical address translations. As a specific example, a processor may include a page table structure that divides physical memory into multiple virtual pages.

[0017] Here, the cores 101 and 102 share access to a higher level or higher cache, such as a second level cache associated with the on-chip interface 110. Higher level or higher refers to a cache level further away or increased from the execution units. In one embodiment, the higher level cache is a last level data cache, i.e., the last cache in the memory hierarchy on the processor 100, such as a second or third level data cache. Note that the higher level cache is not so limited and may be related to or include an instruction cache. A trace cache, which is a type of instruction cache, may instead be coupled after the decoder 125 to store recently decoded traces. Here, instructions refer to macro-instructions (i.e., general instructions recognized by a decoder) that can potentially be decoded into multiple micro-instructions (micro-operations).

[0018] In the depicted configuration, processor 100 also includes an on-chip interface 110. Historically, a memory controller, described in more detail below, has been included in a computer system external to processor 100. In this scenario, on-chip interface 110 communicates with devices external to processor 100, such as system memory 175, a chipset (which often includes a memory controller hub that connects to memory 175 and an I / O controller hub that connects to peripherals), a memory controller hub, a northbridge, or other integrated circuits. And, in this scenario, bus 105 may include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a modified protocol architecture, a differential bus, and a GTL bus.

[0019] Memory 175 may be dedicated to processor 100 or shared with other devices in the system. Common examples of types of memory 175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Devices 180 may include graphics accelerators, processors or cards coupled to a memory controller hub, data storage coupled to an I / O controller hub, wireless transceivers, flash devices, audio controllers, network controllers, or other known devices.

[0020] Recently, however, as more logic and devices are being integrated into a single die, such as an SoC, each of such devices may be incorporated into the processor 100. For example, in one embodiment, the memory controller hub is in the same package and / or die with the processor 100. Here, the portion of the core 110 (the on-core portion) includes one or more controllers for interfacing with other devices, such as memory 175 or graphics device 180. Configurations including interconnects and controllers for interfacing with such devices are often referred to as on-core (or un-core configurations). As an example, the on-chip interface 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 105 for off-chip communication. Furthermore, in an SoC environment, even more devices, such as a network interface, a co-processor, memory 175, graphics processor 180, and any other known computing device / interface, may be integrated into a single die or integrated circuit to provide high functionality and low power consumption in a small form factor.

[0021] In one embodiment, the processor 100 is capable of executing compiler, optimizer, and / or translator code 177 to compile, translate, and / or optimize application code 176 to support or interface with the apparatus and methods described herein. A compiler often includes a program or set of programs that translate source text / code into target text / code. Typically, compilation of program / application code by a compiler is performed in multiple phases and passes to translate high-level programming language code into low-level machine or assembly language code. Furthermore, a single-pass compiler may still be used for a single compilation. The compiler may use any known compilation technique and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

[0022] Larger compilers often include multiple phases, but in most cases these phases are contained within two general phases: (1) the front-end, i.e., where syntactic processing, semantic processing, and some transformation / optimization may generally occur, and (2) the back-end, i.e., where parsing, transformation, optimization, and code generation generally occur. Some compilers refer to the middle, which represents a blurring of the line between the front-end and back-end of the compiler. As a result, references to compiler insertion, association, generation, or other operations may occur in any of the phases or passes mentioned above as well as any other known phases or passes of the compiler. By way of illustration, a compiler potentially inserts operations, calls, functions, etc., in one or more phases of compilation, such as inserting calls / operations in the front-end phase of compilation, and then translating the calls / operations to low-level code during the transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations / calls as well as optimize the code for execution during run-time. As a specific example, binary code (already compiled code) may be dynamically optimized during run-time, where program code may include dynamically optimized code, binary code, or a combination thereof.

[0023] Similar to a compiler, a translator, such as a binary translator, translates code statically or dynamically to optimize and / or transform the code. Thus, reference to executing code, application code, program code, or other software environment may refer to (1) dynamically or statically running a compiler program, optimization code optimizer, or translator to compile program code, maintain software structure, perform other operations, optimize code, or transform code, (2) running main program code that includes operations / calls such as application code that is being optimized / compiled, (3) running other program code, such as libraries associated with the main program code, to maintain software structure, perform other software related operations, or optimize code, or (4) any combination thereof.

[0024] 2A is a schematic and timing diagram illustrating a sample topology 200 with two retimers between an upstream component downstream port 202 and a downstream component upstream port 208 in accordance with an embodiment of the present disclosure. The upstream component downstream port 202 can be a port for a PCIe-based device, such as a CPU or other device capable of generating data packets and transmitting the data packets across a data link that conforms to the PCIe protocol. The downstream component upstream port 208 can be a port for a peripheral component that can receive data packets from a link that conforms to the PCIe protocol. It is understood that the upstream component downstream port 202 and the downstream component upstream port 208 can transmit and receive data packets across the PCIe links, depicted as PCIe links 210a-c.

[0025] Topology 200 can include one or more retimers 204 and 206. Retimers 204 and 206 can act as signal repeaters operating at the physical layer to fine-tune signals from upstream component downstream port 202 and downstream component upstream port 208. The retimers can use Continuous Time Linear Equalization (CTLE), Decision Feedback Equalization (DFE), and Transmit a Impulse Response Equalization (Tx FIR EQ, or simply TxEQ). The retimers are transparent to the data link and transaction layers, but implement a full physical layer.

[0026] The multi-lane PCIe link is split into three link segments (LS) 210a, 210b, and 210c in each direction. Upstream component downstream port 202 may be coupled to retimer 1 204 by multi-lane PCIe link 210a. Retimer 1 204 may be coupled to retimer 2 206 by link segment 210b. And retimer 2 206 may be coupled to downstream component upstream port 208 by link segment 210c.

[0027] The components may also be coupled by sideband linkages: Upstream component downstream port 202 may be coupled to retimer 1 204 by sideband link 212a. Retimer 1 204 may be coupled to retimer 2 206 by sideband link 212b. And retimer 2 206 may be coupled to downstream component upstream port 208 by sideband link 212c.

[0028] The primary function of the retimer (buffer) device is signal retiming. Such function is performed by retimers 204 and 206. The particular retimer device circuitry depends on the PHY used for the link. In general, the retimer circuitry is configured to recover the incoming signal and retransmit it using a local clock and new transmit equalization circuitry, and may typically use well-known circuitry for this purpose, such as a phase-locked loop. The retimer may further include transmitter and receiver circuitry including one or more amplifier circuits, along with various types of well-known signal conditioning circuits used to increase the drive level of the received signal. Such retimer circuits are well known to those skilled in the art of high-speed interconnect technology, and therefore will not be presented in further detail herein.

[0029] Each retimer 204, 206 can have an upstream path and a downstream path. In some implementations, the retimer can include two pseudo ports that can dynamically determine their respective downstream / upstream directions. Additionally, the retimers 204 and 206 can support operation modes including a forwarding mode and a running mode. The retimers 204 and 206 can, in some examples, decode data received on a sublink and re-encode data that it should forward downstream on its own other sublink. As such, the retimer can capture the received bitstream before regenerating and resending the bitstream to other devices or other retimers (or redrivers or repeaters). In some cases, the retimer can change some values ​​in the data it receives, for example, when processing and forwarding ordered set data. Thus, the retimer can potentially support any width option as its maximum width, such as the set of width options defined by a standard such as PCIe.

[0030] As data rates of serial interconnects (e.g., PCIe, UPI, USB, etc.) increase, retimers are increasingly used to extend channel reach. For even longer channel reach, multiple retimers can be cascaded. As signal speeds increase, channel reach is generally expected to shorten as a general matter. Thus, as interconnect technology advances, the use of retimers becomes more and more common. As an example, when PCIe Gen-4, which provides a transfer rate of 16GT / s, is introduced in favor of PCIe Gen-3 (8GT / s), the use of retimers in PCIe interconnects will increase as speeds increase, similar to that of other interconnects.

[0031] In one implementation, a common BGA (Ball Grid Array) footprint may be defined for a PCIe Gen-4 (16GT / s) based retimer. Such a design may address, for example, some of the shortcomings seen with conventional PCIe Gen-3 (8GT / s) retimer devices as well as at least some of the emerging issues with the introduction of PCIe Gen-4. Due to signal loss due to the doubled data rate (8GT / s to 16GT / s), achievable interconnect lengths are significantly shorter with Gen-4. In this and other exemplary interconnect technologies, as data rates increase, retimers thereby become more useful because they can be used to dynamically increase channel lengths that would otherwise be constrained by the increased data rates.

[0032] Although shown as being separate from the upstream and downstream components, the retimer may be part of the upstream or downstream component, on-board with the upstream or downstream component, or on-package with the downstream component.

[0033] The upstream component downstream port 202 may have access to a storage element 222, such as flash storage, a cache, or other memory device. Retimer 1 204 may optionally include a similar storage element 224. Retimer 2 206 may optionally include a similar storage element 226. The downstream component upstream port 208 may optionally include a similar storage element 228.

[0034] FIG. 2B is a schematic diagram of a connected system 250 illustrating an in-band upstream port and retimer configuration according to an embodiment of the present disclosure. As shown in FIG. 2A, an upstream component downstream port 202 may be coupled to a downstream component upstream port 208 by a link 210a-c that is extended by two retimers 206, 206. In this example, the downstream port 202 may be provided with a retimer configuration register address / data register 252 to hold data sent in a configuration access command to one of the two retimers using a field of the extended SKP OS. One or more bits of the SKP OS may contain a command code, data, or address used in the configuration registers (e.g., 256, 258) of the retimers (e.g., 204, 206, respectively) to read data from or write data to the registers. The retimer may respond to the transmitted configuration access command by encoding data in an instance of the extended SKP OS and, by itself, encoding response data in a subsequent instance of the extended SKO OS. Data encoded by the retimers (e.g., 204, 206) may be extracted at the downstream port and recorded in a retimer configuration data return register (e.g., 254). The registers (252, 254) maintained at the upstream device downstream port 202 may be read and written by system software and / or other components of the system that allow (indirect) access to the retimer registers, i.e., one register (e.g., 252) that carries address / data / commands to the retimer, and a second register (e.g., 254) that stores the response back from the retimer. In other implementations, such registers (e.g., 260) may be maintained at the downstream component upstream port 208 instead of, or in addition to, the registers maintained at the upstream component downstream port 202, among others.

[0035] Continuing with the example of FIG. 2B, in conjunction with a mechanism that provides in-band access to the retimer registers, the retimer can be designed with registers that are addressable with well-defined bits and characteristics. In this example, the extended SKP OS is defined / modified as a physical layer generated periodic pattern to carry commands / information to the retimer from the “Retimer Config Reg Addr / Data” (e.g., 252) and responses back from the retimer to be read into the “Retimer Config Data Return” (e.g., 254) with some bits allocated to the CRC for data protection. For example, in PCIe, this can include augmenting the existing SKP Ordered Set (e.g., with CRS Access and CRS Return (CRC protection bits)). Furthermore, flows can be defined that ensure guaranteed delivery of commands / information to the retimer and corresponding responses back. The physical layer mechanism can be augmented to include, among other things, notifications from the retimer (in addition to responses) in case some service is required.

[0036] CPU-CPU symmetric coherency links such as PCIe Gen-6 (PCI Express 6th Generation) with transfer speed of 64.0GT / s, CXL (Compute Express Link 3rd Generation) with transfer speed of 64.0GT / s, and UPI (Ultra Path Interconnect) with frequencies above 32.0GT / s (e.g. 48.0GT / s or 56.0GT / s or 64.0GT / s) are examples of interconnects that require FEC to operate according to CRC. In SoC, it is highly desirable for the same PHY to be multi-protocol capable and used as PCIe / CXL / UPI depending on the device connected as link partner.

[0037] In embodiments of the present disclosure, multiple protocols (e.g., PCIe, CXL, UPI) may share a common PHY. Each protocol, however, may have different latency tolerances and bandwidth requirements. For example, PCIe may be more tolerant of increased latency than CXL. CPU-to-CPU symmetric cache coherent links such as UPI are more sensitive to increased latency.

[0038] Links such as PCIe and CXL may be divided into smaller independent sub-links. For example, a x16 PCIe / CXL link may be divided into up to eight independent links of x2 each. Symmetric cache coherent links may not support such levels of partitioning. Due to differences in latency characteristics and partitioning support, as well as differences in the underlying protocols, the links may use different flow control unit (flit) sizes and flit arrangements, even though they may share the same physical layer.

[0039] In addition to the different performance and operating conditions of the various protocols mentioned above, the operating conditions and performance requirements may also vary for any given protocol. Operating conditions may affect error rates and correlations between errors depending on the system as well as any variations in process, voltage and temperature. Similarly, different applications may have different latency and bandwidth requirements. This disclosure describes mechanisms that can dynamically adjust to those variations.

[0040] This disclosure describes a multi-protocol PHY that can dynamically support different FEC, CRC and flit sizes depending on the performance requirements and operating conditions of the underlying protocols. PHY is an abbreviation for "physical layer" and is an electronic circuit that can implement the physical layer functions of the OSI model.

[0041] The present disclosure enables a link to dynamically select different FEC, CRC, and flit sizes, independently in each direction, based on performance needs under operating conditions. The dynamic selection of FEC, CRC, and flit sizes can be performed autonomously by hardware and / or by hardware assisted by software.

[0042] FIG. 3 is a schematic diagram of a common physical layer (common PHY) supporting multiple interconnect protocols according to an embodiment of the present disclosure. FIG. 3 illustrates an example of a common PHY 300 (both analog and logical PHY) with PAM-4 encoding at higher data rates that can support multiple protocols (e.g., PCIe, CXL, UPI, Cache Coherent Interconnect for Accelerators (CCIX), Open Coherent Accelerator Processor Interface (CAPI), etc.) operating at different data rates. Both analog PHY 302 and logical PHY 304 are common to each supported protocol. Analog PHY 302 can support multi-lane links such as x16 PCIe links, along with 48GT / s and 56GT / s PAM-4 for other interconnect protocols.

[0043] The logical PHY 304 may include a TX logical sub-block 306 and an RX logical sub-block 308. The TX logical sub-block 306 may include logic to prepare a data stream for transmission across the link. For example, the TX logical sub-block 306 may include an idle flit generator 312 to generate flits. The flit size may be determined based on the protocol, the bandwidth, the operating conditions, the protocol in use, etc. The Cyclic Redundancy Check (CRC) code generator 314 may include one or more CRC code generators and a rolling CRC code generator to generate a CRC code. The CRC code is an error detection code to detect accidental changes to data. In an embodiment, the CRC code generator 314 may be bypassed while maintaining clock integrity. The TX logical sub-block 306 may also include a Forward Error Correction (FEC) encoder 316 to encode data with an Error Correcting Code (ECC). The FEC encoder 316 may also be bypassed without compromising clock integrity. Other logical elements such as lane reversal 318, LFSR 320, symbol alignment 322, etc. may also be present in the TX logical sub-block 306. The logical PHY 304 may also include a common retry buffer 340 since all protocols are based on flits.

[0044] The logical PHY 304 may include an RX logical sub-block 308. The RX logical sub-block 308 may include an FEC decoder / bypass 332, a CRC decoder / bypass 334, and an error reporting element t. The FEC decoder 332 may decode ECC bits in a received data block and perform error correction. The CRC decode logic 334 may check for uncorrectable errors and report the errors to an error reporting element 336. A retry buffer 340 may be used to indicate a retry of a data block that includes an uncorrectable error. Other logical elements such as lane reversal 330, LFSR 328, elastic / drift buffer 326, symbol alignment 324, etc. may also be present in the RX logical sub-block 308.

[0045] Logical PHY 304 may also include a static MUX (not shown) to select between different protocols supported by PHY 300. The use of a static MUX promotes reuse of logical elements (including essential parts of what are originally link layer functions, such as CRC and retries), resulting in area / power efficiency as well as pin efficiency and flexible I / O support (the ability to select different protocols depending on the system configuration). The static MUX can direct data to the appropriate physical and logical elements based on the flit size associated with the protocol in use, and direct data to the appropriate CRC encoder / decoder and FEC encoder / decoder.

[0046] In using a common PHY 300 (analog PHY 302 and logical PHY 304), the flit size, FEC, and CRC can potentially differ between different protocols and operating conditions. Any additional logic to facilitate a common PHY is less costly than replicating the logical PHY stack multiple times for each protocol. Instead, data can be electronically directed to the appropriate encoder / decoder based on the protocol in use, which is initially set during link initialization.

[0047] 4 is a schematic diagram of a transmit logical sub-block 400 of a common PHY according to an embodiment of the present disclosure. The transmit logical sub-block 400 is similar to the TX logical sub-block 306 described above. Figure 4 illustrates how data can traverse the transmit logical sub-block 400 based on operating conditions.

[0048] As an example, consider two flit sizes: 128B and 256B, which may be assigned to different protocols or the same protocol. For example, PCIe may only run with 256B flit size, CXL may operate as either 128B or 256B flit size depending on the operating conditions (e.g., higher error rates may push us towards 256B flit size to better amortize more errors and more CRC bits to correct for stronger CRC), and UPI may be 128B. The data path, including ECC and CRC logic, can handle multiple flit sizes. Even though two flit sizes are given as an example, one skilled in the art would recognize that the technique works for a single flit size as well as for more than two flit sizes.

[0049] In this example, the sender logic sub-block 400 includes two CRC generators, CRC#1 Gen 404 and CRC#2 Gen 410. CRC#1 Gen is based on GF(2), which is useful when errors are independent in each lane (i.e., the correction of errors in the lane after FEC is low). CRC#2 Gen is based on GF(2), which is useful when errors in the lane are bursty. 8 ). Each CRC generator also has its rolling CRC variant (e.g., Rolling CRC#1 Gen406 and Rolling CRC#2 Gen408) in case the underlying CRC is not sufficient in terms of reliability. The rolling CRC generators can generate CRC codes based on their respective CRC generators but using different polynomials of the same order.

[0050] A received flit (F1) is only accepted after its CRC is good, and the CRC from a subsequent flit (F2) is also good, after manipulating F1 with a different polynomial. There is also provision to bypass the CRC here if the upper layer stack wants to have its own separate check and does not need a CRC decoder in the PHY. Even though there are only four CRCs in this example (two CRCs each with its rolling CRC variant), one skilled in the art will recognize that more or less CRCs can be used, depending on the requirements.

[0051] Additionally, in this example, three different FEC encoders are used: ECC#1 414, ECC#2 416, and ECC#3 418. An option to bypass FEC is also provided if the measured error rate is acceptable. For example, the bandwidth requirement on a link running the UPI protocol may be 10 Gbps if the link is capable of operating at 48.0 GT / s and the measured raw burst error rate is 10 Gbps at 48.0 GT / s. -9 In such an example, FEC may be bypassed and CRC with retries is utilized to correct errors rather than paying the latency and bandwidth penalty for every flit. Thus, for any given flit size, the number of bits in the flit that can be used for data and / or data+control information payload may vary depending on the number of bits used for FEC and CRC (or 0 if no FEC is used).

[0052] ECC#1 414 in this example can be a 3-way interleaved ECC with single symbol correction capability. This type of ECC encoder can be used when errors in a lane are sufficiently corrected and occur with a high enough probability for burst lengths <=16 to meet reliability needs. ECC#2 416 can be a double bit correcting BCH code that would be used when precoding with PAM-4 is used and results in a very high probability of errors in a given lane turning into two bit flips. ECC#2 416 can have the same low latency characteristics as ECC#1 414, but is more efficient than ECC#1 414. ECC#2 416 can also work well when the burst length is >16. Note that ECC#1 414 is a better alternative when errors after precoding do not result in two bit flips in a lane but multiple bit flips. Even though ECC#3 418 has a higher latency penalty than ECC#1 414 or ECC#2 416, it has a lower low burst error rate (i.e., 10 -4 ~10 -5 In the above embodiment, the ECC code is a two-way interleaved double symbol correcting BCH code used in the case of 100 MHz to 100 MHz (range 100 MHz to 100 MHz). Even though there are only three types of ECC in this example, those skilled in the art will recognize that the number of ECCs can be more or less than three depending on the requirements.

[0053] Buffers may be used to accommodate various flit sizes. For example, for 128B flits, a single buffer 402, 424 may be used. For 256B flits, two 128B buffers 402 and 402a may be used.

[0054] Figure 5 is a schematic diagram of a receive side logical sub-block 500 of a common PHY according to an embodiment of the present disclosure. Figure 5 illustrates the receive side logical sub-block 500, which corresponds to the transmit side logical sub-block 400 described above. Since the receive side logical sub-block 500 needs to correct errors and detect any errors that could not be corrected, the receive side logical sub-block 500 includes a mechanism to log errors (error log 518) and to invoke link level retries by its link partner if necessary.

[0055] The exemplary receiver logic sub-block 500 includes three FEC decoders, an ECC#1 decoder 504 corresponding to the ECC#1 encoder 414, an ECC#2 decoder 506 corresponding to the ECC#2 encoder 416, and an ECC#3 decoder 508 corresponding to the ECC#3 encoder 418. The ECC decoders can correct errors. In an embodiment, certain errors, such as error 530, can be reported to an error log 518 for retry.

[0056] The example receiver logic sub-block 500 includes four CRC decoders, such as a CRC#1 check decoder 510 corresponding to the CRC#1 encoder 404, a rolling CRC#1 check decoder 512 corresponding to the rolling CRC#1 encoder 406, a CRC#2 check decoder 516 corresponding to the CRC#2 encoder 410, and a rolling CRC#2 check decoder 514 corresponding to the rolling CRC#2 encoder 408. The CRC decoders can determine uncorrectable errors (e.g., error 532) and report the uncorrectable errors to an error log 518 for retry.

[0057] Flit size can be similarly accommodated using buffers 502, 502a, and 520.

[0058] FIG. 6 is a process flow diagram of dynamically changing interconnect operating conditions at a common PHY according to an embodiment of the present disclosure. FIG. 6 illustrates how a receiver can adjust flit size, FEC type (including bypass), and CRC type based on its operating conditions. Thus, two components connected by a link can choose to have two different FEC / CRC / flits at the same time (i.e., negotiate to have the same depending on which has the worst FEC / CRC needs). The flit size, FEC type, and CRC type are changed during recovery. The receiver monitors its errors from FIG. 5 along with its performance requirements and makes a decision. This decision can be made automatically or with the help of software by giving a notification through the Configuration and Status Register (CSR) interface 380 shown in FIG. 3 when the link frequency, flit size, FEC, and CRC need to be changed.

[0059] First, an initial FEC and CRC combination may be requested and set (602) based on the protocol selected for use during link initialization between the host device and the connected end device. The initial FEC and CRC combination for the link may also be set by instruction from the BIOS or by setting the FEC / CRC combination to a previous setting that resulted in a stable satisfactory link condition. The FEC / CRC combination is set while the link is in recovery. If on link L0 (604), the link goes back to recovery before acting on the request to change the FEC / CRC combination.

[0060] For example, a request for a different FEC / CRC code may be granted by first restoring the link to the same speed as before, allowing the FEC / CRC combination to be changed, and then the link may return to the L0 state for operation (612).

[0061] If there is a lower bandwidth demand on the link (614), the link may enter recovery to switch to a lower speed (616). In an embodiment, switching to a lower speed may include forgoing the use of FEC as long as the link is capable of operating at a lower frequency without FEC.

[0062] If the link needs to enter recovery for other reasons (618), then the link can enter recovery at the same rate with the same FEC / CRC parameters, including no FEC if applicable. The link can then enter the L0 state and operate with those same FEC / CRC parameters (622). In some embodiments, while the link is recovering, the link can adjust its FEC / CRC parameters based on other inputs, as described at 608 and 614.

[0063] While the link is operating at L0, the PHY may collect error statistics (606). The error statistics may be collected by the error log from CRC and FEC decoding at the receiver (or by the transmitter, if applicable).

[0064] Referring to FIG. 7, an embodiment of a fabric of point-to-point links interconnecting a set of components is depicted. System 700 includes a processor 705 and system memory 710 coupled to a controller hub 715. Processor 705 may include any processing element, such as a microprocessor, host processor, embedded processor, co-processor, or other processor. Processor 705 is coupled to controller hub 715 through a front side bus (FSB) 706. In one embodiment, FSB 706 is a serial point-to-point interconnect, as described below. In another embodiment, link 706 includes a serial differential interconnect architecture that conforms to a different interconnect standard.

[0065] System memory 710 may include any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 700. System memory 710 is coupled to controller hub 715 through memory interface 716. Examples of memory interfaces include a double data rate (DDR) memory interface, a dual channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

[0066] In one embodiment, the controller hub 715 is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of controller hubs 715 include chipsets, memory controller hubs (MCH), northbridges, interconnect controller hubs (ICH) southbridges, and root port controllers / hubs. Often, the term "chipset" refers to two physically separate controller hubs, i.e., a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include an MCH integrated with the processor 705, while the controller hub 715 should communicate with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported through the root complex 715.

[0067] Here, controller hub 715 is coupled to switch / bridge 720 through serial link 719. Input / output modules 717 and 721, which may also be referred to as interfaces / ports 717 and 721, contain / implement a layered protocol stack that provides communication between controller hub 715 and switch 720. In one embodiment, multiple devices can be coupled to switch 720.

[0068] The switch / bridge 720 routes packets / messages upstream from the devices 725, i.e., up the hierarchy toward the root complex to the controller hub 715, and downstream, i.e., down the hierarchy away from the root port controller, from the processor 705 or system memory 710 to the devices 725. The switch 720, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. The devices 725 include any internal or external device or component coupled to an electronic system, such as I / O devices, network interface controllers (NICs), add-in cards, audio processors, network processors, hard drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, portable storage devices, Firewire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices. Often, in PCIe terminology, such devices are referred to as endpoints. Although not specifically shown, the devices 725 may include PCIe-to-PCI / PCI-X bridges to support legacy or other version PCI devices. Endpoint devices in PCIe are often categorized as legacy, PCIe, or root complex embedded endpoints.

[0069] The graphics accelerator 730 is also coupled to the controller hub 715 through a serial link 732. In one embodiment, the graphics accelerator 730 is coupled to an MCH which is coupled to an ICH. The switch 720, and therefore the I / O devices 725, are then coupled to the ICH. The I / O modules 731 and 718 should also implement a layered protocol stack to communicate between the graphics accelerator 730 and the controller hub 715. Similar to the MCH description above, the graphics controller or graphics accelerator 730 itself may be incorporated into the processor 705.

[0070] Referring to FIG. 8, an embodiment of a layered protocol stack is depicted. The layered protocol stack 800 may include any type of layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the following description with reference to FIGS. 7-10 is directed to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, the protocol stack 800 is a PCIe protocol stack including a transaction layer 805, a link layer 810, and a physical layer 820. Interfaces such as interfaces 717, 718, 721, 722, 726, and 731 of FIG. 7 may be represented as a communication protocol stack 800. The representation as a communication protocol stack may also be referred to as modules or interfaces that implement / include the protocol stack.

[0071] PCI Express uses packets to pass information between components. Packets are formed in the Transaction Layer 805 and Data Link Layer 810 to carry information from the transmitting component to the receiving component. As transmitted packets pass through other layers, they are extended with additional information required to handle the packets at those layers. On the receiving side, the reverse process occurs, and packets are converted from their Physical Layer 820 representation to a Data Link Layer 810 representation, and finally (in the case of transaction layer packets) to a form that can be processed by the Transaction Layer 805 of the receiving device.

[0072] [Transaction Layer] In one embodiment, the transaction layer 805 provides an interface between the processing cores of the devices and the interconnect architecture, such as the data link layer 810 and the physical layer 820. In this context, the primary job of the transaction layer 805 is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The transaction layer 805 typically manages credit-based flow control for TLPs. PCIe implements split transactions, i.e., transactions with a request and response separated by time, allowing the link to carry other traffic while the target device gathers data for the response.

[0073] Additionally, PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of its receive buffers at the transaction layer 805. An external device on the other side of the link, such as controller hub 715 in FIG. 7, counts the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction can be transmitted. Upon receiving a response, the amount of credit is restored. The advantage of the credit scheme is that the latency of the credit return does not affect performance unless the credit limit is reached.

[0074] In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an I / O address space, and a message address space. Memory space transactions include one or more of read and write requests to transfer data to / from memory mapped locations. In one embodiment, memory space transactions can use two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access the configuration space of a PCIe device. Transactions to the configuration space include read and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0075] Thus, in one embodiment, the transaction layer 805 constructs the packet header / payload 706. The current format for the packet header / payload can be found in the PCIe specification at the PCIe specification website.

[0076]

[0046] Referring briefly to Figure 9, an embodiment of a PCIe transaction descriptor is depicted. In one embodiment, the transaction descriptor 900 is a mechanism for carrying transaction information. In this regard, the transaction descriptor 900 supports the identification of transactions within a system. Other potential uses include tracking changes to the default transaction ordering and associating transactions with channels.

[0077] The transaction descriptor 900 includes a global identifier field 902, an attribute field 904, and a channel identifier field 906. In the depicted example, the global identifier field 902 is depicted as having a local transaction identifier field 908 and a source identifier field 910. In one embodiment, the global transaction identifier 902 is unique for all pending requests.

[0078] According to one implementation, the local transaction identifier field 908 is a field generated by the requesting agent that is unique for all pending requests requiring completion for that requesting agent. Furthermore, in this example, the source identifier field 910 uniquely identifies the requesting agent within the PCIe hierarchy. Thus, together with the source ID 910, the local transaction identifier field 908 provides a global identification of the transaction within the hierarchy domain.

[0079] The attributes field 904 specifies the characteristics and relationships of the transaction. In this regard, the attributes field 904 is potentially used to provide additional information that allows modification of the default handling of the transaction. In one embodiment, the attributes field 904 includes a priority field 912, a reserved field 914, an ordering field 916, and a no snoop field 918, where the priority subfield 912 may be modified by the initiator to assign a priority to the transaction. The reserved attributes field 914 is reserved for future or vendor-defined use. Potential usage models that use priority or security attributes may be implemented using the reserved attributes field.

[0080] In this example, the ordering attribute field 916 is used to provide any information conveying the type of ordering that may change the default ordering rules. According to one example implementation, an ordering attribute of "0" indicates that the default ordering rules should be applied, and an ordering attribute of "1" indicates relaxed ordering, where writes can pass writes in the same direction and read completions can pass writes in the same direction. The snoop attribute field 918 is utilized to determine whether the transaction is snooped. As shown, the channel ID field 906 identifies the channel with which the transaction is associated.

[0081] [Link Layer] The Link Layer 810, also called the Data Link Layer 810, functions as an intermediate stage between the Transaction Layer 805 and the Physical Layer 820. In one embodiment, the job of the Data Link Layer 810 is to provide a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components on a link. One side of the Data Link Layer 810 accepts the TLPs assembled by the Transaction Layer 805, applies a packet sequence identifier 811, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., CRC 812, and issues the modified TLPs to the Physical Layer 820 for transmission across the physical layer to an external device.

[0082] [Physical Layer] In one embodiment, physical layer 820 includes a logical sub-block 821 and an electrical sub-block 822 for physically transmitting packets to an external device, where logical sub-block 821 is responsible for the "digital" functions of physical layer 820. In this regard, logical sub-block 821 includes a transmit section that prepares outgoing information for transmission by physical sub-block 822, and a receive section that identifies and prepares received information before passing it on to link layer 810.

[0083] The physical block 822 includes a transmitter and a receiver. The transmitter is provided with symbols by the logical sub-block 821, and the transmitter serializes and transmits the symbols to an external device. The receiver is provided with serialized symbols from an external device and converts the received signal into a bit stream. The bit stream is deserialized and provided to the logical sub-block 821. In one embodiment, an 8b / 10b line code is used and 10-bit symbols are transmitted / received, where special symbols are used to frame 823 the packets. Furthermore, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

[0084] As mentioned above, the transaction layer 805, the link layer 810, and the physical layer 820 are described with reference to a specific embodiment of a PCIe protocol stack, but the layered protocol stack is not so limited. Indeed, any layered protocol may be included / implemented. As an example, a port / interface represented as a layered protocol includes (1) a first layer, i.e., a transaction layer, that assembles packets, (2) a second layer, i.e., a link layer, that sequences the packets, and (3) a third layer, i.e., a physical layer, that transmits the packets. As a specific example, the Common Standard Interface (CSI) layered protocol is utilized.

[0085] 10, an embodiment of a PCIe serial point-to-point fabric is shown. Although an embodiment of a PCIe serial point-to-point link is shown, a serial point-to-point link is not so limited in that it includes any transmission path for transmitting serial data. In the embodiment shown, a basic PCIe link includes two low voltage differential drive signal pairs, transmit pair 1006 / 1011 and receive pair 1012 / 1007. Thus, device 1005 includes transmit logic 1006 that transmits data to device 1010 and receive logic 1007 that receives data from device 1010. In other words, two transmit paths, paths 106 and 1017, and two receive paths, paths 1018 and 1019, are included in the PCIe link.

[0086] A transmission path refers to any path for transmitting data, such as a transmission line, copper wire, optical line, wireless communication channel, infrared communication link, or other communication path. A connection between two devices, such as device 1005 and device 1010, is called a link, such as link 1015. A link may support one lane, where each lane represents a set of differential signal pairs (one pair for transmit, one pair for receive). To scale the bandwidth, a link may aggregate multiple lanes, represented by ×N, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or more.

[0087] A differential pair refers to two transmission paths, such as lines 1016 and 1017, for transmitting differential signals. As an example, when line 106 switches from a low voltage level to a high voltage level (i.e., rising), line 1017 drives from a high logic level to a low logic level (i.e., falling). Differential signals potentially exhibit better signal integrity, i.e., better electrical properties such as cross-coupling, voltage overshoot / undershoot, ringing, etc. This allows for better timing windows that allow for faster transmission frequencies.

[0088] It should be noted that the above apparatus, methods, and systems may be implemented in any of the electronic devices or systems described above. As a specific implementation, the following figures provide examples of systems utilizing the disclosures described herein. As the systems are described in more detail below, a wide variety of interconnects are disclosed, described, and modified from the above description. And, as will be apparent, the advantages described above may be applied to any of those interconnects, fabrics, or architectures.

[0089] Referring to FIG. 11, a block diagram of an example computer system formed by a processor including an execution unit that executes instructions where one or more of the interconnects implement one or more features according to an embodiment of the present disclosure is shown. The system 1100 includes components such as a processor 1102 that employs an execution unit that includes logic to execute algorithms to process data in accordance with the present disclosure, for example, in the embodiments described herein. The system 1100 is representative of a processing system based on PENTIUM III, PENTIUM 4, Xeon, Itanium, XScale, and / or StrongARM microprocessors available from Intel Corporation of Santa Clara, California. However, other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may also be used. In one embodiment, the sample system 1000 runs a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington. However, other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used. Thus, embodiments of the present disclosure are not limited to any specific combination of hardware circuitry and software.

[0090] The embodiments are not limited to computer systems. Alternative embodiments of the present disclosure can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can include microcontrollers, digital signal processors (DSPs), systems-on-a-chip, network computers (NetPCs), set-top boxes, network buses, wide area network (WAN) switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0091] In the depicted embodiment, the processor 1102 includes one or more execution units 1108 that implement an algorithm to execute at least one instruction. Although one embodiment may be described in the context of a single processor desktop or server system, alternative embodiments may be included in a multiprocessor system. The system 1100 is an example of a 'hub' system architecture. The computer system 1100 includes a processor 1102 that processes data signals. The processor 1102 may include, as one example, a Complex Instruction Set Computer (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device such as, for example, a digital signal processor. The processor 1102 is coupled to a processor bus 1110 that carries data signals between the processor 1102 and other components in the system 1100. The elements of system 1100 (e.g., graphics accelerator 1112, memory controller hub 1116, memory 1120, I / O controller hub 1124, wireless transceiver 1126, flash BIOS 1128, network controller 1134, audio controller 1136, serial expansion port 1138, I / O controller 1140, etc.) perform their conventional functions that are well known to those skilled in the art.

[0092] In one embodiment, the processor 1102 includes a level 1 (L1) internal cache memory 1104. Depending on the architecture, the processor 1102 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of both internal and external cache depending on the particular implementation and needs. The register file 1106 stores various types of data in various registers, including integer registers, floating point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and an instruction pointer register.

[0093] Execution unit 1108 includes logic to perform integer and floating point operations and is also present in processor 1102. Processor 1102, in one embodiment, includes a microcode (ucode) ROM that stores microcode that, when executed, should perform algorithms for specific macro-instructions or handle complex scenarios, where the microcode is potentially updatable to handle logic bugs / fixes in processor 1102. For one embodiment, execution unit 1108 includes logic to handle a packed instruction set 1109. By including a packed instruction set 1109 in the instruction set of general purpose processor 1102, along with associated circuitry to execute the instructions, operations used by many multimedia applications can be performed with packed data in general purpose processor 1102. Thus, many multimedia applications are more efficiently accelerated and executed by using the full width of the processor's data bus to perform operations on packed data. This potentially eliminates the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0094] Alternate embodiments of the execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuitry. The system 1100 includes a memory 1120. The memory 1120 may include dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. The memory 120 stores instructions and / or data represented by data signals to be executed by the processor 1102.

[0095] It should be noted that any of the above features or aspects of the disclosure may be utilized in one or more of the interconnects depicted in Figure 11. For example, an on-die interconnect (not shown) coupling internal units of the processor 1102 may implement one or more aspects of the above disclosure. Alternatively, the disclosure may relate to the processor bus 1110 (e.g., Intel's Quick Path Interconnect (QPI) or other known high performance computing interconnects), the high bandwidth memory path 1118 to the memory 1120, the point-to-point link (e.g., Peripheral Component Interconnect Express (PCIe) compliant fabric) to the graphics accelerator 1112, the controller hub interconnect 1122, or other interconnects (e.g., USB, PCI, PCIe) coupling the I / O or other depicted components. Some examples of such components include an audio controller 1136, a firmware hub (flash BIOS) 1028, a wireless transceiver 1126, data storage 1124, a legacy I / O controller 1140 including a user input and keyboard interface 1142, a serial expansion port 1138 such as a universal serial bus (USB), and a network controller 1134. The data storage device 1124 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0096] 12, a block diagram of a second system 1200 is shown in accordance with an embodiment of the present disclosure. As shown in FIG. 12, the multiprocessor system 1200 is a point-to-point interconnect system and includes a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250. Each of the processors 1270 and 1280 may be any version of a processor. In one embodiment, 1252 and 1254 are part of a serial point-to-point coherent interconnect fabric, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the present disclosure may be implemented within a QPI architecture.

[0097] Although only two processors 1270, 1280 are shown, it should be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

[0098] Processors 1270 and 1280 are shown as including integrated memory controller (IMC) units 1272 and 1282, respectively. Processor 1270 also includes point-to-point (PP) interfaces 1276 and 1278 as part of its bus controller unit, and similarly, second processor 1280 includes PP interfaces 1286 and 1288. Processors 1270, 1280 may exchange information over point-to-point (PP) interface 1250 using PP interfaces 1278, 1288. As shown in FIG. 12, IMCs 1272 and 1282 couple the processors to their respective memories, i.e., memory 1232 and memory 1234. The memories may be portions of main memory locally attached to each processor.

[0099] Processors 1270, 1280 exchange information with chipset 1290 through respective PP interfaces 1252, 1254 using point-to-point interface circuits 1276, 1294, 1286, 1298. Chipset 1290 also exchanges information with high performance graphics circuit 1238 along high performance graphics interconnect 1239 via interface circuit 1292.

[0100] A shared cache (not shown) may be included in either processor, or may be external to both processors but connected to the processors via the PP interconnect, so that local cache information of either or both processors may be stored in the shared cache when the processors are placed in a low power mode.

[0101] Chipset 1290 may be coupled to a first bus 1216 via an interface 1296. In one embodiment, first bus 1216 may be a bus such as a Peripheral Component Interconnect (PCI) bus, or a PCI Express bus or other third generation I / O interconnect bus, although the scope of the disclosure is not so limited.

[0102] As shown in FIG. 12, various I / O devices 1214 are coupled to a first bus 1216 along with a bus bridge 1218 that couples the first bus 1216 to a second bus 1220. In one embodiment, the second bus 1220 comprises a Low Pin Count (LPC) bus. Various devices are coupled to the second bus 1220 in one embodiment, including, for example, a keyboard and / or mouse 1222, a communication device 1227, and a storage unit 1228, such as a disk drive or other mass storage device that often contains instructions / code and data 1230. Additionally, audio I / O 1224 is shown as being coupled to the second bus 1220. It should be noted that other architectures are possible, and the components and interconnect architectures involved may vary. For example, instead of the point-to-point architecture of FIG. 12, a system may implement a multi-drop bus or other such architecture.

[0103] A wide variety of use cases can be realized using the various inertial and environmental sensors present on the platform, enabling advanced computing operations including perceptual computing, as well as enabling enhancements with respect to power management / battery life, security, and system responsiveness.

[0104] For example, with respect to power management / battery life issues, the ambient light conditions at the platform's location are determined based in part on information from an ambient light sensor, and the display intensity is controlled accordingly. In this manner, the power consumed in operating the display is reduced in certain lighting conditions.

[0105] With regard to security operations, it may be determined whether a user is allowed to access a particular sensitive document based on context information obtained from sensors, such as location information. For example, a user may be permitted to access such documents at work or at home. However, the user is prevented from accessing such documents when the platform is in a public place. This determination is based on location information determined, in one embodiment, for example, via camera recognition of landmarks or a GPS sensor. Other security operations may include providing pairing of devices that are within a proximity range of each other, such as a portable platform described herein and a user's desktop computer, mobile phone, etc., although such sharing may be disabled if the devices exceed a certain range. Furthermore, when pairing a platform described herein with a smartphone, an alarm may be configured to be triggered if the devices are more than a predetermined distance from each other when in a public place. In contrast, when such paired devices are in a secure place, such as at work or at home, the devices may exceed this predetermined distance without triggering such an alarm.

[0106] Responsiveness may also be enhanced using sensor information. For example, even when the platform is in a low power state, the sensors may still be enabled to be moved at a relatively low frequency. Thus, any changes in the platform's position, as determined by, for example, inertial sensors, GPS sensors, etc., are determined. If no such changes are recorded, a faster connection to a traditional wireless hub, such as a Wi-Fi access point or similar wireless enabler, occurs, since in this case there is no need to scan for available wireless networks. Thus, there is a higher level of responsiveness when waking up from a low power state.

[0107] It should be understood that many other cases may be enabled using sensor information acquired via built-in sensors within the platform described herein, and the above examples are merely illustrative. Using the systems described herein, the perceptual computing system may enable the addition of alternative input modalities, including gesture recognition, allowing the system to sense the actions and intent of the user.

[0108] In some embodiments, there may be one or more infrared or other thermal sensing elements, or any other elements that detect the presence or movement of a user. Such sensing elements may include a variety of elements that work together, in sequence, or both. For example, sensing elements may include elements that provide initial sensing, such as light or sound projection, followed by sensing for gesture detection, for example, by an ultrasonic time-of-flight camera or a patterned light camera.

[0109] Also, in some embodiments, the system includes a light generator that generates an illumination line. In some embodiments, the line provides a visual cue of a virtual boundary, i.e., an imaginary or virtual location in space, and the user's action of passing through or breaking through the virtual boundary or surface is interpreted as an intention to collaborate with the computing system. In some embodiments, the represented line may change color if the computing system transitions to a different state for the user. The represented line may be used to provide a visual cue to the user of a virtual boundary in space, and may be used by the system to determine transitions in the state of the computer for the user, including determining when the user wishes to collaborate with the computer.

[0110] In some embodiments, the computer is operative to detect the user's position and interpret the user's hand movements through a virtual boundary as gestures indicating the user's intent to collaborate with the computer, in some embodiments, as the user passes through a virtual line or surface, the light generated by the light generating unit changes, thereby providing visual feedback to the user that they have entered an area for making a gesture to provide input to the computer.

[0111] The display screen may provide a visual indication of the transition of states of the computing system to a user. In some embodiments, a first screen is provided in a first state in which the presence of a user is detected by the system, for example through the use of one or more of the sensing elements.

[0112] In some implementations, the system operates to detect the identity of the user, for example by facial recognition, where a transition to a second screen may be provided in a second state where the computing system recognizes the identity of the user, and where the second screen provides visual feedback to the user that the user has appeared in the new state, and a transition to a third screen may occur in a third state where the user confirms the user's recognition.

[0113] In some embodiments, the computing system may use a transition mechanism to determine the location of the virtual boundary for the user, and the location of the virtual boundary may change depending on the user and the context. The computing system may generate a light, such as an illumination line, to indicate the virtual boundary for interacting with the system. In some embodiments, the computing system may be in a standby state and the light may be generated in a first color. The computing system may detect whether the user has passed the virtual boundary, for example, by detecting the presence and movement of the user using a sensing element.

[0114] In some embodiments, when a user is detected to have crossed the virtual boundary (e.g., the user's hand is closer to the computing system than the virtual boundary line), the computing system may transition to a state in which it receives gesture input from the user, where the mechanism for indicating the transition may include a light indicating the virtual boundary changing to a second color.

[0115] In some embodiments, the computing system may then determine whether a gestural motion is detected, and if so, the computing system may proceed with a gesture recognition process, which may include the use of data from a gesture data library, which may reside in memory within the computing system or may be otherwise accessed by the computing device.

[0116] If the user's gesture is recognized, the computing system may perform a function in response to the input and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not recognized, the computing system may transition to an error state. The mechanism for indicating the error state may include a light indicating the virtual boundary changing to a third color. The system returns to receive additional gestures if the user is within the virtual boundary to collaborate with the computing system.

[0117] As mentioned above, in other embodiments, the system may be configured as a convertible tablet system usable in at least two different modes: tablet mode and notebook mode. The convertible system may include two panels, a display panel and a base panel, such that in tablet mode the two panels are arranged on top of each other. In tablet mode, the display panel faces outward and may provide touch screen functionality as found on traditional tablets. In notebook mode, the two panels may be arranged in an open clamshell configuration.

[0118] In various embodiments, the accelerometer may be a three-axis accelerometer with a data rate of at least 50 Hz. A gyroscope may also be included, which may be a three-axis gyroscope. Additionally, an electronic compass / magnetometer may be present. One or more proximity sensors may also be provided (e.g., when the lid is open, to detect if a person is approaching (or not) the system and adjust power / performance to extend battery life). With regard to Sensor Fusion in an OS, the ability to include an accelerometer, gyroscope, and compass may provide expanded functionality. Additionally, a sensor hub with a real-time clock (RTC) may provide wake-up from the sensor mechanism to receive sensor inputs when the rest of the system is in a low power state.

[0119] In some embodiments, an internal lid / display can be used to open a switch or sensor to indicate the lid is closed / open, put the system into Connected Standby, or automatically wake up from Connected Standby. Other system sensors can include an internal processor, memory, and an ACPI sensor for skin temperature monitoring to enable changes in the processor and system operating state based on sensed parameters.

[0120] In an embodiment, the OS may be Microsoft's Windows 8 OS that implements Connected Standby (also referred to herein as Win8 CS). Win8 CS or other OS with similar states may provide very low ultra-idle power with the platform described herein to allow applications to remain connected, for example to a cloud-based location, with very low power consumption. The platform may support three power states: screen on (normal), connected standby (default "off" state), and shutdown (zero watt power consumption). Thus, in the connected standby state, the platform is logically on (at the lowest power level) even if the screen is off. In such a platform, power management is done to be transparent to applications and may maintain constant connectivity due in part to offloading techniques that allow low-power components to perform operations.

[0121] Referring to diagram 1300 of FIG. 13, an example link training state machine, such as a PCIe Link Training and Status State Machine (LTSSM), is shown. FIG. 13 is a schematic diagram illustrating an example link training state machine, in accordance with an embodiment of the present disclosure. In a system utilizing a PHY according to a particular protocol to support multiple alternative protocols (i.e., to run on top of the PHY), ordered sets may be defined that are to be communicated between two or more devices on the link in association with training the link. For example, training set (TS) ordered sets (OSes) may be sent. In an implementation utilizing PCIe as the PHY protocol, the TS ordered sets may include, among others, TS1 and TS2 ordered sets. The ordered sets and training sequences sent during link training may be based on a particular link training state, with various training states being utilized to accomplish corresponding link training activities and objectives.

[0122] Link training state machine 1300 may represent a link training and state status machine (LTSSM) that represents various states of a multi-lane link, such as one based on a PCIe protocol. In one example as depicted in FIG. 13, link training state machine 1300 may include states such as, among others, a Reset state, a Detect state (e.g., to detect far-end termination (e.g., other devices connected to the lanes)), a Polling state (e.g., to establish symbol lock and set lane polarity), a Configuration or Config state (e.g., to configure the physical lanes of the connection to the link with a particular lane width, lane numbering, etc., while performing lane-to-lane deskew and other link configuration activities), a Loopback state (e.g., to perform testing, fault isolation, equalization, and other tasks), a Recovery state (e.g., used to change the data rate of operation, re-establish bit lock, symbol lock or block alignment, perform lane-to-lane deskew, etc.), and may be utilized to bring the link into an active link state (e.g., L0). The LTSSM 1300 also represents various power states: a fully active state (LO), an electrical idle or standby state (LOs), an L1 (low power standby / dormant state), an L2 (low power sleep state), and an L3 (link off state). The LTSSM 1300 also represents a partial L0 (PL0) state, which are sub-states described herein.

[0123] In one example, the training sequence sent in a particular one (or more) of the link training states may be defined to accommodate negotiation of a particular one of the supported protocols of a particular device. For example, the particular training state may be a training state prior to entering an active link state, or a training state in which the data rate may be upscaled (e.g., beyond the rate supported by the particular one of the supported protocols), such as a PCIe state in which the data rate moves from Gen1 speeds to Gen3 or higher speeds, among others. For example, in the embodiment shown in FIG. 13, the configuration state may be utilized and augmented to enable negotiation of a particular one of multiple protocols in parallel with the link training activities (e.g., lane width determination, lane numbering, deskew, equalization, etc.) originally defined in the training state. For example, a specific training sequence may be defined for the training state, and such training sequence may be augmented to enable information to be communicated (e.g., in one or more fields or symbols of the ordered set) to identify whether each device on the link supports multiple protocols (e.g., at least one protocol stack other than the physical layer protocol stack and corresponding link training state machine), to identify the specific protocols that each device supports, and to agree on one or more protocols for use over a particular PHY (e.g., through a handshake achieved through the transmission of such training sequences across the link (in both the upstream and downstream directions)).

[0124] In one example, a PCIe physical layer may be utilized to support multiple different protocols. Thus, a specific training state in the PCIe LTSSM may be utilized for negotiation of protocols between devices on the link. As described above, the protocol decision may be made even before the link trains to an active state (e.g., L0) at the lowest supported data rate (e.g., PCIe Gen1 data rate). In one example, the PCIe Config state may be used. In fact, the PCIe LTSSM may be used to negotiate protocols by using modified PCIe training sets (e.g., TS1 and TS2) after link width negotiation and in parallel (at least partially) with the lane numbering performed during the Config state.

[0125] While the present disclosure has been described with respect to a limited number of embodiments, numerous modifications and variations therefrom will be apparent to those skilled in the art, and it is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the present disclosure.

[0126] A design may go through various stages from creation to simulation to manufacturing. Data representing the design may represent the design in several ways. First, the hardware may be represented using a hardware description language or another functional description language to aid in simulation. Furthermore, a circuit level model with logic and / or transistor gates may be created at some stage of the design process. Furthermore, most designs reach a data level at some stage that represents the physical placement of various devices within the hardware model. If conventional semiconductor manufacturing techniques are used, the data representing the hardware model may be data specifying the presence or absence of various features on different mask layers for a mask used to manufacture the integrated circuit. In any representation of the design, the data may be stored on any form of machine-readable medium. Memory, or magnetic or optical storage such as a disk, may be machine-readable media for storing such information transmitted via light or radio waves modulated or otherwise generated to carry the information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent copying, buffering, or retransmission of the electrical signal is performed, a new copy is made. Thus, a communications provider or network provider may at least temporarily store on a tangible, machine-readable medium something that embodies the techniques of embodiments of the present disclosure, such as information encoded on a carrier wave.

[0127] A module, as used herein, refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller associated with a non-transitory medium for storing code adapted to be executed by the microcontroller. Thus, in one embodiment, reference to a module refers to hardware that is specifically configured to recognize and / or execute code held on the non-transitory medium. Furthermore, in other embodiments, use of a module refers to a non-transitory medium that includes code that is specifically adapted to be executed by a microcontroller to perform a predetermined operation. And as can be inferred, in still other embodiments, the term module (in this example) may refer to a combination of a microcontroller and a non-transitory medium. In many cases, module boundaries that are shown separately will generally differ and may overlap. For example, a first and second module may share hardware, software, firmware, or a combination thereof, while potentially having some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0128] Use of the phrases "to" or "configured to" in one embodiment refers to arranging, placing together, manufacturing, marketing, importing, and / or designing an apparatus, hardware, logic, or element to perform a designed or determined task. In this example, an apparatus or element thereof that is not in operation is still 'configured to' perform a task for which it is designed, coupled, and / or interconnected. Purely by way of example, a logic gate may provide a 0 or a 1 during operation. However, a logic gate 'configured to' provide an enable signal to a clock does not include any possible logic gate that may provide a 1 or a 0. Instead, the logic gate is one that is coupled in some way such that a 1 or 0 output should enable the clock during operation. Again, note that use of the term "configured to" does not require operation, but instead focuses on potential states of the apparatus, hardware, and / or elements in which the apparatus, hardware, and / or elements are designed to perform a particular task when the apparatus, hardware, and / or elements are in operation.

[0129] Additionally, the use of the phrases "capable of / to" and / or "operable to" in one embodiment refers to any device, logic, hardware, and / or element that is designed to enable use of the device, logic, hardware, and / or element in a particular manner. As noted above, the use of "capable of / to" and / or "operable to" in one embodiment refers to the underlying state of the device, logic, hardware, and / or element, where the device, logic, hardware, and / or element is not operational, but is designed to enable use of the device in a particular manner.

[0130] Value, as used herein, includes any known representation of a number, state, logical state, or binary logical state. Often the use of logic levels, logic values, or logical values ​​are also referred to simply as 1 and 0 to represent binary logic states. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values ​​have been used in computer systems. For example, the decimal number 10 may be represented as a binary value of 1010 and the letter A in hexadecimal. Thus, value includes any representation of information that can be held in a computer system.

[0131] Additionally, a state may be represented by a value or a portion of a value. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. Additionally, the terms "reset" and "set" refer, in one embodiment, to default and updated values ​​or states, respectively. For example, a default value potentially includes a high logical value, i.e., reset, while an updated value potentially includes a low logical value, i.e., set. It should be noted that any combination of values ​​may be utilized to represent any number of states.

[0132] The above method, hardware, software, firmware or code embodiments may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible or computer-readable medium that is executable by a processing element. A non-transitory machine-accessible / readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, non-transitory machine-accessible media include random access memory (DRAM), such as static RAM (SRAM) or dynamic RAM (DRAM), ROM, magnetic or optical storage media, flash memory devices, electrical storage devices, optical storage devices, acoustic storage devices, other forms of storage devices for holding information received from a transitory (propagated) signal (e.g., carrier wave, infrared signal, digital signal), etc. Also, signals should be distributed from a non-transitory medium that can receive information from them.

[0133] The instructions used to program the logic to execute the embodiments of the present disclosure may be stored in a memory in the system, such as a DRAM, cache, flash memory, or other storage. Additionally, the instructions may be distributed over a network or by other computer-readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including, without limitation, a floppy diskette, an optical disk, a compact diskette-type read-only memory (CD-ROM), and an optical magnetic disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic or optical card, a flash memory, or a tangible machine-readable storage used in transmitting information over the Internet via an electrical, optical, acoustic, or other form of propagated signal (e.g., carrier wave, infrared signal, digital signal, etc.). Accordingly, computer-readable media includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0134] References herein to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0135] In the foregoing specification, the detailed description has been given with reference to specific exemplary embodiments. It will be apparent, however, that various improvements and modifications may be made therein without departing from the broad spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings should accordingly be regarded in an illustrative and not a limiting sense. Moreover, the above use of embodiments and other exemplary language does not necessarily refer to the same embodiment or the same example, but may potentially refer to different embodiments in addition to the same embodiment.

[0136] Various aspects and combinations of embodiments have been described above, some of which are illustrated by the following examples.

[0137] Example 1 is an apparatus that includes a physical layer (PHY). The PHY can support multiple interconnect protocols. The PHY can include a logical PHY that supports the multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol and a second set of CRC encoders corresponding to a second interconnect protocol. The PHY can include a multiplexer that directs data to the first set of CRC encoders or the second set of CRC encoders based on a selected interconnect protocol.

[0138] Example 2 may include the subject matter of example 1, wherein the logical PHY has a CRC encoder bypass.

[0139] Example 3 may include any of the subject matter of examples 1-2, and may further include a first set of cyclic redundancy check (CRC) decoders corresponding to the first interconnect protocol and a second set of CRC decoders corresponding to the second interconnect protocol, wherein a multiplexer directs data to either the first set of CRC decoders or the second set of CRC decoders based on the selected interconnect protocol.

[0140] Example 4 may include the subject matter of example 3, wherein the logical PHY has a CRC decoder bypass.

[0141] Example 5 may include the subject matter of any of examples 1-3, and may further include a first set of error correction code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol, wherein a multiplexer directs data to the first set of ECC encoders or the second set of ECC encoders based on the selected interconnect protocol.

[0142] Example 6 may include the subject matter of example 5, wherein the logical PHY has an ECC encoder bypass.

[0143] Example 7 can include the subject matter of example 5, and can further include a first set of error correcting code (ECC) decoders corresponding to the first interconnect protocol and a second set of ECC decoders corresponding to the second interconnect protocol, wherein a multiplexer directs data to the first set of ECC decoders or the second set of ECC decoders based on the selected interconnect protocol.

[0144] Example 8 may include the aspect of example 7, wherein the logical PHY has an ECC decoder bypass.

[0145] Example 9 may include the subject matter of any of examples 1 or 5, and may further include an error log that records uncorrectable errors identified by the CRC decoder or by the ECC decoder.

[0146] Example 10 may include the subject matter of any of Examples 1-9, and may further include a first buffer for buffering a first blit of a first size corresponding to a flit size associated with the first interconnect protocol, and a second buffer for buffering a second flit of a second size corresponding to a flit size associated with the second interconnect protocol.

[0147] Example 11 may include the subject matter of any of Examples 1-10, wherein the first interconnect protocol or the second interconnect protocol comprises one of a Peripheral Component Interconnect Express (PCIe) protocol, a Compute Express Link (CXL) protocol, or an UltraPath Interconnect (UPI) protocol.

[0148] Example 12 is a method that includes identifying, by a physical layer multiplexer, an interconnect protocol from a plurality of interconnect protocols in which to operate the link; identifying a first set of cyclic redundancy check (CRC) encoders from a plurality of sets of CRC encoders based on the identified interconnect protocol; and directing data traffic to the first set of CRC encoders by the multiplexer.

[0149] Example 13 may include the subject matter of example 12, and may further include receiving a request to change the first set of CRC encoders to the second set of CRC encoders, moving the link to a restored state, selecting the second set of CRC encoders, directing data traffic to the second set of CRC encoders, and moving the link to an active state.

[0150] Example 14 may include the subject matter of any of Examples 12-13, and may further include identifying a first set of error correcting code (ECC) encoders from a plurality of sets of ECC encoders based on the identified interconnect protocol, and directing data traffic to the first set of ECC encoders.

[0151] Example 15 may include the subject matter of example 14, and may further include receiving a request to change the first set of ECC encoders to a second set of ECC encoders, moving the link to a recovered state, selecting the second set of ECC encoders, directing data traffic to the second set of ECC encoders, and moving the link to an active state.

[0152] Example 16 may include the subject matter of example 15, and may further include receiving a request to change the first set of CRC encoders to a second set of CRC encoders, moving the link to a restored state, selecting the second set of CRC encoders, directing data traffic to the second set of CRC encoders, and moving the link to an active state.

[0153] Example 17 may include the subject matter of example 14, wherein the link operates in an active state at a first bandwidth, and the method may further include receiving an indication that the link is capable of operating at a second bandwidth lower than the first bandwidth, receiving an indication that the link is capable of operating at the second bandwidth without forward error correction (FEC), transitioning the link to a recovery state, bypassing the first set of ECC encoders, and transitioning the link to the active state.

[0154] Example 18 may include the subject matter of any of Examples 12-17, wherein the interconnect protocol comprises one of a Peripheral Component Interconnect Express (PCIe) protocol, a Compute Express Link (CXL) protocol, or an UltraPath Interconnect (UPI) protocol.

[0155] Example 19 is a system including a host device and an endpoint device. The host device can include a processor core and a transmitting physical layer (PHY). The transmitting PHY can include a transmitting logical PHY supporting multiple interconnect protocols. The transmitting logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol and a second set of CRC encoders corresponding to a second interconnect protocol. The transmitting PHY can include a transmitting multiplexer that directs data to the first set of CRC encoders or to the second set of CRC encoders based on a selected interconnect protocol. The endpoint device can include a receiving PHY including a receiving logical PHY, the receiving logical PHY supporting multiple interconnect protocols including the first interconnect protocol and the second interconnect protocol. The receiving logical PHY can include a first set of cyclic redundancy check (CRC) decoders corresponding to the first interconnect protocol and a second set of CRC decoders corresponding to the second interconnect protocol. The receiving multiplexer can direct the data to either the first set of CRC decoders or the second set of CRC decoders based on the selected interconnect protocol.

[0156] Example 20 may include the subject matter of example 19, wherein the transmitting logic PHY receives a request to change from the first set of CRC encoders to the second set of CRC encoders, transitions a link operated by the selected interconnect protocol to a recovered state, selects the second set of CRC encoders, directs data traffic to the second set of CRC encoders, and transitions the link to an active state; and the receiving logic PHY selects the second set of CRC decoders and directs data traffic to the second set of CRC decoders.

[0157] Example 21 may include any of the subject matter of examples 19-20, where the transmitting logic PHY may include a first set of error correcting code (ECC) encoders corresponding to a first interconnect protocol and a second set of ECC encoders corresponding to a second interconnect protocol. The transmitting multiplexer directs data to the first set of ECC encoders or to the second set of ECC encoders based on the selected interconnect protocol. The receiving logic PHY may include a first set of error correcting code (ECC) decoders corresponding to the first interconnect protocol and a second set of ECC decoders corresponding to the second interconnect protocol. The receiving multiplexer directs data to the first set of ECC decoders or to the second set of ECC decoders based on the selected interconnect protocol.

[0158] Example 22 may include the subject matter of any of Examples 19-21, wherein the receiving PHY further comprises an error log that records uncorrectable errors identified by the ECC decoder and the CRC decoder.

[0159] Example 23 may include the subject matter of example 21, wherein the transmitting logic PHY receives a request to change from the first set of ECC encoders to the second set of ECC encoders, transitions a link operated by the selected interconnect protocol to a recovered state, selects the second set of ECC encoders, directs data traffic to the second set of ECC encoders, and transitions the link to an active state; and the receiving logic PHY selects the second set of ECC decoders and directs data traffic to the second set of ECC decoders.

[0160] Example 24 may include the subject matter of any of examples 19-23, wherein the transmitting logical PHY has an ECC encoder bypass and the receiving logical PHY has an ECC decoder bypass.

[0161] Example 25 may include the subject matter of any of Examples 19-24, wherein the transmitting logical PHY has a CRC encoder bypass and the receiving logical PHY has a CRC decoder bypass.

[0162] Example 26 may include the subject matter of any of Examples 19-25, wherein the first interconnect protocol or the second interconnect protocol comprises one of a Peripheral Component Interconnect Express (PCIe) protocol, a Compute Express Link (CXL) protocol, or an UltraPath Interconnect (UPI) protocol.

[0163] Example 27 may include the subject matter of example 1, wherein the apparatus is coupled to a plurality of devices via links, and the PHY supports a plurality of interconnect protocols, and the PHY can support different combinations of FEC / CRC depending on link characteristics for each of the connected devices and for each protocol used by each device.

[0164] Example 28 may include the subject matter of example 5, wherein the PHY has a first combination of an ECC encoder and a CRC encoder corresponding to a first interconnect protocol supported by the PHY and a second combination of an ECC encoder and a CRC encoder corresponding to a second interconnect protocol supported by the PHY.

[0165] Example 29 may include the subject matter of example 18, wherein the transmitting logical PHY has a first combination of an ECC encoder and a CRC encoder corresponding to a first interconnect protocol supported by the transmitting logical PHY and a second combination of an ECC encoder and a CRC encoder corresponding to a second interconnect protocol supported by the transmitting logical PHY.

[0166] Example 30 may include the subject matter of any of examples 18 or 29, wherein the receiving logical PHY has a first combination of an ECC encoder and a CRC encoder corresponding to a first interconnect protocol supported by the receiving logical PHY and a second combination of an ECC encoder and a CRC encoder corresponding to a second interconnect protocol supported by the receiving logical PHY.

[0167] Example 31 may include the subject of any of examples 1, 11, or 18, and wherein the flit size of the payload may depend on the number of bits used for FEC and CRC (0 if there is no FEC).

[0168] [CROSS REFERENCE TO RELATED APPLICATIONS] Pursuant to 35 U.S.C. § 119(e), this application claims the benefit of U.S. Provisional Application No. 62 / 941,445, filed November 27, 2019, entitled "MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER IN CONSIDERATION OF MODULATION WITH MULTIPLE FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK (CRC) CODES," the entire contents of which are incorporated herein by reference. [Explanation of symbols]

[0169] 100 processors 101,102 cores 300 Common PHY 302 Physical PHY 304 Logic PHY 306,400 Sender Logical Sub-Blocks 308,500 Receiver Logical Sub-Blocks 312 Idle Flit Generation Unit 314,404,410 CRC Encoder 316 FEC Encoder 318,330 Lane Reversal 320,328 LFSR 322,324 Symbol Alignment 326 Elastic / Drift Buffer 332 FEC Decoder 334,510,516 CRC Decoder 336 Error Reporting Element 406,408 Rolling CRC Encoder 414,416,418 ECC Encoder 504,506,508 ECC Decoder 512,514 Rolling CRC Decoder 518 Error Log 800 Protocol Stack 805 Transaction Layer 810 Link Layer 820 Physical Layer

Claims

1. A physical layer that supports multiple interconnect protocols; The physical layer includes: a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol supported by the physical layer; a second set of CRC encoders corresponding to a second interconnect protocol supported by the physical layer; and a multiplexer that directs data to the first set of CRC encoders or to the second set of CRC encoders based on a selected interconnect protocol; having Device.

2. The physical layer includes a CRC encoder bypass.

2. The apparatus of claim 1.

3. The physical layer comprises: a first set of cyclic redundancy check (CRC) decoders corresponding to the first interconnect protocol; a second set of CRC decoders corresponding to the second interconnect protocol; and Further comprising: the multiplexer directs data to the first set of CRC decoders or to the second set of CRC decoders based on the selected interconnect protocol.

3. Apparatus according to claim 1 or 2.

4. the physical layer includes a CRC decoder bypass; 4. The apparatus of claim 3.

5. The physical layer comprises: a first set of error correction code (ECC) encoders corresponding to the first interconnect protocol; a second set of ECC encoders corresponding to the second interconnect protocol; and Further comprising: the multiplexer directs data to the first set of ECC encoders or to the second set of ECC encoders based on the selected interconnect protocol.

2. The apparatus of claim 1.

6. the physical layer includes an ECC encoder bypass; 6. The apparatus of claim 5.

7. The physical layer comprises: a first set of error correcting code (ECC) decoders corresponding to the first interconnect protocol; a second set of ECC decoders corresponding to the second interconnect protocol; and Further comprising: the multiplexer directs data to the first set of ECC decoders or to the second set of ECC decoders based on the selected interconnect protocol.

6. The apparatus of claim 5.

8. The physical layer further comprises an error log that records errors identified by the CRC decoder or by the ECC decoder.

6. The apparatus of claim 5.

9. the physical layer having a first combination of an ECC encoder and a CRC encoder corresponding to the first interconnect protocol supported by the physical layer and a second combination of an ECC encoder and a CRC encoder corresponding to the second interconnect protocol supported by the physical layer.

6. The apparatus of claim 5.

10. The physical layer comprises: a first buffer for buffering first flits of a first size corresponding to a flit size associated with the first interconnect protocol; a second buffer for buffering second flits of a second size corresponding to a flit size associated with the second interconnect protocol; Further comprising 2. The apparatus of claim 1.

11. identifying an interconnect protocol for operating the link from among a plurality of interconnect protocols by a physical layer multiplexer; identifying a first set of cyclic redundancy check (CRC) encoders from a plurality of sets of CRC encoders based on the identified interconnect protocol; directing data traffic through said multiplexer to a first set of said CRC encoders; The method according to claim 1,

12. receiving a request to change the first set of CRC encoders to a second set of CRC encoders; transitioning the link from an active state to a recovery state; selecting a second set of CRC encoders; directing data traffic to a second set of CRC encoders; transitioning said link to said active state; Further comprising The method of claim 11.

13. identifying a first set of error correcting code (ECC) encoders from a plurality of sets of ECC encoders based on the identified interconnect protocol; directing data traffic to a first set of ECC encoders; Further comprising The method of claim 11.

14. receiving a request to change the first set of ECC encoders to a second set of ECC encoders; transitioning the link from an active state to a recovery state; selecting a second set of ECC encoders; directing data traffic to a second set of ECC encoders; transitioning said link to said active state; Further comprising The method of claim 13.

15. receiving a request to change the first set of CRC encoders to a second set of CRC encoders; transitioning the link from an active state to a recovery state; selecting a second set of CRC encoders; directing data traffic to a second set of CRC encoders; transitioning said link to said active state; Further comprising The method of claim 14.

16. the link operates in an active state at a first bandwidth; The method comprises: receiving an indication that the link is capable of operating at a second bandwidth that is lower than the first bandwidth; receiving an indication that the link is capable of operating at the second bandwidth without forward error correction (FEC); transitioning the link from the active state to a recovery state; bypassing a first set of the ECC encoders; transitioning said link to said active state; Further comprising The method of claim 13.

17. the interconnect protocol comprises one of a Peripheral Component Interconnect Express (PCIe) protocol, a Compute Express Link (CXL) protocol, or an UltraPath Interconnect (UPI) protocol; The method of claim 11.

18. A host device and an end device, the host device has a processor core and a transmitting physical layer; the transmitting physical layer has a transmitting logical sub-block supporting multiple interconnect protocols; The sending logical sub-block: a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol supported by the transmitting physical layer; a second set of CRC encoders corresponding to a second interconnect protocol supported by the transmitting physical layer; and a sender multiplexer that directs data to the first set of CRC encoders or to the second set of CRC encoders based on a selected interconnect protocol; having The end device has a receiving physical layer; the receiving physical layer has a receiving logical sub-block supporting a plurality of interconnect protocols including the first interconnect protocol and the second interconnect protocol; The receiving logical sub-block comprises: a first set of cyclic redundancy check (CRC) decoders corresponding to the first interconnect protocol; a second set of CRC decoders corresponding to the second interconnect protocol; a receive multiplexer that directs data to the first set of CRC decoders or to the second set of CRC decoders based on the selected interconnect protocol; having system.

19. The sending logical sub-block: receiving a request to change the first set of CRC encoders to the second set of CRC encoders; transitioning a link operated by the selected interconnect protocol from an active state to a recovery state; Selecting a second set of CRC encoders; directing data traffic to a second set of said CRC encoders; moving the link to the active state; The receiving logical sub-block comprises: selecting a second set of CRC decoders; directing data traffic to a second set of said CRC decoders; 20. The system of claim 18.

20. The sending logical sub-block: a first set of error correction code (ECC) encoders corresponding to the first interconnect protocol; a second set of ECC encoders corresponding to the second interconnect protocol; and Further comprising: the sender multiplexer directs data to the first set of ECC encoders or to the second set of ECC encoders based on the selected interconnect protocol; The receiving logical sub-block comprises: a first set of error correcting code (ECC) decoders corresponding to the first interconnect protocol; a second set of ECC decoders corresponding to the second interconnect protocol; and Further comprising: the receiving multiplexer directs data to the first set of ECC decoders or to the second set of ECC decoders based on the selected interconnect protocol.

20. A system according to claim 18 or 19.

21. the receiving logic sub-block further comprises an error log for recording uncorrectable errors identified by the ECC decoder and the CRC decoder.

21. The system of claim 20.

22. The sending logical sub-block: receiving a request to change the first set of ECC encoders to the second set of ECC encoders; transitioning a link operated by the selected interconnect protocol from an active state to a recovery state; selecting a second set of the ECC encoders; directing data traffic to a second set of ECC encoders; moving the link to the active state; The receiving logical sub-block comprises: selecting a second set of the ECC decoders; directing data traffic to a second set of said ECC decoders; 21. The system of claim 20.

23. the sending logical sub-block has an ECC encoder bypass; the receiving side logic sub-block has an ECC decoder bypass; 21. The system of claim 20.

24. the transmitting logical sub-block includes a CRC encoder bypass; the receiving logic sub-block includes a CRC decoder bypass; 20. The system of claim 18.

25. the first interconnect protocol or the second interconnect protocol comprises one of a Peripheral Component Interconnect Express (PCIe) protocol, a Compute Express Link (CXL) protocol, or an UltraPath Interconnect (UPI) protocol; 20. The system of claim 18.

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