Memory System

Abstract

To suppress deterioration in data access performance in a memory system.SOLUTION: A memory system 100 is a memory system composed of a semiconductor memory device 120 and a memory controller 110. The memory controller issues an active command including a bank number designation section, a bank address section, and a row address section to the semiconductor memory device. When the active command designates to activate two banks, the semiconductor memory device activates a first row and a second row. When the active command designates to activate one bank, the semiconductor memory device activates the first row of the first and second rows.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to memory systems. [Background technology]

[0002] DDR4 and LPDDR5 having multiple bank groups are sometimes used as semiconductor memory devices. In such semiconductor memory devices, when active commands are issued consecutively to two banks belonging to different bank groups, the interval that must be provided between the issuance of two active commands can be shortened (Non-Patent Document 1, Non-Patent Document 2). Therefore, active commands and read / write commands can be issued consecutively without creating an empty cycle on the command bus. [Prior art documents] [Patent documents]

[0003] [Non-Patent Document 1] JEDEC STANDARD DDR4 SDRAM JESD79-4B, JUNE 2017 [Non-Patent Document 2] JEDEC STANDARD Low Power Double Data Rate 5(LPDDR5)JESD209-4A,JANUARY 2020 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the active command and the read / write command are issued successively, there are no free cycles of the command bus for issuing other commands necessary for the operation of the memory system, such as a refresh command, a precharge command, etc. If the issuance of the active command and the read / write command is postponed in order to issue the refresh command or the precharge command, there is a problem that the data access performance of the semiconductor memory device is degraded. [Means for solving the problem]

[0005] The present disclosure can be realized in the following forms.

[0006] According to one embodiment of the present disclosure, there is provided a memory system (100) including a semiconductor memory device (120) having a plurality of bank groups, and a memory controller (110) that issues a command in response to an access request to the semiconductor memory device from an arithmetic device (200) that accesses the semiconductor memory device, wherein the memory controller issues an active command to the semiconductor memory device, the active command including a bank number designation section that is a bit string that designates whether one bank or two banks are to be activated, a bank address section that is a bit string that determines the address of a bank to be accessed, and a row address section that is a bit string that determines the row address of the bank to be accessed; When the active command specifies that two banks are to be made active, the semiconductor memory device activates a first row which belongs to a first bank specified by the bank address and is a row specified by the row address, and a second row which belongs to a second bank specified by a bank address obtained by inverting an inversion target bit, which is any one bit in a bit string defining a bank group in the bank address section, and is a row specified by the row address section; when the active command specifies that one bank is to be made active, the semiconductor memory device activates the first row of the first row and the second row. According to this memory system, by activating two banks, the first bank and the second bank, with one active command, it is possible to reduce the number of active commands issued and free up space on the command bus. This makes it possible to prevent delays in issuing active commands and read / write commands due to the issuance of refresh commands and precharge commands, and to prevent degradation of the data access performance of the semiconductor memory device. [Brief description of the drawings]

[0007] [Figure 1] 1 is an explanatory diagram showing a schematic configuration of a memory system according to an embodiment of the present invention; [Diagram 2] 11 is a flowchart showing the first half of a procedure of memory access processing in the present embodiment. [Diagram 3] 10 is a flowchart showing the latter half of the procedure of memory access processing in the present embodiment. [Figure 4] 1 is an explanatory diagram showing a method of converting an address from a logical address to a physical address in the present embodiment; [Diagram 5] 1 is an explanatory diagram showing a method of converting an address from a logical address to a physical address in the present embodiment; [Figure 6] 10 is a flowchart showing a procedure of an activation process in the present embodiment. [Figure 7] 4 is a timing chart showing an example of an operation of the memory system according to the present embodiment. [Figure 8] 4 is a timing chart showing an example of an operation of the memory system according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A. Embodiment: A1. System Configuration: 1, the memory system 100 of this embodiment includes a memory controller 110 and a semiconductor memory device 120. The memory system 100 executes reading and writing of data to the semiconductor memory device 120 via the memory controller 110 in response to an access request issued by an arithmetic device 200. The arithmetic device 200 corresponds to, for example, a CPU or a GPU (Graphics Processing Unit).

[0009] The memory controller 110 is connected to the arithmetic device 200 via a bus 10, and receives an access request to the semiconductor memory device 120 issued by the arithmetic device 200. The memory controller 110 is also connected to the semiconductor memory device 120 via a bus 20, and issues a command represented by a bit string to the semiconductor memory device 120 in response to the access request. The memory controller 110 issues the above-mentioned command in accordance with a clock signal that is the reference for the operation of the memory system 100. In addition, the memory controller 110 converts the logical address of the data to be accessed, which is included in the access request, into a physical address indicating the storage area on the semiconductor memory device 120 in which the data is stored, as will be described later.

[0010] When the access request is a write access request requesting writing of data to the semiconductor memory device 120, the memory controller 110 issues a write command to the semiconductor memory device 120 to instruct the semiconductor memory device 120 to write data to an address specified in the access request (hereinafter also referred to as an "access target address"). When the access request is a read access request requesting reading of data from the semiconductor memory device 120, the memory controller 110 issues a read command to the semiconductor memory device 120 to instruct the semiconductor memory device 120 to read data from the access target address. The write command and the read command each include a column address portion that specifies a column address of the access target address.

[0011] Before issuing a write command or a read command to the semiconductor memory device 120, the memory controller 110 issues an active command to the semiconductor memory device 120 in order to make the semiconductor memory device 120 accessible (hereinafter also referred to as "active"). The active command includes a bank number designation section, a bank address section, and a row address section. The bank number designation section is represented by 1 bit, and by setting the value of the bank number designation section to either 0 or 1, it is possible to designate whether the semiconductor memory device 120 activates one bank or two banks. In this embodiment, when the bank number designation section is 0, it designates that one bank is to be activated, and when it is 1, it designates that two banks are to be activated.

[0012] The bank address section specifies a bank address in the address to be accessed. In this embodiment, as described later, the number of banks in the semiconductor memory device 120 is 16, so the bank address is expressed by 4 bits. The upper 2 bits of the bank address indicate a bank group address.

[0013] The row address section stores a bit string that indicates the row address of the address to be accessed. Since the row address is several tens of bits, if the command bus width is insufficient, the row address may be divided into two and issued as two active commands.

[0014] The semiconductor memory device 120 is formed by arranging memory cells, which are storage elements, in a matrix, and data can be written to and read from each memory cell in response to a command issued by the memory controller 110. The semiconductor memory device 120 of this embodiment is LPDDR5, and includes bank groups BG0 to BG3. Each of the bank groups BG0 to BG3 includes four banks, with the bank group BG0 including banks B0 to B3, the bank group BG1 including banks B4 to B7, the bank group BG2 including banks B8 to B11, and the bank group BG3 including banks B12 to B15.

[0015] Upon receiving the active command, the semiconductor memory device 120 activates the address to be accessed specified by the bank address section and the row address section (hereinafter also referred to as "activation processing"). When the bank number designation section is 0, the semiconductor memory device 120 activates the first row, which belongs to the first bank designated by the bank address section and is the row designated by the row address section. When the bank number designation section is 1, the semiconductor memory device 120 activates the second row in addition to the first row. The second row means a row that belongs to the second bank determined by the bank address obtained by inverting the most significant bit (hereinafter also referred to as the "inversion target bit") of the bank address section and is determined by the row address section. The activation processing will be described in detail later.

[0016] The semiconductor memory device 120 receives a write command when active and stores and holds data in a column specified by the write command. Also, the semiconductor memory device 120 receives a read command when active and reads out data held in a column specified by the read command. By specifying a burst length in advance, the semiconductor memory device 120 can continuously output data of the burst length from a column specified by a write command or a read command.

[0017] A2.Memory access processing: The memory system 100 executes a memory access process to read and write data to the semiconductor memory device 120 in response to an access request issued by the arithmetic device 200. When executing two memory access processes, the memory system 100 may execute one memory access process in parallel with the execution of the other memory access process as long as the banks to be accessed are different from each other. The memory access process shown in FIG. 2 and FIG. 3 will be described by taking as an example a case where a read access request is issued from the arithmetic device 200. Note that even when a write access request is issued from the arithmetic device 200, the memory system 100 executes a similar memory access process.

[0018] 2, when a read access request is issued from the computing device 200, the memory controller 110 acquires an access target address of the read access request (step S110). The read access request may include multiple access target addresses.

[0019] The memory controller 110 converts the address to be accessed, which is expressed by a logical address, into a physical address (step S120). The conversion from the logical address to the physical address will be described using an example of the conversion into a physical address in which the row address and the column address are each expressed by 2 bits, as shown in FIG. 4. When converting the logical address into a physical address, the memory controller 110 determines the physical address by sequentially allocating the following from the least significant bit of the logical address: a bit (1 bit) corresponding to the inversion target bit of the bank address, a column address (2 bits), a bit string (3 bits) obtained by removing the bit corresponding to the inversion target bit of the bank address, and a row address (2 bits). The address conversion method is the same even if the number of bits representing the row address and the column address is increased. According to this address conversion method, for example, when consecutive logical addresses 0 to 5 are converted into physical addresses, data is alternately arranged in bank B0 (bank address: 0000) and bank B8 (bank address: 1000), which are two banks belonging to different bank groups, as shown in FIG. 5. In FIG. 5, the physical addresses determined when the logical addresses 0 to 5 are converted into physical addresses are indicated by hatching, and the order in which they are determined is indicated by numbers.

[0020] 2, the memory controller 110 sets 0 or 1 in the bank number designation section according to the access target address obtained by the address conversion, and issues an active command including the access target address expressed as a physical address to the semiconductor memory device 120 (step S130). When the access target address is an address for which a read command needs to be issued successively to the first row and the second row described above, the memory controller 110 sets 1 in the bank number designation section. On the other hand, when the access target address is an address for which a read command needs to be issued only to a single row, or an address for which a read command needs to be issued successively to the first row and another row different from the second row, the memory controller 110 sets 0 in the bank number designation section.

[0021] The semiconductor memory device 120 receives the active command and executes the activation process (step S140). As shown in Fig. 6, in the activation process, the semiconductor memory device 120 determines whether the bank number designation part of the received active command is 1 (step S210).

[0022] If the bank number designation section is 1 (step S210: Yes), the semiconductor memory device 120 activates the first row described above (step S220).

[0023] After the interval tRRD_S has elapsed since the issuance of the active command (step S230: Yes), the semiconductor memory device 120 activates the second row described above (step S240) and ends the activation process. The interval tRRD_S means the shortest interval during which two active commands can be issued consecutively to two banks belonging to different bank groups, as determined by the standard of the semiconductor memory device 120. The "interval" means the time between two commands and the period of the clock signal. If the interval tRRD_S has not elapsed (step S230: No), the semiconductor memory device 120 waits without executing step S240 until the interval tRRD_S has elapsed.

[0024] On the other hand, if the bank number designation section is not 1 (step S210: No), that is, if the bank number designation section is 0, the semiconductor memory device 120 activates only the first row of the first and second rows described above (step S222), and terminates the activation process.

[0025] After the activation process is completed, the memory controller 110 determines whether or not all active commands that satisfy the read access request have been issued (step S150), as shown in Fig. 2. If the issuance of the active commands has not been completed (step S150: No), the memory controller 110 executes step S130 again after the interval tRRD_S has elapsed since the previous active command was issued (step S152: Yes). If the interval tRRD_S has not elapsed since the previous active command was issued (step S152: No), the memory controller 110 waits without executing step S130 until the interval tRRD_S has elapsed.

[0026] After the issuance of the active command is completed (step S150: Yes), as shown in FIG. 3, the memory controller 110 issues a read command to the access target address determined by the active command after the interval tRCD_S has elapsed since the issuance of the active command (step S160: Yes) (step S170). The interval tRCD_S means the shortest interval until a read command can be issued after the issuance of an active command, which is determined by the standard of the semiconductor memory device 120. If the interval tRCD_S has not elapsed since the issuance of the first active command (step S160: No), the memory controller 110 waits without executing step S170 until the interval tRCD_S has elapsed.

[0027] The memory controller 110 judges whether or not the issuance of all read commands that satisfy the read access request has been completed (step S180). If the issuance of the read commands has not been completed (step S180: No), the memory controller 110 executes step S170 again after the interval tCCD_S has elapsed since the previous issuance of the read command (step S182: Yes). The interval tCCD_S means the shortest interval during which two read commands can be issued consecutively to two banks that belong to different bank groups, as determined by the standard of the semiconductor memory device 120. If the interval tCCD_S has not elapsed since the previous issuance of the active command (step S182: No), the memory controller 110 waits without executing step S170 until the interval tCCD_S has elapsed.

[0028] After the issuance of the read command is completed (step S180: Yes), in step S190, the semiconductor memory device 120 outputs data in response to the received read command. The semiconductor memory device 120 outputs the data after the interval CL has elapsed since the issuance of the read command. The interval CL means the interval from when the semiconductor memory device 120 receives the read command until when it outputs the data, which is determined by the standard of the semiconductor memory device 120. The output data is output to the calculation device 200 via the memory controller 110. After the completion of step S190, the memory system 100 ends the memory access process.

[0029] The memory access process described above will be described in more detail. Both Fig. 7 and Fig. 8 show an example in which a memory access process for performing read access to row a and row b and a memory access process for performing read access to row c and row d are performed in parallel. Each of the two memory access processes performs data output for two periods four times. Fig. 7 differs from Fig. 8 in that the active command shown in Fig. 7 specifies that one bank is made active, while the active command shown in Fig. 8 specifies that two banks are made active. In Fig. 7 and Fig. 8, the symbol attached to the active command A shown with hatching means that it is an active command A corresponding to the active command A with the same symbol that is divided into two. In addition, the symbol and number attached to the data D indicate that it is data output by the read command R with the same symbol and number.

[0030] 7, since only one bank is activated per one activation command, the memory controller 110 needs to issue one activation command each to row a, row b, row c, and row d. Therefore, there are cases where the command bus is full, such as in the periods T20 to T27.

[0031] 8, when the combination of Row a and Row b and the combination of Row c and Row d correspond to the combination of the first row and the second row described above, it is not necessary to issue an active command to the row corresponding to the second row. Therefore, the command bus can be vacated in the periods T6, T7, T25, and T27.

[0032] As described above, when the two rows to which access is performed correspond to the combination of the first row and the second row, as in the example shown in FIG. 8, it is possible to create space on the command bus, so that other commands necessary for the operation of memory system 100, such as a refresh command or a precharge command, can also be issued.

[0033] According to the memory system 100 of the embodiment described above, by making two banks, the first bank and the second bank, active with one active command, it is possible to reduce the number of active commands issued and create space on the command bus. This makes it possible to prevent delays in issuing active commands, read commands, and write commands due to the issuance of refresh commands and precharge commands, and to prevent degradation of the data access performance of the semiconductor memory device 120.

[0034] Furthermore, when converting a logical address into a physical address, the memory controller 110 determines the physical address by sequentially allocating the following bits from the least significant bit of the logical address: a bit to be inverted in the bank address, a column address, a bit string obtained by removing the bit to be inverted in the bank address, and a row address, so that data can be arranged alternately in the first bank and the second bank. This increases the probability of issuing commands alternately to the first bank and the second bank, further suppressing a decrease in the data access performance of the semiconductor memory device 120.

[0035] B. Other embodiments: (B1) In the above embodiment, the inversion target bit is the most significant bit of the bank address section, but the present disclosure is not limited to this. The inversion target bit may be a predetermined bit in a bit string that defines a bank group in the bank address section.

[0036] (B2) In the above embodiment, when converting a logical address to a physical address, the memory controller 110 determines the physical address by allocating, in order, from the least significant bit of the logical address, a bit corresponding to the inversion target bit in the bank address, a column address, a bit string obtained by excluding the bit corresponding to the inversion target bit in the bank address, and a row address, but the present disclosure is not limited to this. When converting a logical address to a physical address, the memory controller 110 may allocate, after the row address, a bit string obtained by excluding the bit corresponding to the inversion target bit in the bank address.

[0037] (B3) In the above embodiment, when two banks are activated, the semiconductor memory device 120 activates the first row and then the second row, but the present disclosure is not limited thereto. The semiconductor memory device 120 may activate the first row and then the second row.

[0038] The present disclosure is not limited to the above-mentioned embodiment, and can be realized in various configurations without departing from the spirit of the present disclosure. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention column can be appropriately replaced or combined in order to solve some or all of the above-mentioned problems or to achieve some or all of the above-mentioned effects. Furthermore, if the technical feature is not described as essential in this specification, it can be appropriately deleted.

[0039] The control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor and a memory programmed to execute one or more functions embodied in a computer program. Alternatively, the control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method described in the present disclosure may be realized by one or more special-purpose computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured with one or more hardware logic circuits. In addition, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions executed by a computer. [Explanation of symbols]

[0040] 100... memory system, 110... memory controller, 120... semiconductor memory device, 200... arithmetic unit

Claims

1. A memory system (100) comprising a semiconductor memory device (120) having a plurality of bank groups, and a memory controller (110) that issues a command in response to an access request to the semiconductor memory device from an arithmetic device (200) that accesses the semiconductor memory device, The memory controller includes: a bank number designation section which is a bit string designating whether one bank or two banks are to be made active; a bank address section which is a bit string that defines the address of a bank to be accessed; a row address portion which is a bit string that defines a row address to be accessed; to the semiconductor memory device; The semiconductor memory device comprises: (i) When the active command specifies that two banks are to be made active, a first row which belongs to a first bank determined by the bank address section and is determined by the row address section; a second row which belongs to a second bank determined by a bank address obtained by inverting a predetermined inversion target bit in a bit string that defines a bank group in the bank address section, and which is determined by the row address section; Activate the (ii) activating the first row of the first row and the second row when the active command specifies that one bank is to be activated; Memory system.

2. 2. The memory system of claim 1, The memory controller, when converting a logical address to a physical address, determining the physical address by allocating the logical address in the order of the least significant bit of the logical address, a bit corresponding to the inversion target bit in the bank address, a column address, a bit string obtained by excluding the bit corresponding to the inversion target bit in the bank address, and a row address; Memory system.

3. 3. The memory system according to claim 1, The semiconductor memory device comprises: when it is specified by the active command that two banks are to be made active, the first row is made active, and then, after a shortest interval during which the active command can be issued successively to a bank belonging to a bank group different from the bank group to which the first bank belongs, the second row is made active; Memory system.

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