Interface circuit capable of adjusting output impedance of transmission circuit and image sensor including the same

Abstract

To provide an interface circuit capable of adjusting output impedance of a transmission circuit.SOLUTION: An interface circuit includes: a first transmission circuit for outputting a first signal to a transmission line via first transfer pads; and a second transmission circuit for outputting a second signal to the transmission line via second transfer pads. The first transmission circuit includes a first termination resistor block including a first switch and a first termination resistor coupled in series between the first transfer pads. The second transmission circuit includes a second termination resistor block including a second switch and a second termination resistor coupled in series between the second transfer pads. When the first transmission circuit outputs the first signal to a reception circuit, the second termination resistor block detects the first signal. When the first transmission circuit is in a low-power operation mode, the second termination resistor block performs coupling cancellation of the second termination resistor. When the first transmission circuit is in a high-speed data transfer mode, the second termination resistor block performs coupling of the second termination resistor.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to an interface circuit and an image sensor including the same. [Background technology]

[0002] Integrated circuit chips included in electronic devices can transmit and receive data to each other through an interface device. For example, two integrated circuit chips communicating with each other can include respective interface devices. As the data processing capacity of electronic devices gradually increases, various standards capable of providing high-speed data communication between integrated circuit chips tend to be developed and / or proposed. In order to support impedance matching for accurate communication between integrated circuit chips, a receiving interface device that receives data can include a termination circuit. As the number of semiconductor devices connected to an electronic device increases, the semiconductor devices can share a transmission line to communicate with the integrated circuit chip. However, impedance matching between the semiconductor device and the integrated circuit chip may be insufficient, and high-speed data communication may not be performed accurately. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT EMBODIMENT It is an object of the present invention to provide an interface circuit capable of adjusting the output impedance of a transmission circuit, and an image sensor including the same. [Means for solving the problem]

[0004] According to an embodiment of the present invention, there is provided an interface circuit including a first transmission circuit for outputting a first signal to a transmission line via a first transmission pad, and a second transmission circuit for outputting a second signal to the transmission line via a second transmission pad, the first transmission circuit including a first termination resistor block including a first switch and a first termination resistor connected in series between the first transmission pads, the second transmission circuit including a second switch and a second termination resistor connected in series between the second transmission pads, when the first transmission circuit outputs the first signal, the second termination resistor block detects the first signal, and when it is detected that the first transmission circuit is in a low power operation mode, the second termination resistor block disconnects the second termination resistor between the second transmission pads, and when it is detected that the first transmission circuit is in a high speed data transmission mode, the second termination resistor block connects the second termination resistor between the second transmission pads.

[0005] In one embodiment of the present invention, an interface circuit including a first transmission circuit that transmits a differential signal to a transmission line via a transmission pad includes a transmitter that outputs the differential signal, and a termination resistor block that is connected between the transmission pad and adjusts an output impedance of the first transmission circuit, wherein the termination resistor block detects a low power signal sequence output from a second transmission circuit connected to the transmission line, and adjusts the output impedance of the first transmission circuit in response to the low power signal sequence.

[0006] In one embodiment of the present invention, an interface circuit including a first transmission circuit that transmits a signal to a transmission line via a transmission pad includes a transmitter that outputs the signal and a termination resistor block connected between the transmission pad, and when a second transmission circuit connected to the transmission line is in a low power operation mode, the output impedance of the first transmission circuit has high impedance (Hi-Z), and when the second transmission circuit is in a high-speed data transmission mode, the termination resistor block sets the output impedance of the first transmission circuit to a specified impedance different from the high impedance. Effect of the Invention

[0007] According to one embodiment of the present invention, an interface circuit adjusts the output impedance of a transmission circuit, thereby enabling high-speed data communication while multiple image sensors share a transmission line.

[0008] The various yet significant advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a simplified configuration of an electronic device according to an embodiment of the present invention; [Diagram 2] 1 is a diagram illustrating a camera module including an image sensor according to an embodiment of the present invention; [Diagram 3] 1 is a diagram provided to explain data communication in an electronic device according to an embodiment of the present invention; [Figure 4] FIG. 1 is a block diagram of a comparative example provided to explain an electronic device according to an embodiment of the present invention. [Diagram 5] FIG. 1 is a block diagram of a comparative example provided to explain an electronic device according to an embodiment of the present invention. [Figure 6] 1 is a block diagram provided to explain an electronic device according to an embodiment of the present invention; [Figure 7a] 4 is a block diagram for explaining an operation method of an interface circuit according to an embodiment of the present invention; FIG. [Figure 7b] 4 is a block diagram for explaining an operation method of an interface circuit according to an embodiment of the present invention; FIG. [Figure 8a] 4 is a block diagram for explaining an operation method of an interface circuit according to an embodiment of the present invention; FIG. [Figure 8b] 4 is a block diagram for explaining an operation method of an interface circuit according to an embodiment of the present invention; FIG. [Figure 9]4 is a diagram illustrating an operation of a termination resistor block according to an embodiment of the present invention; [Figure 10] 4 is a diagram illustrating an operation of a termination resistor block according to an embodiment of the present invention; [Figure 11] 4 is a diagram illustrating an operation of a termination resistor block according to an embodiment of the present invention; [Figure 12] 4 is a diagram illustrating an operation of a termination resistor block according to an embodiment of the present invention; [Figure 13] 1 shows an eye diagram provided to explain an interface circuit according to an embodiment of the present invention. [Figure 14] 2 is a circuit diagram for explaining the operation of an interface circuit according to an embodiment of the present invention; [Figure 15a] 2 is a circuit diagram for explaining the operation of an interface circuit according to an embodiment of the present invention; [Figure 15b] 2 is a circuit diagram for explaining the operation of an interface circuit according to an embodiment of the present invention; [Figure 15c] 2 is a circuit diagram for explaining the operation of an interface circuit according to an embodiment of the present invention; [Figure 16] 4 illustrates a timing diagram of the operation of an interface according to an embodiment of the present invention. [Figure 17] 4 illustrates a timing diagram of the operation of an interface according to an embodiment of the present invention. [Figure 18] 1 is a diagram illustrating an electronic device including an image sensor according to an embodiment of the present invention; [Figure 19] 1 is a diagram illustrating an electronic device including an image sensor according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram showing a simplified configuration of an electronic device according to an embodiment of the present invention.

[0012] 1, an electronic device 1 according to an embodiment of the present invention may include a display 2, a sensor unit 3, a memory 4, a port 5, a processor 6, a communication unit 7, etc. Furthermore, the electronic device 1 may further include a camera, a wired wireless communication device, a power supply device, etc.

[0013] The port 5 can be a device provided for the electronic device 1 to communicate with other external devices. The electronic device 1 can be a mobile device such as a smartphone or a tablet PC, and should be interpreted to include various other devices including a camera.

[0014] The display 2 can be realized as a device for outputting a screen, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electronic paper display, or a micro-electromechanical system (MEMS) display.

[0015] The overall operation of the electronic device 1 may be controlled by the processor 6. The processor 6 may perform specific calculations, commands, and tasks. The processor 6 may be a central processing unit (CPU), a microprocessor unit (MCU), a system on chip (SoC), an application processor (AP), or the like. In one embodiment, when the electronic device 1 is a tablet PC or a smartphone, the processor 6 may be an application processor (AP), and when the electronic device 1 is a laptop computer or a desktop computer, the processor 6 may be a central processing unit (CPU). The processor 6 may communicate with the display 2, the sensor unit 3, the memory 4, and other devices connected to the port 5 via the bus 8.

[0016] The memory 4 may be a storage medium for storing data necessary for the operation of the electronic device 1, multimedia data, etc. The memory 4 may include a volatile memory such as a random access memory (RAM) or a non-volatile memory such as a flash memory. Furthermore, the memory 4 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device.

[0017] The sensor unit 3 may include various sensors for collecting peripheral information, such as an acoustic sensor, an image sensor, a GPS (global positioning system) sensor, etc. The image sensor may include a CMOS (complementary metal oxide semiconductor) image sensor, a CCD (charge-coupled device) image sensor, etc. as a device for capturing an image.

[0018] The communication unit 7 can be a device for mediating communication between the electronic device 1 and other external electronic devices. The communication unit 7 can transmit and receive data to and from the external electronic devices via various communication interfaces, for example, wired communication interfaces such as a universal serial bus (USB), a local area network (LAN), and a micro-USB, and wireless communication interfaces such as Wifi, Bluetooth, near field communication (NFC), infrared communication, and visible light communication.

[0019] The components 2 to 7 included in the electronic device 1 can communicate with each other via a bus 8. The components 2 to 7 included in the electronic device 1 can transmit and receive data based on various communication standards. In one embodiment, when the electronic device 1 is a mobile device, the components 2 to 7 can transmit and receive data with each other based on a communication standard defined by the Mobile Industry Processor Interface (MIPI) standard.

[0020] The display 2, the sensor unit 3, the processor 6, etc. may include an interface circuit for transmitting and receiving data to and from each other. The interface circuit may include at least one of a transmitting circuit for transmitting data and a receiving circuit for receiving data. For example, the interface circuit may include a transceiver. The interface circuit may support communication through at least one of a D-PHY interface and a C-PHY interface defined in the MIPI standard. The D-PHY interface and the C-PHY interface transmit data in different ways, and the number and arrangement of pads required to transmit data through such interfaces may also differ from each other.

[0021] MIPI D-PHY is a high-speed digital serial interface. When communicating through the MIPI D-PHY interface, a transmitting interface circuit can transmit a signal including data to be transmitted and a clock signal separately, and a receiving interface circuit can process the received signal in a differential signaling format to recover the data.

[0022] To facilitate understanding of the present invention, it is assumed that the interface circuit is defined based on the D-PHY specification. However, the above assumption is not intended to limit the present invention. In addition, although data can be a unidirectional or bi-directional signal, in the embodiment of the present invention, it is assumed that the data is a unidirectional serial signal transmitted from a transmitting circuit to a receiving circuit.

[0023] There is a tendency for the number of camera modules connected to the electronic device 1 to increase. When the sensor unit 3 is an image sensor, the number of sensor units 3 may increase as the number of camera modules increases. As the number of sensor units 3 increases, the number of receiving circuits of the processor 6 that receive data from the transmitting circuits included in the sensor units 3 may also increase. A transmission line between the transmitting circuit of the sensor unit 3 and the receiving circuit of the processor 6 may be formed as a pattern of a printed circuit board (PCB), and the transmission line may be connected to the receiving circuit of the processor 6 via a receiving pad or receiving pin of the processor 6. As the number of receiving circuits of the processor 6 increases, the number of receiving pins of the processor 6 may increase.

[0024] According to an embodiment of the present invention, a plurality of sensor units 3 can share a transmission line. As a result, even if the number of camera modules connected to the electronic device 1 increases, the number of receiving circuits, the number of transmission lines, and the number of receiving pins of the processor 6 can be minimized. Therefore, the chip layout is reduced, the circuit implementation cost is low, and the product can be made smaller. Also, since only one image sensor needs to transmit data at a time, the image sensor that does not transmit data can be used to adjust the output impedance of the transmission circuit. Therefore, signal degradation can be reduced and high-speed data communication can be provided.

[0025] FIG. 2 is a diagram illustrating a camera module including an image sensor according to an embodiment of the present invention.

[0026] A camera module 10 according to an embodiment of the present invention may include an image sensor that captures an image of a subject and generates image data. The camera module 10 may include an optical unit 11, a housing 12 that accommodates the optical unit 11 and the image sensor, a circuit board 13 on which the image sensor is mounted, and a connector 17. The appearance of the camera module 10 may be modified to a form different from that of the embodiment shown in FIG. 2.

[0027] The optical unit 11 may include at least one lens that collects light for photographing a subject. The lens included in the optical unit 11 may be moved to focus the image sensor on the subject, and the lens may be moved by an AF (auto focus) generator provided inside the housing 12.

[0028] The image sensor may be disposed below the optical unit 11 and mounted on the circuit board 13. The image sensor may include a plurality of pixels, a logic circuit that generates image data using electrical signals output from the plurality of pixels, and the like. Each of the plurality of pixels may include a photoelectric element that generates charges in response to light, and a pixel circuit that converts the charges generated by the photoelectric element into an electrical signal. In one embodiment, the image sensor may also include a memory connected to the logic circuit and that stores image data.

[0029] The connector 17 may provide a connection to an external processor, etc. According to an embodiment, the camera module 10 may further include an image processor including a circuit for processing image data, etc. The camera module 10 may transmit and receive data to and from an external device, such as a central processing unit (CPU), an application processor (AP), or a display driver, via the connector 17.

[0030] The camera module 10 may further include a flexible printed circuit board 14 electrically connected to the circuit board 13 and including wiring 15 for connecting the image sensor to an external device (not shown), and a substrate 16 on which a connector 17 is mounted.

[0031] The camera module 10 can transmit and receive data to and from an external device via a predetermined interface. For example, the camera module 10 can transmit and receive data to and from an external device via either a D-PHY interface or a C-PHY interface defined in the MIPI (Mobile Industry Processor Interface) standard.

[0032] As the number of camera modules 10 connected to an electronic device increases, the number of receiving circuits of an external processor connected to the camera modules 10 may increase. The camera modules 10 and the processor may be connected to each other via a transmission line. According to an embodiment of the present invention, the camera modules connected to the electronic device may share the transmission line. Therefore, even if the number of camera modules 10 connected to the electronic device increases, the number of transmission lines and the number of receiving circuits of the processor may be minimized. Also, since only one image sensor needs to transmit data at a time, the output impedance of an image sensor that does not transmit data may be adjusted to reduce signal degradation.

[0033] 3 is a diagram provided to explain data communication of an electronic device according to an embodiment of the present invention. Referring to FIG. 3, an electronic device 20 may include an application processor 21 and an image sensor 24. The image sensor 24 may include a timing controller 25, a row decoder 27, a column decoder 28, and a pixel array 29. The timing controller 25, the row decoder 27, and the column decoder 28 may be logic circuits for controlling the pixel array 29. The pixel array 29 has a plurality of pixels, and the timing controller 25 may control the operations of the row decoder 27 and the column decoder 28 to process signals output by the pixels to generate image data.

[0034] The timing controller 25 may include an interface device 26 that mediates communication with the application processor 21, and the interface device 26 may transmit and receive data to and from the application processor 21 based on a communication standard defined by the MIPI standard. As an example, the interface device 26 may support communication via at least one of a D-PHY interface and a C-PHY interface defined by the MIPI standard.

[0035] The application processor 21 may include a controller 23 and an interface device 22. In one embodiment, the controller 23 may include control logic that controls the overall operation of the application processor 21. The application processor 21 may transmit and receive data to and from the image sensor 24, and the controller 23 may receive image data generated by the image sensor 24 via the interface device 22.

[0036] The application processor 21 and the image sensor 24 may be connected to each other via a transmission line. Each of the interface devices 22, 26 may include a transmitting circuit and a receiving circuit. As the number of image sensors 24 communicating with the application processor 21 increases, the number of receiving circuits included in the interface device 22 of the application processor 21 may increase.

[0037] According to an embodiment of the present invention, multiple image sensors can share a transmission line to communicate with the application processor 21. In this case, since only one image sensor needs to transmit data at a time, the image sensor that is not transmitting data can adjust the output impedance of the transmission circuit. Therefore, the product can be made smaller, signal degradation can be reduced, and high-speed data communication can be provided.

[0038] 4 and 5 are block diagrams of comparative examples provided to explain an electronic device according to an embodiment of the present invention.

[0039] 4, the electronic device 100 may include an AP 120 mounted on a PCB 110, a first image sensor 130 electrically connected to the PCB 110 via a first connector 134, and a second image sensor 140 electrically connected to the PCB 110 via a second connector 144. The first image sensor 130 and the second image sensor 140 may be included in different camera modules.

[0040] The first image sensor 130 may transmit and receive data to and from the AP 120 via the first connector 134, and the second image sensor 140 may transmit and receive data to and from the AP 120 via the second connector 144. The first image sensor 130 may include a first transmission circuit 131, and the second image sensor 140 may include a second transmission circuit 141. When the AP 120 and the first connector 134 are connected, the first transmission circuit 131 may transmit and receive data to and from the AP 120 via a wiring 133 and the first connector 134 included in the circuit board 132. When the AP 120 and the second connector 144 are connected, the second transmission circuit 141 may transmit and receive data to and from the AP 120 via a wiring 143 and the second connector 144 included in the circuit board 142.

[0041] The AP 120 may include a first receiving circuit 121 and a second receiving circuit 122. The first transmission line 135 and the second transmission line 145 may be formed as a pattern on the PCB 110. The first image sensor 130 may transmit and receive data to and from the AP 120 via the first transmission line 135, and the second image sensor 140 may transmit and receive data to and from the AP 120 via the second transmission line 145. The AP 120 and the first and second image sensors 130 and 140 may be connected in a point-to-point manner via the first transmission line 135 and the second transmission line 145. Each of the first transmission line 135 and the second transmission line 145 may include one clock lane and one or more data lanes.

[0042] In the point-to-point coupling, sufficient impedance matching can be performed between the output impedance of the transmitting circuit, the characteristic impedance of the transmission line, and the input impedance of the receiving circuit. If sufficient impedance matching is performed, distortion of the signal waveform is small and reflected waves can be eliminated. However, in the point-to-point coupling, if the number of camera modules connected to the electronic device 100 increases, the number of patterns on the PCB 110 forming the transmission line and the number of receiving circuits included in the AP 120 may increase.

[0043] FIG. 5 may be a diagram provided to explain the operation of an interface that outputs image data and a clock signal in a differential signaling format, for example, a D-PHY interface based on the MIPI standard.

[0044] 5, the electronic device 100 may include an AP 120 and an image sensor 130. The AP 120 may include a receiving circuit 121, and the image sensor 130 may include a transmitting circuit 131. The receiving circuit 121 may include a plurality of receivers RX0 to RX2, and the transmitting circuit 131 may include a plurality of transmitters TX0 to TX1.

[0045] The transmitters TX0 to TX2 can output differential signals, for example, image data D0P, D0N, D1P, D1N and clock signals CLKP and CLKN, in response to input signals IN0 to IN2. The transmitters TX0 to TX2 can output the differential signals on transmission lines L0 to L5 via a plurality of transmission pads TP0 to TP5. The transmission pads TP0 to TP5 can be connected to a plurality of receiving pads RP0 to RP5 via one clock lane and one or more data lanes. For example, the transmission lines L0 and L1 can be referred to as a first data lane, the transmission lines L4 and L5 can be referred to as a second data lane, and the transmission lines L2 and L3 can be referred to as a clock lane.

[0046] The receiving pads RP0 to RP5 may be connected to a plurality of receivers RX0 to RX2. As an example, the receiving pads RP0 to RP5 may be pads provided on a main board on which a processor is mounted. Each of the receivers RX0 to RX2 may be connected to a pair of the receiving pads RP0 to RP5 and may generate data D0, D1 and a clock signal CLK in a differential signaling manner. For example, the receiver RX0 may generate data D0, the receiver RX1 may generate a clock signal CLK, and the receiver RX1 may generate data D1. In the embodiment shown in FIG. 5, six transmitting pads TP0 to TP5, three lanes, and six receiving pads RP0 to RP5 are required to transmit image data in a differential signaling manner.

[0047] The number of camera modules connected to the electronic device 100 can be increased. For example, if there are three camera modules and four data lanes, the AP 120 needs three receiving circuits, 30 transmission pads and 30 reception pads, and 30 patterns on the PCB that form the transmission lines.

[0048] In an embodiment of the present invention, image sensors included in camera modules may share a transmission line to communicate with the AP 120. The image sensors may share the transmission line with each other in a multi-drop manner and be connected to the AP 120. Therefore, the multi-drop manner can minimize the number of receiving circuits, the number of transmission lines, and the number of receiving pads of the AP 120 even if the number of camera modules connected to the electronic device 100 increases.

[0049] In the multi-drop method, only one image sensor needs to transmit data to the AP 120 at a time. Therefore, image sensors that do not transmit data must be in a high impedance (Hi-Z) state. In this case, a transmission line connected to the image sensor that does not transmit data may become stubbed, causing signal degradation due to signal reflection. Furthermore, to assist in impedance matching, a resistor may be connected to the output terminal of the image sensor that does not transmit data. In this case, signal distortion may occur when the operating image sensor is in a low power operation mode.

[0050] According to an embodiment of the present invention, an image sensor that does not transmit data can adjust the output impedance of a transmission circuit, thereby reducing signal degradation and providing high-speed data communication.

[0051] FIG. 6 is a block diagram provided to explain an electronic device according to an embodiment of the present invention.

[0052] Referring to FIG. 6, the electronic device 200 may include an AP 220 mounted on a PCB 210, a first image sensor 230 electrically connected to the PCB 210 via a first connector 234, and a second image sensor 240 electrically connected to the PCB 210 via a second connector 244.

[0053] The first image sensor 230 may transmit and receive data to and from the AP 220 via the first connector 234, and the second image sensor 240 may transmit and receive data to and from the AP 220 via the second connector 244. The first image sensor 230 may include a first transmission circuit 231, and the second image sensor 240 may include a second transmission circuit 241. When the AP 220 and the first connector 234 are connected, the first transmission circuit 231 may transmit and receive data to and from the AP 220 via a wiring 233 and the first connector 234 included in the circuit board 232. When the AP 220 and the second connector 244 are connected, the second transmission circuit 241 may transmit and receive data to and from the AP 120 via a wiring 243 and the second connector 244 included in the circuit board 242.

[0054] The AP 220 may include one receiving circuit 221. The transmission line 250 may be formed as a pattern on the PCB 210. The first and second image sensors 230 and 240 may share the transmission line 250 in a multi-drop manner to communicate with the AP 220. The electronic device 200 may allow only one image sensor to transmit image data to the AP 220 at a time. The image data may include a plurality of frame data, and each frame data may include M (an integer equal to or greater than 2) pieces of line data. Each line data may include a plurality of pixel data. For example, the first image sensor 230 and the second image sensor 240 may alternately transmit line data or alternately transmit frame data.

[0055] According to an embodiment of the present invention, the first image sensor 230 and the second image sensor 240 may be connected in a multi-drop manner. Therefore, even if the number of camera modules connected to the electronic device 200 increases, the number of receiving circuits of the AP 220 and the number of transmission lines 250 can be minimized.

[0056] In the multi-drop method, since only one image sensor needs to transmit data to the AP, the transmission circuit of the image sensor that is not transmitting data may have a high impedance state. In this case, signal degradation may increase and the data transmission speed may be limited. To support impedance matching, resistors may be connected to the output terminals of the transmission circuits of all image sensors. In this case, signal distortion may occur when the operating image sensor is in a low power operation mode.

[0057] According to an embodiment of the present invention, the image sensor may include a termination resistor block capable of adjusting the output impedance of a transmission circuit. For example, if the transmission circuit of the image sensor transmitting data is in a low power operation mode, the transmission circuit of the image sensor not transmitting data may have a high impedance state. If the transmission circuit of the image sensor transmitting data is in a high speed data transmission mode, the transmission circuit of the image sensor not transmitting data may have a specified output impedance. Thus, the electronic device according to an embodiment of the present invention may provide high speed data communication while reducing signal degradation in a multi-drop manner.

[0058] 7a, 7b, 8a and 8b are block diagrams illustrating the method of operation of an interface circuit according to an embodiment of the present invention.

[0059] 7a and 7b, the electronic device 400A, 400B may include one processor 420 and two image sensors 430, 440. The first image sensor 430 may include a first transmission circuit 431, and the first transmission circuit 431 may include a first termination resistor block capable of adjusting an output impedance. The second image sensor 440 may include a second transmission circuit 441, and the second transmission circuit 441 may include a second termination resistor block capable of adjusting an output impedance.

[0060] 7a, when the first image sensor 430 transmits data to the processor 420, the second image sensor 440 may not transmit data. If the first transmission circuit 431 of the first image sensor 430 is in a low power operating mode, the transmission circuit 441 of the second image sensor 440 may have a high impedance state. That is, when the first transmission circuit 431 is in the first mode, the second transmission circuit 441 may have a high impedance state.

[0061] Conversely, as shown in Figure 7b, when the second image sensor 440 transmits data to the processor 420, the first image sensor 430 may not transmit data. If the second transmission circuit 441 of the second image sensor 440 is in a low power operating mode, the transmission circuit 431 of the first image sensor 430 may have a high impedance state. That is, when the second transmission circuit 4410 is in the first mode, the first transmission circuit 431 may have a high impedance state.

[0062] The non-data transmitting image sensor can determine the operation mode of the data transmitting image sensor in the low power operation mode based on the low power signal sequence output by the data transmitting image sensor.

[0063] In Figures 7a and 7b, 410 can be a PCB, 421 can be a receiving circuit, 432 and 442 can be circuit boards, 433 and 443 can be wiring, 434 can be a first connector, 444 can be a second connector, and 450 can be a transmission line.

[0064] 8a and 8b, electronic devices 700A and 700B in FIGS. 8a and 8b have the same configuration as the electronic devices 400A and 400B in FIGS. 7a and 7b, and therefore a duplicated description will be omitted.

[0065] 8a, when the first image sensor 730 transmits data to the processor 720, the second image sensor 740 may not transmit data. If the first transmission circuit 731 of the first image sensor 730 is in the high-speed data transmission mode, the second termination resistor block of the second image sensor 740 may specify the output impedance of the second transmission circuit 741 of the second image sensor 740 to impedance Z. That is, when the first transmission circuit 731 is in the second mode, the output impedance of the second transmission circuit 741 is specified to impedance Z.

[0066] 8b, when the second image sensor 740 transmits data to the processor 720, the first image sensor 730 may not transmit data. If the second transmission circuit 741 of the second image sensor 740 is in the high-speed data transmission mode, the first termination resistor block of the first image sensor 730 may specify that the output impedance of the first transmission circuit 731 of the first image sensor 730 is impedance Z. That is, when the second transmission circuit 741 is in the second mode, the output impedance of the first transmission circuit 731 is specified to impedance Z.

[0067] An image sensor that does not transmit data can determine that the operation mode of the image sensor that transmits data is the high-speed data transmission mode based on the low-power signal sequence output by the image sensor that transmits data.

[0068] The designated impedance value may be determined within a range that allows good impedance matching for a signal transmitted through a transmission line. For example, the designated impedance value may be determined in consideration of the output impedance of a transmitting circuit that outputs data, the distance between a transmitting circuit that does not output data and a processor, etc. Ideally, the designated impedance value may be a value that appears the same as the output impedance Z of a transmitting circuit that outputs data when viewed from a receiving circuit.

[0069] 9 to 12 are diagrams illustrating the operation of the termination resistor block according to one embodiment of the present invention.

[0070] Referring to FIG. 9, a pixel array PA of the image sensor may include a plurality of pixels PX. The plurality of pixels PX may be connected to a plurality of row lines ROW1 to ROWm:ROW and a plurality of column lines COL1 to COLn:COL. The image sensor may drive the plurality of pixels PX in units of a plurality of row lines ROW. As an example, a time required to drive a selected driving line among the plurality of row lines ROW and to read a reset voltage and a pixel voltage from the pixel PX connected to the selected driving line may be referred to as one horizontal period. The image sensor may operate in a rolling shutter manner in which the plurality of row lines ROW are driven in sequence.

[0071] Meanwhile, the frame period FT of the image sensor may be referred to as the time required to read the reset voltages and pixel voltages from all pixels included in the pixel array PA. For example, the frame period FT may be equal to or greater than the product of the number of row lines ROW and the horizontal period. The shorter the frame period FT of the image sensor, the more image frames the image sensor can generate during the same time.

[0072] One frame data may include M (e.g., an integer equal to or greater than 2) pieces of line data. A horizontal blank period may exist between the first line data and the second line data, and a vertical blank period may exist between the first frame data and the second frame data.

[0073] 10, when the image sensor transmits a signal, the operation mode of the transmission circuit may include a low power operation mode and a high speed data transmission mode. The low power operation sections (LP1, LP2) may refer to a section in which the transmission circuit operates in the low power operation mode, and the high speed data transmission section (HS) may refer to a section in which the transmission circuit operates in the high speed data transmission mode. If the transmission circuit is in the low power operation mode, the signal may be a single-ended signal, and if the transmission circuit is in the high speed data transmission mode, the signal may be a differential signal.

[0074] The transmitting circuit outputs a low power signal sequence LP11 in the low power operation sections LP1 and LP2, and when entering the high speed data transmission section HS, it can output low power signal sequences LP11, LP01, and LP00. That is, before entering the high speed data transmission section HS, the low power signal sequence is switched from LP11 to LP01 and then to LP00. The low power signal sequences LP11, LP01, and LP00 can be sequences that inform the transmitting circuit that it is switched from a low power operation mode to a high speed data transmission mode.

[0075] The line data DATA may include a positive data signal DP and a negative data signal DN. During a first low power operation period LP1, the line data DATA may include low power signal sequences LP11, LP01, and LP00. During a high speed data transmission period HS, the line data DATA may include normal data, i.e., payload data, in series with a sync code SYNC. The sync code SYNC may mean a predetermined code for data synchronization before transmitting normal data. During a second low power operation period LP2 in which the transmitting circuit operates in a low power operation mode, the line data DATA may include a low power signal sequence LP11.

[0076] A termination resistor block according to an embodiment of the present invention may detect a low-power signal sequence and determine an operation mode of a transmission circuit that transmits data based on the detection result. For example, when the low-power signal sequence is detected to be "11, 01, 00", the termination resistor block may detect that the operation mode of the transmission circuit that transmits data is switched from the low-power operation mode to the high-speed data transmission mode. Furthermore, when the low-power signal sequence is detected to be "11", the termination resistor block may detect that the operation mode of the transmission circuit that transmits data is the low-power operation mode. Therefore, the termination resistor block of an image sensor that does not transmit data may be used to determine the operation mode of the image sensor that transmits data based on the low-power signal sequence output by the image sensor that transmits data. Furthermore, the image sensor that does not transmit data may adjust the output impedance of the image sensor that does not transmit data based on the operation mode of the image sensor that transmits data.

[0077] For example, if the operation mode of the image sensor transmitting data is a low power operation mode, the transmission circuit of the image sensor not transmitting data can have a high impedance state, and if the operation mode of the image sensor transmitting data is a high speed data transmission mode, the termination resistor block of the image sensor not transmitting data can set the output impedance to a specified impedance.

[0078] If resistors are connected to the output terminals of the transmitting circuits of all image sensors to support impedance matching, signal distortion may occur when the operation mode of the image sensor transmitting data is a low power operation mode. Referring to Fig. 11, during the first low power operation period LP1, when the transmitting circuit 831 outputs a low power signal LP01 in which the positive data signal DP and the negative data signal DN have different levels among the transmitted low power signal sequence, a current may flow in the transmitting circuit of the image sensor not transmitting data. This may cause an error in the low power signal LP01.

[0079] 12, only during a high-speed data transmission section HS in which a transmission circuit of an image sensor transmitting data operates in a high-speed data transmission mode, a termination resistor block of an image sensor not transmitting data can generate a control signal CTRL for setting an output impedance to a designated impedance. Based on the control signal CTRL, the output impedance of a transmission circuit of an image sensor not transmitting data can be set to a designated impedance.

[0080] FIG. 13 shows an eye diagram provided to explain an interface circuit according to one embodiment of the present invention.

[0081] Referring to the eye-diagram of FIG. 13, the eye opening height V2 of the multi-drop method may be smaller than the eye opening height V1 of the point-to-point method. The eye opening height may be measured based on the minimum and maximum voltage levels. In order to increase the eye opening height V2 in the multi-drop method, the data transmission speed needs to be reduced, and therefore high-speed data communication may not be performed accurately.

[0082] The interface circuit according to an embodiment of the present invention may include a termination resistor block capable of adjusting the output impedance of the transmission circuit. Therefore, the eye opening height V2 may be increased in a multi-drop manner. That is, there is an advantage that high-speed data communication is possible while multiple image sensors share a transmission line.

[0083] 14, 15a, 15b, and 15c are circuits for explaining the operation of an interface circuit according to an embodiment of the present invention.

[0084] Referring to FIG. 14, the electronic device 900 may include a first image sensor 930, a second image sensor 940, a processor 920, and transmission lines L0 to L5. The first image sensor 930 may include a first transmission circuit 931 including a plurality of transmitters TX00 to TX02. The plurality of transmitters TX00 to TX02 may transmit data to the transmission lines L0 to L5 via the transmission pads TP00 to TP05. The second image sensor 940 may include a second transmission circuit 941 including a plurality of transmitters TX10 to TX12, and the plurality of transmitters TX10 to TX12 may transmit data to the transmission lines L0 to L5 via the transmission pads TP10 to TP15. The processor 920 may include a reception circuit 921 including a plurality of receivers RX0 to RX2, and the plurality of receivers RX0 to RX2 may receive the data via the reception pads RP0 to RP5.

[0085] Each of the plurality of transmitters TX00, TX01, TX02, TX10, TX11, and TX12 may include a termination resistor block TB00, TB01, TB02, TB10, TB11, and TB12 between corresponding transmission lines. The termination resistor blocks TB10, TB11, and TB12 of the second image sensor 940 that does not transmit data may detect a low power signal sequence output from the first transmission circuit 931 that transmits data, and adjust the output impedance of the second transmission circuit 941 in response to the low power signal sequence. For example, the termination resistor blocks TB10, TB11, and TB12 may electrically connect or disconnect unit resistors between the transmission pads TP10 to TP15 in response to the low power signal sequence.

[0086] The termination resistor blocks TB10, TB11, and TB12 detect the low power signal sequence output by the first transmission circuit 931 in the low power operation mode, and can determine whether the first transmission circuit 931 has entered the high speed data transmission mode based on the detection result. If it is determined that the first transmission circuit 931 has entered the high speed data transmission mode, the termination resistor blocks TB10, TB11, and TB12 can electrically connect unit resistors between the transmission pads TP10 to TP15. Therefore, the output impedance of the second transmission circuit 941 can be set to a designated impedance.

[0087] The termination resistor blocks TB10, TB11, and TB12 detect the low power signal sequence output by the first transmitting circuit 931 in the low power operation mode, and when it is determined that the first transmitting circuit 931 is in the low power operation mode as a result of the detection, the termination resistor blocks TB10, TB11, and TB12 can disconnect the unit resistors between the transmission pads TP10 to TP15. Therefore, the output impedance of the second transmitting circuit 941 can have a high impedance state.

[0088] 15a to 15c will be described on the assumption that one image sensor includes one transmission circuit for convenience of explanation. In Fig. 15a to 15c, each of 900A, 900B, and 900C is referred to as an electronic device.

[0089] 15a, the first transmission circuit 931 may include a high-speed transmitter HS_TX00 and a plurality of low-power transmitters LP_TX00a, LP_TX00b, and the second transmission circuit 941 may include a high-speed transmitter HS_TX10 and a plurality of low-power transmitters LP_TX10a, LP_TX10b. The first transmission circuit 931 and the second transmission circuit 941 may share the transmission lines L0, L1. The first transmission circuit 931 may further include a plurality of transmission pads TP00, TP01 that output signals to the transmission lines L0, L1, and a first termination resistor block TB00 connected between the transmission pads TP00, TP01. The second transmission circuit 941 may further include a plurality of transmission pads TP10, TP11 that output signals to the transmission lines L0, L1, and a second termination resistor block TB10 connected between the transmission pads TP10, TP11.

[0090] The first termination resistor block TB00 may include a first termination circuit T00, a first low power receiver LP_RX00a, LP_RX00b, and a first control logic CL00. The first termination circuit T00 may include a unit resistor and a unit switch element connected to the transmission pads TP00 and TP01 and connected in series with each other. For example, the unit resistor may be connected to the transmission pad TP01, and the unit switch element may be connected to the transmission pad TP00. An input terminal of the first low power receiver LP_RX00a may be connected to the first transmission pad TP00, and an output terminal of the first low power receiver LP_RX00a may be connected to the first control logic CL00. An input terminal of the first low power receiver LP_RX00b may be connected to the second transmission pad TP01, and an output terminal of the first low power receiver LP_RX00b may be connected to the first control logic CL00. The first control logic CL00 generates a control signal CTRL based on the input signals of the first low power receivers LP_RX00a and LP_RX00b, and can control the on / off state of the unit switch element of the first termination circuit T00 based on the control signal CTRL. The first control logic CL00 can be, but is not limited to, a finite state machine (FSM).

[0091] The second termination resistor block TB10 may include a second termination circuit T10, second low power receivers LP_RX10a and LP_RX10b, and a second control logic CL10. The second termination circuit T10 may include a unit resistor and a unit switch element connected to the transmission pads TP10 and TP11 and connected in series with each other. For example, the unit resistor may be connected to the transmission pad TP11, and the unit switch element may be connected to the transmission pad TP10. An input terminal of the second low power receiver LP_RX10a may be connected to the first transmission pad TP10, and an output terminal of the second low power receiver LP_RX10a may be connected to the second control logic CL10. An input terminal of the first low power receiver LP_RX10b may be connected to the second transmission pad TP11, and an output terminal of the second low power receiver LP_RX10b may be connected to the second control logic CL10. The second control logic CL10 generates a control signal CTRL based on the input signals of the second low power receivers LP_RX10a, LP_RX10b, and can control the on / off state of the unit switch element of the second termination circuit T10 based on the control signal CTRL.

[0092] According to an embodiment, the first transmitting circuit 931 can transmit data, and the second transmitting circuit 941 can not transmit data. The first low power transmitters LP_TX00a, LP_TX00b can output low power signal sequences to the transmission lines L0, L1 via a plurality of transmission pads TP00, TP01 in a low power operation mode. The second low power receivers LP_RX10a, LP_RX10b can receive the low power signal sequences output by the first low power transmitters LP_TX00a, LP_TX00b. The second low power receiver LP_RX10a can receive the positive data signal of the signal, and the second low power receiver LP_RX10b can receive the negative data signal of the signal.

[0093] The second control logic CL10 may receive the positive data signal and the negative data signal from the second low power receivers LP_RX10a and LP_RX10b. When a low power signal sequence of a specific pattern, for example, a "11", "01", or "00" pattern, is detected, the second control logic CL10 may determine that the first transmission circuit 931 enters a high-speed data transmission mode. The low power signal sequence is not limited to the above-mentioned pattern, and various other patterns may be used to identify the high-speed data transmission mode. The second control logic CL10 may turn on a unit switch element of the second termination circuit T10. When the unit switch element of the second termination circuit T10 is turned on, a unit resistor may be connected between the transmission pads TP10 and TP11.

[0094] The second control logic CL10 may determine that the first transmission circuit 931 is in the low power operation mode when a low power signal sequence of a specific pattern, for example, a "11" pattern, is detected. The low power signal sequence is not limited to the above-mentioned pattern, and various other patterns may be used to identify the low power operation mode. The second control logic CL10 may turn off the unit switch element of the second termination circuit T10. When the unit switch element of the second termination circuit T10 is turned off, the unit resistor may be disconnected between the transmission pads TP10 and TP11.

[0095] That is, when the first transmission circuit 931 is in the low power operation mode, the unit resistor of the second termination circuit T10 may not be connected between the transmission pads TP10 and TP11, and the output impedance of the second transmission circuit 941 may have a high impedance. When the first transmission circuit 931 is in the high-speed data transmission mode, the unit resistor of the second termination circuit T10 may be connected between the transmission pads TP10 and TP11, and the output impedance of the second transmission circuit 941 may be set to a designated impedance. The designated impedance may be the sum of the turn-on resistance of the unit switch element of the second termination circuit T10 and the resistance value of the unit resistor. Therefore, the first and second termination circuits T00 and T10 may perform impedance matching for signals transmitted to the transmission pads TP00, TP01, TP10, and TP11.

[0096] According to another embodiment, the second transmitting circuit 941 can transmit data, and the first transmitting circuit 931 can not transmit data. The second low power transmitters LP_TX10a, LP_TX10b can output low power signal sequences to the transmission lines L0, L1 via a plurality of transmission pads TP10, TP11. The first low power receivers LP_RX00a, LP_RX00b can receive the low power signal sequences output by the second low power transmitters LP_TX10a, LP_TX10b, and output them to the first control logic CL00.

[0097] The first control logic CL00 may determine that the second transmission circuit 941 enters a high-speed data transmission mode when a low-power signal sequence of a specific pattern, for example, a "11", "01", or "00" pattern, is detected. The first control logic CL00 may turn on a unit switch element of the first termination circuit T00. When the unit switch element of the first termination circuit T00 is turned on, a unit resistor may be connected to the transmission pads TP00 and TP01.

[0098] The first control logic CL00 may determine that the second transmission circuit 941 is in the low power operation mode when a low power signal sequence of a specific pattern, for example, a “11” pattern, is detected. The first control logic CL00 may turn off the unit switch element of the first termination circuit T00. When the unit switch element of the first termination circuit T00 is turned off, the unit resistor may be disconnected from the transmission pads TP00 and TP01.

[0099] That is, when the second transmission circuit 941 is in the low power operation mode, the unit resistor of the first termination circuit T00 is not connected to the transmission pads TP00 and TP01, and the output impedance of the first transmission circuit 931 may have a high impedance. When the second transmission circuit 941 is in the high-speed data transmission mode, the unit resistor of the first termination circuit T00 may be connected to the transmission pads TP00 and TP01, and the output impedance of the first transmission circuit 931 may be set to a specified impedance. Thus, the first and second termination circuits T00 and T10 may perform impedance matching for signals transmitted to the transmission pads TP00, TP01, TX10, and TX11.

[0100] 15b, unlike FIG 15a, each of the first termination circuit T00 and the second termination circuit T10 may include unit switch elements connected in series between the transmission pads TP00 and TP01, and unit resistors connected in series between the unit switch elements. Each of the first termination circuit T00 and the second termination circuit T10 in FIG 15b has symmetry of impedance loads, thereby further reducing the impedance difference.

[0101] 15c, unlike FIG 15b, each of the first termination circuit T00 and the second termination circuit T10 may include unit switch elements connected in series between the transmission pads TP00 and TP01, and unit resistors connected in series between the unit switch elements, and may further include a common mode capacitor between the unit resistors. Each of the first termination circuit T00 and the second termination circuit T10 of FIG 15c can stably transmit data in a high-speed data transmission mode.

[0102] Although FIGS. 15a to 15c have been described with one image sensor including one transmission circuit for the sake of convenience, the number of transmission circuits included in one image sensor may be changed in various ways.

[0103] 16 and 17 show timing diagrams of an interface operation according to one embodiment of the present invention.

[0104] 16, during a first time interval D1, the first image sensor IS1 is enabled to transmit data, and the transmitting circuit of the first image sensor IS1 may output a low-power signal sequence in a low-power operation mode. During the first time interval D1, the output impedance of the transmitting circuit of the second image sensor IS2 may have a high impedance. During the first time interval D1, the termination resistor block of the second image sensor IS2 may sense the low-power signal sequence output by the first image sensor IS1 and connect a unit resistor between the transmission pads at a first time t1. Thus, during a second time interval D2, the output impedance of the transmitting circuit of the second image sensor IS2 may be set to a specified impedance.

[0105] During the second time period D2, the transmitter circuit of the first image sensor IS1 can output data in a high-speed data transmission mode, and during the second time period D2, the termination resistor block of the second image sensor IS2 can perform impedance matching for the data output by the first image sensor IS1.

[0106] At a second time t2, the termination resistor block of the second image sensor IS2 may sense the low power signal sequence output by the first image sensor IS1 and disconnect the unit resistor between the transmission pads. Thus, during a third time interval D3, the output impedance of the transmission circuit of the second image sensor IS2 may have a high impedance. During the third time interval D3, the transmission circuit of the first image sensor IS1 may be disabled after operating in the low power operation mode. During a fourth time interval D4, the second image sensor IS2 may be disabled.

[0107] During the fourth time period D4, the first image sensor IS1 and the second image sensor IS2 are both disabled, thereby reducing power consumption.

[0108] During the fifth time interval D5, the second image sensor IS2 is enabled to transmit data, and the transmitting circuit of the second image sensor IS2 can output a low-power signal sequence in a low-power operation mode. When the second image sensor IS2 is enabled in a disabled state, an initialization time is required. During the fifth time interval D5, the output impedance of the transmitting circuit of the first image sensor IS1 can have a high impedance.

[0109] At a fifth time t5, the termination resistor block of the first image sensor IS1 may sense the low-power signal sequence output by the second image sensor IS2 and connect the unit resistor between the transmission pads, so that the output impedance of the transmission circuit of the second image sensor IS2 may be set to a specified impedance during a sixth time period D6.

[0110] During the sixth time interval D6, the transmitting circuit of the second image sensor IS2 can output data in a high-speed data transmission mode. During the sixth time interval D6, the termination resistor block of the first image sensor IS1 can perform impedance matching for the data output by the second image sensor IS2.

[0111] During the sixth time interval D6, the termination resistor block of the first image sensor IS1 may sense the low power signal sequence output by the second image sensor IS2 and disconnect the unit resistor from the transmission pad at the sixth time t6. Therefore, during the seventh time interval D7, the output impedance of the transmission circuit of the first image sensor IS1 may have a high impedance.

[0112] During a seventh time interval D4, the transmission circuit of the second image sensor IS2 may be disabled after operating in a low power operating mode.

[0113] The processor (AP) may appear to operate only one image sensor during the first to seventh time intervals D1 to D7.

[0114] Referring to Figure 17, unlike Figure 16, during the fourth time period D4, the first image sensor IS1 and the second image sensor IS2 are not disabled, and the transmitting circuit of the first image sensor IS1 can maintain the low power signal sequence at "11" in the low power operating mode.

[0115] During the fifth time interval D5, the transmitter circuit of the second image sensor IS2 may output a low-power signal sequence in the low-power operating mode. The second image sensor IS2 may not require an initialization time because it continues to be enabled. During the seventh time interval D4, the transmitter circuit of the second image sensor IS2 may continue to remain enabled after operating in the low-power operating mode.

[0116] 16, the first image sensor IS1 and the second image sensor IS2 are disabled during the vertical blanking period, whereas in FIG 17, the first image sensor IS1 and the second image sensor IS2 are enabled during the vertical blanking period, so that the vertical blanking time can be reduced compared to the embodiment shown in FIG 16. Therefore, the frame rate can be increased.

[0117] In this specification, an embodiment in which the number of camera modules sharing a transmission line is two has been shown and described, but the number of camera modules sharing a transmission line can be modified in various ways without departing from the technical spirit of the present invention.

[0118] 18 and 19 are diagrams illustrating an electronic device including an image sensor according to an embodiment of the present invention.

[0119] Referring to FIG. 18, an electronic device 1000 may include a camera module group 1100, an application processor 1200, a PMIC (power management integrated circuit) 1300, and an external memory 1400.

[0120] The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the drawings show an embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged, the embodiment is not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. In some embodiments, the camera module group 1100 may be modified to include n camera modules (n is a natural number equal to or greater than 4). In one embodiment, at least one of the camera modules 1100a, 1100b, and 1100c included in the camera module group 1100 may include an image sensor according to any one of the embodiments described above with reference to FIGS. 1 to 17.

[0121] Hereinafter, the detailed configuration of the camera module 1100b will be described in more detail with reference to FIG. 19. The following description can also be applied to the camera modules 1100a and 1100b, which differ depending on the embodiment.

[0122] Referring to FIG. 19, a camera module 1100b may include a prism 1105, an optical path folding element (hereinafter, “OPFE”) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0123] The prism 1105 includes a reflecting surface 1107 made of a light reflecting material, and is capable of changing the path of light L incident from the outside.

[0124] In some embodiments, the prism 1105 can change the path of the light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 can change the path of the light L incident in the first direction X to the perpendicular second direction Y by rotating the reflective surface 1107 of the light reflective material about the central axis 1106 in the direction A or by rotating the central axis 1106 in the direction B. At this time, the OPFE 1110 can also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0125] As shown in some embodiments, the maximum rotation angle of prism 1105 in the A direction can be less than or equal to 15 degrees in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, although the embodiments are not limited thereto.

[0126] In some embodiments, prism 1105 can move around 20 degrees in the plus (+) or minus (-) B direction, or between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees, where the angle of movement can be the same angle in the plus (+) or minus (-) B direction, or a similar angle within a range of 1 degree.

[0127] In some embodiments, the prism 1105 can move the reflective surface 1106 of the light-reflective material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106.

[0128] The OPFE 1110 may include, for example, optical lenses consisting of m groups (where m is a natural number). The m lenses may move in a second direction Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is Z, when the m optical lenses included in the OPFE 1110 are moved, the optical zoom ratio of the camera module 1100b may be changed to an optical zoom ratio of 3Z, 5Z, or more than 5Z.

[0129] The actuator 1130 can move the OPFE 1110 or an optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0130] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b by a control signal provided via a control signal line CSLb.

[0131] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information required for the camera module 1100b to generate image data using light L provided from the outside. The calibration data 1147 may include, for example, information on the degree of rotation, information on a focal length, information on an optical axis, etc. If the camera module 1100b is implemented in the form of a multi-state camera in which the focal length changes depending on the position of an optical lens, the calibration data 1147 may include a focal length value for each position (or state) of the optical lens and information on auto focusing.

[0132] The storage unit 1150 may store image data sensed through the image sensor 1142. The storage unit 1150 may be disposed outside the image sensing device 1140 and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140. In some embodiments, the storage unit 1150 may be implemented in an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiment is not limited thereto.

[0133] 18 and 19 together, in some embodiments, each of the multiple camera modules 1100a, 1100b, 1100c can include an actuator 1130. As a result, each of the multiple camera modules 1100a, 1100b, 1100c can include the same or different calibration data 1147 from one another depending on the operation of the actuator 1130 included therein.

[0134] In some embodiments, one of the multiple camera modules 1100a, 1100b, and 1100c (e.g., 1100b) may be a folded lens type camera module including the prism 1105 and OPFE 1110 described above, and the remaining camera modules (e.g., 1100a, 1100b) may be a vertical type camera module that does not include the prism 1105 and the OPFE 1110, but the embodiments are not limited to this.

[0135] In some embodiments, one of the camera modules 1100a, 1100b, and 1100c (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, infrared rays (IR). In this case, the application processor 1200 may merge image data provided by such a depth camera with image data provided by another camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0136] In some embodiments, at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules 1100a, 1100b, 1100c may have different fields of view (fields of view) from each other. In this case, for example, but not limited to, the optical lenses of at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules 1100a, 1100b, 1100c may be different from each other.

[0137] In some embodiments, the viewing angles of the camera modules 1100a, 1100b, and 1100c may be different from each other, and in this case, the optical lenses included in the camera modules 1100a, 1100b, and 1100c may also be different from each other, but are not limited to this.

[0138] In some embodiments, each of the multiple camera modules 1100a, 1100b, and 1100c may be arranged to be physically separated from each other. That is, instead of the multiple camera modules 1100a, 1100b, and 1100c sharing the sensing area of ​​one image sensor 1142, an independent image sensor 1142 may be arranged inside each of the multiple camera modules 1100a, 1100b, and 1100c.

[0139] 18 again, the application processor 1200 may include an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c may be implemented separately from each other in separate semiconductor chips.

[0140] The image processing device 1210 may include multiple sub-image processors 1212 a , 1212 b , 1212 c , an image generator 1214 , and a camera module controller 1216 .

[0141] The image processing device 1210 may include a number of sub-image processors 1212a, 1212b, 1212c corresponding to the number of camera modules 1100a, 1100b, 1100c.

[0142] Image data generated from each of the camera modules 1100a, 1100b, and 1100c may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through separate image signal lines ISLa, ISLb, and ISLc. For example, image data generated from the camera module 1100a may be provided to the sub-image processor 1212a through the image signal line ISLa, image data generated from the camera module 1100b may be provided to the sub-image processor 1212b through the image signal line ISLb, and image data generated from the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line ISLc. Such image data transmission may be performed using, for example, a camera serial interface (CSI) based on a Mobile Industry Processor Interface (MIPI), but the embodiment is not limited thereto.

[0143] Meanwhile, in some embodiments, one sub-image processor may be arranged to correspond to a plurality of camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may be integrated into one sub-image processor, instead of being implemented separately from each other as shown in the figure, and image data provided from camera module 1100a and camera module 1100c may be selected via a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0144] The image data provided to each of the sub-image processors 1212a, 1212b, and 1212c may be provided to an image generator 1214. The image generator 1214 may generate an output image using the image data provided from each of the sub-image processors 1212a, 1212b, and 1212c by image generation information or a mode signal.

[0145] Specifically, the image generator 1214 may generate an output image by merging at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal. Also, the image generator 1214 may select one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal to generate an output image.

[0146] In some embodiments, the image generation information can include a zoom signal or zoom factor, and in some embodiments, the mode signal can be based on a mode selected by a user, for example.

[0147] When the image generation information is a zoom signal (zoom factor) and each of the camera modules 1100a, 1100b, and 1100c has a different observation field of view (viewing angle), the image generator 1214 may perform different operations according to the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 may merge the image data output from the camera module 1100a and the image data output from the camera module 1100c, and then generate an output image using the merged image signal and the image data output from the camera module 1100b that is not used for the merging. If the zoom signal is a second signal different from the first signal, the image generator 1214 may generate an output image by selecting one of the image data output from each of the camera modules 1100a, 1100b, and 1100c without performing such image data merging. However, the embodiment is not limited thereto, and the method of processing the image data may be modified as necessary.

[0148] In some embodiments, the image generator 1214 can receive multiple image data with different exposure times from at least one of the multiple sub-image processors 1212a, 1212b, 1212c, and perform HDR (high dynamic range) processing on the multiple image data to generate merged image data with increased dynamic range.

[0149] The camera module controller 1216 can provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated from the camera module controller 1216 can be provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0150] Any one of the camera modules 1100a, 1100b, and 1100c can be designated as a master camera (e.g., 1100b) by image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a and 1100c) can be designated as slave cameras. Such information can be included in a control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c via control signal lines CSLa, CSLb, and CSLc that are separated from each other.

[0151] The camera modules operating as the master and the slave can be changed depending on the zoom factor or the operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom ratio, the camera module 1100b can operate as the master and the camera module 1100a can operate as the slave. Conversely, when the zoom factor indicates a high zoom ratio, the camera module 1100a can operate as the master and the camera module 1100b can operate as the slave.

[0152] In some embodiments, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a sync enable signal. For example, if the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit a sync enable signal to the camera module 1100b. The camera module 1100b that has received the sync enable signal may generate a sync signal based on the provided sync enable signal and provide the generated sync signal to the camera modules 1100a and 1100c via a sync signal line (SSL). The camera module 1100b and the camera modules 1100a and 1100c may transmit image data to the application processor 1200 in synchronization with the sync signal.

[0153] In some embodiments, the control signals provided from the camera module controller 1216 to the camera modules 1100a, 1100b, 1100c may include mode information in response to a mode signal. Based on such mode information, the camera modules 1100a, 1100b, 1100c may operate in a first operation mode and a second operation mode in association with a sensing speed.

[0154] In a first operation mode, the camera modules 1100a, 1100b, and 1100c may generate image signals at a first rate (e.g., generate image signals at a first frame rate), encode the image signals at a second rate higher than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second rate may be 30 times or less than the first rate.

[0155] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in the memory 1230 provided inside or the external storage 1400 of the application processor 1200, and then reads and decodes the encoded image signal from the memory 1230 or the storage 1400, and can display image data generated based on the decoded image signal. For example, a corresponding sub-processor among the plurality of sub-processors 1212a, 1212b, and 1212c of the image processing device 1210 can perform decoding and image processing on the decoded image signal.

[0156] In the second operation mode, the camera modules 1100a, 1100b, 1100c may generate image signals at a third rate lower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be unencoded signals. The application processor 1200 may perform image processing on the received image signals or store the image signals in the memory 1230 or the storage 1400.

[0157] The PMIC 1300 can supply power, for example, a power supply voltage, to each of the multiple camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 can supply a first power to the camera module 1100a via a power signal line PSLa, supply a second power to the camera module 1100b via a power signal line PSLb, and supply a third power to the camera module 1100c via a power signal line PSLc.

[0158] The PMIC 1300 generates power corresponding to each of the camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and may adjust the power level. The power control signal PCON may include a power adjustment signal for each operation mode of the camera modules 1100a, 1100b, and 1100c. For example, the operation mode may include a low power mode, and in this case, the power control signal PCON may include information on the camera module operating in the low power mode and the power level to be set. The power levels provided to each of the camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Also, the power levels may be dynamically changed.

[0159] The present invention is not limited by the above-described embodiments and the attached drawings, but by the appended claims. Therefore, various substitutions, modifications, and changes can be made by a person having ordinary skill in the art within the scope of the technical idea of ​​the present invention described in the claims, and these also belong to the scope of the present invention. [Explanation of symbols]

[0160] 100, 200 electronic equipment 110, 210 PCB 120, 220 AP 130, 230 First image sensor 131, 231 First transmission circuit 140, 240 Second image sensor 141, 241 Second transmission circuit 135 First Transmission Line 145 Second Transmission Line 250 Transmission Line

Claims

1. a pixel array configured to generate an electric charge in response to light; a logic circuit configured to convert the charges into first image data; an interface circuit configured to transmit the first image data to an external processor via a first transmission line and a second transmission line; the interface circuit includes a control logic disposed between the first transmission line and the second transmission line, a first switch, a first resistor, a second resistor, and a second switch disposed in series between the first transmission line and the second transmission line, and a common mode capacitor disposed between the first resistor and the second resistor; the interface circuit is configured to couple the first transmission line and the second transmission line when the interface circuit does not transmit the first image data to the external processor; the control logic is configured to control the first switch and the second switch to couple the first transmission line and the second transmission line via the first resistor and the second resistor when the interface circuit does not transmit the first image data to the external processor. Image sensor.

2. the interface circuitry is configured to transmit the first image data in accordance with a MIPI standard; 2. The image sensor of claim 1.

3. the interface circuit is configured to monitor a state of the first transmission line and the second transmission line; The interface circuit is configured to couple or decouple the first transmission line and the second transmission line based on a monitoring result.

3. The image sensor according to claim 2.

4. The MIPI standard is MIPI D-PHY.

3. The image sensor according to claim 2.

5. when the interface circuit detects transmission of second image data, different from the first image data, via the first transmission line and the second transmission line, the interface circuit is configured to couple the first transmission line and the second transmission line.

5. The image sensor according to claim 4.

6. a pixel array configured to generate an electric charge in response to light; a logic circuit configured to convert the charges into image data; an interface circuit configured to transmit the image data to an external processor via a first transmission line and a second transmission line in accordance with MIPI D-PHY; the interface circuit includes a first switch, a first resistor, a second resistor, and a second switch, which are arranged in series between the first transmission line and the second transmission line, and a common mode capacitor arranged between the first resistor and the second resistor; the interface circuit is configured to couple the first transmission line and the second transmission line via the first switch, the first resistor, the second switch, and the second resistor. Image sensor.

7. the interface circuit transmits the image data as frames or lines of the pixel array; 7. The image sensor according to claim 6.

8. the interface circuit is configured to couple the first transmission line and the second transmission line when the interface circuit does not transmit the image data to the external processor.

8. The image sensor according to claim 7.

9. the interface circuit is configured to monitor a state of the first transmission line and the second transmission line; the interface circuit is configured to couple the first transmission line and the second transmission line based on a monitoring result.

7. The image sensor according to claim 6.

10. a pixel array configured to generate an electric charge in response to light; a logic circuit configured to convert the charges into first image data; an interface circuit configured to transmit the first image data to an external processor via a first transmission line and a second transmission line in accordance with MIPI D-PHY; when the interface circuit detects transmission of second image data, different from the first image data, via the first transmission line and the second transmission line, the interface circuit is configured to adjust an impedance of the first transmission line. the interface circuit includes a first switch, a first resistor, a second resistor, and a second switch, which are arranged in series between the first transmission line and the second transmission line, and a common mode capacitor arranged between the first resistor and the second resistor; the interface circuit is configured to couple the first transmission line and the second transmission line via the first switch, the first resistor, the second resistor, and the second switch to adjust the impedance. Image sensor.

Images