Solid-state imaging device

Abstract

To provide a solid imaging device of a backside illumination type, in which the PLS characteristic is improved.SOLUTION: A solid imaging device includes a first semiconductor substrate 111, a photoelectric conversion unit 111b disposed on the first semiconductor substrate 111 and converting incident light into charges, a charge accumulation unit MN that holds the charges transferred from the photoelectric conversion unit 111b through a transfer transistor TX1, and a wiring layer stacked on the first semiconductor substrate 111 and including a plurality of metal wires M1, M2, and M3. The incident light enters the first semiconductor substrate 111 from a back surface side that is on the opposite side to the wiring layer. Between the photoelectric conversion unit 111b and the metal wire, light absorption films 121 and 123 are further provided.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device. [Background technology]

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors are becoming more popular than CCD (Charge Coupled Device) image sensors as solid-state imaging devices used in various cameras such as digital still cameras, smartphones, and in-vehicle cameras. This is because CMOS image sensors are superior in terms of power consumption and readout speed, and their back side illumination (BSI) structure has dramatically improved their sensitivity.

[0003] Conventional CMOS image sensors use a rolling shutter method that sequentially reads out pixel signals from each pixel row by row. In this case, for example, when capturing an image of a fast-moving subject, the image can become distorted. To address this issue, CMOS image sensors have been developed that use a global shutter method that simultaneously reads out all pixels to the charge storage section and outputs the signal.

[0004] However, to achieve this, it is necessary to reduce the area of ​​the photodiode and provide a charge storage section (memory node section), which causes the number of saturated electrons and sensitivity characteristics to deteriorate compared to the rolling shutter method.

[0005] In addition, in the global shutter method, the read signal is temporarily stored in the charge storage section. If parasitic light gets into the charge storage section during this time, it will become noise. In order to suppress the sensitivity to such parasitic light, called PLS (Parasitic Light Sensitivity), the charge storage section is shielded from light by a metal light-shielding film.

[0006] In the case of a front-illuminated image sensor, it is easy to place a light-shielding film directly above the charge storage area. However, in the case of a back-illuminated type, light is irradiated from the back side of the substrate, so the same light-shielding method as for the front-illuminated type is ineffective.

[0007] In response to this, Patent Document 1 discloses that in a back-illuminated image sensor, deep elements are formed from the back side of the substrate, and a metal film is embedded therein to serve as a light-shielding film.

[0008] Patent Document 2 also discloses a structure in which a first substrate and a second substrate are connected by Cu-Cu bonding in a back-illuminated image sensor. Here, a PD (photodiode) and a gate and drain of a transistor that reads out charge from the PD are provided on the first substrate, and a memory node section and a transistor that reads out charge from the memory node to an FD (field diffusion) are arranged on the second substrate. Furthermore, the memory node section of the second substrate is connected to the drain section of the transistor of the first substrate, and a wiring capacitance (structure sandwiching a high dielectric constant material) for securing capacitance is arranged on the second substrate to expand the PD area. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent No. 6052353 [Patent Document 2] Patent No. 4835780 Summary of the Invention [Problem to be solved by the invention]

[0010] In a global shutter type image sensor, the drain of the transfer transistor that reads out the electric charge is connected to the memory node. As a result, the drain also causes PLS. Therefore, in order to improve the PLS characteristics, it is desirable to shield the drain from light as well.

[0011] In addition, in the case of back-illuminated devices, light incident from the back side of the substrate can be reflected by the wiring and leak into the drain section, causing PLS. This is particularly noticeable when there is high incident light (when the angle of incidence of light is large).

[0012] An object of the present disclosure is to improve the PLS characteristics in a back-illuminated solid-state imaging device. [Means for solving the problem]

[0013] The solid-state imaging device of the present disclosure includes a first semiconductor substrate, a photoelectric conversion unit arranged on the first semiconductor substrate and converting incident light into electric charges, a charge storage unit that holds electric charges transferred from the photoelectric conversion unit via a transfer transistor, and a wiring layer that is stacked on the first semiconductor substrate and includes a plurality of wirings. Incident light is incident on the first semiconductor substrate from the back side, which is the side opposite to the wiring layer. The solid-state imaging device further includes a light absorbing film between the photoelectric conversion unit and the wirings. Effect of the Invention

[0014] According to the solid-state imaging device of the present disclosure, a light absorbing film is provided between the photoelectric conversion unit and the wiring, so that it is possible to suppress the occurrence of parasitic photosensitivity caused by reflection of light incident from the back surface side by metal wiring or the like. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing a pixel circuit of a solid-state imaging device according to the first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing a planar layout pattern corresponding to FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line XX' in FIG. [Figure 4] FIG. 4 is a diagram showing a manufacturing process of an exemplary solid-state imaging device according to the present disclosure. [Diagram 5] FIG. 5 is a diagram showing the manufacturing process of the solid-state imaging device, following FIG. [Figure 6] FIG. 6 is a diagram showing the manufacturing process of the solid-state imaging device, following FIG. [Figure 7] FIG. 7 is a diagram showing the manufacturing process of the solid-state imaging device, following FIG. [Figure 8] FIG. 8 is a diagram showing the manufacturing process of the solid-state imaging device, following FIG. [Figure 9] FIG. 9 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to the second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] (Embodiment 1) Hereinafter, a first embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a diagram showing a pixel circuit of a global shutter system in an exemplary solid-state imaging device of this embodiment.

[0017] Figure 1 shows the pixel system with two pixels per cell, with one of the pixels enclosed in a dashed rectangle. Each pixel is equipped with a photodiode PD, which is the photoelectric conversion section, a transfer transistor TX1 that reads out charge from the PD to a memory node MN, a transfer transistor TX2 that reads out charge from the memory node section to a floating diffusion FD, and a global reset transistor GRST that resets the charge of the PD. In addition, the amplification transistor SF, reset transistor RS, and selection transistor SEL are shared between the two pixels.

[0018] Each transistor has the following functions. First, the GRST transistor is turned on to reset the charge in the PD. After that, exposure begins in the PD, and charge is generated by photoelectric conversion. Next, the RS transistor and TX2 transistor are turned on to reset and empty the charge in the memory node MN. Next, the TX1 transistor is turned on, and the charge generated in the PD is transferred to and accumulated in the memory node MN (charge storage section). Because this is a global shutter system, charge is read out simultaneously in all pixels.

[0019] The memory node section is electrically connected to the MIM capacitor, and the upper electrode of the MIM capacitor is connected to the power supply voltage PVDD. The charge held in the memory node MN is read out to the FD in sequence according to the timing chart of the TX2 transistor after the RS transistor is turned on to reset the charge in the FD. This changes the potential in the FD, and the voltage corresponding to the potential change is applied to the SF transistor as the gate voltage. The voltage amplified by the SF transistor is output to the vertical signal line (PIXOUT) in the pixel selected by the SEL transistor.

[0020] FIG. 2 is a diagram showing a planar layout pattern corresponding to the circuit diagram of FIG.

[0021] It has a two-pixel, one-cell configuration, with two photodiodes PD arranged vertically. A TX1 transistor that reads out charge from PD to a memory node MN, a TX2 transistor that reads out charge from MN to a floating diffusion FD, and a GRST transistor that resets PD are arranged for each pixel. In contrast, an amplification transistor SF, a reset transistor RS, and a selection transistor SEL are arranged for each two pixels.

[0022] MN is located between the TX1 transistor and the TX2 transistor, and is electrically connected to an MIM capacitor (not shown in FIG. 2). In addition, MN, the SF transistor, the SEL transistor, and the RS transistor are disposed between pixels.

[0023] By reducing the area of ​​the memory node MN and disposing it between the pixels, the area of ​​the PD can be increased.

[0024] The drain of the GRST transistor, which resets the PD, is connected to VDD, which is shared by the two pixels above and below. The charge held in the memory node MN is transferred to the FD by turning on the TX2 transistor. The FD is also shared by the two pixels above and below. The RS transistor is placed adjacent to the FD.

[0025] Next, Fig. 3 is a diagram that shows a schematic cross section taken along line XX' in Fig. 2. That is, Fig. 3 shows a cross section corresponding to the photodiode PD, the TX1 transistor, the memory node MN, and the TX2 transistor.

[0026] As shown in FIG. 3, the solid-state imaging device has a structure in which a sensor side chip 101 and a logic side chip 102 are bonded together, and is a back-illuminated image sensor.

[0027] The sensor side chip 101 includes a first semiconductor substrate 111 and a wiring layer, and mainly includes components related to pixel characteristics such as photodiodes, memory nodes, etc. The logic side chip 102 includes a second semiconductor substrate 152 and a wiring layer, and mainly includes transistors such as signal processing, drive circuits, and control circuits, and a wiring layer.

[0028] The wiring layer of the sensor chip 101 has a structure in which a TEOS (tetra ethoxy silane) film 112, which is an insulating film, is laminated, in which multiple layers (four layers in the example of FIG. 3) of metal wiring M1, M2, M3, and M4 and via plugs V1, V2, and V3 connecting these layers are formed. As the insulating film, a Si-CN film 113, a P-SiN film 114, a SiCN / SiCO film 115, etc. are also used.

[0029] A photodiode 111b and a memory node MN are formed on the first semiconductor substrate 111. A TX1 transistor that reads out charge from the photodiode 111b to the memory node MN and a TX2 transistor that reads out charge from the memory node MN are formed in the TEOS film 112 directly below the first semiconductor substrate 111. Note that the TX1 transistor and the TX2 transistor are shown only to show the positions where they are formed, and are not shown in terms of the specific structures such as the source and drain. A polysilicon layer 130 provided in the TEOS film 112 is electrically connected to the memory node MN.

[0030] Furthermore, a metal-insulator-metal (MIM) capacitor 124 is formed in the TEOS film 112 directly below the first semiconductor substrate 111. The MIM capacitor 124 includes electrodes made of a material having a property of absorbing light. For example, the lower electrode 121 and the upper electrode 123 are TiN electrodes. An insulating film 122 made of a high dielectric constant material, such as HfO2, is provided between the lower electrode 121 and the upper electrode 123 to form an MIM structure.

[0031] The MIM capacitor 124 absorbs the light 161 incident on the photodiode 111b from the back side, thereby suppressing the light 161 from being reflected by the metal wiring M1 or the like and entering the memory node MN, the TX1 transistor (particularly the drain), or the like. That is, in FIG. 3, when the lower electrode 121 reflects light, there is a possibility that the light 161 may enter the memory node MN as shown by the dashed line, which causes parasitic photosensitivity. However, since the lower electrode 121 is formed of TiN or the like that absorbs light, such reflection does not occur and the light shown by the dashed line is not generated, so that the parasitic photosensitivity can be suppressed. It is sufficient that at least one of the lower electrode 121 and the upper electrode 123 functions as a light absorbing film.

[0032] For this purpose, the MIM capacitor 124 (particularly the lower electrode 121) is provided in a region that covers the photodiode 111b (a region that overlaps with the photodiode 111b when viewed perpendicularly to the rear surface of the first semiconductor substrate 111).

[0033] The lower electrode 121 is connected to the memory node MN through a via plug 131 and a polysilicon layer 130. The upper electrode 123 is connected to a metal wiring M1 connected to PVDD, and the capacitance of the MIM capacitor 124 can be adjusted by applying a voltage of PVDD. The upper electrode 123 is connected to the metal wiring M1 through a contact plug 132.

[0034] Here, it is desirable to place the MIM capacitor 124 in the wiring layer of the sensor side chip 101. This is for the purpose of suppressing parasitic light sensitivity as described above, as well as for facilitating manufacture.

[0035] In other words, since the MIM capacitor 124 is provided for the photodiode 111b for each pixel, if the MIM capacitor 124 is arranged on the logic-side chip 102, Cu-Cu bonding is required for each pixel pitch between the sensor-side chip 101 and the logic-side chip 102. This requires extremely high accuracy of alignment, making processing difficult. In particular, the yield is expected to worsen as the pixel pitch becomes smaller and the pixel density increases.

[0036] In contrast, when the MIM capacitor 124 is provided on the sensor chip 101 as shown in Fig. 3, Cu-Cu bonding is not required for each pixel pitch. Therefore, the precision required for bonding chips can be reduced. As a result, it is easy to respond to miniaturization and high pixel density of solid-state imaging devices.

[0037] Next, the memory node MN will be described. It is provided on the deep side (the wiring layer side, or the side opposite to the back surface where light is incident) of the first semiconductor substrate 111. Also, the area of ​​the photodiode 111b is increased and disposed in the inter-element isolation region between the photodiodes 111b (pixels) which has accordingly become narrower. For this reason, the area of ​​the memory node MN is reduced and disposed below the inter-element isolation region. Reducing the area of ​​the memory node MN makes it difficult for incident light to enter the memory node MN, improving the parasitic light sensitivity characteristics. Specifically, it is desirable to make the width of the memory node MN smaller than the width of the inter-element isolation region.

[0038] Furthermore, when the area of ​​the memory node MN is reduced, the capacity of the memory node MN to store electric charge is reduced. Therefore, the memory node MN is electrically connected to the MIM capacitor 124 to ensure the necessary capacity.

[0039] In addition, as an MIM capacitor for ensuring the required capacitance for the memory node MN, it is possible to form it by sandwiching a high dielectric constant material between metal wiring. However, in this case, it may affect the wiring in the part where the capacitance should be kept small. For example, in the configuration of Patent Document 2, the capacitance of the wiring becomes extremely high, and there is a possibility that a read failure of the transfer transistor occurs.

[0040] In contrast, if an MIM capacitor 124 is formed separately from the metal wiring as shown in FIG. 3, the effect on the wiring capacitance can be suppressed.

[0041] Moreover, by increasing the area of ​​the photodiode 111b, the saturation characteristics can be improved.

[0042] Next, the DTI (Deep Trench Isolation) 141 and the metal grid 142 will be described.

[0043] The DTI 141 is an element isolation layer formed by forming a groove from the back surface side of the first semiconductor substrate 111 and filling it with an insulating material, and is disposed between pixels. If a light-shielding material, such as tungsten, is used to fill the groove, the DTI 141 also functions as a light-shielding film. In the solid-state imaging device of FIG. 3, the DTI 141 is also disposed around the photodiode 111b to separate it from other adjacent photodiodes (not shown). The DTI 141 suppresses color mixing between pixels. Furthermore, by disposing the memory node MN between pixels and disposing the DTI 141 above it (back surface side), the memory node MN can be shielded from light.

[0044] The metal grid 142 is a metal layer patterned on the first semiconductor substrate 111 and functions as a light shielding film to prevent color mixing between pixels, etc. It is particularly useful for preventing incident light with a large angle from entering the adjacent photodiode 111b.

[0045] If the metal grid 142 is placed on the DTI 141 and is formed using the same material (such as tungsten) as that used to embed the DTI 141, the DTI 141 and the metal grid 142 can be formed integrally, reducing the number of manufacturing steps and enabling stable formation.

[0046] The logic-side chip 102 is formed using a second semiconductor substrate 152. Although detailed configuration is omitted, a TEOS film 112 is provided on the uppermost layer on the second semiconductor substrate 152, and is bonded to the TEOS film 112 of the sensor-side chip 101 via a SiCN film 116.

[0047] <Method of Manufacturing Solid-State Imaging Device> Next, a method for manufacturing the solid-state imaging device of the present disclosure will be described. Since it is a back-illuminated image sensor, it is manufactured by bonding the sensor chip 101 and the logic chip 102 together.

[0048] Fig. 4 is a diagram showing the manufacturing process of the sensor side chip 101. Fig. 4 is shown upside down compared to Fig. 3 (and is further shown as seen from the opposite side of line XX').

[0049] A P-type substrate 151 is prepared, and an N-type epitaxial layer is formed thereon. This epitaxial layer becomes the first semiconductor substrate 111 in Fig. 3. Photodiode 111b is formed in first semiconductor substrate 111 by implanting P-type ions near the substrate surface and N-type ions deeper into the substrate. The portion other than photodiode 111b remains as N-type layer 111a.

[0050] Next, in order to form a memory node MN, N-type ions are implanted near the surface of the N-type layer 111a, after which the gate electrodes of the transistors (TX1, TX2, etc.) of each pixel are formed.

[0051] It is desirable to suppress damage to the substrate when connecting the MIM capacitor 124 to the memory node MN, so a polysilicon layer 130 is formed to perform the connection.

[0052] Next, an interlayer insulating film (TEOS film 112, however, in FIG. 4, the thickness thereof reaches the underside of the lower electrode 121) is formed. Furthermore, a via plug 131 for connection to the polysilicon layer 130 is formed. For example, the via plug 131 is formed by forming a hole by etching and filling it with a conductor.

[0053] Next, the lower electrode 121 is formed. For this, a TiN film is deposited on the formed portion of the TEOS film 112, and then etching is performed using a mask having the pattern of the lower electrode 121. As a result, the lower electrode 121 connected to the polysilicon layer 130 through the via plug 131 is formed.

[0054] Next, an HfO2 film, which is a high dielectric constant material, is deposited, and a TiN film is further deposited thereon to form the upper electrode 123. After that, the TiN film and the HfO2 film are etched using a mask having the pattern of the upper electrode 123. As a result, an MIM capacitor 124 in which the insulating film 122 is sandwiched between the lower electrode 121 and the upper electrode 123 is formed.

[0055] Thereafter, the remaining portion of the TEOS film 112 in FIG. 4 and other wiring layers therein (not shown) are formed in sequence.

[0056] 5 will now be described. Here, a wiring layer is formed on the TEOS film 112 including the MIM capacitor 124.

[0057] First, a contact hole for connecting to the upper electrode 123 is formed in the TEOS film 112 including the MIM capacitor 124, and a metal thin film is deposited to form a contact plug 132. Then, an insulating layer including metal wirings M1, M2, M3, and M4 and via plugs V1, V2, and V3 is formed. The insulating layer is mainly the TEOS film 112, and has a configuration in which a Si-CN film 113, a P-SiN film 114, and a SiCN / SiCO film 115 are sandwiched between multiple TEOS films 112.

[0058] The metal wirings M1 to M4 and the via plugs V1 to V3 may be formed using a normal wiring flow such as a damascene method. That is, after forming a wiring groove pattern in an insulating layer (mainly a TEOS film 112) by etching or the like, a metal thin film is formed on the entire surface so as to fill the wiring groove pattern. Furthermore, the surface of the metal thin film is flattened by a CMP (chemical mechanical polishing) method or the like, and the metal wirings M1 to M4 and the via plugs V1 to V3 are formed in the wiring groove pattern.

[0059] After the metal wirings M1 and M2 are formed, a P-SiN film 114 is formed before the next layer of the TEOS film 112. Similarly, after the metal wirings M3 and M4 are formed, a SiCN / SiCO film 115 is formed before the next layer of the TEOS film 112 is formed.

[0060] After the SiCN / SiCO film 115 is formed on the metal wiring M4, a TEOS film 112 and a SiCN film 116 are further formed.

[0061] Next, as shown in FIG. 6, the sensor side chip 101 of FIG. 5 is bonded to the logic side chip 102. In FIG. 6, the sensor side chip 101 shown in FIG. 5 is again shown upside down. The bonding is performed by bonding the SiCN films 116 provided on the respective TEOS films 112. For example, the surfaces of both chips to be bonded are activated by plasma treatment or the like, and brought into contact with each other. This allows the chips to be bonded by the action of van der Waals forces (intermolecular forces). Furthermore, annealing is performed to form covalent bonds on the bonding surfaces, strengthening the bond.

[0062] Fig. 7 shows the state after such bonding. In addition to being physically bonded, the sensor chip 101 and the logic chip 102 are electrically connected using TSVs (Through-Silicon) (TSVs are not shown). Alternatively, a method of exposing Cu pads or the like at the bonding interface between both chips and bonding the pads together to ensure electrical continuity (Cu-Cu bonding) may be used.

[0063] After bonding the chips together, the substrate 151 is polished away to expose the photodiode 111b.

[0064] Next, the process of FIG. 8 will be described. Here, the DTI 141 is formed for the purpose of shading the memory node MN and reducing crosstalk. For this purpose, the first semiconductor substrate 111 (N-type layer 111a) is etched up to the vicinity of the memory node MN to form a deep trench 143. Next, a seed layer (not shown) such as TiN is deposited to cover the side and bottom of the trench 143, and then a tungsten film 144 is formed in the trench 143 and on the first semiconductor substrate 111. Furthermore, the tungsten film 144 is planarized by the CMP method. This state is shown in FIG. 8.

[0065] From the viewpoint of light blocking, it is desirable to provide the depth of the trench 143 up to directly above the memory node MN without leaving the N-type layer 111a in between. However, it is possible that the memory node MN may be damaged due to etching or the like when forming the trench 143. Therefore, in order to avoid this, the N-type layer 111a is left between the memory node MN and the trench 143. If the above damage is avoided or repaired, there is no need to leave the N-type layer 111a.

[0066] Thereafter, the tungsten film 144 is etched and patterned so as to open above the photodiode 111b, thereby forming the metal grid 142 (see FIG. 3).

[0067] If an oxide film were used as the filling material for the trenches 143 for forming the DTI 141, it would need to be formed in a separate process from the metal grid 142. In contrast, by using tungsten as the filling material in the above process, it is possible to fill the trenches 143 and form the tungsten film for forming the metal grid 142 in the same process. This reduces the number of processes and suppresses manufacturing costs.

[0068] (Embodiment 2) Next, a solid-state imaging device according to a second embodiment of the present disclosure will be described with reference to Fig. 9. Since many of the configurations are common to the solid-state imaging device according to the first embodiment shown in Fig. 3, the same components are given the same reference numerals, and differences will be mainly described. Also, the pixel circuit and planar layout pattern are the same as those in Figs. 1 and 2.

[0069] The solid-state imaging device in Fig. 3 has four layers of metal wiring M1, M2, M3, and M4, and three layers of via plugs V1, V2, and V3 that connect them. In contrast, the solid-state imaging device in Fig. 9 has three wiring layers, and the fourth layer of metal wiring M4 and the third layer of via plug V3 connected thereto are not formed. Accordingly, the TEOS film 112 in the layer that included the metal wiring M4 in Fig. 3 is also not formed.

[0070] In a structure in which the sensor side chip 101 and the logic side chip 102 are bonded together, electromagnetic waves are generated in the circuit of the logic side chip 102, and these waves may enter the sensor side chip 101 and become noise, which may deteriorate the pixel characteristics. Therefore, wiring for blocking electromagnetic waves is arranged in at least one of the sensor side chip 101 and the logic side chip 102, and the photodiode portion is blocked.

[0071] 3, the fourth-layer metal wiring M4 is arranged as a shield layer for this purpose. However, the MIM capacitor 124 is arranged between the wiring layer and the photodiode 111b, and is laid out to cover the photodiode 111b. Therefore, the MIM capacitor 124 functions to block electromagnetic waves from the logic-side chip 102. In other words, even if the fourth-layer metal wiring M4 is omitted, image quality degradation caused by electromagnetic waves from the logic-side chip 102 can be suppressed.

[0072] 9, the dashed arrow indicates electromagnetic waves 162 from the logic-side chip 102. Even without the fourth-layer metal wiring M4, the electromagnetic waves 162 are blocked by the MIM capacitor 124 and are prevented from penetrating into the photodiode 111b.

[0073] As described above, according to the solid-state imaging device of the second embodiment, the fourth metal wiring M4 and the insulating film layer including this can be omitted, so that the materials and manufacturing steps can be reduced, leading to cost reduction. [Industrial Applicability]

[0074] INDUSTRIAL APPLICABILITY The technique disclosed herein can improve the PLS characteristics in a back-illuminated solid-state imaging device, making the device useful as a solid-state imaging device for use in various cameras. [Explanation of symbols]

[0075] TX1 Transfer transistor TX2 Transfer transistor M1, M2, M3, M4 metal wiring V1, V2, V3, V4 via plugs MN Memory node (charge storage section) 101 Sensor chip 102 Logic chip 111 First semiconductor substrate 111a N-type layer 111b Photodiode 112 TEOS membrane 113Si-CN film 114 P-SiN film 115 SiCN / SiCO film 116 SiCN film 121 Lower electrode 122 Insulating film 123 Upper electrode 124 MIM Capacitor 130 Polysilicon layer 131 Via Plug 132 Contact plug 141 DTI (device isolation region) 142 Metal Grid 143 Trench 144 Tungsten Film 151 P type board 151 Substrate 152 Second semiconductor substrate 161 light 162 Electromagnetic Waves

Claims

1. A first semiconductor substrate; A photoelectric conversion unit arranged on the first semiconductor substrate and configured to convert incident light into electric charges; a charge storage unit that stores charges transferred from the photoelectric conversion unit via a transfer transistor; a floating diffusion to which charges are transferred from the charge storage unit via another transfer transistor; a wiring layer including a plurality of metal wirings and laminated on the first semiconductor substrate; the incident light is incident on the first semiconductor substrate from a back surface side opposite to the wiring layer, A light absorbing film is further provided between the photoelectric conversion unit and the metal wiring, The light absorbing film is formed using titanium nitride, a metal-insulator-metal (MIM) capacitor having an insulating film made of a high dielectric constant material sandwiched between an upper electrode and a lower electrode, at least the lower electrode being made of the light absorbing film; 2. A solid-state imaging device, comprising: a first semiconductor substrate having a first insulating film and a second insulating film formed therein; a second insulating film formed therein; and a second insulating film formed therein.

2. In claim 1, A solid-state imaging device characterized in that the MIM capacitor is located below the photoelectric conversion section and is provided in a region that overlaps with the photoelectric conversion section when viewed perpendicularly to the back surface of the first semiconductor substrate.

3. In claim 2, The solid-state imaging device, wherein the MIM capacitor is connected to the charge storage section.

4. In any one of claims 1 to 3, a second semiconductor substrate bonded to the first semiconductor substrate via the wiring layer; The solid-state imaging device, wherein the light absorbing film is provided on the first semiconductor substrate side.

Images