Semiconductor Device

Abstract

A semiconductor device 1a comprises: a package 100 having a rectangular shape when viewed in plan and including a first side 101, a second side 102 parallel to the first side 101, a third side 103 orthogonal to the first side 101 and the second side 102, and a fourth side 104 parallel to the third side 103 and orthogonal to the first side 101 and the second side 102; a power supply terminal PVIN1 (or PVIN2) provided on the first side 101; a power ground terminal PGND1 (or PGND2) provided on the second side 102; a switch output terminal SW1 (or SW2) provided on the second side 102; an upper switch 11H connected between the power supply terminal PVIN1 (or PVIN2) and the switch output terminal SW1 (or SW2); and a lower switch 11L connected between the switch output terminal SW1 (or SW2) and the power ground terminal PGND1 (or PGND2).

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Conventionally, various proposals have been made regarding the pin arrangement of semiconductor devices (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 096573 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in order to optimize the PCB (printed circuit board) layout, there is room for further consideration regarding the pin arrangement of the semiconductor device.

[0005] In view of the above problems found by the present inventors, the invention disclosed in this specification has an object to provide a semiconductor device capable of optimizing the PCB layout. [Means for solving the problem]

[0006] The semiconductor device disclosed in this specification has a configuration (first configuration) having a package that is rectangular in plan view, having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, or the third side, or the fourth side; a power ground terminal provided on the second side, or the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; and a lower switch connected between the switch output terminal and the power ground terminal.

[0007] In the semiconductor device having the above-mentioned first configuration, it is preferable that the upper switch, the lower switch, and the switch output terminal are provided for each of a plurality of channels (second configuration).

[0008] In addition, in the semiconductor device having the above-mentioned second configuration, it is preferable that the switch output terminals provided for each of the plurality of channels are arranged symmetrically between at least two channels (third configuration).

[0009] In the semiconductor device having the second or third configuration, it is preferable that the power supply terminal and the power ground terminal are provided for each of the plurality of channels (fourth configuration).

[0010] In addition, in the semiconductor device having the above-mentioned fourth configuration, it is preferable that the power supply terminals provided for each of the plurality of channels are arranged symmetrically between at least two channels (fifth configuration).

[0011] In addition, in a semiconductor device having the fourth or fifth configuration, the power ground terminals provided for each of the plurality of channels may be configured to be symmetrically arranged between at least two of the channels (sixth configuration).

[0012] Alternatively, in the semiconductor device having the second or third configuration, at least one of the power power supply terminal and the power ground terminal may be configured to be shared by the multiple channels (seventh configuration).

[0013] Moreover, the semiconductor device having any one of the above first to seventh configurations may be configured (eighth configuration) further including a heat dissipation pad exposed on the top surface of the package.

[0014] In addition, in a semiconductor device having any of the above first to eighth configurations, it is preferable that the thermal resistance from the semiconductor chip sealed in the package to the top surface is smaller than the thermal resistance from the semiconductor chip to the bottom surface of the package (ninth configuration).

[0015] In addition, in a semiconductor device having any one of the above first to ninth configurations, the upper switch and the lower switch may be configured (tenth configuration) to be biased toward the second side in a plan view.

[0016] In addition, in a semiconductor device having any one of the first to tenth configurations above, the upper switch and the lower switch may be configured (eleventh configuration) to be arranged in a vertical row along a second direction perpendicular to a first direction in which the first side and the second side extend in a plan view.

[0017] In the semiconductor device having any one of the first to eleventh configurations, the lower switch may have a larger element size than the upper switch (twelfth configuration).

[0018] In the semiconductor device having any one of the first to twelfth configurations, the power supply terminal and the power ground It is preferable that all of the terminals are provided on the third side or the fourth side, and the power ground terminals are arranged closer to the second side than the power power supply terminals (thirteenth configuration).

[0019] In addition, a semiconductor device having any one of the first to thirteenth configurations above may be configured (fourteenth configuration) to have an output feedback control unit that drives the upper switch and the lower switch so that the output current supplied from the switch output terminal to a load matches a predetermined target value.

[0020] In the semiconductor device having the fourteenth configuration, the output feedback control section may be configured to perform output feedback control of a bottom detection fixed on-time type (fifteenth configuration).

[0021] In addition, the module disclosed in this specification has a configuration (16th configuration) including a printed circuit board, a semiconductor device having any one of the configurations 1 to 15 above, and a load that receives an output current from the semiconductor device.

[0022] In the module having the sixteenth configuration, the semiconductor device is mounted on a first main surface of the printed circuit board, and includes a power supply line connected to the power supply terminal, a power ground Terminals and a switch output line connected to the switch output terminal may be laid on the second main surface of the printed circuit board (seventeenth configuration).

[0023] In addition, in a module having the above-mentioned 17th configuration, the main portions of the power power supply line and the power ground line may be configured (18th configuration) to be laid in parallel along a first direction in which the first side and the second side extend in a plan view.

[0024] In the module having the eighteenth configuration, it is preferable that a plurality of the semiconductor devices are mounted on the first main surface along the first direction (nineteenth configuration).

[0025] In addition, in the module having any one of the seventeenth to nineteenth configurations, the power supply line and the Power At least one of the ground lines may be arranged so as to overlap the semiconductor device in a plan view (twentieth configuration).

[0026] In addition, in a module having any one of the seventeenth to twentieth configurations, it is preferable that a bypass capacitor is connected between the power supply line and the power ground line on the second main surface (twenty-first configuration).

[0027] In the module having the twenty-first configuration, the bypass capacitor may be mounted so as to overlap the semiconductor device in a plan view (twenty-second configuration).

[0028] In addition, in a module having the above-mentioned 21st or 22nd configuration, it is preferable that the bypass capacitor is mounted at a position where the closed loop formed together with the upper switch and the lower switch is smallest (23rd configuration).

[0029] In addition, in a module having any of the above-mentioned 16th to 23rd configurations, the power supply terminal, the switch output terminal, the power ground terminal, and the discrete components externally attached thereto, which are provided for each of the plurality of channels, may be configured to be symmetrically arranged between at least two channels (24th configuration).

[0030] Moreover, the module having any one of the sixteenth to twenty-fourth configurations may be configured (twenty-fifth configuration) further including a heat sink attached to the semiconductor device.

[0031] In addition, in the module having the above-mentioned 16th configuration, the semiconductor device and at least some of the discrete components externally attached to it may be configured to be mounted on the same side of the printed circuit board (26th configuration).

[0032] In addition, the module having the above-mentioned 26th configuration may be configured (27th configuration) further having a heat sink that is commonly attached to both the semiconductor device and the discrete component mounted on the same side of the printed circuit board.

[0033] Moreover, the module having any one of the sixteenth to twenty-seventh configurations may be configured (twenty-eighth configuration) further including a boost circuit that generates a boosted voltage from a battery voltage and supplies the boosted voltage to the power supply terminal.

[0034] In the module having any one of the sixteenth to twenty-eighth configurations, the load may be a light emitting diode (twenty-ninth configuration). Effect of the Invention

[0035] According to the invention disclosed in this specification, it is possible to provide a semiconductor device that allows the PCB layout to be optimized. [Brief description of the drawings]

[0036] [Figure 1] Example of application of LED driver IC (2ch) [Diagram 2] Example of LED driver IC (3ch) application [Diagram 3] Circuit configuration of LED driver IC [Figure 4] Diagram showing bottom detection on-time fixed output feedback control [Diagram 5] Diagram for evaluating power loss in LED driver ICs [Figure 6] Three-sided view showing the LED driver IC package [Figure 7] A perspective view of the LED driver IC package [Figure 8] A perspective view showing an example of a heat sink attached to an LED driver IC. [Figure 9] Diagram for evaluating the thermal resistance of an LED driver IC [Figure 10A]A diagram showing the pin arrangement (first example) of an LED driver IC (2ch) [Figure 10B] A diagram showing the pin arrangement (second example) of an LED driver IC (2ch) [Figure 11A] A diagram showing the pin arrangement (first example) of an LED driver IC (3ch) [Figure 11B] Pin arrangement (second example) of LED driver IC (3ch) [Figure 12] A diagram showing the internal structure of the LED driver IC (2ch) shown in Figure 10A. [Figure 13A] A diagram showing the internal structure of the LED driver IC (3ch) shown in Figure 11A. [Figure 13B] A diagram showing the internal structure of the LED driver IC (3ch) shown in Figure 11B. [Figure 14A] PCB layout diagram for LED driver IC (2ch) using synchronous rectification method [Figure 14B] Diagram showing the PCB layout of an LED driver IC (2ch) that uses diode rectification [Figure 14C] Another PCB layout diagram for an LED driver IC (2ch) that uses synchronous rectification [Figure 14D] Another PCB layout diagram for an LED driver IC (2ch) that uses diode rectification [Figure 15] PCB layout diagram for LED driver IC (3ch) [Figure 16] A diagram showing the formation of a closed loop for bypass capacitors. [Figure 17] Diagram showing vertical arrangement of LED driver ICs (3ch) [Figure 18] A diagram showing the PCB layout (comparison example) of an LED driver IC (3ch) [Figure 19] FIG. 13 is a diagram showing a first modified example of a pin arrangement. [Figure 20] FIG. 13 is a diagram showing a second modified example of a pin arrangement. [Figure 21] FIG. 11 is a diagram showing a third modified example of a pin arrangement. [Figure 22] FIG. 11 is a diagram showing a fourth modified example of a pin arrangement. [Diagram 23] Diagram showing PCB layout variations [Figure 24] A diagram showing an example of QFP adoption [Diagram 25] A diagram showing the PCB layout with the LED driver IC (3ch) and discrete components mounted on the same surface. [Figure 26] A diagram showing the α-β cross section of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] <LED[light emitting diode]ドライバIC> 1 is a diagram showing an example of a configuration of an LED lamp module to which a two-channel LED driver IC is applied. The LED lamp module X of this example configuration includes a two-channel LED driver IC1a, a boost circuit 2, an MCU [micro control unit] 3, light-emitting diodes LED1 and LED2 (in this figure, an LED string in which a plurality of light-emitting diode elements are connected in series), and various discrete components (capacitors C1 and C2, capacitors C11 to C13, capacitors C21 to C23, inductors L1 and L2, resistors R1 and R2, and sense resistors Rs1 and Rs2).

[0038] The LED driver IC1a is a semiconductor device that steps down the boosted voltage Vbst to supply power to the light emitting diodes LED1 and LED2. The LED driver IC1a has a plurality of external terminals (such as a VIN pin, a VREG5 pin, a GND pin, a TON pin, a SO pin, a CSB pin, a SCK pin, a SI pin, a PVIN1 pin, a BOOT1 pin, a SW1 pin, a PGND1 pin, an SNSP1 pin, an SNSN1 pin, a PVIN2 pin, a BOOT2 pin, a SW2 pin, a PGND2 pin, an SNSP2 pin, and an SNSN2 pin) as means for establishing electrical connection with the outside of the IC.

[0039] The VIN pin is the input voltage supply terminal for the signal system. The VREG5 pin is the output terminal of the internal regulator. The GND pin is the ground terminal for the signal system. The TON pin is the resistor connection terminal for setting the on time. The SO pin is the serial data output terminal for SPI [serial peripheral interface] communication. The CSB pin is the chip select input terminal for SPI communication. The SCK pin is the serial clock input terminal for SPI communication. The SI pin is the serial data input terminal for SPI communication.

[0040] The PVIN1 pin and PVIN2 pin are respectively power system input voltage supply terminals (= power power supply terminals). The BOOT1 pin and BOOT2 pin are respectively bootstrap capacitor connection terminals for driving the upper gate. The SW1 pin and SW2 pin are respectively switch output terminals. The PGND1 pin and PGND2 pin are respectively power system ground terminals (= power ground terminals). The SNSP1 pin and SNSP2 pin are respectively output current sense input terminals (+). The SNSN1 pin and SNSN2 pin are respectively output current sense input terminals (-).

[0041] The external terminals with a "1" at the end of their reference numbers (PVIN1, SW1, PGND1, SNSP1, and SNSN1) are all for the first channel, while the external terminals with a "2" at the end of their reference numbers (PVIN2, SW2, PGND2, SNSP2, and SNSN2) are all for the second channel.

[0042] The VIN pin is connected to the application terminal of the battery voltage +B (e.g., 13V). The GND pin is connected to the ground terminal. A capacitor C1 (=input smoothing capacitor) is connected between the VIN pin and the GND pin. A capacitor C2 (=output smoothing capacitor of the internal regulator) is connected between the VREG5 pin and the GND pin. A resistor R1 (=on-time setting resistor) is connected between the TON pin and the ground terminal. A resistor R2 (=pull-up resistor) is connected between the SO pin and the application terminal of the power supply voltage Vcc (e.g., 5V). The SO pin, CSB pin, SCK pin, and SI pin are each connected to MCU3.

[0043] The PVIN1 pin is connected to an application terminal of a boost voltage Vbst (for example, 65V). The SW1 pin is connected to a first terminal of an inductor L1. A second terminal of the inductor L1 is connected to a first terminal of a sense resistor Rs1. A second terminal of the sense resistor Rs1 is connected to an anode of the light-emitting diode LED1. A cathode of the light-emitting diode LED1 is connected to a ground terminal. A capacitor C11 (=bypass capacitor) is connected between the PVIN1 pin and the PGND1 pin. A capacitor C12 (=bootstrap capacitor) is connected between the BOOT1 pin and the SW1 pin. A capacitor C13 (=output smoothing capacitor) is connected between the anode of the light-emitting diode LED1 and the ground terminal. Both ends of the sense resistor Rs1 are connected to the SNSP1 pin and the SNSN1 pin, respectively.

[0044] The PVIN2 pin is connected to the application terminal of the boost voltage Vbst. The SW2 pin is connected to a first terminal of the inductor L2. The second terminal of the inductor L2 is connected to a first terminal of the sense resistor Rs2. The second terminal of the sense resistor Rs2 is connected to the anode of the light-emitting diode LED2. The cathode of the light-emitting diode LED2 is connected to the ground terminal. A capacitor C21 (=bypass capacitor) is connected between the PVIN2 pin and the PGND2 pin. A capacitor C22 (=bootstrap capacitor) is connected between the BOOT2 pin and the SW2 pin. A capacitor C23 (=output smoothing capacitor) is connected between the anode of the light-emitting diode LED2 and the ground terminal. Both ends of the sense resistor Rs2 are connected to the SNSP2 pin and the SNSN2 pin, respectively.

[0045] The boost circuit 2 is a DC / DC converter that boosts the battery voltage +B to generate a boosted voltage Vbst.

[0046] The MCU3 operates by receiving a power supply voltage Vcc, and performs SPI communication with the LED driver IC1a.

[0047] Fig. 2 is a diagram showing an example of the configuration of an LED lamp module to which a three-channel LED driver IC is applied. The LED lamp module X of this example is based on the above-mentioned Fig. 1, but has a three-channel LED driver IC1b instead of the two-channel LED driver IC1a.

[0048] In addition, due to the three-channel nature of the LED driver IC1b, in addition to the external terminals mentioned above, it is equipped with a group of external terminals for the third channel (PVIN3 pin, BOOT3 pin, SW3 pin, PGND3 pin, SNSP3 pin, and SNSN3 pin).

[0049] Furthermore, in addition to the above-mentioned components, the LED lamp module X is provided with a third channel light emitting diode LED3 and various discrete components (capacitors C31 to C33, an inductor L3, and a sense resistor Rs3).

[0050] The PVIN3 pin is the power input voltage supply terminal (= power supply terminal). The BOOT3 pin is the bootstrap capacitor connection terminal for the upper gate drive. The SW3 pin is the switch output terminal. The PGND3 pin is the power ground terminal (= power ground terminal). The SNSP3 pin is the output current sense input terminal (+). The SNSN3 pin is the output current sense input terminal (-).

[0051] The PVIN3 pin is connected to the application terminal of the boost voltage Vbst. The SW3 pin is connected to the first terminal of the inductor L3. The second terminal of the inductor L3 is connected to the first terminal of the sense resistor Rs3. The second terminal of the sense resistor Rs3 is connected to the anode of the light-emitting diode LED3. The cathode of the light-emitting diode LED3 is connected to the ground terminal. A capacitor C31 (= bypass capacitor) is connected between the PVIN3 pin and the PGND3 pin. A capacitor C32 (= bootstrap capacitor) is connected between the BOOT3 pin and the SW3 pin. A capacitor C33 (= output smoothing capacitor) is connected between the anode of the light-emitting diode LED3 and the ground terminal. Both ends of the sense resistor Rs3 are connected to the SNSP3 pin and the SNSN3 pin, respectively.

[0052] In the following, when there is no need to distinguish between the LED drivers IC1a and 1b, they may be simply referred to as the LED driver IC1.

[0053] <Circuit configuration> 3 is a diagram showing the circuit configuration of the LED driver IC1 (particularly the output stage periphery). The LED driver IC1 of this configuration example is configured by integrating an upper switch 11H, a lower switch 11L, an upper driver 12H, a lower driver 12L, a controller 13, an on-time setting unit 14, a slope voltage generating unit 15, a sense amplifier 16, an error amplifier 17, a comparator 18, and a diode D1 for bootstrap as a means for driving the light emitting diode LED* of the *th channel (where *=1, 2, or 3). Of course, the LED driver IC1 may also integrate other components (such as various protection circuits) than those mentioned above.

[0054] The upper switch 11H is connected between the PVIN pin and the SW* pin, and is turned on / off in response to the upper gate signal GH. An NMOSFET [N-channel type metal oxide semiconductor field effect transistor] or the like can be suitably used as the upper switch 11H. In this case, the upper switch 11H is turned on when GH=H (=BOOT*) and turned off when GH=L (=SW*). It is also possible to use a PMOSFET [P-channel type MOSFET] instead of an NMOSFET as the upper switch 11H. In this case, the bootstrap diode D1, the capacitor C*2, and the BOOT* pin are not required.

[0055] The lower switch 11L is connected between the SW* pin and the PGND* pin, and is turned on / off in response to the lower gate signal GL. An NMOSFET or the like can be suitably used as the lower switch 11L. In this case, the lower switch 11L is turned on when GL=H (=VDRV5) and turned off when GL=L (=PGND*).

[0056] The upper switch 11H and the lower switch 11L connected in this way form a half-bridge output stage that outputs a square-wave switch voltage Vsw from the SW* pin. Note that, although a synchronous rectification type half-bridge output stage is shown in this figure, if a diode rectification type is used, a diode can be used as the lower switch 11L.

[0057] The high-side driver 12H generates the high-side gate signal GH based on the high-side control signal SH input from the controller 13. The high level of the high-side gate signal GH is the terminal voltage of the BOOT* pin (≒Vsw+VDRV5), while the low level of the high-side gate signal GH is the terminal voltage of the SW* pin (≒Vsw).

[0058] The low-side driver 12L generates a low-side gate signal GL based on a low-side control signal SL input from the controller 13. The high level of the low-side gate signal GL is a constant voltage VDRV5 (internal power supply voltage VREG or a separate external input voltage). On the other hand, the low level of the low-side gate signal GL is the terminal voltage (ground voltage) of the PGND* pin.

[0059] The controller 13 includes, for example, an RS flip-flop that receives inputs of a set signal SET and a reset signal RST, and generates an upper control signal SH and a lower control signal SL to complementarily turn on / off the upper switch 11H and the lower switch 11L.

[0060] More specifically, the controller 13 generates the upper control signal SH and the lower control signal SL so as to turn on the upper switch 11H and turn off the lower switch 11L at the rising timing of the set signal SET, and to turn off the upper switch 11H and turn on the lower switch 11L at the rising timing of the reset signal RST.

[0061] However, the term "complementary" in this specification should be understood in a broad sense to include not only the case where the on / off states of the upper switch 11H and the lower switch 11L are completely reversed, but also the case where a simultaneous off period (so-called dead time) is provided to prevent through current.

[0062] The on-time setting unit 14 raises the reset signal RST to a high level when a predetermined on-time Ton has elapsed from the rising timing of the set signal SET (and thus the on-timing of the upper switch 11H). The on-time setting unit 14 has a function of arbitrarily setting the on-time Ton according to the resistance value of the resistor R1 connected to the TON pin. The on-time setting unit 14 also has a function of varying the on-time Ton so as to suppress fluctuations in the switching frequency Fsw based on the terminal voltages of the PVIN pin and the SNSN pin.

[0063] The slope voltage generator 15 detects the inductor current IL flowing during the on-period of the low-side switch 11L, and generates a slope voltage Vslp including information on the inductor current IL. The slope voltage Vslp becomes higher as the inductor current IL flowing during the on-period of the low-side switch 11L becomes larger, and becomes lower as the inductor current IL becomes smaller.

[0064] The sense amplifier 16 amplifies the voltage between the terminals of the SNSP* pin and the SNSN* pin (= the voltage across the sense resistor Rs*) to generate a sense voltage Vs. The sense voltage Vs becomes higher as the output current ILED (= the average inductor current IL_ave) flowing through the sense resistor Rs* becomes larger, and becomes lower as the output current ILED becomes smaller.

[0065] The error amplifier 17 outputs a current according to the difference between the reference voltage VISET (= analog dimming voltage) input to the non-inverting input terminal (+) and the sense voltage Vs (more precisely, the sum voltage of the offset voltage Vofs and the sense voltage Vs) input to the inverting input terminal (-), and generates a control voltage Vc by charging and discharging a capacitor (not shown). Note that the control voltage Vc rises when VISET > Vs and falls when VISET < Vs.

[0066] The comparator 18 generates a set signal SET by comparing the slope voltage Vslp input to the inverting input terminal (-) and the control voltage Vc input to the non-inverting input terminal (+). The set signal SET becomes low level when Vc < Vslp and high level when Vc > Vslp. Therefore, the lower the control voltage Vc, the later the rising timing of the set signal SET (and thus the on-timing of the upper switch 11H), and conversely, the higher the control voltage Vc, the earlier the rising timing of the set signal SET.

[0067] Among the above components, the upper driver 12H, the lower driver 12L, the controller 13, the on-time setting unit 14, the slope voltage generation unit 15, the sense amplifier 16, the error amplifier 17, and the comparator 18 function as an output feedback control unit of the bottom detection on-time fixed method, and the upper switch 11H and the lower switch 11L are driven complementarily so that the output current ILED supplied from the switch output terminal SW* to the light-emitting diode LED* matches a predetermined target value.

[0068] <Output Feedback Control> Figure 4 is a diagram showing the output feedback control of the bottom detection on-time fixed method, and depicts the inductor current IL and the switch voltage Vsw in order from the top.

[0069] While the upper switch 11H is off and the lower switch 11L is on, the switch voltage Vsw is at a low level (= the negative voltage -VDSW generated between the drain and source of the lower switch 11L). At this time, the inductor current IL flowing from the PGND* pin to the SW* pin via the lower switch 11L decreases as the energy of the inductor L* is released.

[0070] Then, when the inductor current IL decreases to a bottom value IL_btm according to the control voltage Vc, Vc>Vslp, and the set signal SET rises to a high level. As a result, the upper switch 11H turns on and the lower switch 11L turns off. At this time, the switch voltage Vsw becomes a high level (≒PVIN), so the inductor current IL flowing from the PVIN pin to the SW* pin via the upper switch 11H increases.

[0071] After that, when a predetermined on-time Ton has elapsed, the reset signal RST rises to a high level, the upper switch 11H turns off, and the lower switch 11L turns on, so that the inductor current IL again starts to decrease from an increasing state. As a result, the inductor current IL has a ripple waveform that repeatedly increases and decreases between a peak value IL_pk and a bottom value IL_btm.

[0072] Here, the bottom value IL_btm of the inductor current IL varies according to the difference between the sense voltage Vs (corresponding to the average inductor current IL_ave) and the reference voltage VISET (corresponding to the target value of the average inductor current IL_ave). Also, the ripple amplitude ΔIL (=IL_pk-IL_btm) of the inductor current IL is determined according to the on-time Ton.

[0073] Therefore, by repeating the above series of operations, the LED driver IC1 performs output feedback control of the bottom detection fixed on-time type so that the average inductor current IL_ave (and therefore the output current ILED) matches a predetermined target value.

[0074] However, the output feedback control method of the LED driver IC1 is not necessarily limited to the above, and for example, instead of the bottom detection fixed on-time method, a peak detection fixed off-time method or a hysteresis window method may be adopted. Alternatively, a PWM [pulse width modulation] control method may be adopted.

[0075] <Power loss> 5 is a diagram for evaluating the power loss of the LED driver IC1. The upper part of the diagram shows the switch current Isw and the switch voltage Vsw, and the lower part shows the power loss Psw (=Isw×Vsw).

[0076] As shown in this figure, in the LED driver IC1, when the upper switch 11H and the lower switch 11L are driven complementarily, switching loss Psw_loss (= Vbst × ILED / 2 + (Tsw_on + Tsw_off) × Fsw) and conduction loss Pcon_loss (= ILED × ILED × Fsw × (RonH × Ton + RonL × Toff)) are generated.

[0077] In particular, when the boost voltage Vbst is several tens of volts (e.g., 65 V) and the switching frequency Fsw is several MHz (e.g., 2.2 MHz), the power loss (=Psw_loss+Pcon_loss) of the LED driver IC1 described above increases, which in turn increases the heat generated by the LED driver IC1. Therefore, the package of the LED driver IC1 is required to have high heat dissipation properties.

[0078] <Package> 6 and 7 are three-sided views (top, front, side) and a perspective view, respectively, showing the package of the LED driver IC 1. The package 100 shown here is a 48-pin HTSSOP (heat-sink thin-shrink small outline package), and is formed in a rectangular shape in plan view (rectangular shape in plan view) having a first side 101, a second side 102, a third side 103, and a fourth side 104.

[0079] First side 101 corresponds to a first long side (for example, 12.5 mm), and a total of 24 external terminals are provided on first side 101. In Fig. 6, pins 1 to 24 are sequentially arranged from the left end to the right end of first side 101.

[0080] The second side 102 corresponds to a second long side parallel to the first side 101, and is provided with a total of 24 external terminals, similar to the first side 101. In FIG. 6, 25 pins to 48 pins are sequentially arranged from the right end to the left end of the second side 102.

[0081] The third side 103 corresponds to a first short side (for example, 6.1 mm) that is perpendicular to the first side 101 and the second side 102. No external terminals are provided on the third side 103.

[0082] The fourth side 104 corresponds to a second short side that is parallel to the third side 103 and perpendicular to the first side 102 and the second side 102. No external terminals are provided on the fourth side 104 either.

[0083] The 48 external terminals are each led out from the long side surfaces (corresponding to the first side 101 and the second side 102 in a plan view) of the package 100. In addition, each external terminal is bent midway to form a step between its base and tip end in a so-called gull-wing shape in a side view of the package 100.

[0084] Moreover, a heat dissipation pad 111 and a 1-pin mark 112 are formed on a top surface 110 (corresponding to the first main surface that does not face the printed circuit board) of the package 100. On the other hand, nothing is formed on a bottom surface 120 (corresponding to the second main surface that faces the printed circuit board) of the package 100.

[0085] The heat dissipation pad 111 is the back surface of an island on which a semiconductor chip is mounted exposed on the top surface 110 of the package 100. The size of the heat dissipation pad 111 may be such that the long side length (= the length of one side parallel to the long side of the package 100) is about 0.4 times the first side 101 and the second side 102 (e.g., 5 mm), and the short side length (= the length of one side parallel to the short side of the package 100) is about 0.7 times the third side 103 and the fourth side 104 (e.g., 4.2 mm).

[0086] Providing such heat dissipation pad 111 can improve the heat dissipation properties of package 100. In particular, if heat dissipation pad 111 is exposed on top surface 110 of package 100 instead of on bottom surface 120 of package 100, a heat sink can be attached to heat dissipation pad 111, thereby further improving the heat dissipation properties of package 100.

[0087] 8 is a perspective view showing an example of a heat sink attached to the LED driver IC 1. The heat sink 200 of this configuration example has a base portion 210 (for example, 60 mm×50 mm) and a plurality of heat dissipation fins 220 (for example, 50 mm×50 mm).

[0088] A plurality of heat dissipation fins 220 are provided on the top surface of the base portion 210 (corresponding to the first main surface of the LED driver IC1 that does not face the package 100). With this configuration, the surface area of ​​the heat sink 200 can be increased, and the heat dissipation performance of the package 100 can be improved. The base portion 210 and the heat dissipation fins 220 may be integrally formed, or may be formed separately and then assembled.

[0089] When attaching the heat sink 200 to the LED driver IC1, it is advisable to apply thermal grease 230 to the bottom surface of the base portion 210 (corresponding to the second main surface facing the package 100 of the LED driver IC1) and then attach it to the package 100 of the LED driver IC1 (especially the thermal pad 111).

[0090] 9 is a schematic vertical cross-sectional view for evaluating the thermal resistance of the LED driver IC1. As shown in this figure, in the LED driver IC1 in which the heat dissipation pad 111 is exposed on the top surface 110 of the package 100, the thermal resistance θ1 from the semiconductor chip 130 sealed in the package 100 to the top surface 110 is extremely small compared to the thermal resistance θ2 from the semiconductor chip 130 to the bottom surface 120 (θ1<<θ2, for example, θ1=3°C / W, θ2=100°C / W). Therefore, heat can be quickly released from the heat dissipation pad 111 (and further the heat sink 200 attached thereto), so that the maximum allowable loss of the LED driver IC1 can be increased.

[0091] <Pin arrangement> Next, we propose a new pin arrangement for the LED driver IC1 described above that can optimize the PCB layout.

[0092] 10A is a plan view showing a pin arrangement (first example) of the LED driver IC1a (2ch). Note that the dashed lines in the figure are auxiliary lines for illustratively showing the connection relationship between the power supply terminals (PVIN1, PVIN2), the power ground terminals (PGND1, PGND2), and the switch output terminals (SW1, SW2) and the upper switch 11H and the lower switch 11L, and are different from the actual wiring pattern and element formation pattern.

[0093] In addition, in the following description, in a plan view of package 100, the first direction in which first side 101 and second side 102 extend is referred to as the x-direction (the up-down direction on the paper in this figure), and the second direction perpendicular to this (= the direction in which third side 103 and fourth side 104 extend) is referred to as the y-direction (the left-right direction on the paper in this figure).

[0094] Pins 1 to 3 are assigned as the power supply terminals (PVIN1) for the first channel. Pins 5 to 7 and 9 are assigned as the external terminals for SPI communication (SI, SCK, CSB, SO). Pins 11 to 13 and 15 are assigned as the external terminals for signals (GND, TON, VIN, VREG5). Pins 22 to 24 are assigned as the power supply terminals (PVIN2) for the second channel.

[0095] The output current sense input terminals (SNSN2, SNSP2) of the second channel are assigned to pins 25 and 26. The bootstrap capacitor connection terminal (BOOT2) of the second channel is assigned to pin 28. The switch output terminal (SW2) of the second channel is assigned to pins 30 to 32. The power ground terminal (PGND2) of the second channel is assigned to pins 34 to 36.

[0096] The power ground terminal (PGND1) of the first channel is assigned to pins 37 to 39. The switch output terminal (SW1) of the first channel is assigned to pins 41 to 43. The bootstrap capacitor connection terminal (BOOT1) of the first channel is assigned to pin 45. The output current sense input terminal (SNSN1) of the first channel is assigned to pins 47 and 48. 、 SNSP1) is assigned.

[0097] Thus, in the LED driver IC1a of this configuration example, the power supply terminals (PVIN1, PVIN2) are provided on the first side 101 (the left side in this figure) of the package 100. On the other hand, the power ground terminals (PGND1, PGND2) and the switch output terminals (SW1, SW2) are provided on the second side 102 (the right side in this figure) of the package 100.

[0098] 10B is a plan view showing the pin arrangement (second example) of the LED driver IC1a (2ch). Note that the dashed lines in the figure are auxiliary lines for illustratively showing the connection relationship between the power supply terminals (PVIN1, PVIN2), the power ground terminals (PGND1, PGND2), and the switch output terminals (SW1, SW2) and the upper switch 11H and the lower switch 11L, and are different from the actual wiring pattern and element formation pattern.

[0099] The output current sense input terminals (SNSN1, SNSP1) of the first channel are assigned to pins 1 and 2. The power ground terminal (PGND1) of the first channel is assigned to pins 3, 4, and 15. The switch output terminal (SW1) of the first channel is assigned to pins 6 and 7. The bootstrap capacitor connection terminal (BOOT1) of the first channel is assigned to pin 8.

[0100] The power ground terminal (PGND2) of the second channel is assigned to pins 16, 21, and 22. The bootstrap capacitor connection terminal (BOOT2) of the second channel is assigned to pin 17. The switch output terminal (SW2) of the second channel is assigned to pins 18 and 19. The output current sense input terminals (SNSP2, SNSN2) of the second channel are assigned to pins 23 and 24.

[0101] The power supply terminals (PVIN2) of the second channel are assigned to pins 25 and 33. The power supply terminals (PVIN1) of the first channel are assigned to pins 34 and 48.

[0102] A group of external terminals for signals (VIN, TON, 5VREG, and GND) are assigned to pins 36 to 39. A group of external terminals for SPI communication (SI, SCK, CSB, and SO) are assigned to pins 41 to 43 and 45.

[0103] As can be seen from Figures 10A and 10B, various variations in the pin arrangement of the LED driver IC1a (2ch) are possible as long as they do not deviate from the basic concept of providing power supply terminals (PVIN1, PVIN2) on the first side 101 (the left side in this figure) of the package 100 and power ground terminals (PGND1, PGND2) and switch output terminals (SW1, SW2) on the second side 102 (the right side in this figure) of the package 100.

[0104] 11A is a plan view showing a pin arrangement (first example) of the LED driver IC1b (3ch). Note that the dashed lines in the figure are auxiliary lines for illustratively showing the connection relationships between the power supply terminals (PVIN1 to PVIN3), the power ground terminals (PGND1 to PGND3), and the switch output terminals (SW1 to SW3) and the upper switch 11H and the lower switch 11L, and are different from the actual wiring pattern and element formation pattern.

[0105] Pins 1 and 2 are assigned as the power supply terminals (PVIN1) of the first channel. Pins 4 to 6 and 8 are assigned as the external terminals for SPI communication (SI, SCK, CSB, and SO). Pins 10 to 13 are assigned as the external terminals for signals (VREG5, GND, TON, VIN5). Pins 14 and 15 are assigned as the power supply terminals (PVIN2) of the second channel. Pins 23 and 24 are assigned as the power supply terminals (PVIN3) of the third channel.

[0106] The switch output terminal (SW3) of the third channel is assigned to pins 25 and 26. The bootstrap capacitor connection terminal (BOOT3) of the third channel is assigned to pin 27. The power ground terminal (PGND3) of the third channel is assigned to pins 28 and 29. The output current sense input terminals (SNSP3, SNSN3) of the third channel are assigned to pins 30 and 31.

[0107] The switch output terminal (SW2) of the second channel is assigned to pins 34 and 35. The bootstrap capacitor connection terminal (BOOT2) of the second channel is assigned to pin 36. The power ground terminal (PGND2) of the second channel is assigned to pins 37 and 38. The output current sense input terminals (SNSP2, SNSN2) of the second channel are assigned to pins 39 and 40.

[0108] The output current sense input terminals (SNSN1, SNSP1) of the first channel are assigned to pins 42 and 43. The power ground terminal (PGND1) of the first channel is assigned to pins 44 and 45. The bootstrap capacitor connection terminal (BOOT1) of the first channel is assigned to pin 46. The switch output terminal (SW1) of the first channel is assigned to pins 47 and 48.

[0109] Thus, in the LED driver IC1b of this configuration example, the power supply terminals (PVIN1 to PVIN3) are provided on the first side 101 (the left side in this figure) of the package 100. On the other hand, the power ground terminals (PGND1 to PGND3) and the switch output terminals (SW1 to SW3) are provided on the second side 102 (the right side in this figure) of the package 100.

[0110] 11B is a plan view showing a pin arrangement (second example) of the LED driver IC1b (3ch). Note that the dashed lines in the figure are auxiliary lines for illustratively showing the connection relationships between the power supply terminals (PVIN1, PVIN2), the power ground terminals (PGND1, PGND2), and the switch output terminals (SW1 to SW3) and the upper switch 11H and the lower switch 11L, and are different from the actual wiring pattern and element formation pattern.

[0111] The output current sense input terminals (SNSN1, SNSP1) of the first channel are assigned to pins 1 and 2. The power ground terminal PGND1 of the first channel is assigned to pins 3 and 4. The switch output terminal (SW1) of the first channel is assigned to pins 6 and 7. The bootstrap capacitor connection terminal (BOOT1) of the first channel is assigned to pin 8.

[0112] The bootstrap capacitor connection terminal (BOOT3) of the third channel is assigned to pin 10. The switch output terminal (SW3) of the third channel is assigned to pins 11 and 12. The output current sense input terminals (SNSP3, SNSN3) of the third channel are assigned to pins 13 and 14. The power ground terminal PGND3 of the third channel is assigned to pins 15 and 16.

[0113] The bootstrap capacitor connection terminal (BOOT2) of the second channel is assigned to pin 17. The switch output terminal (SW2) of the second channel is assigned to pins 18 and 19. The power ground terminal (PGND2) of the second channel is assigned to pins 21 and 22. The output current sense input terminals (SNSP2, SNSN2) of the second channel are assigned to pins 23 and 24.

[0114] The power supply pin (PVIN2) of the second channel is assigned to pin 25. The power supply pin (PVIN3) of the third channel is assigned to pins 33 and 34. The power supply pin (PVIN1) of the first channel is assigned to pin 48.

[0115] A group of external terminals for signals (VIN, TON, 5VREG, and GND) are assigned to pins 36 to 39. A group of external terminals for SPI communication (SI, SCK, CSB, and SO) are assigned to pins 41 to 43 and 45.

[0116] As can be seen from Figures 11A and 11B, various variations in the pin arrangement of the LED driver IC1b (3ch) are possible as long as they do not deviate from the basic concept of providing power supply terminals (PVIN1 to PVIN3) on a first side 101 (the left side in this figure) of the package 100 and power ground terminals (PGND1 to PGND3) and switch output terminals (SW1 to SW3) on a second side 102 (the right side in this figure) of the package 100.

[0117] <Internal structure> Fig. 12 is a bottom perspective view (= a view of the package 100 seen from the bottom surface 120) showing the internal structure of the LED driver IC1a (2ch) shown in Fig. 10A. Therefore, in this figure, the first side 101 is the right side, and the second side 102 is the left side, which is the opposite to Fig. 10A.

[0118] A semiconductor chip 130 on which the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel and the upper switch 11H (ch2) and the lower switch 11L (ch2) of the second channel are integrated is die-bonded to an island 140 having a rectangular shape in a plan view. The island 140 is supported inside the package 100 by a support frame 151 extending toward the third side 103 and a support frame 152 extending toward the fourth side 104. The back surface of the island 140 is exposed to the top surface 110 of the package 100 as the heat dissipation pad 111 mentioned above.

[0119] Wires W11 are stretched between the drain pad of the upper switch 11H (ch1) and the three PVIN1 pins. Wires W12 are stretched between the source pad of the upper switch 11H (ch1) and the drain pad of the lower switch 11L (ch1) and the three SW1 pins. Wires W13 are stretched between the source pad of the lower switch 11L (ch1) and the three PGND1 pins.

[0120] Wires W21 are stretched between the drain pad of the upper switch 11H (ch2) and the three PVIN2 pins. Wires W22 are stretched between the source pad of the upper switch 11H (ch2) and the drain pad of the lower switch 11L (ch2) and the three SW2 pins. Wires W23 are stretched between the source pad of the lower switch 11L (ch2) and the three PGND2 pins.

[0121] The lower switch 11L (ch1 / ch2) has a larger element size than the upper switch 11H (ch1 / ch2). With such an element design, it is possible to increase the current capacity of the lower switch 11L (ch1 / ch2) more than the current capacity of the upper switch 11H (ch1 / ch2). For example, if it is desired to maintain a constant output power, it is necessary to reduce the output current ILED as the output voltage VLED increases, and conversely, to increase the output current ILED as the output voltage VLED decreases. In other words, the lower the on-duty of the half-bridge output stage, the larger the output current ILED must flow, and therefore the above element design is effective.

[0122] In addition, the upper switch 11H (ch1) and the lower switch 11L (ch1), as well as the upper switch 11H (ch2) and the lower switch 11L (ch2), are each arranged in a vertical row in the order shown in the figure along the y direction perpendicular to the first side 101 when viewed in a plan view of the semiconductor chip 130.

[0123] Furthermore, the switch formation regions in which the upper switches 11H (ch1 / ch2) and the lower switches 11L (ch1 / ch2) are formed are unevenly disposed toward the second side 102 of the package 100 when the semiconductor chip 130 is seen in a plan view.

[0124] Furthermore, the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel are each positioned closer to the third side 103 of the package 100 in a planar view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN1, PGND1, SW1) of the first channel.

[0125] On the other hand, the upper switch 11H (ch2) and the lower switch 11L (ch2) of the second channel are each positioned closer to the fourth side 104 of the package 100 in a planar view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN2, PGND, SW2) of the second channel.

[0126] By adopting such an element layout, the lengths of the wires W11 to W13 and the wires W21 to W23 can be minimized, making it possible to reduce the resistance components, capacitance components, and inductance components of each wire as much as possible.

[0127] Fig. 13A is a bottom perspective view showing the internal structure of the LED driver IC1b (3ch) shown in Fig. 11A. Therefore, in contrast to Fig. 11A, the first side 101 is the right side and the second side 102 is the left side.

[0128] The semiconductor chip 130 has integrated thereon an upper switch 11H (ch1) and a lower switch 11L (ch1) of the first channel, an upper switch 11H (ch2) and a lower switch 11L (ch2) of the second channel, and an upper switch 11H (ch3) and a lower switch 11L (ch3) of the third channel.

[0129] A wire W11 is stretched between the drain pad of the upper switch 11H (ch1) and the two PVIN1 pins. A wire W12 is stretched between the source pad of the upper switch 11H (ch1) and the drain pad of the lower switch 11L (ch1) and the two SW1 pins. A wire W13 is stretched between the source pad of the lower switch 11L (ch1) and the two PGND1 pins.

[0130] A wire W21 is stretched between the drain pad of the upper switch 11H (ch2) and the two PVIN2 pins. A wire W22 is stretched between the source pad of the upper switch 11H (ch2) and the drain pad of the lower switch 11L (ch2) and the two SW2 pins. A wire W23 is stretched between the source pad of the lower switch 11L (ch2) and the two PGND2 pins.

[0131] A wire W31 is stretched between the drain pad of the upper switch 11H (ch3) and the two PVIN3 pins. A wire W32 is stretched between the source pad of the upper switch 11H (ch3) and the drain pad of the lower switch 11L (ch3) and the two SW3 pins. A wire W33 is stretched between the source pad of the lower switch 11L (ch3) and the two PGND3 pins.

[0132] In addition, the lower switch 11L (ch1 / ch2 / ch3) has a larger element size than the upper switch 11H (ch1 / ch2 / ch3). With such an element design, it is possible to increase the current capacity of the lower switch 11L (ch1 / ch2 / ch3) more than the current capacity of the upper switch 11H (ch1 / ch2 / ch3). For example, if it is desired to maintain a constant output power, it is necessary to reduce the output current ILED as the output voltage VLED increases, and conversely, to increase the output current ILED as the output voltage VLED decreases. In other words, the lower the on-duty of the half-bridge output stage, the larger the output current ILED must flow, and therefore the above element design is effective.

[0133] In addition, the upper switch 11H (ch1) and the lower switch 11L (ch1), the upper switch 11H (ch2) and the lower switch 11L (ch2), and the upper switch 11H (ch3) and the lower switch 11L (ch3) are each arranged in a vertical row in the order shown in the figure along the y direction perpendicular to the first side 101 when viewed in a plan view of the semiconductor chip 130.

[0134] Furthermore, the switch formation region in which the upper switches 11H (ch1 / ch2 / ch3) and the lower switches 11L (ch1 / ch2 / ch3) are formed is unevenly disposed toward the second side 102 of the package 100 when the semiconductor chip 130 is seen in a plan view.

[0135] Furthermore, the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel are each positioned closer to the third side 103 of the package 100 in a planar view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN1, PGND1, SW1) of the first channel.

[0136] On the other hand, the upper switch 11H (ch2) and the lower switch 11L (ch2) of the second channel are each arranged in the center in the y direction in a planar view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN2, PGND2, SW2) of the second channel.

[0137] In addition, the upper switch 11H (ch3) and the lower switch 11L (ch3) of the third channel are each positioned closer to the fourth side 104 of the package 100 in a planar view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN3, PGND3, SW3) of the third channel.

[0138] By adopting such an element layout, the lengths of the wires W11 to W13, the wires W21 to W23, and the wires W31 to W33 can be minimized, making it possible to reduce the resistance components, capacitance components, and inductance components of each as much as possible.

[0139] Fig. 13B is a bottom perspective view showing the internal structure of the LED driver IC1b (3ch) shown in Fig. 11B. Therefore, in contrast to Fig. 11B, the first side 101 is the right side and the second side 102 is the left side.

[0140] The semiconductor chip 130 has integrated thereon an upper switch 11H (ch1) and a lower switch 11L (ch1) of the first channel, an upper switch 11H (ch2) and a lower switch 11L (ch2) of the second channel, and an upper switch 11H (ch3) and a lower switch 11L (ch3) of the third channel.

[0141] A wire W11 is stretched between the drain pad of the upper switch 11H (ch1) and the PVIN1 pin. A wire W12 is stretched between the source pad of the upper switch 11H (ch1) and between the drain pad of the lower switch 11L (ch1) and the two SW1 pins. A wire W13 is stretched between the source pad of the lower switch 11L (ch1) and the two PGND1 pins.

[0142] A wire W21 is stretched between the drain pad of the upper switch 11H (ch2) and the PVIN2 pin. A wire W22 is stretched between the source pad of the upper switch 11H (ch2) and between the drain pad of the lower switch 11L (ch2) and the two SW2 pins. A wire W23 is stretched between the source pad of the lower switch 11L (ch2) and the two PGND2 pins.

[0143] A wire W31 is stretched between the drain pad of the upper switch 11H (ch3) and the PVIN3 pin and between the drain pad of the lower switch 11L (ch3) and the two SW3 pins. A wire W31S is stretched between the PVIN3 (S) pin and the subpad of the semiconductor chip 130. A wire W32 is stretched between the source pad of the upper switch 11H (ch3) and between the drain pad of the lower switch 11L (ch3) and the two SW3 pins. A wire W33 is stretched between the source pad of the lower switch 11L (ch3) and the two PGND3 pins.

[0144] In addition, the lower switch 11L (ch1 / ch2 / ch3) has a larger element size than the upper switch 11H (ch1 / ch2 / ch3). With such an element design, it is possible to increase the current capacity of the lower switch 11L (ch1 / ch2 / ch3) more than the current capacity of the upper switch 11H (ch1 / ch2 / ch3). For example, if it is desired to maintain a constant output power, it is necessary to reduce the output current ILED as the output voltage VLED increases, and conversely, to increase the output current ILED as the output voltage VLED decreases. In other words, the lower the on-duty of the half-bridge output stage, the larger the output current ILED must flow, and therefore the above element design is effective.

[0145] In addition, the upper switch 11H (ch1) and the lower switch 11L (ch1), the upper switch 11H (ch2) and the lower switch 11L (ch2), and the upper switch 11H (ch3) and the lower switch 11L (ch3) are each arranged in a vertical row in the order shown in the figure along the y direction perpendicular to the first side 101 when viewed in a plan view of the semiconductor chip 130.

[0146] Moreover, the switch formation region in which the upper switches 11H (ch1 / ch2 / ch3) and the lower switches 11L (ch1 / ch2 / ch3) are formed is unevenly disposed toward the first side 101 of the package 100 in a plan view of the semiconductor chip 130. Moreover, the logic formation region in which the controller 13 and the like are formed is unevenly disposed toward the second side of the package 100 in a plan view of the semiconductor chip 130.

[0147] Furthermore, the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel are each positioned closer to the third side 103 of the package 100 in a planar view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN1, PGND1, SW1) of the first channel.

[0148] On the other hand, the upper switch 11H (ch2) and the lower switch 11L (ch2) of the second channel are each positioned closer to the fourth side 104 of the package 100 in a planar view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN2, PGND2, SW2) of the second channel.

[0149] In addition, the upper switch 11H (ch3) and the lower switch 11L (ch3) of the third channel are each arranged in the center in the y direction when viewed in a plan view of the semiconductor chip 130 so as to be as close as possible to the external terminal group (PVIN3, PGND3, SW3) of the third channel.

[0150] By adopting such an element layout, the lengths of the wires W11 to W13, the wires W21 to W23, and the wires W31 to W33 can be minimized, making it possible to reduce the resistance components, capacitance components, and inductance components of each as much as possible.

[0151] 13A, the upper switch 11H (ch1 / ch2 / ch3) and the lower switch 11L (ch1 / ch2 / ch3) are each formed in a vertically elongated shape (the length in the x direction is greater than the length in the y direction). As a result, it becomes easier to arrange the PGND pin closer to the end of the first side 101 than the SW1 to SW3 pins.

[0152] <PCBレイアウト> Next, the optimization of the PCB layout achieved by the above pin arrangement will be described in detail with specific examples.

[0153] Fig. 14A is a plan view showing the layout of a printed circuit board on which the LED driver IC1a (2ch) shown in Fig. 10A is mounted. The LED lamp module X of this configuration example has a printed circuit board 300 (hereinafter referred to as PCB300), a 2-channel LED driver IC1a, various discrete components externally attached thereto (only the above-mentioned capacitors C11 and C21, capacitors C13 and C23, inductors L1 and L2, and sense resistors Rs1 and Rs2 are illustrated in this figure), and light-emitting diodes LED1 and LED2 (not shown). In addition, although not shown in this figure, a heat sink 200 is attached to the heat dissipation pad 111 of the LED driver IC1a.

[0154] The LED driver IC1a is mounted on the first main surface (front side of the paper) of the PCB 300, as indicated by a thin solid line. More specifically, the LED driver IC1a is mounted in a state rotated 90 degrees counterclockwise in FIG. 10. That is, in this figure, the left-right direction of the paper corresponds to the aforementioned x direction, and the up-down direction of the paper corresponds to the aforementioned y direction. Therefore, the power supply terminals (PVIN1, PVIN2) provided on the first side 101 of the package 100 are led out downward on the paper, and the power ground terminals (PGND1, PGND2) and the switch output terminals (SW1, SW2) provided on the second side 102 of the package 100 are led out upward on the paper.

[0155] On the other hand, various wirings (power supply lines 310-312, power ground lines 320-322, switch output lines 331-333 and 341-343, power supply line 360) and various discrete components (capacitors C11 and C21, capacitors C13 and C23, inductors L1 and L2, sense resistors Rs1 and Rs2) connected to the LED driver IC1a are laid or mounted on the second main surface (back side of the paper) of the PCB 300 as indicated by dashed lines. Each of these will be described in detail below.

[0156] The main portion of the power supply line 310 connected to the power supply terminals (PVIN1, PVIN2) of the LED driver IC1a, and the main portion of the power ground line 320 connected to the power ground terminals (PGND1, PGND2) of the LED driver IC1a are laid in parallel along the x direction (left-right direction on the paper) when viewed in a plan view of the PCB 300.

[0157] Furthermore, the main portions of the power supply line 310 and the power ground line 320 are laid so as to overlap the package 100 of the LED driver IC 1a when the PCB 300 is seen in a plan view.

[0158] Specifically, with reference to this figure, the main portion of the power supply line 310 is laid in a straight line along a route that runs from the outside of the third side 103, passes near the first side 101 on the rear side of the package 100, and reaches the outside of the fourth side 104.

[0159] On the other hand, the main portion of the power ground line 320 is laid in a straight line along a route that runs from the outside of the third side 103, passes near the second side 102 on the back surface of the package 100, and reaches the outside of the fourth side 104, with a specified gap between it and the main portion of the power supply line 310.

[0160] Capacitors C11 and C21 (=bypass capacitors) are connected between the main portion of the power supply line 310 and the main portion of the power ground line 320. In particular, as shown in this figure, the capacitors C11 and C21 should be mounted so as to overlap the LED driver IC1a in a plan view of the PCB 300.

[0161] Further, the power supply line 310 has branch portions 311 and 312 each branching off from the main portion. Referring to this figure, the branch portions 311 and 312 each branch off from the main portion of the power supply line 310 passing through the rear surface of the package 100 toward the power supply terminals (PVIN1, PVIN2) downward on the paper surface, and are electrically connected to the power supply terminals (PVIN1, PVIN2) through vias or through holes (not shown) penetrating between the first and second main surfaces of the PCB 300.

[0162] In addition, the power ground line 320 has branch portions 321 and 322 branched off from the main portion. In accordance with this figure, the branch portions 321 and 322 are branched off from the main portion of the power ground line 320 passing through the rear surface of the package 100 toward the power ground terminals (PGND1, PGND2) upward on the paper surface, and are electrically connected to the power ground terminals (PGND1, PGND2) through vias or through holes (not shown) that penetrate between the first and second main surfaces of the PCB 300. The power ground lines 321 and 322 may be shared. When the power ground lines 321 and 322 are shared, the branch portions branched off from the main portion of the power supply line 310 become a single line.

[0163] The switch output lines 331-333 that conduct between the switch output terminal (SW1) of the first channel and the light emitting diode LED1 are laid from the rear region of the switch output terminal (SW1) upward in the drawing. An inductor L1 is mounted between the switch output line 331 and the switch output line 332. A sense resistor Rs1 is mounted between the switch output line 332 and the switch output line 333. A capacitor C13 is mounted between the switch output line 333 and a branch portion 321 of the power ground line 320 that is extended to a position adjacent thereto.

[0164] The switch output lines 341 to 343 that conduct between the switch output terminal (SW2) of the second channel and the light emitting diode LED2 are laid from the rear region of the switch output terminal (SW2) upward in the drawing. An inductor L2 is mounted between the switch output line 341 and the switch output line 342. A sense resistor Rs2 is mounted between the switch output line 342 and the switch output line 343. A capacitor C23 is mounted between the switch output line 343 and a branch portion 322 of the power ground line 320 that is extended to a position adjacent thereto.

[0165] In the LED lamp module X of this configuration example, the power supply terminals (PVIN1, PVIN2), switch output terminals (SW1, SW2), power ground terminals (PGND1, PGND2) provided for each of the multiple channels, and the discrete components (C11 and C21, C13 and C23, L1 and L2, Rs1 and Rs2) externally attached to these, as well as the branch portions 311 and 312 of the power supply line 310, the branch portions 321 and 322 of the power ground line 320, and the switch output lines 331-333 and 341-343 are arranged symmetrically between the first channel and the second channel.

[0166] A brief explanation will be given of external terminals and wiring other than those mentioned above. A power supply line 360 ​​extending downward from the rear surface of the package 100 is connected to the VIN pin provided on the first side 101 of the package 100. Logic signals are input from the bottom side of the page to the SPI communication terminals (SI, SCK, CSB, SO) provided on the first side 101.

[0167] The above-mentioned Fig. 14A is a plan view showing the layout of a printed circuit board on which an LED driver IC1a (2ch) having a half-bridge output stage of a synchronous rectification system is mounted. On the other hand, Fig. 14B shows a plan view showing the layout of a printed circuit board on which an LED driver IC1a (2ch) that employs a diode rectification system instead of a synchronous rectification system is mounted.

[0168] The differences between Fig. 14B and Fig. 14A will be described. Diodes D11 and D21 are discrete components externally attached to the LED driver IC1a. As indicated by the dashed lines, diodes D11 and D21 are mounted on the second main surface of the PCB 300. Diode D11 is used as the lower switch 11L of the first channel, and diode D21 is used as the lower switch 11L of the second channel.

[0169] The diode D11 is preferably mounted so that the cathode terminal of the diode D11 is electrically connected to the switch output line 331 and the anode terminal of the diode D11 is electrically connected to the power ground line 320. In order to reduce the size of the closed loop of the first channel (see FIG. 16 described later), it is preferable to place the anode terminal of the diode D11 as close as possible to the capacitor C11.

[0170] The diode D21 is preferably mounted so that the cathode terminal of the diode D21 is electrically connected to the switch output line 341 and the anode terminal of the diode D21 is electrically connected to the power ground line 320. In order to reduce the size of the closed loop of the second channel (see FIG. 16 described later), it is preferable to place the anode terminal of the diode D21 as close as possible to the capacitor C21.

[0171] In the configuration example shown in Fig. 14B, one power ground terminal PGND1 and one power ground terminal PGND2 are provided for each of the first and second channels. However, as shown in Fig. 19 described later, the power ground terminal may be shared by the first and second channels.

[0172] Next, layouts of printed circuit boards other than those shown in Figures 14A and 14B will be described. Figure 14C is a plan view showing another layout of a printed circuit board on which an LED driver IC1a (2ch) having a half-bridge output stage of a synchronous rectification system is mounted. Figure 14D is a plan view showing another layout of a printed circuit board on which an LED driver IC1a (2ch) having a half-bridge output stage of a diode rectification system is mounted. Below, parts of Figure 14C that differ from Figure 14A and parts of Figure 14D that differ from Figure 14B will be described.

[0173] 14C and 14D, the power supply line 310 and the power ground line 320 are enlarged as compared with the layout shown in Figures 14A and 14B. Therefore, in the layout shown in Figures 14C and 14D, unlike the layout shown in Figures 14A and 14B, the power supply line 360, a line for transmitting a logic signal (not shown), the switch output line 330, and the switch output line 340 are laid on the first main surface of the PCB 300.

[0174] The switch output line 330 provides electrical continuity between the switch output terminal (SW1) of the first channel and the switch output line 331. The switch output line 330 is electrically connected to the switch output line 331 through a via or a through hole (not shown) that penetrates between the first main surface and the second main surface of the PCB 300. In the layouts shown in Figures 14C and 14D, unlike the layouts shown in Figures 14A and 14B, the switch output line 331 does not overlap the switch output terminal (SW1) in a plan view of the PCB 300.

[0175] The switch output line 340 is a switch output terminal (SW2) of the second channel and a switch output line 34114C and 14D, unlike the layouts shown in FIGS. 14A and 14B, the switch output line 341 does not overlap with the switch output terminal (SW2) in a plan view of the PCB 300. The switch output line 340 is electrically connected to the switch output line 341 through a via or a through hole (not shown) that penetrates between the first and second main surfaces of the PCB 300. In the layouts shown in FIGS. 14C and 14D, the switch output line 341 does not overlap with the switch output terminal (SW2) in a plan view of the PCB 300, unlike the layouts shown in FIGS.

[0176] Fig. 15 is a plan view showing the layout of a printed circuit board on which the LED driver IC1b (3ch) shown in Fig. 11A is mounted. The LED lamp module X of this configuration example has a PCB300, a 3-channel LED driver IC1b, various discrete components externally attached thereto (in this figure, only the above-mentioned capacitors C11, C21, and C31, capacitors C13, C23, and C33, inductors L1 to L3, and sense resistors Rs1 to Rs3 are illustrated), and light-emitting diodes LED1 to LED3 (not shown). In addition, although not shown in this figure, a heat sink 200 is attached to the heat dissipation pad 111 of the LED driver IC1b.

[0177] The LED driver IC1b is mounted on the first main surface (front side of the paper) of the PCB 300, as indicated by a thin solid line. More specifically, the LED driver IC1b is mounted in a state rotated 90 degrees counterclockwise in FIG. 11. That is, in this figure, the left-right direction on the paper surface corresponds to the previously mentioned x direction, and the up-down direction on the paper surface corresponds to the previously mentioned y direction. Therefore, the power supply terminals (PVIN1 to PVIN3) provided on the first side 101 of the package 100 are led out downward on the paper surface, and the power ground terminals (PGND1 to PGND3) and switch output terminals (SW1 to SW3) provided on the second side 102 of the package 100 are led out upward on the paper surface.

[0178] On the other hand, various wirings (power supply lines 310-312, power ground lines 320-323, switch output lines 331-333, 341-343, and 351-353, power supply line 360) and various discrete components (capacitors C11, C21, and C31, capacitors C13, C23, and C33, inductors L1-L3, and sense resistors Rs1-Rs3) connected to the LED driver IC1b are laid or mounted on the second main surface (the back side of the paper) of the PCB 300 as indicated by dashed lines. Each of these will be described in detail below.

[0179] The main portion of the power supply line 310 connected to the power supply terminals (PVIN1 to PVIN3) of the LED driver IC1b and the main portion of the power ground line 320 connected to the power ground terminals (PGND1 to PGND3) of the LED driver IC1b are laid in parallel along the x direction (left-right direction on the paper) when viewed in a plan view of the PCB 300.

[0180] Furthermore, the main portions of the power supply line 310 and the power ground line 320 are laid so as to overlap the package 100 of the LED driver IC 1b when the PCB 300 is seen in a plan view.

[0181] Specifically, with reference to this figure, the main portion of the power supply line 310 is laid in a straight line along a route that runs from the outside of the third side 103, passes near the first side 101 on the rear side of the package 100, and reaches the outside of the fourth side 104.

[0182] On the other hand, the main portion of the power ground line 320 is laid in a straight line along a route that runs from the outside of the third side 103, passes near the second side 102 on the back surface of the package 100, and reaches the outside of the fourth side 104, with a specified gap between it and the main portion of the power supply line 310.

[0183] Capacitors C11, C21, and C31 (bypass capacitors) are connected between the main portion of the power supply line 310 and the main portion of the power ground line 320. In particular, the capacitors C11, C21, and C31 should be mounted so as to overlap the LED driver IC1b in a plan view of the PCB 300, as shown in this figure.

[0184] Further, the power supply line 310 has branch portions 311-313 each branching off from the main portion. In accordance with this figure, the branch portions 311-313 each branch off from the main portion of the power supply line 310 passing through the rear surface of the package 100 toward the power supply terminals (PVIN1-PVIN3) downward on the paper surface, and are electrically connected to the power supply terminals (PVIN1-PVIN3) through vias or through holes (not shown) that penetrate between the first and second main surfaces of the PCB 300.

[0185] Further, the power ground line 320 has branch portions 321-323 each branching off from the main portion. In accordance with this figure, the branch portions 321-323 each branch off from the main portion of the power ground line 320 passing through the rear surface of the package 100 toward the power ground terminals (PGND1-PGND3) and are electrically connected to the power ground terminals (PGND1-PGND3) through vias or through holes (not shown) that penetrate between the first and second main surfaces of the PCB 300.

[0186] The switch output lines 331-333 that conduct between the switch output terminal (SW1) of the first channel and the light emitting diode LED1 are laid from the rear region of the switch output terminal (SW1) upward in the drawing. An inductor L1 is mounted between the switch output line 331 and the switch output line 332. A sense resistor Rs1 is mounted between the switch output line 332 and the switch output line 333. A capacitor C13 is mounted between the switch output line 333 and a branch portion 321 of the power ground line 320 that is extended to a position adjacent thereto.

[0187] The switch output lines 341 to 343 that conduct between the switch output terminal (SW2) of the second channel and the light emitting diode LED2 are laid from the rear region of the switch output terminal (SW2) upward in the drawing. An inductor L2 is mounted between the switch output line 341 and the switch output line 342. A sense resistor Rs2 is mounted between the switch output line 342 and the switch output line 343. A capacitor C23 is mounted between the switch output line 343 and a branch portion 322 of the power ground line 320 that is extended to a position adjacent thereto.

[0188] Switch output lines 351-353 that conduct between the switch output terminal (SW3) of the third channel and the light emitting diode LED3 are laid from the rear region of the switch output terminal (SW3) upward in the drawing. An inductor L3 is mounted between the switch output line 351 and the switch output line 352. A sense resistor Rs3 is mounted between the switch output line 352 and the switch output line 353. A capacitor C33 is mounted between the switch output line 353 and a branch portion 323 of the power ground line 320 that is extended to a position adjacent thereto.

[0189] In the LED lamp module X of this configuration example, the power supply terminals (PVIN1 to PVIN3), the switch output terminals (SW1 to SW3), the power ground terminals (PGND1 to PGND3) provided for each of the multiple channels, and the discrete components (C11, C21 and C31, C13, C23 and C33, L1 to L3, Rs1 to Rs3) externally attached thereto, as well as the branch portions 311 to 313 of the power supply line 310, the branch portions 321 to 323 of the power ground line 320, and the switch output lines 331 to 333, 341 to 343, and 351 to 353 are arranged symmetrically between at least two channels. Specifically, the respective components are arranged symmetrically between the first channel and the second channel and between the first channel and the third channel.

[0190] The external terminals and wirings other than those described above will also be briefly explained. A power line 360 laid from the back region downward in the drawing plane is connected to the VIN pin provided on the first side 101 of the package 100. Further, logic signals are input to the SPI communication terminals (SI, SCK, CSB, SO) provided on the first side 101 from the lower side of the drawing plane.

[0191] It should be noted that the same changes as those from the aforementioned FIG. 14A to the aforementioned FIGS. 14B to 14D can also be implemented for FIG. 15.

[0192] <Bypass capacitor> Next, the optimal layout of the capacitor C*1 (where *=1, 2, or 3) that functions as a bypass capacitor will be considered with reference to the drawings. FIG. 16 is a diagram showing the formation of a closed loop of the capacitor C*1.

[0193] As shown in this figure, the capacitor C*1 of the *-th channel forms a closed loop (11H → PVIN* → C*1 → PGND* → 11L) together with the upper switch 11H and the lower switch 11L. The smaller this closed loop is, the smaller the influence of the transient current accompanying the power supply fluctuation can be suppressed. Therefore, it is desirable to mount the capacitor C*1 at a position where the above closed loop is minimized.

[0194] Specifically, as shown in the aforementioned FIGS. 14A to 14D and FIG. 15, it is desirable to mount the capacitor C*1 so as to overlap with the LED driver ICs 1a to 1b in a plan view of the PCB 300. Furthermore, it is desirable to mount it on (or in the vicinity of) the line segment connecting the PVIN* pin and the PGND* pin.

[0195] <Vertical arrangement of LED driver ICs> 17 is a diagram showing a vertical arrangement of LED driver IC1b (3ch). In the LED lamp module X of this configuration example, m LED driver ICs 1b(1) to 1b(m) (where m≧2) are mounted vertically along the x direction (left-right direction on the paper) on the first main surface of the PCB 300.

[0196] The LED driver ICs 1b(1) to 1b(m) each adopt the pin arrangement shown in FIG. 11. Therefore, the power supply line 310 and the power ground line 320 are respectively connected to the LED driver ICs 1b(1) to 1b(m) as shown in FIG. I C They can be laid in a straight line along the x direction (left-right direction on the paper) so as to pass through the backs of each of 1b(1) to 1b(m).

[0197] Also, LED drivers I C Since each of the switch output lines 1b(1) to 1b(m) can be led out upward on the page, even if the number of channels increases, it is possible to line up the light-emitting diodes LED1 to LED(3m) of all channels along the x direction (left to right on the page).

[0198] In this way, by adopting the pin arrangement described above, it is possible to simplify the wiring pattern laid on PCB 300, which in turn makes it possible to optimize the PCB layout, such as preventing short circuits between wiring patterns and reducing the wiring pattern area.

[0199] In this diagram, the LED driver I C We have taken the example of a vertical arrangement of 1b (3ch), but the LED driver I C The same can be said about the vertical arrangement of 1a (2ch).

[0200] <Comparative Example> Next, in order to more clearly understand the effects of the pin arrangements (FIGS. 10 to 15) described thus far, differences in PCB layout will be described while citing a comparative example that employs a pin arrangement different from the above.

[0201] FIG. 18 is a plan view showing the layout of a printed circuit board on which an LED driver IC1c (3ch) employing a pin arrangement different from that described above is mounted.

[0202] As shown in the figure, in the LED driver IC1c, the external terminal group (PVIN1, PGND1, SW1) of the first channel is arranged in a concentrated manner on a first side 101 of the package 100. On the other hand, the external terminal group (PVIN2, PGND2, SW2) of the second channel and the external terminal group (PVIN3, PGND3, SW3) of the third channel are arranged in a concentrated manner on a second side 102 of the package 100.

[0203] For this reason, the components of the first channel and the components of the second and third channels have to be installed or disposed separately on both sides of the LED driver IC1c.

[0204] With reference to this figure, the components of the first channel (power supply line 411, branch portion 421 of power ground line 420, switch output lines 431-433, capacitors C11 and C13, inductor L1, and sense resistor Rs1) are all arranged on the first side 101 of package 100.

[0205] On the other hand, the components of the second channel (power supply line 412, branch portion 422 of power ground line 420, switch output lines 441 to 443, capacitors C21 and C23, inductor L2, and sense resistor Rs2) are all arranged on the second side 102 of package 100.

[0206] In addition, the components of the third channel (power supply line 413, branch portion 423 of power ground line 420, switch output lines 451 to 453, capacitors C31 and C33, inductor L3, and sense resistor Rs3) are all arranged on the second side 102 of package 100.

[0207] Thus, if the pin arrangement of this comparative example is adopted, the wiring pattern laid on PCB400 will become extremely complex, and it will no longer be possible to arrange the light-emitting diodes LED1 to LED3 of all channels side by side in the x direction (left and right direction on the paper).

[0208] On the other hand, if the pin arrangement proposed earlier (Figures 10 to 15) is adopted, it is possible to avoid such problems and optimize the PCB layout.

[0209] <Modification> The pin arrangement and PCB layout described above can be modified in various ways. Some modifications will be briefly described below.

[0210] 19 is a diagram showing a first modified example of the pin arrangement. As shown in this diagram, the power ground terminal (PGND) does not necessarily have to be provided for each of a plurality of channels, and may be shared by a plurality of channels.

[0211] 20 is a diagram showing a second modified example of the pin arrangement. As shown in this diagram, the power supply terminal (PVIN) does not necessarily need to be provided for each of a plurality of channels, and may be shared by a plurality of channels.

[0212] 21 is a diagram showing a third modified example of the pin arrangement. As shown in this figure, the positions of the power ground terminal (PGND) and the switch output terminal (SW) provided on the second side 102 may be interchanged.

[0213] 22 is a diagram showing a fourth modified example of the pin arrangement. As shown in this figure, the power supply terminal (VIN) for the signal system does not necessarily have to be provided on the first side 101, but may be provided on the second side .

[0214] 23 is a diagram showing a modified example of the PCB layout. As shown in this figure, at least one of the power supply line 310 and the power ground line 320 (the power supply line 310 in this figure) may be laid in a position that does not overlap the package 100.

[0215] 24 is a diagram showing an example of using a QFP (quad flat package). As shown in the figure, the package 100 is not necessarily limited to an SOP, and a QFP may also be used.

[0216] In this case, for example, the SW1 pin and SW2 pin may be arranged on the second side 102, the PVIN1 pin and PGND1 pin of the first channel may be arranged on the third side 103, and the PVIN2 pin and PGND2 pin of the second channel may be arranged on the fourth side 104. Also, the PVIN1 pin and PVIN2 pin may be arranged closer to the first side 101, and the PGND1 pin and PGND2 pin may be arranged closer to the second side 102. Furthermore, the PVIN1 pin and PVIN2 pin may be arranged in positions opposite to each other. Similarly, the PGND1 pin and PGND2 pin may be arranged in positions opposite to each other.

[0217] By adopting such a pin arrangement, the power supply line 310 and the power ground line 320 can be laid in parallel and in a straight line, as in the above-mentioned FIG. 14A.

[0218] <Same surface mounting> Fig. 25 is a plan view showing the layout of a printed circuit board on which the LED driver IC1b (3ch) shown in Fig. 11B and a plurality of discrete components externally attached thereto are mounted on the same surface. The LED lamp module X of this configuration example has a PCB300, the 3-channel LED driver IC1b (three in this figure) shown in Fig. 11B, various discrete components externally attached thereto (a capacitor C, an inductor L, and a sense resistor R are exemplified in this figure), and light-emitting diodes LED1 to LED9 (not shown). Although not shown in this figure, a heat sink 200 is attached to the heat dissipation pad 111 of the LED driver IC1b.

[0219] The LED driver IC1b is mounted on the first main surface (front side of the paper) of the PCB300, as indicated by the thin solid line. At least a portion of the various wiring and discrete components connected to the LED driver IC1b are laid or mounted on the first main surface (front side of the paper) of the PCB300, as indicated by the solid line, and the rest are laid or mounted on the second main surface (back side of the paper) of the PCB300, as indicated by the dashed line. Each will be described in detail below.

[0220] The main portion of the power supply line 310 connected to the power supply terminals (PVIN1 to PVIN3) of the LED driver IC1b is laid along the x direction on the first main surface of the PCB 300 at a position not overlapping with the package 100 of the LED driver IC1b.

[0221] On the other hand, the main portion of the power ground line 320 connected to the power ground terminals (PGND1 to PGND3) of the LED driver IC1b is laid along the x direction on the second main surface of the PCB 300 at a position overlapping with the package 100 of the LED driver IC1b.

[0222] Further, the power supply line 310 has branch portions 311-313 each branching off from the main portion. Referring to this figure, the branch portions 311-313 each branch off from the main portion of the power supply line 310 toward the power supply terminals (PVIN1-PVIN3) on the first main surface of the PCB 300, and are electrically connected to the power supply terminals (PVIN1-PVIN3).

[0223] Further, the power ground line 320 has branch portions 321-325 each branching off from the main portion. Referring to this figure, the branch portions 321-323 each branch off from the main portion of the power ground line 320 toward the power ground terminals (PGND1-PGND3) on the second main surface of the PCB 300, and are electrically connected to the power ground terminals (PGND1-PGND3) through vias or through holes (not shown) that penetrate between the first and second main surfaces of the PCB 300.

[0224] Moreover, branch portion 324 branches off from the main portion of power ground line 320 towards branch portions 311-313 of power supply line 310 on the second main surface of PCB 300. Note that a bypass capacitor C is mounted between branch portions 311-313 of power supply line 310 and branch portion 324 of power ground line 320.

[0225] Meanwhile, the branch line portion 325 branches off from the main portion of the power ground line 320 on the second main surface of the PCB 300 towards the switch output lines 333 to 353 which will be described later.

[0226] The switch output lines 331 to 333 connected to the switch output terminals (SW1) of the LED driver IC1b are laid on the first main surface of the PCB300 toward the corresponding light emitting diodes (LED3, LED6, and LED9 in this figure). An inductor L is mounted on the first main surface of the PCB300 between the switch output line 331 and the switch output line 332. A sense resistor R is mounted on the first main surface of the PCB300 between the switch output line 332 and the switch output line 333. An output capacitor C is mounted on the first main surface of the PCB300 between the switch output line 333 and a branch portion 325 of the power ground line 320 that is extended to a position adjacent to the switch output line 333.

[0227] The switch output lines 341 to 343 connected to the switch output terminals (SW2) of the LED driver IC1b are laid on the first main surface of the PCB300 toward the corresponding light emitting diodes (LED1, LED4, and LED7 in this figure). An inductor L is mounted on the first main surface of the PCB300 between the switch output line 341 and the switch output line 342. A sense resistor R is mounted on the first main surface of the PCB300 between the switch output line 342 and the switch output line 343. An output capacitor C is mounted on the first main surface of the PCB300 between the switch output line 343 and a branch portion 325 of the power ground line 320 extended to a position adjacent thereto.

[0228] The switch output lines 351 to 353 connected to the switch output terminals (SW3) of the LED driver IC1b are laid on the first main surface of the PCB300 toward the corresponding light emitting diodes (LED2, LED5, and LED8 in this figure). An inductor L is mounted on the first main surface of the PCB300 between the switch output line 351 and the switch output line 352. A sense resistor R is mounted on the first main surface of the PCB300 between the switch output line 352 and the switch output line 353. An output capacitor C is mounted on the first main surface of the PCB300 between the switch output line 353 and a branch portion 323 of the power ground line 320 extended to a position adjacent thereto.

[0229] Although not shown in this figure, it is advisable to mount small signal discrete components on the second main surface of PCB 300.

[0230] In addition, when mounting the LED driver IC and the discrete components attached to it on the same surface of the printed wiring board, the number of channels and pin arrangement of the LED driver IC do not matter. That is, in this figure, not only the LED driver IC1b (3ch) shown in Figure 11B, but also the LED driver IC1b (3ch) shown in Figure 11A and the LED driver IC1a (2ch) shown in Figures 10A and 10B can be mounted on the same surface with the discrete components.

[0231] Fig. 26 is a diagram showing an α-β cross section of Fig. 25. As described above, in the LED lamp module X of Fig. 25, the three LED driver IC1b and at least some of the discrete components externally attached thereto (the inductor L, the sense resistor R, and the output capacitor C) are all mounted on the same surface (the first main surface) of the PCB300.

[0232] Therefore, by devising a shape of the heat sink 200 to be attached to the LED driver IC1b, it is possible to attach the heat sink 200 in common to both the LED driver IC1b and the discrete components (such as the inductor L) mounted on the same surface of the PCB 300.

[0233] For example, as shown in the figure, an extension 240 extending from the base 210 of the heat sink 200 toward the top of the inductor L may be provided, and thermal grease 250 may be applied to the bottom surface of the extension 240 and attached to the top surface of the inductor L. With this configuration, it is possible to improve the heat dissipation of not only the LED driver IC1b but also the discrete components.

[0234] For example, as shown in this figure, arranging discrete components of the same height in a row makes it easier to design the shape of the heat sink 200 (especially the extension 240). In this figure, the LED driver IC1b and the inductor L are bonded to the heat sink 200, but other discrete components can also be bonded to the heat sink 200 as necessary.

[0235] <Other Modifications> In this way, in addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Industrial Applicability]

[0236] The invention disclosed in this specification can be used, for example, in a multi-channel LED driver IC mounted on an in-vehicle LED lamp module. [Explanation of symbols]

[0237] 1, 1a, 1b LED driver IC (semiconductor device) 2. Boost circuit 3. MCU 11H Upper switch (NMOSFET) 11L Lower switch (NMOSFET) 12H Upper driver 12L Lower Driver 13 Controller 14 ON time setting section 15 Slope voltage generator 16 Sense Amplifier 17 Error Amplifier 18 Comparator 100 packages 101 Side 1 102 Side 2 103 Third Side 104th 4 Side 110 Top surface 111 Heat dissipation pad 112 1 pin mark 120 Bottom surface 130 Semiconductor Chips 140 Island 151, 152 Support frame 200 Heatsink 210 Base 220 Heat dissipation fin 230 Thermal grease 240 Extension 250 Thermal grease 300 Printed Circuit Board 310 Power supply line (main section) 311, 312, 313 Power supply lines (branch section) 320 Power ground line (main section) 321, 322, 323, 324, 325 Power ground lines (branch sections) 330~333, 340~343, 351~353 Switch Line 360 Power Line C1, C2, C11 to C13, C21 to C23, C31 to C33 capacitors D1, D11, D21 Diodes L1, L2, L3 Inductors LED1, LED2, LED3 Light Emitting Diodes R1, R2 resistance Rs1, Rs2, Rs3 Sense resistors W11~W13, W21~W23, W31~W33 Wire X LED Lamp Module

Claims

1. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having the upper switch, the lower switch, the switch output terminal, the power supply terminal, and the power ground terminal are each provided for each of a plurality of channels.

2. 2. The semiconductor device according to claim 1, wherein the switch output terminals provided for each of the plurality of channels are arranged symmetrically between at least two of the channels.

3. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having The semiconductor device, wherein the upper switch, the lower switch, the power supply terminal, and the power ground terminal are provided for each of a plurality of channels.

4. 4. The semiconductor device according to claim 1, wherein the power supply terminals provided for each of the plurality of channels are arranged symmetrically between at least two of the channels.

5. 5. The semiconductor device according to claim 1, wherein the power ground terminals provided for each of the plurality of channels are arranged symmetrically between at least two of the channels.

6. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; a heat dissipation pad exposed on a top surface of the package; The semiconductor device has

7. 7. The semiconductor device according to claim 6, wherein at least one of said power supply terminal and said power ground terminal is shared by a plurality of channels.

8. 8. The semiconductor device according to claim 6, wherein a thermal resistance from the semiconductor chip sealed in the package to the top surface is smaller than a thermal resistance from the semiconductor chip to a bottom surface of the package.

9. 9. The semiconductor device according to claim 1, wherein the upper switches and the lower switches are unevenly arranged near the second side in a plan view.

10. The semiconductor device according to any one of claims 1 to 9, wherein the upper switch and the lower switch are arranged in a vertical row along a second direction perpendicular to a first direction in which the first side and the second side extend, when viewed in a plan view.

11. 11. The semiconductor device according to claim 1, wherein the lower switch has an element size larger than that of the upper switch.

12. 12. The semiconductor device according to claim 1, wherein the power supply terminal and the power ground terminal are both provided on the third side or the fourth side, and the power ground terminal is arranged closer to the second side than the power supply terminal.

13. The semiconductor device according to any one of claims 1 to 12, further comprising an output feedback control unit that drives the upper switch and the lower switch so that the output current supplied from the switch output terminal to a load coincides with a predetermined target value.

14. 14. The semiconductor device according to claim 13, wherein said output feedback control section performs output feedback control of a bottom detection on-time fixed type.

15. A printed circuit board; A semiconductor device according to any one of claims 1 to 14, A load that receives an output current from the semiconductor device; A module having

16. the semiconductor device is mounted on a first main surface of the printed circuit board, 16. The module of claim 15, wherein a power supply line connected to the power supply terminal, a power ground line connected to the power ground terminal, and a switch output line connected to the switch output terminal are laid on a second main surface of the printed circuit board.

17. 17. The module according to claim 16, wherein main portions of the power supply line and the power ground line are laid in parallel along a first direction in which the first side and the second side extend in a plan view.

18. The module according to claim 17 , wherein a plurality of the semiconductor devices are mounted on the first main surface along the first direction.

19. 19. The module according to claim 16, wherein at least one of said power supply line and said power ground line is laid so as to overlap said semiconductor device in a plan view.

20. 20. The module according to claim 16, wherein a bypass capacitor is connected to the second main surface between the power supply line and the power ground line.

21. The module according to claim 20 , wherein the bypass capacitor is mounted so as to overlap the semiconductor device in a plan view.

22. 22. The module of claim 20 or 21, wherein the bypass capacitor is mounted at a position where a closed loop formed with the upper switch and the lower switch is minimized.

23. A printed circuit board; A semiconductor device according to any one of claims 1 to 5, A load that receives an output current from the semiconductor device; having A module, wherein the power supply terminal, the switch output terminal, the power ground terminal, and the discrete components externally attached thereto, which are provided for each of the multiple channels, are arranged symmetrically between at least two channels.

24. The module according to any one of claims 15 to 23, further comprising a heat sink attached to the semiconductor device.

25. The module according to claim 15 , wherein the semiconductor device and at least a portion of the discrete components externally attached thereto are mounted on the same surface of the printed circuit board.

26. 26. The module of claim 25, further comprising a heat sink commonly attached to both the semiconductor device and the discrete components mounted on the same side of the printed circuit board.

27. The module according to any one of claims 15 to 26, further comprising a boost circuit that generates a boosted voltage from a battery voltage and supplies the boosted voltage to the power supply terminal.

28. The module of any one of claims 15 to 27, wherein the load is a light emitting diode.

29. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having A semiconductor device, wherein a thermal resistance from a semiconductor chip sealed in the package to a top surface of the package is smaller than a thermal resistance from the semiconductor chip to a bottom surface of the package.

30. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having The semiconductor device, wherein the upper switch and the lower switch are unevenly disposed toward the second side in a plan view.

31. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having The semiconductor device, wherein the upper switch and the lower switch are arranged in a vertical row along a second direction perpendicular to a first direction in which the first side and the second side extend in a plan view.

32. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having The semiconductor device, wherein the lower switch has an element size larger than that of the upper switch.

33. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having the power supply terminal and the power ground terminal are both provided on the third side or the fourth side, and the power ground terminal is arranged closer to the second side than the power supply terminal.

34. a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; having The semiconductor device further comprises an output feedback control section that drives the upper switch and the lower switch so that an output current supplied from the switch output terminal to a load coincides with a predetermined target value.

35. A printed circuit board, a semiconductor device mounted on the printed circuit board; A load that receives an output current from the semiconductor device; having The semiconductor device includes: a package having a rectangular shape in a plan view, the package having a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side; a power supply terminal provided on the first side, the third side, or the fourth side; a power ground terminal provided on the second side, the third side, or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; a lower switch connected between the switch output terminal and the power ground terminal; A module having

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