Semiconductor Device

Abstract

The present invention provides a semiconductor device which has favorable electrical characteristics. The present invention provides a semiconductor device which has high reliability. This semiconductor device includes a first transistor, a second transistor, a first insulation layer, and a second insulation layer. The first transistor includes a first semiconductor layer, a first gate insulation layer, and a first gate electrode. The first semiconductor layer includes a metal oxide. The second transistor includes a second semiconductor layer, a second gate insulation layer, and a second gate electrode. The second semiconductor layer includes crystalline silicon. The first insulation layer has a region which overlaps with the first transistor with the second insulation layer interposed therebetween. The second insulation layer has a region which overlaps with the second transistor with the first insulation layer interposed therebetween. The second insulation layer has a greater film density than the first insulation layer.

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device. 2. Description of the Related Art One embodiment of the present invention relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have been attracting attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel among the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Metal oxides that can be used for the semiconductor layer can be formed by sputtering or the like, and therefore can be used for the semiconductor layer of transistors that constitute large display devices. In addition, since it is possible to use a part of the production equipment for transistors that use polycrystalline silicon or amorphous silicon by improving it, capital investment can be reduced. In addition, transistors that use metal oxides have higher field-effect mobility than those that use amorphous silicon, and therefore a high-performance display device provided with a driver circuit can be realized.

[0005] Display devices are becoming larger in screen size, with development being carried out with screen sizes of 60 inches or more diagonally, and even 120 inches or more in mind. In addition, screen resolution is also tending to become higher, from full high vision (1920 x 1080 pixels, also known as "2K"), to ultra high vision (3840 x 2160 pixels, also known as "4K"), to super high vision (7680 x 4320 pixels, also known as "8K").

[0006] Larger screen sizes and higher definitions tend to increase the wiring resistance in the display section. Patent Document 2 discloses a technology for forming a low-resistance wiring layer using copper (Cu) in order to suppress the increase in wiring resistance in a liquid crystal display device using amorphous silicon transistors. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2014-7399 A [Patent Document 2] JP 2004-163901 A Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device.Another object of one embodiment of the present invention is to provide a small-sized semiconductor device.Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] Another object of one embodiment of the present invention is to provide a high-definition display device. Another object of one embodiment of the present invention is to provide a display device with high operation speed. Another object of one embodiment of the present invention is to provide a display device with high reliability. Another object of one embodiment of the present invention is to provide a display device with a narrow frame. Another object of one embodiment of the present invention is to provide a display device with low power consumption. Another object of one embodiment of the present invention is to provide a novel display device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The first semiconductor layer includes a metal oxide. The first gate electrode has a region overlapping with the first semiconductor layer through the first gate insulating layer. The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate electrode. The second semiconductor layer includes crystalline silicon. The second gate electrode has a region overlapping with the second semiconductor layer through the second gate insulating layer. The first insulating layer has a region overlapping with the first transistor through the second insulating layer. The second insulating layer has a region overlapping with the second transistor through the first insulating layer. The second insulating layer preferably has a film density higher than that of the first insulating layer.

[0012] In the above-described semiconductor device, the first gate electrode preferably has a region overlapping with the second insulating layer via the first semiconductor layer.

[0013] In the above-mentioned semiconductor device, the first transistor preferably has a third gate insulating layer and a third gate electrode. The third gate electrode preferably has a region overlapping with the first semiconductor layer through the third gate insulating layer. The second insulating layer preferably has a region overlapping with the third gate insulating layer through the third gate electrode.

[0014] In the above-described semiconductor device, the first transistor preferably has a third gate electrode. The third gate electrode preferably has a region overlapping with the first semiconductor layer via the first insulating layer and the second insulating layer.

[0015] In the above-described semiconductor device, the third gate electrode is preferably formed by processing the same conductive film as that of the second gate electrode.

[0016] In the above-mentioned semiconductor device, the second semiconductor layer preferably has a first region and a pair of second regions sandwiching the first region, and the first region preferably has a region overlapping with the second gate electrode. The third gate electrode preferably has crystalline silicon. Each of the second region and the third gate electrode preferably has one or more elements selected from boron, aluminum, gallium, indium, phosphorus, arsenic, antimony, and bismuth.

[0017] In the above-described semiconductor device, the first semiconductor layer preferably has a region overlapping with the second insulating layer via the first gate electrode.

[0018] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The first semiconductor layer includes a metal oxide. The first gate electrode has a region overlapping with the first semiconductor layer through the first gate insulating layer. The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate electrode. The second semiconductor layer includes crystalline silicon. The second gate electrode has a region overlapping with the second semiconductor layer through the second gate insulating layer. The first gate insulating layer includes a first insulating layer and a second insulating layer on the first insulating layer. The second insulating layer has a region overlapping with the second transistor through the first insulating layer. In addition, the second insulating layer preferably has a higher film density than the first insulating layer.

[0019] In the above-described semiconductor device, the first gate electrode is preferably formed by processing the same conductive film as the second gate electrode.

[0020] In the above-mentioned semiconductor device, the second semiconductor layer preferably has a first region and a pair of second regions sandwiching the first region, and the first region preferably has a region overlapping with the second gate electrode. The first gate electrode preferably has crystalline silicon. The second region and the first gate electrode preferably each have one or more elements selected from boron, aluminum, gallium, indium, phosphorus, arsenic, antimony, and bismuth.

[0021] In the above-described semiconductor device, the second semiconductor layer preferably has a region overlapping with the first insulating layer via the second gate electrode.

[0022] In the above-described semiconductor device, the second gate electrode preferably has a region overlapping with the first insulating layer via the second semiconductor layer.

[0023] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of forming a first transistor having a first semiconductor layer having crystalline silicon, a first gate insulating layer, and a first gate electrode, forming a first insulating layer over the first transistor, forming a second insulating layer having a higher film density than the first insulating layer over the first insulating layer, forming a second semiconductor layer having a metal oxide over the second insulating layer, forming a second gate insulating layer over the second insulating layer and the second semiconductor layer, forming a conductive film over the second gate insulating layer, and processing the conductive film to form a second gate electrode of a second transistor including the second semiconductor layer and the second gate insulating layer, and a wiring electrically connected to the first semiconductor layer. Effect of the Invention

[0024] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, a highly reliable semiconductor device, a small-sized semiconductor device, a semiconductor device with low power consumption, or a novel semiconductor device can be provided.

[0025] According to one embodiment of the present invention, a high-definition display device can be provided. A display device with high operation speed can be provided. A display device with high reliability can be provided. A display device with a narrow frame can be provided. A display device with low power consumption can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0027] 1A, 1B, and 1C are cross-sectional views showing configuration examples of a semiconductor device. 2A, 2B, and 2C are cross-sectional views showing configuration examples of a semiconductor device. 3A and 3B are cross-sectional views showing configuration examples of a semiconductor device. 4A and 4B are cross-sectional views showing configuration examples of a semiconductor device. FIG. 5 is a cross-sectional view showing a configuration example of a semiconductor device. 6A, 6B, and 6C are cross-sectional views showing configuration examples of a semiconductor device. 7A and 7B are cross-sectional views showing configuration examples of a semiconductor device. 8A and 8B are cross-sectional views showing configuration examples of a semiconductor device. 9A, 9B, and 9C are cross-sectional views showing configuration examples of a semiconductor device. 10A, 10B, and 10C are cross-sectional views showing configuration examples of a semiconductor device. 11A, 11B, and 11C are cross-sectional views showing configuration examples of a semiconductor device. 12A, 12B, and 12C are cross-sectional views showing configuration examples of semiconductor devices. 13A, 13B, and 13C are cross-sectional views showing configuration examples of a semiconductor device. FIG. 14 is a cross-sectional view showing a configuration example of a semiconductor device. 15A and 15B are cross-sectional views showing configuration examples of a semiconductor device. 16A and 16B are cross-sectional views showing configuration examples of a semiconductor device. 17A and 17B are cross-sectional views showing configuration examples of a semiconductor device. 18A and 18B are cross-sectional views showing configuration examples of a semiconductor device. 19A and 19B are cross-sectional views showing configuration examples of a semiconductor device. 20A and 20B are cross-sectional views showing configuration examples of a semiconductor device. 21A and 21B are cross-sectional views showing configuration examples of a semiconductor device. 22A, 22B, 22C, 22D, and 22E are cross-sectional views illustrating a method for manufacturing a semiconductor device. 23A, 23B, and 23C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 24A, 24B, and 24C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 25A, 25B, and 25C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 26A and 26B are cross-sectional views illustrating a method for manufacturing a semiconductor device. Fig. 27A is a diagram for explaining a laser processing device, and Fig. 27B and Fig. 27C are diagrams for explaining an irradiation method of the laser processing device. 28A, 28B and 28C are top views of the display device. FIG. 29 is a cross-sectional view of the display device. FIG. 30 is a cross-sectional view of the display device. FIG. 31 is a cross-sectional view of the display device. FIG. 32 is a cross-sectional view of the display device. FIG. 33 is a cross-sectional view of the display device. Fig. 34A is a block diagram of a display device, and Fig. 34B and Fig. 34C are circuit diagrams of the display device. Figures 35A, 35C and 35D are circuit diagrams of the display device, and Figure 35B is a timing chart of the display device. Fig. 36A is a diagram showing a configuration example of a display module, and Fig. 36B is a schematic cross-sectional view of the display module. Fig. 37A is a diagram showing a configuration example of an electronic device, and Fig. 37B is a schematic cross-sectional view of the electronic device. 38A, 38B, 38C, 38D, and 38E are diagrams showing configuration examples of electronic devices. 39A, 39B, 39C, 39D, 39E, 39F, and 39G are diagrams showing configuration examples of electronic devices. 40A, 40B, 40C, and 40D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0029] In each figure described in this specification, the size, layer thickness, or area of ​​each component may be exaggerated for clarity.

[0030] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and do not limit the numbers.

[0031] In this specification, the terms "above" and "below" indicating the position are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0032] In this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, the terms source and drain can be used interchangeably.

[0033] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of a current flowing through a semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Note that, depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be determined to be one.

[0034] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action." Here, the "something having some electrical action" is not particularly limited as long as it allows transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0035] In this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film".

[0036] In this specification, the phrase "top surface shapes roughly match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the edge of the upper layer may be located inside the edge of the lower layer, or the edge of the upper layer may be located outside the edge of the lower layer. In this case, the phrase "top surface shapes roughly match" is also used.

[0037] In this specification, unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state) when the voltage V gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0038] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0039] In this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0040] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0041] The touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. The touch panel can have a display panel and a touch sensor panel. Alternatively, the touch panel can have a function as a touch sensor inside or on the surface of the display panel.

[0042] In this specification and the like, a touch panel substrate on which a connector and / or an IC are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0043] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described.

[0044] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The first gate electrode has a region overlapping with the first semiconductor layer through the first gate insulating layer. The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate electrode. The second gate electrode has a region overlapping with the second semiconductor layer through the second gate insulating layer. The first insulating layer preferably has a region overlapping with the first transistor through the second insulating layer. The second insulating layer preferably has a region overlapping with the second transistor through the first insulating layer. In addition, the second insulating layer preferably has a lower hydrogen permeability than the first insulating layer. By using a film having a higher film density than the first insulating layer for the second insulating layer, it is possible to suppress permeation of hydrogen from the first insulating layer side to the first transistor side.

[0045] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The first gate electrode has a region overlapping with the first semiconductor layer through the first gate insulating layer. The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate electrode. The second gate electrode has a region overlapping with the second semiconductor layer through the second gate insulating layer. The first gate insulating layer preferably includes a first insulating layer and a second insulating layer on the first insulating layer. The second insulating layer preferably has a region overlapping with the second transistor through the first insulating layer. In addition, the second insulating layer preferably has a lower hydrogen permeability than the first insulating layer. By using a film having a higher film density than the first insulating layer for the second insulating layer, hydrogen permeation from the first insulating layer side to the first transistor side can be suppressed.

[0046] The first transistor can be a transistor including a metal oxide (hereinafter also referred to as an oxide semiconductor) (hereinafter also referred to as an OS transistor). The OS transistor has an extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, the OS transistor has an extremely small source-drain leakage current in an off state (hereinafter also referred to as an off-current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. By using an OS transistor, a semiconductor device with low power consumption can be provided.

[0047] The second transistor may be a transistor having silicon (hereinafter also referred to as a Si transistor). In particular, a transistor having low temperature polysilicon (LTPS: Low Temperature Poly Silicon) (hereinafter also referred to as an LTPS transistor) may be preferably used. An LTPS transistor has high field-effect mobility and good frequency characteristics. By using an LTPS transistor, a semiconductor device with high operating speed can be obtained.

[0048] In the semiconductor device according to one embodiment of the present invention, a Si transistor is used for a transistor that requires high field-effect mobility, and an OS transistor is used for a transistor that requires low leakage current. By providing these transistors on the same substrate, component costs and mounting costs can be reduced. In addition, the semiconductor device according to one embodiment of the present invention includes an OS transistor and a Si transistor, and thus can be a semiconductor device that achieves both low power consumption and high-speed operation. In addition, the semiconductor device has good electrical characteristics and high reliability.

[0049] The semiconductor device according to one embodiment of the present invention can be applied to a display device. For example, an OS transistor can be used as a transistor that functions as a switch for controlling conduction or non-conduction of a wiring, and a Si transistor can be used as a transistor for controlling a current. In particular, it is preferable to use an LTPS transistor as a transistor for controlling a current. With such a configuration, a display device that achieves both low power consumption and high-speed operation can be obtained. In addition, a display device with favorable electrical characteristics and high reliability can be obtained.

[0050] The first insulating layer has a region located between the OS transistor and the Si transistor. The first insulating layer preferably has a region overlapping with the OS transistor and a region overlapping with the Si transistor. The first insulating layer has a region from which hydrogen is released when heat is applied. Hydrogen released from the first insulating layer terminates dangling bonds of silicon in the Si transistor, making the Si transistor have good electrical characteristics. In addition, the Si transistor can have high reliability.

[0051] However, when hydrogen desorbed from the first insulating layer diffuses into the OS transistor, the hydrogen removes oxygen from the metal oxide, causing oxygen vacancies (hereafter referred to as V O In addition, oxygen vacancies (V O ) with hydrogen (hereafter referred to as V O Hydrogen can be a carrier supply source. In particular, when hydrogen diffuses into the channel formation region, the carrier concentration in the channel formation region increases, which may deteriorate the electrical characteristics of the OS transistor. In the semiconductor device according to one embodiment of the present invention, a second insulating layer having low hydrogen permeability is provided between the first insulating layer and the OS transistor, which can suppress diffusion of hydrogen into the OS transistor and provide an OS transistor with favorable electrical characteristics. In addition, the OS transistor can have high reliability.

[0052] The semiconductor device according to one embodiment of the present invention can be manufactured by forming an OS transistor after forming a Si transistor. Since the OS transistor can be manufactured at a low temperature, the OS transistor can be formed without deteriorating the electrical characteristics and reliability of the Si transistor, and a semiconductor device having both good electrical characteristics and high reliability can be obtained.

[0053] A more specific configuration example will be described below with reference to the drawings.

[0054] <Configuration example 1> [Configuration Example 1-1] 1A shows a schematic cross-sectional view of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 includes a transistor 20 and a transistor 30. FIG 1A shows a schematic cross-sectional view of the transistor 20 and the transistor 30 in the channel length direction.

[0055] The semiconductors used in the transistors 20 and 30 may each be a Group 14 semiconductor (silicon, germanium, etc.), a compound semiconductor such as gallium arsenide, an organic semiconductor, or a metal oxide. The semiconductors used in the transistors 20 and 30 may each be a non-single crystal semiconductor (amorphous semiconductor, microcrystalline semiconductor, polycrystalline semiconductor, etc.) or a single crystal semiconductor. The semiconductors used in the transistors 20 and 30 may be the same type of material or different types of materials.

[0056] For example, amorphous silicon can be used as the semiconductor used in the transistors 20 and 30. In particular, amorphous silicon is easy to mass-produce and can be easily provided on a large-area substrate. Generally, amorphous silicon used in transistors contains a lot of hydrogen. For this reason, amorphous silicon containing a lot of hydrogen is sometimes called "hydrogenated amorphous silicon" or "a-Si:H". In addition, amorphous silicon can be formed at a lower temperature than polycrystalline silicon, so the maximum temperature during the manufacturing process can be reduced. Therefore, materials with low heat resistance can be used for the substrate, conductive layer, insulating layer, and the like.

[0057] For example, silicon having crystallinity, such as microcrystalline silicon, polycrystalline silicon, or single crystal silicon, can also be used as a semiconductor used in the transistor 20 and the transistor 30. In particular, polycrystalline silicon called low temperature polysilicon (LTPS) can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.

[0058] For example, a metal oxide can be used as a semiconductor used in the transistor 20 and the transistor 30. Typically, an oxide semiconductor containing indium can be used. A transistor using a metal oxide can achieve higher field-effect mobility and higher reliability than a transistor using amorphous silicon. In addition, a transistor using a metal oxide has excellent mass productivity and can be easily provided on a large-area substrate.

[0059] The transistor 20 includes a semiconductor layer 108, an insulating layer 110, and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 has a region overlapping with the semiconductor layer 108 with the insulating layer 110 interposed therebetween and functions as a gate electrode. The transistor 20 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 108. For example, a metal oxide can be suitably used as the semiconductor layer 108.

[0060] The transistor 30 includes a semiconductor layer 308, an insulating layer 135, and a conductive layer 306. The insulating layer 135 functions as a gate insulating layer. The conductive layer 306 has a region overlapping with the semiconductor layer 308 via the insulating layer 135, and functions as a gate electrode. The transistor 30 is a so-called top-gate transistor in which a gate electrode is provided on the semiconductor layer 308. For example, silicon can be suitably used as the semiconductor layer 308. For example, crystalline silicon can be suitably used as the semiconductor layer 308, and in particular, low-temperature polysilicon (LTPS) can be suitably used.

[0061] In the semiconductor device 10 which is one embodiment of the present invention, different materials can be used for the semiconductor layer 108 of the transistor 20 and the semiconductor layer 308 of the transistor 30. By including transistors whose semiconductor layers are made of different materials, the semiconductor device 10 can be a high-performance semiconductor device that takes advantage of the advantages of each transistor. By providing the transistor 20 above the transistor 30, the semiconductor device 10 can be made small. By using the semiconductor device which is one embodiment of the present invention for a display device, a high-definition display device can be obtained.

[0062] The transistor 20 will now be described in detail.

[0063] The semiconductor layer 108 includes a region 108i and a pair of regions 108n. The region 108i overlaps with the conductive layer 112 with the insulating layer 110 interposed therebetween, and functions as a channel formation region. The higher the electrical resistance of the region 108i in a state in which a channel is not formed, the more preferable it is. For example, the sheet resistance of the region 108i is 1×10 7 Ω / □ or more is preferable, and 1×10 8 Ω / □ or more is preferable, and 1×10 9 Ω / □ or higher is preferable.

[0064] The pair of regions 108n are provided with the region 108i therebetween. The region 108n has a lower resistance than the region 108i and functions as a source region and a drain region. The lower the electrical resistance of the region 108n, the more preferable it is. For example, the sheet resistance value of the region 108n is 1 Ω / □ or more and 1×10 3 It is preferable that the resistance is less than Ω / □, and more preferably 1Ω / □ or more and 8×10 2 It is preferable that the resistance is Ω / □ or less. The above upper and lower limits can be combined in any manner.

[0065] When no channel is formed, the electrical resistance of the region 108i is 1×10 times that of the region 108n. 6 1×10 times more 12 times or less is preferable, and even more preferably 1×10 6 1×10 times more 11 times or less is preferable, and even more preferably 1×10 6 1×10 times more 10 It is preferable that the above upper limit value and lower limit value be combined in any manner.

[0066] By using the resistance value in the above range, the transistor 20 can have excellent switching characteristics, that is, a high on-state current and a low off-state current.

[0067] The carrier concentration in the region 108i functioning as a channel formation region is preferably as low as possible. 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is 1×10 16 cm -3 More preferably, it is 1×10 13 cm -3 More preferably, it is 1×10 12 cm -3 The lower limit of the carrier concentration in the region 108i is not particularly limited, but is preferably 1×10 -9 cm -3 It can be said that:

[0068] On the other hand, the carrier concentration in the region 108n is, for example, 5×10 18 cm -3 More than 1×10 19 cm -3 More preferably, 5×10 19 cm -3 The upper limit of the carrier concentration in the region 108n is not particularly limited, but may be, for example, 5×10 21 cm -3 , or 1 × 10 22 cm -3 etc.

[0069] By setting the carrier concentration within the above range, the transistor 20 can have excellent switching characteristics, i.e., a high on-current and a low off-current.

[0070] The region 108n is a region containing a first element. As the first element, for example, one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, helium, neon, argon, krypton, and xenon can be used. As the first element, in particular, one or more of hydrogen, boron, nitrogen, and phosphorus can be preferably used.

[0071] The concentration of the first element in the semiconductor layer 108 can be analyzed by, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When XPS analysis is used, the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or the back side with XPS analysis. When the concentration of the first element is low, the first element may not be detected in the analysis or may be below the detection limit. In particular, since the concentration of the first element is low in the region 108i, the first element may not be detected in the analysis or may be below the detection limit.

[0072] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) exhibiting semiconductor characteristics. The semiconductor layer 108 preferably contains at least indium and oxygen. When the semiconductor layer 108 contains an oxide of indium, carrier mobility can be increased. For example, a transistor capable of passing a larger current than that in the case of using amorphous silicon can be realized. Furthermore, the semiconductor layer 108 can use a metal oxide containing at least zinc and oxygen. When the semiconductor layer 108 contains an oxide of zinc, carrier mobility can be increased.

[0073] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 108, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0074] The semiconductor layer 108 preferably contains a metal oxide. Alternatively, the semiconductor layer 108 may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (polycrystalline polysilicon, microcrystalline silicon, single crystal silicon, etc.).

[0075] When a metal oxide is used as the semiconductor layer 108, it is preferable that the semiconductor layer 108 contains, for example, indium, an element M (M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, it is preferable that the element M is one or more of aluminum, gallium, yttrium, and tin. It is further preferable that the element M contains either one or both of gallium and tin.

[0076] For example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (hereinafter, also referred to as IGZO) can be suitably used as the semiconductor layer 108. For example, an oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 or a ratio close to that can be used as the semiconductor layer 108.

[0077] In addition to indium, gallium, and zinc, an oxide containing one or more of aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium can also be used for the semiconductor layer 108. In particular, it is preferable to use an oxide containing tin, aluminum, or silicon in addition to indium, gallium, and zinc for the semiconductor layer because a transistor with high field-effect mobility can be realized.

[0078] When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used to deposit the In-M-Zn oxide preferably has an atomic ratio of In to element M of 1 or more. The atomic ratios of metal elements in such a sputtering target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In: Examples include M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, etc. In the above, when two or more elements are contained as the element M, the proportion of the element M in the above atomic ratio corresponds to the sum of the numbers of atoms of the two or more metal elements.

[0079] The sputtering target is preferably a target containing a polycrystalline oxide, since it is easy to form a semiconductor layer having crystallinity. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer is In:M:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer to be formed may be close to In:M:Zn=4:2:3 [atomic ratio].

[0080] When the atomic ratio is described as In:M:Zn=4:2:3 or thereabout, it includes the case where, when In is 4, the element M is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When the atomic ratio is described as In:M:Zn=5:1:6 or thereabout, it includes the case where, when In is 5, M is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. When the atomic ratio is described as In:M:Zn=1:1:1 or thereabout, it includes the case where, when In is 1, the element M is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0081] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 preferably contains a metal oxide containing at least indium and oxygen. The semiconductor layer 108 may also contain zinc in addition to these. The semiconductor layer 108 may also contain gallium.

[0082] For example, the semiconductor layer 108 may have a metal element atomic ratio of In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:4, In:Ga:Zn=5:1:5, In:Ga:Zn=5:1:6, In :Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:4, In:Ga:Zn=10:1:5, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, or metal oxide films close to these can be used.

[0083] The composition of the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 20. For example, by increasing the indium content in the semiconductor layer 108, carrier mobility is improved, and a transistor with high field-effect mobility can be realized.

[0084] One of the indicators for evaluating the reliability of transistors is the Gate Bias Stress Test (GBT), which applies an electric field to the gate and holds it there. Among them, a test in which a positive potential is applied to the gate with respect to the source potential and drain potential and it is held at high temperature is called the Positive Bias Temperature Stress (PBTS) test, and a test in which a negative potential is applied to the gate and it is held at high temperature is called the Negative Bias Temperature Stress (NBTS) test. In addition, the PBTS test and the NBTS test, which are performed under irradiation with light such as white LED light, are called the Positive Bias Temperature Illumination Stress (PBTIS) test and the Negative Bias Temperature Illumination Stress (NBTIS) test, respectively.

[0085] In particular, in an n-type transistor using an oxide semiconductor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows), so the amount of change in the threshold voltage in a PBTS test is one of the important items to focus on as an index of the reliability of the transistor.

[0086] By using a metal oxide film that does not contain gallium or has a low gallium content for the semiconductor layer 108, the amount of variation in threshold voltage in the PBTS test can be reduced. When gallium is contained, the composition of the semiconductor layer 108 preferably contains less gallium than indium. This makes it possible to realize a highly reliable transistor.

[0087] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the more significant the degradation in the PBTS test. The generation of the defect levels can be suppressed by reducing the gallium content in the part of the semiconductor layer that contacts the gate insulating layer.

[0088] The reason why PBTS degradation can be suppressed by not including gallium or by reducing the gallium content is, for example, as follows. Gallium contained in the semiconductor layer 108 has a property of attracting oxygen more easily than other metal elements (for example, indium and zinc). Therefore, it is presumed that at the interface between the metal oxide film containing a large amount of gallium and the insulating layer 110 containing oxide, gallium bonds with excess oxygen in the insulating layer 110, which makes it easier to generate carrier (here, electron) trap sites. Therefore, it is considered that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing the threshold voltage to fluctuate.

[0089] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, a metal oxide film in which the atomic ratio of In is higher than that of Ga can be applied to the semiconductor layer 108. It is more preferable to use a metal oxide film in which the atomic ratio of Zn is higher than that of Ga. In other words, it is preferable to apply a metal oxide film in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga to the semiconductor layer 108.

[0090] When a metal oxide film containing indium and gallium is used as the semiconductor layer 108, the ratio of the number of gallium atoms to the number of atoms of the metal element contained in the metal oxide (atomic ratio) can be set to be greater than 0 and less than 50%, preferably 0.05% or more and 30% or less, more preferably 0.1% or more and 15% or less, and more preferably 0.1% or more and 5% or less. By including gallium in the semiconductor layer 108, oxygen deficiency (hereinafter referred to as V O This has the effect of making it less likely for the above-mentioned problems (also referred to as "friction") to occur.

[0091] A metal oxide film that does not contain gallium may be applied to the semiconductor layer 108. For example, In-Zn oxide may be applied to the semiconductor layer 108. In this case, by increasing the atomic ratio of In to the atomic number of metal elements contained in the metal oxide film, the field effect mobility of the transistor can be increased. On the other hand, by increasing the atomic ratio of Zn to the atomic number of metal elements contained in the metal oxide, a metal oxide film with high crystallinity is obtained, so that the fluctuation of the electrical characteristics of the transistor is suppressed and the reliability can be improved. In addition, a metal oxide film that does not contain gallium or zinc, such as indium oxide, may be applied to the semiconductor layer 108. By using a metal oxide film that does not contain gallium at all, the fluctuation of the threshold voltage, particularly in the PBTS test, can be made extremely small.

[0092] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide film having an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these can be used.

[0093] In particular, it is preferable to use a metal oxide film in which the atomic ratio of In is higher than the atomic ratio of the element M for the semiconductor layer 108. It is also preferable to use a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of the element M.

[0094] It is preferable to use a metal oxide film having crystallinity for the semiconductor layer 108. For example, a metal oxide film having a c-axis aligned crystal (CAAC) structure, a nano crystal (nc) structure, a polycrystalline structure, a microcrystalline structure, or the like, which will be described later, can be used. By using a metal oxide film having crystallinity for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0095] The higher the crystallinity of the semiconductor layer 108, the more the density of defect states in the film can be reduced. On the other hand, by using a metal oxide film with low crystallinity, a transistor capable of passing a large current can be realized.

[0096] The semiconductor layer 108 may have a stacked structure in which layers with different compositions, layers with different crystallinity, or layers with different impurity concentrations are stacked.

[0097] When a metal oxide film is formed by a sputtering method, the higher the substrate temperature (stage temperature) during film formation, the higher the crystallinity of the formed metal oxide film. Also, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during film formation (also called the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide film. In this way, the crystallinity of the formed metal oxide film can be controlled by the substrate temperature and the oxygen flow rate ratio in the film formation gas.

[0098] The insulating layer 110 functions as a gate insulating layer of the transistor 20. The insulating layer 110 in contact with the semiconductor layer 108 preferably contains an oxide or an oxynitride. The insulating layer 110 may have a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 may have an insulating film capable of releasing oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 under an oxygen atmosphere, performing heat treatment under an oxygen atmosphere after the insulating layer 110 is formed, performing plasma treatment or the like under an oxygen atmosphere after the insulating layer 110 is formed, or forming an oxide film or an oxynitride film on the insulating layer 110 under an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (e.g., dinitrogen monoxide or ozone) may be used instead of or in addition to oxygen.

[0099] In this specification, an oxynitride refers to a material having a higher oxygen content than nitrogen, and a nitride oxide refers to a material having a higher nitrogen content than oxygen. For example, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0100] The insulating layer 110 can be formed by, for example, a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method, a thermal CVD method, and the like. In particular, it is preferable to form the insulating layer 110 by a plasma enhanced CVD (PECVD) method.

[0101] For example, the insulating layer 110 can be an insulating film containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the insulating layer 110 may have a stacked structure of two layers or a stacked structure of three or more layers.

[0102] A material such as hafnium oxide, which has a higher dielectric constant than silicon oxide or silicon oxynitride, can be used as the insulating layer 110. This allows the insulating layer 110 to be thicker and suppresses leakage current due to tunnel current. In particular, crystalline hafnium oxide is preferable because it has a higher dielectric constant than amorphous hafnium oxide.

[0103] The conductive layer 112 functions as a gate electrode of the transistor 20. The conductive layer 112 is preferably formed using a low-resistance material. By using a low-resistance material for the conductive layer 112, parasitic resistance can be reduced, and a transistor having high on-state current can be obtained, and a semiconductor device having high on-state current can be provided. For example, it is preferable to use a conductive film containing a metal or an alloy as the conductive layer 112 because the electrical resistance can be reduced. Note that a conductive film containing an oxide may be used for the conductive layer 112. Furthermore, by reducing the wiring resistance in a large display device or a high-definition display device, signal delay can be suppressed and high-speed driving can be achieved.

[0104] The conductive layer 112 can be made of one or more selected from chromium, copper, aluminum, gold, silver, zinc, niobium, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt. The conductive layer 112 may be made of an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements. Copper is particularly preferable because it has low resistance and is easy to mass-produce.

[0105] The conductive layer 112 may have a stacked structure. When the conductive layer 112 has a stacked structure, a second conductive layer is provided on the upper or lower part, or both, of a first conductive layer having low resistance. The second conductive layer is preferably made of a conductive material that is less likely to be oxidized (has oxidation resistance) than the first conductive layer. In addition, the second conductive layer is preferably made of a material that suppresses the diffusion of components of the first conductive layer. As the second conductive layer, for example, metal oxides such as indium oxide, indium zinc oxide, indium tin oxide (ITO), indium tin oxide containing silicon (ITSO), and zinc oxide, or metal nitrides such as titanium nitride, tantalum nitride, molybdenum nitride, and tungsten nitride can be suitably used.

[0106] The conductive layer 112 can also be made of an oxide conductor or a metal oxide film such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0107] Here, an oxide conductor (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is supplied to the oxygen vacancies, a donor level is formed in the vicinity of the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor.

[0108] The conductive layer 112 may have a stacked structure of a conductive film containing an oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. In this case, it is preferable to use a conductive film containing an oxide conductor on the side in contact with an insulating layer that functions as a gate insulating film.

[0109] The semiconductor device 10 preferably further includes an insulating layer 118. The insulating layer 118 functions as a protective insulating layer that protects the transistor 20 and the transistor 30. The insulating layer 118 can be formed using an inorganic insulating material such as an oxide, an oxynitride, a nitride oxide, or a nitride. More specifically, the insulating layer 118 can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate. The insulating layer 118 may have a stacked structure of two or more layers.

[0110] In this specification, when an oxynitride and a nitride oxide each containing the same element are described, the oxynitride includes a material that satisfies either one or both of the following: the oxygen content is higher than that of the nitride oxide and the nitrogen content is lower. Similarly, the nitride oxide includes a material that satisfies either one or both of the following: the oxygen content is lower than that of the oxynitride and the nitrogen content is higher. For example, when silicon oxynitride and silicon nitride oxide are described, the silicon oxynitride includes a material that has a higher oxygen content and a lower nitrogen content than that of silicon nitride oxide. Similarly, the silicon nitride oxide includes a material that has a lower oxygen content and a higher nitrogen content than that of silicon oxynitride.

[0111] The insulating layer 118 may function as a supply source of the first element for the region 108n. For example, the insulating layer 118 can function as a supply source of hydrogen for the region 108n. By supplying the first element to the region 108n, the resistance of the region 108n can be reduced. Note that since the region 108i has the conductive layer 112 between it and the insulating layer 118, the first element is less likely to be supplied, and the resistance of the region 108i can be prevented from being reduced.

[0112] When hydrogen is used as the first element, the insulating layer 118 may be formed using a mixed gas containing a gas containing hydrogen. This allows hydrogen to be effectively supplied to the region 108n exposed during the formation of the insulating layer 118, and the resistance of the region 108n can be further reduced. Examples of the gas containing hydrogen include hydrogen (H2), ammonia (NH3), and silane (SiH4).

[0113] The transistor 20 can have high electrical characteristics by increasing the resistance of the region 108i and decreasing the resistance of the region 108n.

[0114] The semiconductor device 10 includes an insulating layer 118 that covers the semiconductor layer 108, the insulating layer 110, and the conductive layer 112. The insulating layer 118 functions as a protective insulating layer for the transistor 20.

[0115] A conductive layer 120a and a conductive layer 120b are provided over the insulating layer 118. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108n through openings provided in the insulating layer 110 and the insulating layer 118, respectively. The conductive layer 120a functions as one of a source electrode and a drain electrode of the transistor 20, and the conductive layer 120b functions as the other of the source electrode and drain electrode.

[0116] The conductive layer 120a and the conductive layer 120b can be formed using a material that can be used for the conductive layer 112. The conductive layer 120a and the conductive layer 120b can also be formed using one or more selected from titanium, tungsten, tantalum, niobium, and molybdenum. In particular, a tantalum nitride film is preferably used for the conductive layer 112. A tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself; therefore, the tantalum nitride film can be preferably used as a conductive film in contact with the semiconductor layer 108 or in the vicinity of the semiconductor layer 108.

[0117] Next, the transistor 30 will be described in detail.

[0118] The semiconductor layer 308 includes a region 308i and a pair of regions 308n. The region 308i overlaps with the conductive layer 306 with the insulating layer 135 interposed therebetween and functions as a channel formation region.

[0119] The pair of regions 308n are provided with the region 308i therebetween. The region 308n has a lower resistance than the region 308i and functions as a source region and a drain region.

[0120] The region 308n is a region containing a second element. The second element may be a group 13 element or a group 15 element. The second element may be, for example, one or more elements selected from boron, aluminum, gallium, indium, phosphorus, arsenic, antimony, and bismuth. When the transistor 30 is an n-channel transistor, one or more elements of phosphorus or arsenic may be preferably used as the second element. When the transistor 30 is a p-channel transistor, one or more elements of boron or aluminum may be preferably used as the second element. In addition, in order to control the threshold voltage of the transistor 30, the second element may be added to the region 308i functioning as a channel formation region.

[0121] Regarding the analysis of the concentration of the second element in the semiconductor layer 308, the above description of the first element can be referred to, and therefore a detailed description thereof will be omitted.

[0122] The semiconductor layer 308 preferably contains silicon. There is no particular limitation on the crystallinity of a semiconductor material used for the semiconductor layer 308, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of transistor characteristics. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single crystal silicon).

[0123] The insulating layer 135 functions as a gate insulating layer of the transistor 30. The insulating layer 135 in contact with the semiconductor layer 308 preferably contains an oxide or an oxynitride. The insulating layer 135 can be formed using any of the materials that can be used for the insulating layer 110.

[0124] The conductive layer 306 can be formed using any of the materials that can be used for the conductive layer 112 .

[0125] The semiconductor device 10 includes an insulating layer 103, an insulating layer 110, and an insulating layer 118 which cover the semiconductor layer 308, the insulating layer 135, and the conductive layer 306. The insulating layer 103, the insulating layer 110, and the insulating layer 118 function as protective insulating layers for the transistor 30.

[0126] The insulating layer 103 functioning as a protective insulating layer for the transistor 30 can be formed by appropriately using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, or the like. The insulating layer 103 can be formed, for example, of a single layer or a stack of an oxide insulating film, an oxynitride insulating film, a nitride oxide insulating film, or a nitride insulating film. The insulating layer 103 can be formed using one or more inorganic insulating materials selected from, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate.

[0127] In order to improve the interface characteristics with the semiconductor layer 108, at least a region of the insulating layer 103 in contact with the semiconductor layer 108 is preferably formed of an oxide film or an oxynitride film. When a film other than an oxide film or an oxynitride film, such as a silicon nitride film, is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable to perform pretreatment such as oxygen plasma treatment on the surface in contact with the semiconductor layer 108 to oxidize the surface or the vicinity of the surface.

[0128] The insulating layer 103 preferably has a layered structure. Fig. 1A shows an example of a four-layer structure in which an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, and an insulating layer 103d are stacked in this order from the conductive layer 306 side. The insulating layer 103a has a region in contact with the conductive layer 306. The insulating layer 103d has a region in contact with the semiconductor layer 108.

[0129] For the insulating layers 103a, 103b, 103c, and 103d, an inorganic insulating material such as an oxide, an oxynitride, a nitride oxide, or a nitride can be suitably used. More specifically, for the insulating layers 103a, 103b, 103c, and 103d, an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used. The insulating layers 103a, 103b, 103c, and 103d may be made of different materials or the same material.

[0130] An insulating film containing oxygen is preferably used as the insulating layer 103a located on the formation surface side of the insulating layer 103. The insulating layer 103a can be an insulating film containing at least silicon and oxygen, typically a silicon oxide film or a silicon oxynitride film.

[0131] The insulating layer 103b is preferably an insulating film that contains hydrogen and from which hydrogen is released by application of heat. Hydrogen released from the insulating layer 103b terminates dangling bonds of silicon in the semiconductor layer 308, thereby improving the electrical characteristics of the transistor 30. The insulating layer 103b can be an insulating film containing nitrogen. The insulating layer 103b can be an insulating film containing at least silicon and nitrogen, typically a silicon nitride film or a silicon nitride oxide film.

[0132] The insulating layer 103c is preferably a dense film capable of suppressing diffusion of impurities from below. The insulating layer 103c is preferably a film capable of blocking impurities including metal elements and hydrogen contained in a member (e.g., a substrate) on the surface on which the insulating layer 103c is to be formed. Examples of impurities including hydrogen include hydrogen and water. The insulating layer 103c is preferably a film capable of blocking impurities including hydrogen. For this reason, an insulating layer formed under conditions in which the film formation rate is slower than that of the insulating layer 103b can be used for the insulating layer 103c.

[0133] The insulating layer 103c can be an insulating film containing nitrogen. For example, the insulating layer 103c can be an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film, or an insulating film containing an oxide, such as aluminum oxide or hafnium oxide. In particular, it is preferable to use a dense silicon nitride film formed by using a plasma CVD apparatus as the insulating layer 103c. By using such an insulating film containing nitrogen, it is possible to suppress the diffusion of impurities from the surface to be formed, even if the insulating layer is thin.

[0134] The insulating layer 103c preferably has lower hydrogen permeability than the insulating layer 103b. The insulating layer 103c is preferably an insulating film that is denser than the insulating layer 103b. The insulating layer 103c is preferably an insulating film that has a higher film density than the insulating layer 103b. By using such an insulating film for the insulating layer 103c, hydrogen contained in the insulating layer 103b can be prevented from diffusing toward the insulating layer 103d. Therefore, hydrogen contained in the insulating layer 103b can be efficiently supplied to the semiconductor layer 308, and dangling bonds of silicon contained in the semiconductor layer 308 can be terminated, resulting in a transistor 30 having favorable electrical characteristics.

[0135] The film density can be evaluated using X-ray reflectivity (XRR) or transmission electron microscopy (TEM) images. For example, when the film densities of insulating layers 103b and 103c are different, they may be observed as different contrasts in a transmission electron microscope (TEM) image of a cross section of insulating layer 103, and may be distinguishable from each other. However, when the compositions and film densities are similar, the boundary between them may be unclear.

[0136] By providing the insulating layer 103c, it is possible to prevent hydrogen contained in the insulating layer 103b from diffusing into the semiconductor layer 108 of the transistor 20. When a metal oxide is used for the semiconductor layer 108, hydrogen diffused into the semiconductor layer 108 removes oxygen from the semiconductor layer 108, causing oxygen deficiency (V O ) is generated. In addition, this oxygen vacancy (V O ) with hydrogen (hereafter referred to as V O Hydrogen (also referred to as H) can be a carrier supply source. In particular, when hydrogen diffuses into the region 108i, which is a channel formation region, the carrier concentration in the region 108i increases, and the electrical characteristics of the transistor 20 deteriorate. In the semiconductor device 10 according to one embodiment of the present invention, by providing the insulating layer 103c between the insulating layer 103b containing a lot of hydrogen and the semiconductor layer 108, diffusion of hydrogen from the insulating layer 103b to the semiconductor layer 108 can be suppressed, and the transistor 20 can have favorable electrical characteristics.

[0137] It is preferable that the insulating layer 103c has a lower hydrogen concentration than the insulating layer 103b. By using such an insulating film for the insulating layer 103c, the amount of hydrogen released from the insulating layer 103c itself is reduced, and oxygen deficiency (V O ) or V O The increase in H can be suppressed.

[0138] It is preferable that the semiconductor device 10 has at least a region where the semiconductor layer 308 overlaps with the insulating layer 103c via the insulating layer 103b. With such a configuration, it is possible to obtain a semiconductor device having good electrical characteristics and high reliability. Furthermore, it is preferable that the semiconductor device 10 has at least a region where the semiconductor layer 108 overlaps with the insulating layer 103b via the insulating layer 103c.

[0139] For example, a silicon nitride film can be used for each of the insulating layer 103b and the insulating layer 103c. When the insulating layer 103b is formed using a plasma CVD apparatus, for example, a mixed gas of silane, nitrogen, and ammonia can be used as a deposition gas. By using ammonia, the insulating layer 103b can contain a large amount of hydrogen. When the insulating layer 103c is formed using a plasma CVD apparatus, for example, a mixed gas of silane, nitrogen, and ammonia can be used as a deposition gas. It is preferable to form the insulating layer 103c with a smaller ammonia flow rate than that of the insulating layer 103b. By reducing the ammonia flow rate compared to that of the insulating layer 103b, the insulating layer 103c can have low hydrogen permeability. Furthermore, the amount of hydrogen contained in the insulating layer 103c is reduced, and the amount of hydrogen released from the insulating layer 103c can be reduced. Note that ammonia does not have to be used to form the insulating layer 103c. For example, a mixed gas of silane and nitrogen may be used as a deposition gas when forming the insulating layer 103c.

[0140] The transistor 20 is provided over the insulating layer 103, and the insulating layer 103d has a region in contact with the semiconductor layer 108. The insulating layer 103d in contact with the semiconductor layer 108 is preferably formed using an insulating film containing oxide or oxynitride. In particular, the insulating layer 103d is preferably an oxide film or an oxynitride film. Furthermore, the insulating layer 103d is preferably a dense insulating film on whose surface impurities such as water are unlikely to be adsorbed. Furthermore, it is preferable to use an insulating film with as few defects as possible and in which impurities such as water and hydrogen are reduced.

[0141] It is more preferable that the insulating layer 103d has a region that contains oxygen in excess of the stoichiometric composition. In other words, the insulating layer 103d is preferably an insulating film that can release oxygen by heating. For example, oxygen can be supplied into the insulating layer 103d by forming the insulating layer 103d in an oxygen atmosphere, performing heat treatment in an oxygen atmosphere on the insulating layer 103d after the formation of the insulating layer 103d, performing plasma treatment or the like in an oxygen atmosphere after the formation of the insulating layer 103d, or forming an oxide film or an oxynitride film on the insulating layer 103d in an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (e.g., nitrous oxide or ozone) may be used instead of or in addition to oxygen. Alternatively, an insulating film that can release oxygen by application of heat may be formed on the insulating layer 103d, and then oxygen may be supplied from the insulating film into the insulating layer 103d by applying heat.

[0142] When the metal oxide film to be the semiconductor layer 108 is formed by a sputtering method in an oxygen-containing atmosphere, oxygen can be supplied to the insulating layer 103d. Then, by performing heat treatment after forming the metal oxide film to be the semiconductor layer, oxygen in the insulating layer 103d is supplied to the metal oxide film, and oxygen vacancies (V O ) can be reduced.

[0143] The insulating layer 103d can be preferably an insulating film containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. In particular, it is preferable to use a silicon oxide film or a silicon oxynitride film as the insulating layer 103d.

[0144] The insulating layer 103d is preferably an insulating film that releases as little hydrogen or water as possible. By using such an insulating film, hydrogen or water can be prevented from diffusing from the insulating layer 103d to the semiconductor layer 108 due to heat applied during a heat treatment or other process, and the carrier concentration in the region 108i can be reduced.

[0145] Furthermore, the insulating layer 103c is preferably made of an insulating film through which oxygen does not easily diffuse. This makes it possible to suppress a reduction in the amount of oxygen supplied to the semiconductor layer 108, which would otherwise occur due to diffusion of oxygen from the insulating layer 103d below the insulating layer 103b, when heat treatment is performed to supply oxygen from the insulating layer 103d to the semiconductor layer 108 (or a metal oxide film that becomes the semiconductor layer 108).

[0146] The thickness of the insulating layer 103 can be determined based on the dielectric constant and thickness of each of the insulating layers 103a to 103d, taking into consideration the dielectric constant required for the insulating layer 103 and the dielectric strength performance required for the insulating layer 103. That is, the thicknesses of the insulating layers 103a to 103d can be adjusted to each other within a range that satisfies the above-mentioned requirements.

[0147] It is preferable to use a dense insulating film for the insulating layer 103c, but such an insulating film may have a large stress. When an insulating film with a large stress is used, defects such as warping of the substrate and peeling off may occur. Therefore, the insulating layer 103c does not need to be particularly thick as long as it has a thickness that can block hydrogen diffusion from the insulating layer 103b side to the semiconductor layer 108 side. The thickness of the insulating layer 103c is, for example, preferably 10 nm to 200 nm, more preferably 20 nm to 150 nm, even more preferably 30 nm to 150 nm, even more preferably 30 nm to 100 nm, and even more preferably 50 nm to 100 nm. The above upper and lower limits can be combined arbitrarily.

[0148] It is preferable that the four insulating films of the insulating layer 103 are successively formed without exposure to the air using a plasma CVD apparatus. For example, it is preferable that the insulating layer 103b is formed in a treatment chamber in which the insulating layer 103a is formed. Alternatively, a treatment chamber in which the insulating layer 103a is formed and a treatment chamber in which the insulating layer 103b is formed may be connected via a gate valve or the like, and after the insulating layer 103a is formed, the insulating layer 103b may be transferred to a treatment chamber in which the insulating layer 103b is formed under reduced pressure without exposure to the air. When the insulating layer 103a and the insulating layer 103b are successively formed in the same treatment chamber in the same apparatus, it is preferable that the insulating layer 103a and the insulating layer 103b are formed at the same temperature. It is also preferable that the insulating layer 103b and the insulating layer 103c, and the insulating layer 103c and the insulating layer 103d are successively formed without exposure to the air.

[0149] 1A shows an example in which the insulating layer 103 has a four-layer structure including insulating layers 103a, 103b, 103c, and 103d, but one embodiment of the present invention is not limited thereto. The insulating layer 103 preferably has an insulating layer 103b and an insulating layer 103c on the insulating layer 103b, and may have no insulating layer 103a. For example, the insulating layer 103 may have a two-layer structure including the insulating layer 103b and the insulating layer 103c. Note that in the case where the semiconductor layer 108 is provided over the insulating layer 103, it is preferable that the insulating layer 103d is provided so that the insulating layer 103d is in contact with the semiconductor layer 108. Alternatively, a different layer may be provided between the insulating layer 103b and the insulating layer 103c.

[0150] A conductive layer 312a and a conductive layer 312b are provided over the insulating layer 110. The conductive layer 312a and the conductive layer 312b are electrically connected to the region 308n through openings provided in the insulating layer 110 and the insulating layer 103, respectively. The conductive layer 312a functions as one of a source electrode and a drain electrode of the transistor 30, and the conductive layer 312b functions as the other of the source electrode and drain electrode.

[0151] The conductive layer 312a and the conductive layer 312b can be formed using a material that can be used for the conductive layer 112. The conductive layer 312a, the conductive layer 312b, and the conductive layer 112 are preferably formed using the same material. The conductive layer 312a, the conductive layer 312b, and the conductive layer 112 are preferably formed by processing the same conductive film. By processing the same conductive film, the manufacturing cost can be reduced and the production yield can be increased.

[0152] An insulating layer 118 is provided over the conductive layer 312a and the conductive layer 312b. The insulating layer 118 can be formed using any of the materials that can be used for the insulating layer 103.

[0153] A conductive layer 320a and a conductive layer 320b are provided on the insulating layer 118. The conductive layer 320a and the conductive layer 320b are electrically connected to the conductive layer 312a or the conductive layer 312b, respectively, through an opening provided in the insulating layer 118. Fig. 1A shows an example in which the conductive layer 320a is electrically connected to the region 308n through the conductive layer 312a, and the conductive layer 320b is electrically connected to the region 308n through the conductive layer 312b.

[0154] The conductive layer 320a and the conductive layer 320b can be formed using a material that can be used for the conductive layer 112. Furthermore, it is preferable to use the same material for the conductive layer 320a, the conductive layer 320b, the conductive layer 120a, and the conductive layer 120b. Furthermore, it is preferable to form the conductive layer 320a, the conductive layer 320b, the conductive layer 120a, and the conductive layer 120b by processing the same conductive film. By processing and forming the conductive layer from the same conductive film, it is possible to reduce manufacturing costs and increase production yields.

[0155] [Configuration Example 1-2] An example of a configuration different from the semiconductor device 10 described above is shown in FIG. 1B. The semiconductor device 10A shown in FIG. 1B has a transistor 20A and a transistor 30. FIG. 1B shows a schematic cross-sectional view of the transistor 20A and the transistor 30 in the channel length direction. The semiconductor device 10A differs from the semiconductor device 10 mainly in that the configuration of the insulating layer 110 is different.

[0156] In the semiconductor device 10A, the insulating layer 110 is processed so that its top surface shape is approximately the same as that of the conductive layer 112. The insulating layer 110a is also processed so that its top surface shape is approximately the same as that of the conductive layer 312a and the conductive layer 312b. The insulating layer 110a is preferably made of the same material as that of the insulating layer 110. By using the same material, the insulating layer 110 and the insulating layer 110a can be manufactured through the same process, which can reduce manufacturing costs and increase production yields. The insulating layer 110 and the insulating layer 110a can be processed, for example, using a resist mask for processing the conductive layer 112, the conductive layer 312a, and the conductive layer 312b.

[0157] As shown in FIG. 1B, the insulating layer 118 has a region in contact with the region 108n. With this configuration, the first element can be supplied from the insulating layer 118 to the region 108n. For example, hydrogen contained in the insulating layer 118 diffuses into the region 108n, thereby lowering the resistance of the region 108n. Since the region 108i has the conductive layer 112 between it and the insulating layer 118, less hydrogen diffuses into the region 108i than into the region 108n, and the region 108i has a higher resistance than the region 108n. That is, the region 108n, which is a self-aligned low-resistance region, can be formed.

[0158] 1A shows an example in which the insulating layer 110 and the conductive layer 112 have substantially the same top surface shape, and the insulating layer 110a and the conductive layer 312a and the conductive layer 312b have substantially the same top surface shape, but one embodiment of the present invention is not limited to this. An end of the insulating layer 110 may be located outside an end of the conductive layer 112. Similarly, an end of the insulating layer 110a may be located outside an end of the conductive layer 312a and the conductive layer 312b. In addition, an end of the insulating layer 110 is preferably located inside an end of the semiconductor layer 108.

[0159] [Configuration Example 1-3] An example of a configuration different from the semiconductor device 10 described above is shown in FIG. 1C. The semiconductor device 10B shown in FIG. 1C has a transistor 20 and a transistor 30A. FIG. 1C shows a schematic cross-sectional view of the transistor 20 and the transistor 30A in the channel length direction. The semiconductor device 10B differs from the semiconductor device 10 mainly in that the configuration of the insulating layer 135 is different.

[0160] In the transistor 30A, the insulating layer 135 is processed so as to have a top surface shape that is approximately the same as that of the conductive layer 306. The insulating layer 135 can be processed using a resist mask for processing the conductive layer 306, for example.

[0161] 1C, the insulating layer 103 has a region in contact with the region 308n. For example, the insulating layer 103 may contain a second element, and the second element may be diffused into the semiconductor layer 108 in contact with the insulating layer 103 to form the region 308n. With this configuration, the region 308n, which is a self-aligned low-resistance region, can be formed.

[0162] [Configuration Example 1-4] An example of a configuration different from the above-described semiconductor device 10 is shown in Fig. 2A. The semiconductor device 10C shown in Fig. 2A has a transistor 20 and a transistor 30. Fig. 2A shows a schematic cross-sectional view of the transistor 20 and the transistor 30 in the channel length direction. The semiconductor device 10C mainly differs from the semiconductor device 10 in that the semiconductor device 10C does not have the conductive layer 312a and the conductive layer 312b.

[0163] The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through openings provided in the insulating layer 135, the insulating layer 103, the insulating layer 110, and the insulating layer 118. The conductive layer 320a functions as one of a source electrode and a drain electrode of the transistor 30, and the conductive layer 320b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 312a and the conductive layer 312b, manufacturing costs can be reduced.

[0164] The openings in which the conductive layers 120a and 120b are formed and the openings in which the conductive layers 320a and 320b are formed may be formed in different steps or may be formed in the same step. By forming these openings in the same step, the manufacturing cost can be reduced.

[0165] [Configuration Example 1-5] An example of a configuration different from the semiconductor device 10 described above is shown in FIG. 2B. A semiconductor device 10D shown in FIG. 2B includes a transistor 20B and a transistor 30. FIG. 2B shows a schematic cross-sectional view of the transistor 20B and the transistor 30 in the channel length direction. The semiconductor device 10D differs from the semiconductor device 10 mainly in that it includes conductive layers 151a and 151b and in that it includes conductive layers 351a and 351b instead of the conductive layers 312a and 312b.

[0166] The transistor 20B has a conductive layer 151a and a conductive layer 151b over the region 108n. The conductive layer 151a and the conductive layer 151b each have a region in contact with the region 108n. The conductive layer 151a functions as one of a source electrode and a drain electrode of the transistor 20B, and the conductive layer 151b functions as the other of the source electrode and drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108n through the conductive layer 151a or the conductive layer 151b, respectively.

[0167] The semiconductor device 10D has a conductive layer 351a and a conductive layer 351b over the insulating layer 103. The conductive layer 351a and the conductive layer 351b are electrically connected to the region 308n through openings provided in the insulating layer 135 and the insulating layer 103, respectively. The conductive layer 351a functions as one of a source electrode and a drain electrode of the transistor 30, and the conductive layer 351b functions as the other of the source electrode and drain electrode. The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through the conductive layer 351a or the conductive layer 351b, respectively.

[0168] The conductive layer 151a, the conductive layer 151b, the conductive layer 351a, and the conductive layer 351b can each be formed using a material that can be used for the conductive layer 112. Furthermore, the conductive layer 151a, the conductive layer 151b, the conductive layer 351a, and the conductive layer 351b are preferably formed using the same material. Furthermore, the conductive layer 151a, the conductive layer 151b, the conductive layer 351a, and the conductive layer 351b are preferably formed by processing the same conductive film. By processing and forming the conductive layer from the same conductive film, manufacturing costs can be reduced and production yields can be increased.

[0169] [Configuration Example 1-6] An example of a configuration different from the semiconductor device 10 described above is shown in FIG. 2C. The semiconductor device 10E shown in FIG. 2C includes a transistor 20C and a transistor 30B. FIG. 2C shows a schematic cross-sectional view of the transistor 20C and the transistor 30B in the channel length direction. The semiconductor device 10E differs from the semiconductor device 10 mainly in that it includes a conductive layer 153 and an insulating layer 137, and in that it includes a conductive layer 315 and an insulating layer 133 instead of the conductive layer 312a and the conductive layer 312b.

[0170] The transistor 20C includes a conductive layer 153 and an insulating layer 137. The conductive layer 153 has a region overlapping with the semiconductor layer 108, the insulating layer 110, and the conductive layer 112 with the insulating layer 137 interposed therebetween. In the transistor 20C, the conductive layer 153 functions as a first gate electrode (also referred to as a back gate electrode). The insulating layer 137 functions as a first gate insulating layer. In this case, the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode), and the insulating layer 110 functions as a second gate insulating layer.

[0171] For example, the transistor 20C can increase the current that can flow in an on state by applying the same potential to the conductive layer 112 and the conductive layer 153. In the transistor 20C, a potential for controlling a threshold voltage can be applied to one of the conductive layer 112 and the conductive layer 153, and a potential for controlling the on state and off state of the transistor 20C can be applied to the other. Furthermore, the electrical characteristics of the transistor 20C can be stabilized by electrically connecting one of the conductive layer 112 and the conductive layer 153 to the source.

[0172] The insulating layer 137 functioning as the first gate insulating layer preferably functions as a barrier layer that suppresses diffusion of impurities from the surface where the insulating layer 137 is formed to the semiconductor layer 108 or the like. Examples of the impurities include metal components contained in the conductive layer 153. The insulating layer 137 preferably satisfies one or more of the following, and more preferably satisfies all of the following: high withstand voltage, low film stress, low hydrogen or water release, low diffusion of hydrogen or water, and few defects. The insulating layer 137 can be an insulating film that can be used for the insulating layer 110. The description of the insulating layer 110 can be referred to for the insulating layer 137, and detailed description thereof will be omitted.

[0173] 2C shows an example in which the end of the conductive layer 153 is roughly aligned with the end of the conductive layer 112; however, one embodiment of the present invention is not limited to this example. The end of the conductive layer 153 may be located outside the end of the conductive layer 112. Alternatively, the end of the conductive layer 153 may be located inside the end of the conductive layer 112.

[0174] The transistor 30B includes a conductive layer 315 and an insulating layer 133. The conductive layer 315 has a region overlapping with the semiconductor layer 308, the insulating layer 135, and the conductive layer 306 with the insulating layer 133 interposed therebetween. In the transistor 20C, the conductive layer 315 functions as a first gate electrode (back gate electrode). The insulating layer 133 functions as a first gate insulating layer. In this case, the conductive layer 306 functions as a second gate electrode (top gate electrode), and the insulating layer 135 functions as a second gate insulating layer.

[0175] For example, the transistor 30B can increase the current that can flow in an on state by applying the same potential to the conductive layer 306 and the conductive layer 315. In addition, the transistor 30B can apply a potential to one of the conductive layer 306 and the conductive layer 315 for controlling a threshold voltage, and apply a potential to the other for controlling the on state and off state of the transistor 30B. Furthermore, the electrical characteristics of the transistor 30B can be stabilized by electrically connecting one of the conductive layer 306 and the conductive layer 315 to the source.

[0176] The insulating layer 133 functioning as the first gate insulating layer preferably functions as a barrier layer that suppresses diffusion of impurities from the surface of the insulating layer 133 to the semiconductor layer 308 or the like. Examples of the impurities include metal components contained in the conductive layer 315. The insulating layer 133 preferably satisfies one or more of the following, and more preferably satisfies all of the following: high withstand voltage, low film stress, low release of hydrogen or water, low diffusion of hydrogen or water, and few defects. The insulating layer 133 can be formed using an insulating film that can be used for the insulating layer 110.

[0177] The conductive layer 315 can be formed using any of the materials that can be used for the conductive layer 112 .

[0178] 2C shows an example in which the end of the conductive layer 315 roughly coincides with the end of the conductive layer 306; however, one embodiment of the present invention is not limited to this. The end of the conductive layer 315 may be located outside the end of the conductive layer 306. Alternatively, the end of the conductive layer 315 may be located inside the end of the conductive layer 306.

[0179] The conductive layer 353a and the conductive layer 353b are electrically connected to the region 308n through openings provided in the insulating layer 135 and the insulating layer 103, respectively. The conductive layer 353a serves as one of a source electrode and a drain electrode of the transistor 30B, and the conductive layer 353b serves as the other of the source electrode and drain electrode. The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through the conductive layer 353a or the conductive layer 353b, respectively.

[0180] The conductive layer 353a, the conductive layer 353b, and the conductive layer 153 can each be formed using a material that can be used for the conductive layer 112. The conductive layer 353a, the conductive layer 353b, and the conductive layer 153 are preferably formed using the same material. The conductive layer 353a, the conductive layer 353b, and the conductive layer 153 are preferably formed by processing the same conductive film. By processing and forming the conductive layer from the same conductive film, manufacturing costs can be reduced and production yields can be increased.

[0181] [Configuration Example 1-7] An example of a configuration different from the semiconductor device 10E described above is shown in FIG. 3A. The semiconductor device 10F shown in FIG. 3A has a transistor 20C and a transistor 30B. FIG. 3A shows a schematic cross-sectional view of the transistor 20C and the transistor 30B in the channel length direction. The semiconductor device 10F is mainly different from the semiconductor device 10E in that it does not have an insulating layer 103d.

[0182] The conductive layer 153 functioning as a first gate electrode (backgate electrode) of the transistor 20C has a region in contact with the insulating layer 103c. The conductive layers 353a and 353b functioning as a source electrode and a drain electrode of the transistor 30B have regions in contact with the insulating layer 103c. The semiconductor device 10F does not include the insulating layer 103d, thereby reducing manufacturing costs.

[0183] 3A shows an example in which the insulating layer 103 has a three-layer structure of insulating layers 103a, 103b, and 103c, but one embodiment of the present invention is not limited to this. The insulating layer 103 preferably has the insulating layer 103b and the insulating layer 103c over the insulating layer 103b, and may have a structure without the insulating layer 103a. For example, the insulating layer 103 can have a two-layer structure of the insulating layer 103b and the insulating layer 103c.

[0184] [Configuration Example 1-8] An example of a configuration different from the semiconductor device 10E described above is shown in FIG. 3B. The semiconductor device 10G shown in FIG. 3B has a transistor 20D and a transistor 30B. FIG. 3B shows a schematic cross-sectional view of the transistor 20D and the transistor 30B in the channel length direction. The semiconductor device 10G differs from the semiconductor device 10E mainly in that it does not have an insulating layer 137 and has a conductive layer 106 instead of the conductive layer 153.

[0185] In the transistor 20D, the conductive layer 106 has a region overlapping with the semiconductor layer 108, the insulating layer 110, and the conductive layer 112 with the insulating layer 103 interposed therebetween. In the transistor 20D, the conductive layer 106 functions as a first gate electrode (back gate electrode). The insulating layer 103 functions as a first gate insulating layer. In this case, the conductive layer 112 functions as a second gate electrode (top gate electrode), and the insulating layer 110 functions as a second gate insulating layer.

[0186] For example, the transistor 20D can increase the current that can flow in an on state by applying the same potential to the conductive layer 112 and the conductive layer 106. In addition, the transistor 20D can apply a potential to one of the conductive layer 112 and the conductive layer 106 for controlling a threshold voltage, and apply a potential to the other for controlling the on state and off state of the transistor 20D. Furthermore, the electrical characteristics of the transistor 20D can be stabilized by electrically connecting one of the conductive layer 112 and the conductive layer 106 to the source.

[0187] The insulating layer 103 preferably includes an insulating layer 103d. It is preferable that the insulating layer 103d is provided on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, and the semiconductor layer 108 is provided in contact with the insulating layer 103d. By configuring the insulating layer 103d containing an oxide or oxynitride to be in contact with the semiconductor layer 108, oxygen deficiency (V O ) or V O H can be reduced.

[0188] The conductive layer 106 can be formed using a material that can be used for the conductive layer 112. The conductive layer 106 and the conductive layer 306 are preferably formed using the same material. The conductive layer 106 and the conductive layer 306 are preferably formed by processing the same conductive film. By processing the same conductive film, the manufacturing cost can be reduced and the production yield can be increased.

[0189] 3B shows an example in which the end of the conductive layer 106 is roughly aligned with the end of the conductive layer 112; however, one embodiment of the present invention is not limited to this example. The end of the conductive layer 106 may be located outside the end of the conductive layer 112. Alternatively, the end of the conductive layer 106 may be located inside the end of the conductive layer 112.

[0190] [Configuration Example 1-9] An example of a configuration different from the semiconductor device 10G described above is shown in FIG. 4A. The semiconductor device 10H shown in FIG. 4A has a transistor 20D and a transistor 30B. FIG. 4A shows a schematic cross-sectional view of the transistor 20D and the transistor 30B in the channel length direction. The semiconductor device 10H is mainly different from the semiconductor device 10G in that the semiconductor device 10H does not have the conductive layer 312a and the conductive layer 312b.

[0191] The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through openings provided in the insulating layer 135, the insulating layer 103, the insulating layer 110, and the insulating layer 118. The conductive layer 320a functions as one of a source electrode and a drain electrode of the transistor 30B, and the conductive layer 320b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 312a and the conductive layer 312b, the manufacturing cost can be reduced.

[0192] [Configuration Example 1-10] An example of a configuration different from the semiconductor device 10E described above is shown in FIG. 4B. The semiconductor device 10I shown in FIG. 4B has a transistor 20E and a transistor 30B. FIG. 4B shows a schematic cross-sectional view of the transistor 20E and the transistor 30B in the channel length direction. The semiconductor device 10I is mainly different from the semiconductor device 10E in that the semiconductor device 10I has a conductive layer 105 instead of the conductive layer 153.

[0193] In the transistor 20E, the conductive layer 105 has a region overlapping with the semiconductor layer 108, the insulating layer 110, and the conductive layer 112 with the insulating layer 135 and the insulating layer 103 interposed therebetween. In the transistor 20E, the conductive layer 105 functions as a first gate electrode (back gate electrode). The insulating layer 135 and the insulating layer 103 function as a first gate insulating layer. In this case, the conductive layer 112 functions as a second gate electrode (top gate electrode), and the insulating layer 110 functions as a second gate insulating layer.

[0194] For example, the transistor 20E can increase the current that can flow in an on state by applying the same potential to the conductive layer 112 and the conductive layer 105. The transistor 20E can also apply a potential to one of the conductive layer 112 and the conductive layer 105 for controlling a threshold voltage and apply a potential to the other for controlling the on state and off state of the transistor 20E. The electrical characteristics of the transistor 20E can also be stabilized by electrically connecting one of the conductive layer 112 and the conductive layer 105 to the source.

[0195] The conductive layer 105 can be made of a material that can be used for the semiconductor layer 308. Furthermore, the conductive layer 105 preferably contains a second element. For example, the conductive layer 105 preferably contains crystalline silicon and one or more elements selected from boron, aluminum, gallium, indium, phosphorus, arsenic, antimony, and bismuth. Furthermore, the conductive layer 105 preferably contains the same second element as the region 308n. Since the conductive layer 105 and the region 308n can be manufactured through the same process, manufacturing costs can be reduced and production yields can be increased.

[0196] 4B shows an example in which the end of the conductive layer 105 is roughly aligned with the end of the conductive layer 112; however, one embodiment of the present invention is not limited to this example. The end of the conductive layer 105 may be located outside the end of the conductive layer 112. Alternatively, the end of the conductive layer 105 may be located inside the end of the conductive layer 112.

[0197] [Configuration Example 1-11] An example of a configuration different from the semiconductor device 10E described above is shown in FIG. 5. The semiconductor device 10J shown in FIG. 5 has a transistor 20F and a transistor 30B. FIG. 5 shows a schematic cross-sectional view of the transistor 20F and the transistor 30B in the channel length direction. The semiconductor device 10J differs from the semiconductor device 10E mainly in that the semiconductor device 10J has a conductive layer 107 instead of the conductive layer 153.

[0198] In the transistor 20F, the conductive layer 107 has a region overlapping with the semiconductor layer 108, the insulating layer 110, and the conductive layer 112 with the insulating layer 133, the insulating layer 135, and the insulating layer 103 interposed therebetween. In the transistor 20F, the conductive layer 107 functions as a first gate electrode (back gate electrode). The insulating layers 133, 135, and 103 function as a first gate insulating layer. At this time, the conductive layer 112 functions as a second gate electrode (top gate electrode), and the insulating layer 110 functions as a second gate insulating layer.

[0199] For example, the transistor 20F can increase the current that can flow in an on state by applying the same potential to the conductive layer 112 and the conductive layer 107. In the transistor 20F, a potential for controlling a threshold voltage can be applied to one of the conductive layer 112 and the conductive layer 107, and a potential for controlling the on state and off state of the transistor 20F can be applied to the other. Furthermore, the electrical characteristics of the transistor 20F can be stabilized by electrically connecting one of the conductive layer 112 and the conductive layer 107 to the source.

[0200] The conductive layer 107 and the conductive layer 315 can each be formed using a material that can be used for the conductive layer 112. The conductive layer 107 and the conductive layer 315 are preferably formed using the same material. The conductive layer 107 and the conductive layer 315 are preferably formed by processing the same conductive film. By processing the same conductive film, the manufacturing cost can be reduced and the production yield can be increased.

[0201] 5 shows an example in which the end portions of the conductive layer 107 are roughly aligned with the end portions of the conductive layer 112; however, this is not limited to this embodiment of the present invention. The end portions of the conductive layer 107 may be positioned outside the end portions of the conductive layer 112. Alternatively, the end portions of the conductive layer 107 may be positioned inside the end portions of the conductive layer 112.

[0202] <Configuration example 2> An example of a configuration different from the above-described semiconductor device 10 to semiconductor device 10J will be described.

[0203] [Configuration Example 2-1] 6A shows a schematic cross-sectional view of the semiconductor device 12. The semiconductor device 12 includes a transistor 22 and a transistor 30. In FIG 6A, a schematic cross-sectional view of the transistor 22 and the transistor 30 in the channel length direction is shown.

[0204] The transistor 22 includes a semiconductor layer 108, an insulating layer 110, and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode. The transistor 22 is a so-called bottom-gate transistor in which a gate electrode is provided under the semiconductor layer 108. For example, a metal oxide can be suitably used as the semiconductor layer 108. Compared with the above-described top-gate transistor 20, the bottom-gate transistor 22 requires fewer manufacturing steps, and the manufacturing cost of the semiconductor device 12 can be reduced.

[0205] The transistor 22 has a conductive layer 120a and a conductive layer 120b over the region 108n. The conductive layer 120a and the conductive layer 120b each have a region in contact with the region 108n. The conductive layer 120a serves as one of a source electrode and a drain electrode of the transistor 22, and the conductive layer 120b serves as the other of the source electrode and drain electrode.

[0206] The transistor 30 includes a semiconductor layer 308, an insulating layer 135, and a conductive layer 306. The insulating layer 135 functions as a gate insulating layer. The conductive layer 306 functions as a gate electrode. The transistor 30 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 308. The semiconductor layer 308 can be preferably made of, for example, silicon.

[0207] The semiconductor device 12 includes an insulating layer 118 that covers the transistor 22 and the transistor 30. The insulating layer 118 functions as a protective insulating layer for the transistor 22 and the transistor 30.

[0208] [Configuration Example 2-2] An example of a configuration different from the semiconductor device 12 described above is shown in Fig. 6B. The semiconductor device 12A shown in Fig. 6B has a transistor 22 and a transistor 30. Fig. 6B shows a schematic cross-sectional view of the transistor 22 and the transistor 30 in the channel length direction. The semiconductor device 12A differs from the semiconductor device 12 mainly in that the semiconductor device 12A does not have an insulating layer 103d.

[0209] The conductive layer 112 functioning as the gate electrode of the transistor 22 has a region in contact with the insulating layer 103c. The conductive layers 312a and 312b functioning as the source and drain electrodes of the transistor 30 have regions in contact with the insulating layer 103c. By not providing the insulating layer 103d, the manufacturing cost of the semiconductor device 12A can be reduced.

[0210] 6B shows an example in which the insulating layer 103 has a three-layer structure of insulating layers 103a, 103b, and 103c, but one embodiment of the present invention is not limited to this. The insulating layer 103 preferably has the insulating layer 103b and the insulating layer 103c over the insulating layer 103b, and may have a structure without the insulating layer 103a. For example, the insulating layer 103 can have a two-layer structure of the insulating layer 103b and the insulating layer 103c.

[0211] [Configuration Example 2-3] An example of a configuration different from the semiconductor device 12 described above is shown in Fig. 6C. The semiconductor device 12B shown in Fig. 6C has a transistor 22 and a transistor 30. Fig. 6C shows a schematic cross-sectional view of the transistor 22 and the transistor 30 in the channel length direction. The semiconductor device 12B differs from the semiconductor device 12 mainly in that the semiconductor device 12B does not have the conductive layer 312a and the conductive layer 312b.

[0212] The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through openings provided in the insulating layer 135, the insulating layer 103, and the insulating layer 110. The conductive layer 320a functions as one of a source electrode and a drain electrode of the transistor 30, and the conductive layer 320b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 312a and the conductive layer 312b, the manufacturing cost can be reduced.

[0213] [Configuration Example 2-4] An example of a configuration different from the semiconductor device 12B described above is shown in Fig. 7A. The semiconductor device 12C shown in Fig. 7A has a transistor 22A and a transistor 30. Fig. 7A shows a schematic cross-sectional view of the transistor 22A and the transistor 30 in the channel length direction. The semiconductor device 12C differs from the semiconductor device 12B mainly in that it has a conductive layer 106 instead of the conductive layer 112 and does not have the insulating layer 110.

[0214] In the transistor 22A, the conductive layer 106 has a region overlapping with the semiconductor layer 108 with the insulating layer 103 interposed therebetween. In the transistor 22A, the conductive layer 106 functions as a gate electrode. The insulating layer 103 functions as a gate insulating layer.

[0215] It is preferable that the insulating layer 103d is provided on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, and the semiconductor layer 108 is provided in contact with the insulating layer 103d. By configuring the insulating layer 103d containing an oxide or an oxynitride to be in contact with the semiconductor layer 108, oxygen deficiency (V O ) or V O H can be reduced.

[0216] The conductive layer 106 and the conductive layer 306 can each be formed using a material that can be used for the conductive layer 112. Furthermore, the conductive layer 106 and the conductive layer 306 are preferably formed using the same material. Furthermore, the conductive layer 106 and the conductive layer 306 are preferably formed by processing the same conductive film. By processing and forming the conductive layer 106 and the conductive layer 306 using the same conductive film, manufacturing costs can be reduced and production yields can be increased.

[0217] [Configuration Example 2-5] An example of a configuration different from the semiconductor device 12B described above is shown in Fig. 7B. The semiconductor device 12D shown in Fig. 7B has a transistor 22B and a transistor 30. Fig. 7B shows a schematic cross-sectional view of the transistor 22B and the transistor 30 in the channel length direction. The semiconductor device 12D differs from the semiconductor device 12B mainly in that it has a conductive layer 105 instead of the conductive layer 112 and does not have the insulating layer 110.

[0218] In the transistor 22B, the conductive layer 105 has a region overlapping with the semiconductor layer 108 with the insulating layer 135 and the insulating layer 103 interposed therebetween. In the transistor 22B, the conductive layer 105 functions as a gate electrode. The insulating layer 135 and the insulating layer 103 function as a gate insulating layer.

[0219] It is preferable that the insulating layer 103d is provided on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, and the semiconductor layer 108 is provided in contact with the insulating layer 103d. By configuring the insulating layer 103d containing an oxide or an oxynitride to be in contact with the semiconductor layer 108, oxygen deficiency (V O ) or V O H can be reduced.

[0220] [Configuration Example 2-6] An example of a configuration different from the semiconductor device 12C described above is shown in FIG. 8A. The semiconductor device 12E shown in FIG. 8A has a transistor 22A and a transistor 30B. FIG. 8A shows a schematic cross-sectional view of the transistor 22A and the transistor 30B in the channel length direction. The semiconductor device 12E is mainly different from the semiconductor device 12C in that it has a conductive layer 315 and an insulating layer 133.

[0221] The transistor 30B includes a conductive layer 315 and an insulating layer 133. The conductive layer 315 has a region overlapping with the semiconductor layer 308, the insulating layer 135, and the conductive layer 306 with the insulating layer 133 interposed therebetween. In the transistor 30B, the conductive layer 315 functions as a first gate electrode (back gate electrode). The insulating layer 133 functions as a first gate insulating layer. In this case, the conductive layer 306 functions as a second gate electrode (top gate electrode), and the insulating layer 135 functions as a second gate insulating layer.

[0222] For example, the transistor 30B can increase the current that can flow in an on state by applying the same potential to the conductive layer 306 and the conductive layer 315. In addition, the transistor 30B can apply a potential to one of the conductive layer 306 and the conductive layer 315 for controlling a threshold voltage, and apply a potential to the other for controlling the on state and off state of the transistor 30B. Furthermore, the electrical characteristics of the transistor 30B can be stabilized by electrically connecting one of the conductive layer 306 and the conductive layer 315 to the source.

[0223] 8A shows an example in which the end of the conductive layer 315 roughly coincides with the end of the conductive layer 306; however, one embodiment of the present invention is not limited to this. The end of the conductive layer 315 may be located outside the end of the conductive layer 306. Alternatively, the end of the conductive layer 315 may be located inside the end of the conductive layer 306.

[0224] [Configuration Example 2-7] An example of a configuration different from the semiconductor device 12E described above is shown in FIG. 8B. The semiconductor device 12F shown in FIG. 8B has a transistor 22C and a transistor 30B. FIG. 8B shows a schematic cross-sectional view of the transistor 22C and the transistor 30B in the channel length direction. The semiconductor device 12F is mainly different from the semiconductor device 12E in that it has a conductive layer 107 instead of the conductive layer 106.

[0225] In the transistor 22C, the conductive layer 107 has a region overlapping with the semiconductor layer 108 with the insulating layer 133, the insulating layer 135, and the insulating layer 103 interposed therebetween. In the transistor 22C, the conductive layer 107 functions as a gate electrode. The insulating layer 133, the insulating layer 135, and the insulating layer 103 function as gate insulating layers.

[0226] The conductive layer 107 and the conductive layer 315 can each be formed using a material that can be used for the conductive layer 112. The conductive layer 107 and the conductive layer 315 are preferably formed using the same material. The conductive layer 107 and the conductive layer 315 are preferably formed by processing the same conductive film. By processing the same conductive film, the manufacturing cost can be reduced and the production yield can be increased.

[0227] <Configuration example 3> An example of a configuration different from the semiconductor devices 10 to 10J and the semiconductor devices 12 to 12F described above will be described.

[0228] [Configuration Example 3-1] 9A shows a schematic cross-sectional view of the semiconductor device 14. The semiconductor device 14 includes a transistor 20 and a transistor 34. In FIG 9A, a schematic cross-sectional view of the transistor 20 and the transistor 34 in the channel length direction is shown.

[0229] The transistor 20 includes a semiconductor layer 108, an insulating layer 110, and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode. The transistor 20 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 108. For example, a metal oxide can be suitably used as the semiconductor layer 108. The above description of the transistor 20 can be referred to for the transistor 20, and detailed description thereof will be omitted.

[0230] The transistor 34 includes a semiconductor layer 308, an insulating layer 135, and a conductive layer 306. The insulating layer 135 functions as a gate insulating layer. The conductive layer 306 functions as a gate electrode. The transistor 34 is a so-called bottom-gate transistor in which a gate electrode is provided under the semiconductor layer 308. The semiconductor layer 308 can be preferably made of, for example, silicon.

[0231] The transistor 34 has a conductive layer 317a and a conductive layer 317b over the region 308n. The conductive layer 317a and the conductive layer 317b each have a region in contact with the region 308n. The conductive layer 317a serves as one of a source electrode and a drain electrode of the transistor 34, and the conductive layer 317b serves as the other of the source electrode and drain electrode.

[0232] The semiconductor device 14 includes an insulating layer 103, an insulating layer 110, and an insulating layer 118 which cover the semiconductor layer 308, the insulating layer 135, the conductive layer 306, the conductive layer 317a, and the conductive layer 317b. The insulating layer 103, the insulating layer 110, and the insulating layer 118 function as protective insulating layers for the transistor 34.

[0233] The insulating layer 103 can be described above, and therefore a detailed description thereof will be omitted.

[0234] A conductive layer 312a and a conductive layer 312b are provided on the insulating layer 110. The conductive layer 312a and the conductive layer 312b are electrically connected to the region 308n through openings provided in the insulating layer 110 and the insulating layer 103, respectively.

[0235] The conductive layer 312a and the conductive layer 312b can be formed using a material that can be used for the conductive layer 112. The conductive layer 312a, the conductive layer 312b, and the conductive layer 112 are preferably formed using the same material. The conductive layer 312a, the conductive layer 312b, and the conductive layer 112 are preferably formed by processing the same conductive film. By processing the same conductive film, the manufacturing cost can be reduced and the production yield can be increased.

[0236] A conductive layer 320a and a conductive layer 320b are provided on the insulating layer 118. The conductive layer 320a and the conductive layer 320b are electrically connected to the conductive layer 312a or the conductive layer 312b, respectively, through an opening provided in the insulating layer 118. Fig. 9A shows an example in which the conductive layer 320a is electrically connected to the region 308n through the conductive layer 312a, and the conductive layer 320b is electrically connected to the region 308n through the conductive layer 312b.

[0237] It is preferable that the insulating layer 103d is provided on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, and the semiconductor layer 108 is provided in contact with the insulating layer 103d. By configuring the insulating layer 103d containing an oxide or an oxynitride to be in contact with the semiconductor layer 108, oxygen deficiency (V O ) or V O H can be reduced.

[0238] [Configuration Example 3-2] An example of a configuration different from the above-described semiconductor device 14 is shown in FIG. 9B. The semiconductor device 14A shown in FIG. 9B has a transistor 20 and a transistor 34A. FIG. 9B shows a schematic cross-sectional view of the transistor 20 and the transistor 34A in the channel length direction. The semiconductor device 14A differs from the semiconductor device 14 mainly in that the semiconductor device 14A does not have the conductive layer 317a and the conductive layer 317b.

[0239] The conductive layer 312a and the conductive layer 312b are electrically connected to the region 308n through openings provided in the insulating layer 103 and the insulating layer 110, respectively. The conductive layer 312a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 312b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 317a and the conductive layer 317b, the manufacturing cost can be reduced.

[0240] [Configuration Example 3-3] An example of a configuration different from the semiconductor device 14A described above is shown in FIG. 9C. The semiconductor device 14B shown in FIG. 9C has a transistor 20 and a transistor 34A. FIG. 9C shows a schematic cross-sectional view of the transistor 20 and the transistor 34A in the channel length direction. The semiconductor device 14B is mainly different from the semiconductor device 14A in that the semiconductor device 14B does not have the conductive layer 312a and the conductive layer 312b.

[0241] The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through openings provided in the insulating layer 103, the insulating layer 110, and the insulating layer 118. The conductive layer 320a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 320b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 312a and the conductive layer 312b, the manufacturing cost can be reduced.

[0242] [Configuration Example 3-4] An example of a configuration different from the semiconductor device 14A described above is shown in FIG. 10A. The semiconductor device 14C shown in FIG. 10A includes a transistor 20C and a transistor 34A. FIG. 10A shows a schematic cross-sectional view of the transistor 20C and the transistor 34A in the channel length direction. The semiconductor device 14C differs from the semiconductor device 14A mainly in that it includes a conductive layer 153 and an insulating layer 137, and in that it includes a conductive layer 353a and a conductive layer 353b instead of the conductive layer 312a and the conductive layer 312b.

[0243] As for the transistor 20C, the above description can be referred to, and therefore a detailed description thereof will be omitted.

[0244] The conductive layer 353a and the conductive layer 353b are each electrically connected to the region 308n through an opening provided in the insulating layer 103. The conductive layer 353a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 353b functions as the other of the source electrode and drain electrode.

[0245] The conductive layer 153, the conductive layer 353a, and the conductive layer 353b can each be formed using a material that can be used for the conductive layer 112. The conductive layer 153, the conductive layer 353a, and the conductive layer 353b are preferably formed using the same material. The conductive layer 153, the conductive layer 353a, and the conductive layer 353b are preferably formed by processing the same conductive film. By processing and forming the conductive layer from the same conductive film, manufacturing costs can be reduced and production yields can be increased.

[0246] [Configuration Example 3-5] An example of a configuration different from the semiconductor device 14C described above is shown in FIG. 10B. The semiconductor device 14D shown in FIG. 10B has a transistor 20C and a transistor 34A. FIG. 10B shows a schematic cross-sectional view of the transistor 20C and the transistor 34A in the channel length direction. The semiconductor device 14D is mainly different from the semiconductor device 14C in that it does not have an insulating layer 103d.

[0247] The conductive layer 153 functioning as a first gate electrode (backgate electrode) of the transistor 20C has a region in contact with the insulating layer 103c. The conductive layers 353a and 353b functioning as a source electrode and a drain electrode of the transistor 34A have regions in contact with the insulating layer 103c. The semiconductor device 14D does not include the insulating layer 103d, thereby reducing manufacturing costs.

[0248] 10B shows an example in which the insulating layer 103 has a three-layer structure of insulating layers 103a, 103b, and 103c, but one embodiment of the present invention is not limited to this. The insulating layer 103 preferably has the insulating layer 103b and the insulating layer 103c over the insulating layer 103b, and may have a structure without the insulating layer 103a. For example, the insulating layer 103 can have a two-layer structure of the insulating layer 103b and the insulating layer 103c.

[0249] [Configuration Example 3-6] An example of a configuration different from the semiconductor device 14C described above is shown in FIG. 10C. The semiconductor device 14E shown in FIG. 10C has a transistor 24 and a transistor 34A. FIG. 10C shows a schematic cross-sectional view of the transistor 24 and the transistor 34A in the channel length direction. The semiconductor device 14E differs from the semiconductor device 14C mainly in that it does not have the insulating layer 137, that it has a conductive layer 105 instead of the conductive layer 153, and that it has a conductive layer 312a and a conductive layer 312b instead of the conductive layer 353a and the conductive layer 353b.

[0250] Regarding the transistor 24, the above description of the transistor 20E can be referred to, and therefore a detailed description thereof will be omitted.

[0251] The conductive layer 312a and the conductive layer 312b are electrically connected to the region 308n through openings provided in the insulating layer 103 and the insulating layer 110. The conductive layer 312a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 312b functions as the other of the source electrode and drain electrode.

[0252] The conductive layer 312a and the conductive layer 312b can be formed using a material that can be used for the conductive layer 112. The conductive layer 112, the conductive layer 312a, and the conductive layer 312b are preferably formed using the same material. The conductive layer 112, the conductive layer 312a, and the conductive layer 312b are preferably formed by processing the same conductive film. By processing the same conductive film, the manufacturing cost can be reduced and the production yield can be increased.

[0253] [Configuration Example 3-7] An example of a configuration different from the semiconductor device 14E described above is shown in Fig. 11A. The semiconductor device 14F shown in Fig. 11A has a transistor 24 and a transistor 34A. Fig. 11A shows a schematic cross-sectional view of the transistor 24 and the transistor 34A in the channel length direction. The semiconductor device 14F differs from the semiconductor device 14E mainly in that the semiconductor device 14F does not have the conductive layer 312a and the conductive layer 312b.

[0254] Regarding the transistor 24 and the transistor 34A, the above description can be referred to, so detailed description thereof will be omitted.

[0255] [Configuration Example 3-8] An example of a configuration different from the semiconductor device 14E described above is shown in FIG. 11B. The semiconductor device 14G shown in FIG. 11B has a transistor 24A and a transistor 34A. FIG. 11B shows a schematic cross-sectional view of the transistor 24A and the transistor 34A in the channel length direction. The semiconductor device 14G is mainly different from the semiconductor device 14E in that the semiconductor device 14G has a conductive layer 106 instead of the conductive layer 105.

[0256] Regarding the transistor 24A, the above description of the transistor 20D can be referred to, and therefore a detailed description thereof will be omitted.

[0257] [Configuration Example 3-9] An example of a configuration different from the semiconductor device 14G described above is shown in FIG. 11C. The semiconductor device 14H shown in FIG. 11C has a transistor 24A and a transistor 34A. FIG. 11C shows a schematic cross-sectional view of the transistor 24A and the transistor 34A in the channel length direction. The semiconductor device 14H is mainly different from the semiconductor device 14G in that the semiconductor device 14H does not have the conductive layer 312a and the conductive layer 312b.

[0258] Regarding the transistor 24A and the transistor 34A, the above description can be referred to, and therefore a detailed description thereof will be omitted.

[0259] <Configuration Example 4> An example of a configuration different from the above-described semiconductor devices 10 to 10J, semiconductor devices 12 to 12F, and semiconductor devices 14 to 14H will be described.

[0260] [Configuration Example 4-1] 12A shows a schematic cross-sectional view of the semiconductor device 16. The semiconductor device 16 has a transistor 22 and a transistor 34. In FIG 12A, a schematic cross-sectional view of the transistor 22 and the transistor 34 in the channel length direction is shown.

[0261] The transistor 22 includes a semiconductor layer 108, an insulating layer 110, and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode. The transistor 22 is a so-called bottom-gate transistor in which a gate electrode is provided under the semiconductor layer 108. For example, a metal oxide can be suitably used as the semiconductor layer 108. The above description of the transistor 22 can be referred to for the transistor 22, and detailed description thereof will be omitted.

[0262] The transistor 34 includes a semiconductor layer 308, an insulating layer 135, and a conductive layer 306. The insulating layer 135 functions as a gate insulating layer. The conductive layer 306 functions as a gate electrode. The transistor 34 is a so-called bottom-gate transistor in which a gate electrode is provided under the semiconductor layer 308. For example, silicon can be suitably used as the semiconductor layer 308. The above description of the transistor 34 can be referred to for the transistor 34, and detailed description thereof will be omitted.

[0263] The semiconductor device 16 includes an insulating layer 118 that covers the transistor 22 and the transistor 34. The insulating layer 118 functions as a protective insulating layer for the transistor 22 and the transistor 34.

[0264] [Configuration Example 4-2] An example of a configuration different from the above-described semiconductor device 16 is shown in Fig. 12B. The semiconductor device 16A shown in Fig. 12B has a transistor 22 and a transistor 34. Fig. 12B shows a schematic cross-sectional view of the transistor 22 and the transistor 34 in the channel length direction. The semiconductor device 16A mainly differs from the semiconductor device 16 in that it does not have an insulating layer 103d.

[0265] The conductive layer 112 functioning as the gate electrode of the transistor 22 has a region in contact with the insulating layer 103c. The conductive layers 312a and 312b have a region in contact with the insulating layer 103c. The semiconductor device 16A does not include the insulating layer 103d, thereby reducing manufacturing costs.

[0266] 12B shows an example in which the insulating layer 103 has a three-layer structure of insulating layers 103a, 103b, and 103c, but one embodiment of the present invention is not limited to this. The insulating layer 103 preferably has the insulating layer 103b and the insulating layer 103c over the insulating layer 103b, and may have a structure without the insulating layer 103a. For example, the insulating layer 103 can have a two-layer structure of the insulating layer 103b and the insulating layer 103c.

[0267] [Configuration Example 4-3] An example of a configuration different from the semiconductor device 16 described above is shown in Fig. 12C. The semiconductor device 16B shown in Fig. 12C has a transistor 22 and a transistor 34A. Fig. 12C shows a schematic cross-sectional view of the transistor 22 and the transistor 34A in the channel length direction. The semiconductor device 16B differs from the semiconductor device 16 mainly in that the semiconductor device 16B does not have the conductive layer 317a and the conductive layer 317b.

[0268] The conductive layer 312a and the conductive layer 312b are each electrically connected to the region 308n through an opening provided in the insulating layer 103. The conductive layer 312a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 312b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 317a and the conductive layer 317b, the manufacturing cost can be reduced.

[0269] [Configuration Example 4-4] An example of a configuration different from the semiconductor device 16B described above is shown in Fig. 13A. The semiconductor device 16C shown in Fig. 13A has a transistor 22 and a transistor 34A. Fig. 13A shows a schematic cross-sectional view of the transistor 22 and the transistor 34A in the channel length direction. The semiconductor device 16C differs from the semiconductor device 16B mainly in that the semiconductor device 16C does not have the conductive layer 312a and the conductive layer 312b.

[0270] The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through openings provided in the insulating layer 103 and the insulating layer 110, respectively. The conductive layer 320a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 320b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 312a and the conductive layer 312b, the manufacturing cost can be reduced.

[0271] [Configuration Example 4-5] An example of a configuration different from the above-described semiconductor device 16 is shown in Fig. 13B. A semiconductor device 16D shown in Fig. 13B has a transistor 26 and a transistor 34. Fig. 13B shows a schematic cross-sectional view of the transistor 26 and the transistor 34 in the channel length direction. The semiconductor device 16D differs from the semiconductor device 16 mainly in that it has a conductive layer 109 instead of the conductive layer 112 and does not have the conductive layer 312a and the conductive layer 312b.

[0272] In the transistor 26, the conductive layer 109 has a region overlapping with the semiconductor layer 108 with the insulating layer 103 interposed therebetween. In the transistor 26, the conductive layer 109 functions as a gate electrode. The insulating layer 103 functions as a gate insulating layer.

[0273] It is preferable that the insulating layer 103d is provided on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, and the semiconductor layer 108 is provided in contact with the insulating layer 103d. By configuring the insulating layer 103d containing an oxide or an oxynitride to be in contact with the semiconductor layer 108, oxygen deficiency (V O ) or V O H can be reduced.

[0274] The conductive layer 109, the conductive layer 317a, and the conductive layer 317b can each be formed using a material that can be used for the conductive layer 112. The conductive layer 109, the conductive layer 317a, and the conductive layer 317b are preferably formed using the same material. The conductive layer 109, the conductive layer 317a, and the conductive layer 317b are preferably formed by processing the same conductive film. By processing and forming the conductive layer from the same conductive film, manufacturing costs can be reduced and production yields can be increased.

[0275] The conductive layer 320a and the conductive layer 320b are electrically connected to the conductive layer 317a and the conductive layer 317b, respectively, through openings provided in the insulating layer 103. The conductive layer 317a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 317b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 312a and the conductive layer 312b, the manufacturing cost can be reduced.

[0276] [Configuration Example 4-6] An example of a configuration different from the semiconductor device 16 described above is shown in FIG. 13C. The semiconductor device 16E shown in FIG. 13C includes a transistor 26A and a transistor 34A. FIG. 13C shows a schematic cross-sectional view of the transistor 26A and the transistor 34A in the channel length direction. The semiconductor device 16E is mainly different from the semiconductor device 16 in that it includes a conductive layer 105 instead of the conductive layer 112 and does not include the conductive layer 317a, the conductive layer 317b, the conductive layer 312a, and the conductive layer 312b.

[0277] In the transistor 26A, the conductive layer 105 has a region overlapping with the semiconductor layer 108 with the insulating layer 103 interposed therebetween. In the transistor 26A, the conductive layer 105 functions as a gate electrode. The insulating layer 103 functions as a gate insulating layer.

[0278] It is preferable that the insulating layer 103d is provided on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, and the semiconductor layer 108 is provided in contact with the insulating layer 103d. By configuring the insulating layer 103d containing an oxide or an oxynitride to be in contact with the semiconductor layer 108, oxygen deficiency (V O ) or V O H can be reduced.

[0279] The conductive layer 320a and the conductive layer 320b are each electrically connected to the region 308n through an opening provided in the insulating layer 103. The conductive layer 320a functions as one of a source electrode and a drain electrode of the transistor 34A, and the conductive layer 320b functions as the other of the source electrode and drain electrode. By not providing the conductive layer 317a, the conductive layer 317b, the conductive layer 312a, and the conductive layer 312b, manufacturing costs can be reduced.

[0280] [Configuration Example 4-7] An example of a configuration different from the semiconductor device 16E described above is shown in Fig. 14. The semiconductor device 16F shown in Fig. 14 has a transistor 26B and a transistor 34A. Fig. 14 shows a schematic cross-sectional view of the transistor 26B and the transistor 34A in the channel length direction. The semiconductor device 16F differs from the semiconductor device 16E mainly in that the semiconductor device 16F has a conductive layer 106 instead of the conductive layer 105.

[0281] In the transistor 26B, the conductive layer 106 has a region overlapping with the semiconductor layer 108 with the insulating layer 135 and the insulating layer 103 interposed therebetween. In the transistor 26B, the conductive layer 106 functions as a gate electrode. The insulating layer 135 and the insulating layer 103 function as gate insulating layers.

[0282] It is preferable that the insulating layer 103d is provided on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, and the semiconductor layer 108 is provided in contact with the insulating layer 103d. By configuring the insulating layer 103d containing an oxide or an oxynitride to be in contact with the semiconductor layer 108, oxygen deficiency (V O ) or V O H can be reduced.

[0283] The conductive layer 106 and the conductive layer 306 can each be formed using a material that can be used for the conductive layer 112. The conductive layer 106 and the conductive layer 306 are preferably formed using the same material. The conductive layer 106 and the conductive layer 306 are preferably formed by processing the same conductive film. By processing and forming the conductive layer from the same conductive film, manufacturing costs can be reduced and production yields can be increased.

[0284] (Embodiment 2) In this embodiment mode, a more specific structure example and a manufacturing method of the semiconductor device described in the above embodiment mode will be described.

[0285] <Configuration Example 5> [Configuration Example 5-1] 15A is a schematic cross-sectional view of a semiconductor device 600. The semiconductor device 600 includes a top-gate transistor 620 and a top-gate transistor 630. FIG 15A shows a schematic cross-sectional view of the transistor 620 and the transistor 630 in the channel length direction. Note that the semiconductor device 600 corresponds to the semiconductor device 10E described in the first embodiment.

[0286] The transistor 620 includes a semiconductor layer 108, an insulating layer 110, an insulating layer 137, a conductive layer 112, a conductive layer 153, an insulating layer 118, and the like. The conductive layer 153 has a region that overlaps with the semiconductor layer 108 with the insulating layer 137 interposed therebetween. The conductive layer 112 has a region that overlaps with the semiconductor layer 108 with the insulating layer 110 interposed therebetween.

[0287] In the transistor 620, the conductive layer 153 functions as a first gate electrode (bottom gate electrode), and the conductive layer 112 functions as a second gate electrode (top gate electrode). Part of the insulating layer 137 functions as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.

[0288] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 153 functions as a channel formation region. Note that for ease of description, the portion of the semiconductor layer 108 overlapping with the conductive layer 112 may be referred to as a channel formation region hereinafter; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 153.

[0289] The conductive layer 112 may be electrically connected to the conductive layer 153 through an opening (not shown) provided in the insulating layer 110 and the insulating layer 137. This allows the conductive layer 112 and the conductive layer 153 to be applied with the same potential.

[0290] Note that the conductive layer 153 and the conductive layer 112 may not be electrically connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 620 may be applied to the other of the pair of gate electrodes. In this case, the threshold voltage when the transistor 620 is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0291] The insulating layer 137 can have a stacked structure. Since the above description can be referred to for the insulating layer 137, detailed description thereof will be omitted.

[0292] Note that in the case where a metal film or an alloy film which is unlikely to diffuse into the insulating layer 137 is used for the conductive layer 153, the insulating layer 137 may have a single-layer structure.

[0293] In the semiconductor device of one embodiment of the present invention, planarization treatment is not required in the manufacturing process of the transistor 620 and the transistor 630. Alternatively, the semiconductor device of one embodiment of the present invention does not need to have a planarization film. By not performing the planarization treatment or not providing a planarization film, manufacturing costs can be reduced and production yields can be increased.

[0294] 15A illustrates a configuration in which the transistor 620 and the transistor 630 do not have an overlapping region. It is preferable that at least the conductive layer 306 and the conductive layer 112 do not have an overlapping region. When the transistor 620 and the transistor 630 have an overlapping region, the coverage may be poor during the manufacture of the transistor 620 due to unevenness of the transistor 630. By using a configuration in which the transistor 620 and the transistor 630 do not have an overlapping region, a decrease in coverage during the manufacture of the transistor 620 can be suppressed.

[0295] The conductive layers 353a, 353b, and 153 can be formed by processing the same conductive film; however, when planarization treatment is not performed or a planarization film is not provided in the manufacturing process of the transistor 620 and the transistor 630, the heights of the conductive layers 353a and 353b may be different from that of the conductive layer 153. Similarly, the conductive layers 120a, 120b, 320a, and 320b can be formed by processing the same conductive film; however, the heights of the conductive layers 120a and 120b may be different from that of the conductive layers 320a and 320b.

[0296] 15A illustrates a structure in which the transistor 620 and the transistor 630 do not overlap with each other; however, this is not a limitation of one embodiment of the present invention. The transistor 620 and the transistor 630 may overlap with each other. By having an overlapping region between the transistor 620 and the transistor 630, the area of ​​the semiconductor device 600 occupied by the transistor 620 and the transistor 630 can be reduced, and the semiconductor device 600 can be made smaller. For example, when the semiconductor device 600 is used in a display device, the area of ​​the transistor 620 and the transistor 630 occupied in a pixel can be reduced, and a high-definition display device can be provided. Furthermore, the area of ​​a driver circuit portion can be reduced, and a display device with a small frame can be provided.

[0297] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described.

[0298] Oxygen vacancies formed in the channel formation region of the semiconductor layer 108 affect transistor characteristics and are problematic. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies and they can become carrier sources. When a carrier source is generated in the channel formation region, the electrical characteristics of the transistor 620 fluctuate, typically causing a shift in the threshold voltage. Therefore, it is preferable that the oxygen vacancies in the region 108i, which is the channel formation region, are as small as possible.

[0299] Thus, in one embodiment of the present invention, an insulating film in the vicinity of a channel formation region of the semiconductor layer 108, specifically, the insulating layer 110 located above the channel formation region and the insulating layer 137 located below the channel formation region, includes an oxide film or an oxynitride film. By transferring oxygen from the insulating layer 137 and the insulating layer 110 to the channel formation region by heat or the like during a manufacturing process, oxygen vacancies in the channel formation region can be reduced.

[0300] The semiconductor layer 108 preferably has a region in which the atomic ratio of In to the element M is greater than 1. The higher the In content, the more the field-effect mobility of the transistor can be improved.

[0301] Here, in the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is weaker than that between Ga and oxygen, so when the In content is high, oxygen vacancies are likely to form in the metal oxide film. The same tendency is observed when element M is used instead of Ga. When many oxygen vacancies exist in the metal oxide film, the electrical characteristics and reliability of the transistor are deteriorated.

[0302] However, in one embodiment of the present invention, a metal oxide material with a high In content can be used because an extremely large amount of oxygen can be supplied to the channel formation region of the semiconductor layer 108 containing a metal oxide. As a result, a transistor having extremely high field-effect mobility, stable electrical characteristics, and high reliability can be realized.

[0303] For example, metal oxides in which the atomic ratio of In to element M is 1.5 or more, or 2 or more, or 3 or more, or 3.5 or more, or 4 or more can be suitably used.

[0304] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is preferably In:M:Zn=4:2:3 or close to it. Alternatively, the atomic ratio of In, M, and Zn is preferably In:M:Zn=5:1:6 or close to it. Furthermore, the composition of the semiconductor layer 108 may be such that the atomic ratio of In, element M, and Zn in the semiconductor layer 108 is approximately equal. That is, the semiconductor layer 108 may contain a material in which the atomic ratio of In, element M, and Zn is In:M:Zn=1:1:1 or close to it.

[0305] For example, a display device with a narrow frame width (also called a narrow frame) can be provided by using the above-mentioned transistor with high field-effect mobility in a gate driver that generates a gate signal. Also, a display device with a small number of wirings connected to the display device can be provided by using the above-mentioned transistor with high field-effect mobility in a source driver (particularly, a demultiplexer connected to an output terminal of a shift register of the source driver).

[0306] Even if the semiconductor layer 108 has a region in which the atomic ratio of In to the element M is greater than 1, the field-effect mobility may be reduced if the semiconductor layer 108 has high crystallinity. The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD) or a transmission electron microscope (TEM).

[0307] Here, the channel formation region of the semiconductor layer 108 has a low impurity concentration and a low defect state density (reduced oxygen vacancies), so that the carrier concentration in the film can be reduced. A transistor using such a metal oxide film for a channel formation region of the semiconductor layer rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a transistor using such a metal oxide film can have an extremely small off-current.

[0308] When a metal oxide film with high crystallinity is used for the semiconductor layer 108, damage during processing of the semiconductor layer 108 or during deposition of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, when a metal oxide film with relatively low crystallinity is used for the semiconductor layer 108, electrical conductivity is improved, and a transistor with high field-effect mobility can be realized.

[0309] The semiconductor layer 108 is preferably made of a metal oxide film having a c-axis aligned crystal (CAAC) structure, a metal oxide film having a nano crystal (nc) structure, or a metal oxide film having a mixture of the CAAC structure and the nc structure, as described below.

[0310] The semiconductor layer 108 may have a laminated structure of two or more layers.

[0311] For example, a semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked can be used. For example, when an In-M-Zn oxide is used, it is preferable to stack two or more films formed from a sputtering target in which the atomic ratio of In, element M, and Zn is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn=1:3:2, or a ratio close to these values.

[0312] A stack of two or more metal oxide films having different crystallinity can be used for the semiconductor layer 108. In that case, it is preferable to use the same oxide target and to form the films under different film formation conditions in succession without exposure to air.

[0313] In this case, the semiconductor layer 108 may have a stacked structure of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, the semiconductor layer 108 may have a stacked structure of a metal oxide film having an nc structure and a metal oxide film having an nc structure. Note that the description of CAC (Cloud-Aligned Composite) can be used for the function or material configuration of a metal oxide that can be suitably used for the metal oxide film.

[0314] For example, the oxygen flow rate ratio during deposition of the first metal oxide film is set to be larger than the oxygen flow rate ratio during deposition of the second metal oxide film. By increasing the oxygen flow rate during deposition of the first metal oxide film, oxygen can be effectively supplied to the insulating layer 103d. The oxygen supplied to the insulating layer 103d diffuses into the semiconductor layer 108 by the process of applying heat, and oxygen vacancies (V O ) can be reduced. Furthermore, if excess oxygen is present at the interface between the insulating layer 110 functioning as a gate insulating layer and the semiconductor layer 108, reliability may be deteriorated. By reducing the oxygen flow rate during deposition of the second metal oxide film, an increase in excess oxygen at the interface between the insulating layer 110 functioning as a gate insulating layer and the semiconductor layer 108 can be suppressed, and reliability can be improved.

[0315] More specifically, the oxygen flow ratio during the formation of the first metal oxide film is set to 5% to 100%, preferably 10% to 80%, more preferably 15% to 70%, more preferably 20% to 70%, more preferably 25% to 60%, more preferably 30% to 60%, more preferably 30% to 50%, and typically 40%. The oxygen flow ratio during the formation of the second metal oxide film is lower than the oxygen flow ratio during the formation of the first metal oxide film, and is set to 5% to 70%, preferably 5% to 60%, more preferably 5% to 50%, more preferably 5% to 40%, more preferably 10% to 40%, more preferably 15% to 40%, more preferably 20% to 40%, and typically 30%. Alternatively, the deposition gas used during the formation of the first metal oxide film may be set to a condition in which oxygen is not used. The conditions such as pressure, temperature, and power during film formation may be different between the first metal oxide film and the second metal oxide film, but it is preferable to make the conditions other than the oxygen flow rate ratio the same, since this can shorten the time required for the film formation process.

[0316] With such a structure, the transistor 620 can have excellent electrical characteristics and high reliability.

[0317] 15A, the transistor 620 may include a conductive layer 120a and a conductive layer 120b over an insulating layer 118. The conductive layer 120a functions as one of a source electrode and a drain electrode, and the conductive layer 120b functions as the other of the source electrode and the drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108n through an opening 141a and an opening 141b provided in the insulating layer 118, respectively.

[0318] The transistor 630 is provided over the substrate 102 and includes a semiconductor layer 308, an insulating layer 135, an insulating layer 133, a conductive layer 315, a conductive layer 306, and the like. The conductive layer 315 has a region that overlaps with the semiconductor layer 308 with the insulating layer 133 interposed therebetween. The conductive layer 306 has a region that overlaps with the semiconductor layer 308 with the insulating layer 135 interposed therebetween.

[0319] In the transistor 630, the conductive layer 315 functions as a first gate electrode (bottom gate electrode), and the conductive layer 306 functions as a second gate electrode (top gate electrode). Part of the insulating layer 133 functions as a first gate insulating layer, and part of the insulating layer 135 functions as a second gate insulating layer.

[0320] A portion of the semiconductor layer 308 overlapping with at least one of the conductive layer 306 and the conductive layer 315 functions as a channel formation region. Note that for ease of description, the portion of the semiconductor layer 308 overlapping with the conductive layer 306 will be referred to as a channel formation region in some cases below; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 306 but overlaps with the conductive layer 315.

[0321] The conductive layer 306 may be electrically connected to the conductive layer 315 through an opening (not shown) provided in the insulating layer 135 and the insulating layer 133. This allows the conductive layer 306 and the conductive layer 315 to be applied with the same potential.

[0322] Note that the conductive layer 306 and the conductive layer 315 may not be electrically connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 630 may be applied to the other of the pair of gate electrodes. In this case, the threshold voltage when the transistor 630 is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0323] 15A, the transistor 630 includes a conductive layer 353a and a conductive layer 353b over an insulating layer 103. The conductive layer 353a functions as one of a source electrode and a drain electrode, and the conductive layer 353b functions as the other of the source electrode and the drain electrode. The conductive layer 353a and the conductive layer 353b are electrically connected to the region 308n through an opening 343a and an opening 343b provided in the insulating layer 103 and the insulating layer 135, respectively.

[0324] The transistor 630 includes a conductive layer 320a and a conductive layer 320b over an insulating layer 118. The conductive layer 320a and the conductive layer 320b are electrically connected to a conductive layer 353a and a conductive layer 353b through an opening 341a and an opening 341b provided in the insulating layer 118, the insulating layer 110, and the insulating layer 137, respectively.

[0325] In the following, a configuration example of a transistor having a configuration partially different from that of the above-mentioned configuration example 5-1 will be described. Note that in the following, the description of the parts that overlap with the above-mentioned configuration example 5-1 may be omitted. Also, in the drawings shown below, the parts having the same functions as the above-mentioned configuration examples may be hatched with the same pattern and may not be labeled with a reference symbol.

[0326] [Configuration Example 5-2] An example of a configuration different from the above-described semiconductor device 600 is shown in FIG. 15B. The semiconductor device 600A shown in FIG. 15B includes a transistor 620A and a transistor 630A. FIG. 15B shows a schematic cross-sectional view of the transistor 620A and the transistor 630A in the channel length direction. The semiconductor device 600A is mainly different from the semiconductor device 600 in that the conductive layer 153, the conductive layer 353a, and the conductive layer 353b have a stacked structure.

[0327] An enlarged view of a region P surrounded by a dashed line in Fig. 15B is shown in Fig. 16A. An enlarged view of a region Q surrounded by a dashed line in Fig. 15B is shown in Fig. 16B.

[0328] Each of the conductive layers 353a and 353b has a stacked structure of a conductive layer 353A and a conductive layer 353B over the conductive layer 353A. The conductive layer 153 has a stacked structure of a conductive layer 153A and a conductive layer 153B over the conductive layer 153A.

[0329] The conductive layer 153A and the conductive layer 353A can be formed using a material that can be used for the conductive layer 112. In the openings 343a and 343b, the conductive layer 353A having a region in contact with the insulating layer 103b is preferably formed using a material that has particularly low hydrogen permeability. By using a material with low hydrogen permeability for the conductive layer 353A, it is possible to prevent hydrogen contained in the insulating layer 103b from diffusing into the semiconductor layer 108 through the openings 343a and 343b.

[0330] The conductive layer 153B and the conductive layer 353B can be formed using any of the materials that can be used for the conductive layer 112.

[0331] The conductive layer 153A and the conductive layer 353A are preferably made of the same material. The conductive layer 153A and the conductive layer 353A are preferably formed by processing the same conductive film. The conductive layer 153B and the conductive layer 353B are preferably made of the same material. The conductive layer 153B and the conductive layer 353B are preferably formed by processing the same conductive film. By processing the same conductive film to form them, the manufacturing cost can be reduced and the production yield can be increased.

[0332] [Configuration Example 5-3] FIG. 17A shows an example of a configuration different from the semiconductor device 600 described above. The semiconductor device 600B shown in FIG. 17A includes a transistor 620B and a transistor 630B. FIG. 17A shows a schematic cross-sectional view of the transistor 620B and the transistor 630B in the channel length direction. The semiconductor device 600B is different from the semiconductor device 600 mainly in that the semiconductor device 600B includes a conductive layer 106 instead of the conductive layer 153 and does not include the conductive layer 353a and the conductive layer 353b. The semiconductor device 600B corresponds to the semiconductor device 10H described in the first embodiment.

[0333] The transistor 620B includes a semiconductor layer 108, an insulating layer 110, an insulating layer 103, a conductive layer 112, a conductive layer 106, an insulating layer 118, and the like. The conductive layer 106 has a region that overlaps with the semiconductor layer 108 with the insulating layer 103 interposed therebetween. The conductive layer 112 has a region that overlaps with the semiconductor layer 108 with the insulating layer 110 interposed therebetween.

[0334] In the transistor 620B, the conductive layer 106 functions as a first gate electrode (bottom gate electrode), and the conductive layer 112 functions as a second gate electrode (top gate electrode). Part of the insulating layer 103 functions as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.

[0335] A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of description, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 will be referred to as a channel formation region in some cases below; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106.

[0336] The conductive layer 112 may be electrically connected to the conductive layer 106 through an opening (not shown) provided in the insulating layer 110, the insulating layer 103, and the insulating layer 135. This allows the conductive layer 112 and the conductive layer 106 to be applied with the same potential.

[0337] Note that the conductive layer 106 and the conductive layer 112 may not be electrically connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 620B may be applied to the other. In this case, the threshold voltage when the transistor 620B is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0338] In the transistor 630B, the conductive layer 315 functions as a first gate electrode (bottom gate electrode), and the conductive layer 306 functions as a second gate electrode (top gate electrode). Part of the insulating layer 133 functions as a first gate insulating layer, and part of the insulating layer 135 functions as a second gate insulating layer.

[0339] A portion of the semiconductor layer 308 overlapping with at least one of the conductive layer 306 and the conductive layer 315 functions as a channel formation region. Note that for ease of description, the portion of the semiconductor layer 308 overlapping with the conductive layer 306 will be referred to as a channel formation region in some cases below; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 306 but overlaps with the conductive layer 315.

[0340] The conductive layer 306 may be electrically connected to the conductive layer 315 through an opening (not shown) provided in the insulating layer 135 and the insulating layer 133. This allows the conductive layer 306 and the conductive layer 315 to be applied with the same potential.

[0341] Note that the conductive layer 306 and the conductive layer 315 may not be electrically connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 630B may be applied to the other. In this case, the threshold voltage when the transistor 630B is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0342] 17A, the transistor 630B includes a conductive layer 320a and a conductive layer 320b over an insulating layer 118. The conductive layer 320a functions as one of a source electrode and a drain electrode, and the conductive layer 320b functions as the other of the source electrode and the drain electrode. The conductive layer 320a and the conductive layer 320b are electrically connected to the region 308n through an opening 341a or an opening 341b provided in the insulating layer 118, the insulating layer 110, the insulating layer 103, and the insulating layer 135, respectively.

[0343] In the semiconductor device of one embodiment of the present invention, planarization treatment is not required in the manufacturing process of the transistor 620B and the transistor 630B. The conductive layer 106 and the conductive layer 306 can be formed by processing the same conductive film; however, the heights of the conductive layer 106 and the conductive layer 306 may be different.

[0344] Similarly, the conductive layers 120a, 120b, 320a, and 320b can be formed by processing the same conductive film, but the heights of the conductive layers 120a and 120b, and the heights of the conductive layers 320a and 320b may be different.

[0345] [Configuration Example 5-4] An example of a configuration different from the semiconductor device 600B described above is shown in FIG. 17B. The semiconductor device 600C shown in FIG. 17B includes a transistor 620C and a transistor 630C. FIG. 17B shows a schematic cross-sectional view of the transistor 620C and the transistor 630C in the channel length direction. The semiconductor device 600C is mainly different from the semiconductor device 600B in that the conductive layer 120a, the conductive layer 120b, the conductive layer 320a, and the conductive layer 320b have a stacked structure.

[0346] An enlarged view of a region R surrounded by a dashed line in Fig. 17B is shown in Fig. 18A. An enlarged view of a region S surrounded by a dashed line in Fig. 17B is shown in Fig. 18B.

[0347] Each of the conductive layers 320a and 320b has a stacked structure of a conductive layer 320A and a conductive layer 320B on the conductive layer 320A. Each of the conductive layers 120a and 120b has a stacked structure of a conductive layer 120A and a conductive layer 120B on the conductive layer 120A.

[0348] The conductive layer 120A and the conductive layer 320A can be formed using a material that can be used for the conductive layer 112. In the openings 341a and 341b, the conductive layer 320A having a region in contact with the insulating layer 103b is preferably formed using a material that has low hydrogen permeability. For example, the conductive layer 320A can be formed using one or more selected from tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, and molybdenum. The conductive layer 320A may be formed using an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements. By using a material that has low hydrogen permeability for the conductive layer 320A, it is possible to suppress diffusion of hydrogen contained in the insulating layer 103b into the semiconductor layer 108 through the openings 341a and 341b.

[0349] The conductive layer 120B and the conductive layer 320B can be formed using any of the materials that can be used for the conductive layer 112.

[0350] The conductive layer 120A and the conductive layer 320A are preferably made of the same material. The conductive layer 120B and the conductive layer 320B are preferably made of the same material. In addition, the conductive layer 120A and the conductive layer 320A are preferably formed by processing the same conductive film. The conductive layer 120B and the conductive layer 320B are preferably formed by processing the same conductive film. By processing the same conductive film to form the conductive layer 120a, the conductive layer 120b, the conductive layer 320a, and the conductive layer 320b, the manufacturing cost can be reduced and the production yield can be increased.

[0351] [Configuration Example 5-5] 19A shows a schematic cross-sectional view of a semiconductor device 602. The semiconductor device 602 includes a bottom-gate transistor 622 and a top-gate transistor 632. FIG 19A shows a schematic cross-sectional view of the transistor 622 and the transistor 632 in the channel length direction. Note that the semiconductor device 602 corresponds to the semiconductor device 12E described in Embodiment 1.

[0352] The semiconductor layer 108 can have a stacked structure of two or more layers. For example, the oxygen flow rate ratio during the formation of the first metal oxide film is set to be smaller than the oxygen flow rate ratio during the formation of the second metal oxide film. Alternatively, the first metal oxide film is formed under conditions that oxygen is not allowed to flow. This allows oxygen to be effectively supplied during the formation of the second metal oxide film. In addition, the first metal oxide film can be a film with lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, by making the second metal oxide film provided in the upper portion a film with higher crystallinity than the first metal oxide film, damage during the formation of the conductive layer 120a and the conductive layer 120b can be suppressed.

[0353] More specifically, the oxygen flow ratio during the formation of the first metal oxide film is set to 0% or more and less than 70%, preferably 5% or more and less than 60%, more preferably 5% or more and less than 50%, more preferably 5% or more and less than 40%, more preferably 5% or more and less than 30%, more preferably 5% or more and less than 20%, more preferably 5% or more and less than 15%, and typically 10%. The oxygen flow ratio during the formation of the second metal oxide film is higher than the oxygen flow ratio during the formation of the first metal oxide film, and is set to 50% or more and less than 100%, preferably 60% or more and less than 100%, more preferably 80% or more and less than 100%, even more preferably 90% or more and less than 100%, and typically 100%. The conditions during the formation of the first metal oxide film and the second metal oxide film, such as pressure, temperature, and power, may be different, but it is preferable to set the conditions other than the oxygen flow ratio to be the same, since this can shorten the time required for the film formation process.

[0354] With such a structure, the transistor 622 can have excellent electrical characteristics and high reliability.

[0355] [Configuration Example 5-6] An example of a configuration different from the above-described semiconductor device 602 is shown in FIG. 19B. The semiconductor device 602A shown in FIG. 19B includes a transistor 622A and a transistor 632A. FIG. 19B shows a schematic cross-sectional view of the transistor 622A and the transistor 632A in the channel length direction. The semiconductor device 602A is mainly different from the semiconductor device 602 in that the conductive layer 120a, the conductive layer 120b, the conductive layer 320a, and the conductive layer 320b have a stacked structure.

[0356] An enlarged view of a region T surrounded by a dashed line in Fig. 19B is shown in Fig. 20A. An enlarged view of a region U surrounded by a dashed line in Fig. 19B is shown in Fig. 20B.

[0357] Each of the conductive layers 320a and 320b has a stacked structure of a conductive layer 320A and a conductive layer 320B on the conductive layer 320A. Each of the conductive layers 120a and 120b has a stacked structure of a conductive layer 120A and a conductive layer 120B on the conductive layer 120A.

[0358] The conductive layer 120A and the conductive layer 320A can be made of a material that can be used for the conductive layer 112. In the openings 341a and 341b, the conductive layer 320A having a region in contact with the insulating layer 103b is preferably made of a material that has low hydrogen permeability. By using a material with low hydrogen permeability for the conductive layer 320A, it is possible to prevent hydrogen contained in the insulating layer 103b from diffusing into the semiconductor layer 108 through the openings 341a and 341b.

[0359] The conductive layer 120B and the conductive layer 320B can be formed using any of the materials that can be used for the conductive layer 112.

[0360] The conductive layer 120A and the conductive layer 320A are preferably made of the same material. The conductive layer 120B and the conductive layer 320B are preferably made of the same material. In addition, the conductive layer 120A and the conductive layer 320A are preferably formed by processing the same conductive film. The conductive layer 120B and the conductive layer 320B are preferably formed by processing the same conductive film. By processing the same conductive film to form the conductive layer 120a, the conductive layer 120b, the conductive layer 320a, and the conductive layer 320b, the manufacturing cost can be reduced and the production yield can be increased.

[0361] [Configuration Example 5-7] 21A shows a schematic cross-sectional view of the semiconductor device 604. The semiconductor device 604 includes a top-gate transistor 624 and a bottom-gate transistor 634. FIG. 21A shows a schematic cross-sectional view of the transistor 624 and the transistor 634 in the channel length direction. Note that the semiconductor device 604 corresponds to the semiconductor device 14F described in Embodiment 1.

[0362] [Configuration Example 5-8] FIG. 21B shows an example of a configuration different from that of the semiconductor device 604 described above. The semiconductor device 604A shown in FIG. 21B includes a transistor 624A and a transistor 634A. FIG. 21B shows a schematic cross-sectional view of the transistor 624A and the transistor 634A in the channel length direction. The semiconductor device 604A differs from the semiconductor device 604 mainly in that the semiconductor device 604A includes a conductive layer 106 instead of the conductive layer 105. The semiconductor device 604A corresponds to the semiconductor device 14H described in the first embodiment.

[0363] <Production method example> A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the semiconductor device 600 illustrated in the above-described configuration example will be described as an example. In addition, an example in which crystalline silicon is used for the semiconductor layer 308 and metal oxide is used for the semiconductor layer 108 will be described.

[0364] The thin films (insulating film, semiconductor film, conductive film, etc.) that constitute the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0365] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0366] The thin film constituting the semiconductor device can be processed by photolithography or the like. Alternatively, the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like. Also, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0367] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0368] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0369] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0370] [Formation of Conductive Layer 315, Insulating Layer 133, and Semiconductor Layer 308] A conductive film is formed over the substrate 102 and processed by etching to form a conductive layer 315 that functions as a first gate electrode of the transistor 630. At this time, the conductive layer 315 is preferably processed to have a tapered end. This can improve the step coverage of the insulating layer 133 to be formed next. The conductive film is preferably formed by a sputtering method using a sputtering target of a metal or alloy.

[0371] Subsequently, the insulating layer 133 is formed to cover the substrate 102 and the conductive layer 315. The insulating layer 133 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0372] Next, an amorphous film 308a that will become the semiconductor layer 308 is formed to cover the insulating layer 133 (FIG. 22A). For example, amorphous silicon can be used as the amorphous film 308a. The amorphous film 308a can be formed by using a PECVD method, a LPCVD (Low Pressure CVD) method, a sputtering method, or the like.

[0373] Next, the amorphous film 308a is crystallized to form a semiconductor film 308p (FIG. 22B). For example, a solid-phase growth method, laser crystallization, or the like can be used as the crystallization method. For example, a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalytic metal, or the like can be used as the solid-phase growth method. These methods may also be used in combination. For example, after the amorphous film 308a is crystallized using the solid-phase growth method, a semiconductor film 308p with few defects and high crystallinity can be formed by further irradiating it with a laser beam. For example, an excimer laser beam using XeCl, a second harmonic or a third harmonic of a YAG laser, or the like can be used as the laser beam.

[0374] Note that, although an example in which the amorphous film 308a is crystallized to form the crystalline semiconductor film 308p is described here, one embodiment of the present invention is not limited to this. The crystalline semiconductor film 308p may be formed directly on the insulating layer 133. Alternatively, the amorphous film 308a may not be crystallized and may be left as an amorphous film in the subsequent process. A transistor using an amorphous semiconductor can reduce the number of manufacturing steps and the manufacturing cost.

[0375] Next, channel doping is performed on the semiconductor film 308p by adding a low concentration of an impurity element imparting p-type conductivity or an impurity element imparting n-type conductivity. The channel doping may be performed on the entire semiconductor film 308p, or may be selectively performed on a part of the semiconductor film 308p. The impurity element imparting p-type conductivity may be one or more selected from boron, aluminum, and gallium. The impurity element imparting n-type conductivity may be one or more of phosphorus and arsenic. For example, boron is used as the impurity element, and the concentration of boron is 1×10 16 atoms / cm 3 5×10 or more 17 atoms / cm 3 Add the following concentrations:

[0376] Next, the semiconductor film 308p is processed to form island-shaped semiconductor layers 308 (FIG. 22C).

[0377] [Formation of insulating layer 135 and conductive layer 306] An insulating layer 135 is formed to cover the insulating layer 133 and the semiconductor layer 108. The insulating layer 135 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0378] Next, a conductive film is formed over the insulating layer 135 and processed by etching to form a conductive layer 306 that functions as a second gate electrode of the transistor 630 (FIG. 22D). At this time, it is preferable to process the conductive layer 306 so that an end portion thereof has a tapered shape. This can improve the step coverage of the insulating layer 103 to be formed next. The conductive film is preferably formed by a sputtering method using a sputtering target of a metal or alloy.

[0379] By using a conductive film containing copper as the conductive layer 306, wiring resistance can be reduced. For example, when the semiconductor device according to one embodiment of the present invention is applied to a large display device or a display device with high resolution, a conductive film containing copper is preferably used. Even when a conductive film containing copper is used for the conductive layer 306, the insulating layer 103 prevents copper from diffusing toward the semiconductor layer 108, so that a highly reliable transistor can be realized.

[0380] Then, the second element is supplied to the semiconductor layer 308 (FIG. 22E). The second element can be supplied by a plasma ion doping method, an ion implantation method, or the like. In FIG. 22E, the supply of the second element is indicated by an arrow. By supplying the second element using the conductive layer 306 as a mask, a region 308i can be formed in the semiconductor layer 308 in a region overlapping with the conductive layer 306, and a region 308n can be formed in the semiconductor layer 308 in a region not overlapping with the conductive layer 306 in a self-aligned manner (FIG. 23A). Note that an example in which the second element is supplied using the conductive layer 306 as a mask has been described, but one embodiment of the present invention is not limited thereto. A resist mask may be formed over the insulating layer 135 or the conductive layer 306, and the second element may be supplied using the resist mask as a mask. Furthermore, a lightly doped drain (LDD) region may be formed between the region 308i and the region 308n. The LDD region preferably has a lower concentration of the second element than the region 308n. By providing the LDD region, hot carrier degradation can be suppressed.

[0381] Subsequently, a heat treatment or laser light irradiation may be performed. The second element added to the region 308n can be activated by the heat treatment or the laser light irradiation. In addition, the activation treatment can repair defects in the semiconductor layer 308 that occur when the second element is added, and recover the crystallinity.

[0382] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, dry air (CDA: Clean Dry Air) may be used. The heat treatment can be performed using an electric furnace, a rapid thermal annealing (RTA: Rapid Thermal Annealing) device, or the like. By using an RTA device, the heat treatment time can be shortened. The temperature of the heat treatment is preferably 300° C. or higher and lower than the distortion point of the substrate, more preferably 350° C. or higher and 650° C. or lower, more preferably 400° C. or higher and 600° C. or lower, and even more preferably 450° C. or higher and 600° C. or lower. The above upper and lower limits can be combined arbitrarily. Note that the activation treatment does not need to be performed after the addition of the second element. The activation treatment may be performed at any stage after the addition of the second element. In addition, it may be performed together with a later heat treatment or a step in which heat is applied. In addition, the activation treatment may be performed by combining the heat treatment with laser light irradiation.

[0383] [Formation of insulating layer 103, conductive layer 353a, conductive layer 353b, and conductive layer 153] Subsequently, the insulating layer 103 is formed to cover the insulating layer 135 and the conductive layer 306. The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like (FIG. 23B). Here, the insulating layer 103 is formed by stacking insulating layers 103a, 103b, 103c, and 103d. It is particularly preferable that each insulating layer constituting the insulating layer 103 is formed by a PECVD method. The above description can be referred to for the formation of the insulating layer 103, and therefore a detailed description thereof will be omitted.

[0384] Subsequently, heat treatment may be performed. By the heat treatment, hydrogen is diffused from the insulating layer 103c to the semiconductor layer 308, and the hydrogen can terminate (hereinafter also referred to as hydrogenation) dangling bonds of the semiconductor layer 308.

[0385] The heat treatment can be performed in an atmosphere containing hydrogen, a rare gas, or nitrogen. In particular, it is preferable to perform the heat treatment in an atmosphere containing hydrogen. The temperature of the heat treatment is preferably 200° C. or higher and lower than the distortion point of the substrate, more preferably 250° C. or higher and 500° C. or lower, more preferably 300° C. or higher and 450° C. or lower, and even more preferably 350° C. or higher and 450° C. or lower. The above upper and lower limits can be combined arbitrarily. Note that the heat treatment does not have to be performed after the addition of the second element. The heat treatment may be performed at any stage after the addition of the second element. In addition, it may be performed together with a later heat treatment or a step in which heat is applied.

[0386] Next, the insulating layer 103 and the insulating layer 135 are partially removed to form an opening 343a and an opening 343b that reach the region 308n.

[0387] Next, a conductive film is formed over the insulating layer 103 so as to cover the openings 343a and 343b, and the conductive film is processed to form the conductive layers 353a and 353b, and also to form the conductive layer 153 which functions as the first gate electrode of the transistor 620 (FIG. 23C). At this time, it is preferable to process the conductive layers 353a, 353b, and 153 so that their end portions have tapered shapes. This can improve the step coverage of the insulating layer 137 to be formed next.

[0388] [Formation of insulating layer 137] Subsequently, the insulating layer 137 is formed to cover the insulating layer 103, the conductive layer 353a, the conductive layer 353b, and the conductive layer 153 (FIG. 24A). The insulating layer 137 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0389] After the insulating layer 137 is formed, a treatment for supplying oxygen to the insulating layer 137 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 137 by a plasma ion doping method or an ion implantation method.

[0390] [Formation of Semiconductor Layer 108] Next, a metal oxide film 108f that will become the semiconductor layer 108 is formed on the insulating layer 137 (FIG. 24C).

[0391] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. FIG. 24B shows a schematic cross-sectional view of the inside of a sputtering device when the metal oxide film 108f is formed on the insulating layer 137. Also, a target 193 installed inside the sputtering device and a plasma 194 formed below the target 193 are shown. For example, when oxygen gas is used when forming the metal oxide film 108f, oxygen can be suitably supplied into the insulating layer 137. Note that in FIG. 24B, the oxygen supplied to the insulating layer 137 is indicated by an arrow.

[0392] The metal oxide film 108f is preferably a dense film with as few defects as possible. The metal oxide film 108f is preferably a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable to use a metal oxide film having crystallinity as the metal oxide film 108f.

[0393] When forming the metal oxide film 108f, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter, also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with increased on-current can be obtained.

[0394] When the semiconductor layer 108 has a stacked structure, it is preferable to deposit the films successively in the same deposition chamber using the same sputtering target, since this can improve the interface. In particular, the deposition conditions for each metal oxide film may be different in terms of pressure, temperature, power, and the like during deposition, but it is preferable to keep the conditions other than the oxygen flow rate the same, since this can shorten the time required for the deposition process. In addition, when metal oxide films with different compositions are stacked, it is preferable to deposit the films successively without exposing them to the air.

[0395] It is preferable to set the deposition conditions so that the metal oxide film 108f is a metal oxide film having a CAAC structure, a metal oxide film having an nc structure, or a metal oxide film having a mixture of the CAAC structure and the nc structure. Since the deposition conditions under which the metal oxide film to be deposited has a CAAC structure and the deposition conditions under which the metal oxide film has an nc structure vary depending on the composition of the sputtering target used, the substrate temperature, oxygen flow rate ratio, pressure, power, and the like may be appropriately set according to the composition.

[0396] The substrate temperature during deposition of the metal oxide film 108f is preferably from room temperature to 450° C., more preferably from room temperature to 300° C., even more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, when a large glass substrate or a resin substrate is used as the substrate 102, it is preferable to set the substrate temperature to be from room temperature to less than 140° C., as this increases productivity. In addition, by depositing the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced. The above upper and lower limits can be combined arbitrarily.

[0397] Before forming the metal oxide film 108f, it is preferable to perform a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 137, and a treatment for supplying oxygen into the insulating layer 137. For example, a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment can be performed in an atmosphere containing oxygen. By performing a plasma treatment in an atmosphere containing oxygen, for example, an atmosphere containing nitrous oxide gas, oxygen can be supplied to the insulating layer 137. Furthermore, by performing a plasma treatment in an atmosphere containing nitrous oxide gas, organic substances on the surface of the insulating layer 137 can be suitably removed. After such a treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 137 to the air.

[0398] Next, the metal oxide film 108f is processed to form island-shaped semiconductor layers 108 (FIG. 25A).

[0399] The metal oxide film 108f may be processed by using either or both of a wet etching method and a dry etching method. At this time, a part of the insulating layer 110 that does not overlap with the semiconductor layer 108 may be removed. By removing a part of the insulating layer 110, the thickness of the insulating layer 110 in the region that does not overlap with the semiconductor layer 108 becomes thinner than the thickness of the insulating layer 110 in the region that overlaps with the semiconductor layer 108.

[0400] After the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108, heat treatment may be performed to remove hydrogen or water in the metal oxide film 108f or the semiconductor layer 108. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108. The heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, reduce defects, improve crystallinity, etc.).

[0401] By the heat treatment, oxygen can also be supplied from the insulating layer 137 to the metal oxide film 108f or the semiconductor layer 108. In the case where oxygen is supplied from the insulating layer 137, it is preferable to perform the heat treatment before processing into the semiconductor layer 108.

[0402] The temperature of the heat treatment can be typically 150° C. or higher and lower than the strain point of the substrate, or 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower. Note that the heat treatment does not necessarily have to be performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108. The heat treatment may be performed at any stage after the metal oxide film 108f is formed. The heat treatment may also be performed together with a later heat treatment or a step in which heat is applied.

[0403] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, the heat treatment can be performed in the atmosphere containing a rare gas or nitrogen, and then in an atmosphere containing oxygen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, dry air (CDA: Clean Dry Air) can be used. Note that it is preferable that the atmosphere for the heat treatment does not contain hydrogen, water, or the like. By using a gas that has been highly purified to a dew point of −40° C. or less, preferably −60° C. or less, and more preferably −100° C. or less, it is possible to prevent hydrogen, water, or the like from being taken into the semiconductor layer 108 as much as possible. The heat treatment can be performed using an electric furnace, a rapid thermal annealing (RTA: Rapid Thermal Annealing) device, or the like. By using an RTA device, the heat treatment time can be shortened.

[0404] It is preferable to form the insulating layer 110 immediately after forming the semiconductor layer 108. When the surface of the semiconductor layer 108 is exposed, water may be adsorbed onto the surface of the semiconductor layer 108. If water is adsorbed onto the surface of the semiconductor layer 108, hydrogen may diffuse into the semiconductor layer 108 by a subsequent heat treatment or the like, and V O H may be formed. V O Since H can be a carrier generation source, it is preferable that the amount of adsorbed water in the semiconductor layer 108 is small.

[0405] [Formation of insulating layer 110 and conductive layer 112] Subsequently, the insulating layer 110 is formed to cover the insulating layer 137 and the semiconductor layer 108 (FIG. 25B). The insulating layer 110 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0406] Before the insulating layer 110 is formed, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. As a result, impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, and a highly reliable transistor can be realized. This is particularly preferable when the surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating layer 110. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. In addition, it is preferable to perform the plasma treatment and the formation of the insulating layer 110 in succession without exposure to the air.

[0407] Heat treatment may be performed after the insulating layer 110 is formed. By performing the heat treatment, impurities in the insulating layer 110 and adsorbed water on the surface of the insulating layer 110 can be removed. The heat treatment can be performed at a temperature of 200° C. or higher and 400° C. or lower in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas. Note that the heat treatment does not necessarily have to be performed after the insulating layer 110 is formed. The heat treatment may be performed at any stage after the insulating layer 110 is formed. Alternatively, the heat treatment may be performed together with a later heat treatment or a step in which heat is applied.

[0408] After the insulating layer 110 is formed or after the above-mentioned heat treatment for removing hydrogen or water is performed, a treatment for supplying oxygen to the insulating layer 110 may be performed. For example, a plasma treatment or a heat treatment may be performed in an atmosphere containing oxygen. Alternatively, oxygen may be supplied to the insulating layer 110 by a plasma ion doping method, an ion implantation method, or the like. For example, a PECVD apparatus can be suitably used for the plasma treatment. When the insulating layer 110 is formed using a PECVD apparatus, it is preferable to perform a plasma treatment in vacuum successively after the formation of the insulating layer 110. By performing the formation of the insulating layer 110 and the plasma treatment in vacuum successively, productivity can be increased.

[0409] When heat treatment is performed after treatment for supplying oxygen to the insulating layer 110, the heat treatment may be performed after a film (e.g., a metal oxide film) is formed on the insulating layer 110. If heat treatment is performed in a state where the insulating layer 110 is exposed, the oxygen supplied to the insulating layer 110 may be desorbed to the outside of the insulating layer 110. By performing heat treatment after a film (e.g., a metal oxide film) is formed on the insulating layer 110, the oxygen supplied to the insulating layer 110 can be prevented from being desorbed to the outside of the insulating layer 110.

[0410] Next, a conductive film is formed over the insulating layer 110 and processed by etching to form a conductive layer 112 that functions as a second gate electrode of the transistor 620 (FIG. 25B). The conductive film is preferably formed by a sputtering method using a sputtering target of a metal or alloy.

[0411] A wet etching method can be suitably used to form the conductive layer 112. For example, an etchant containing hydrogen peroxide can be used for the wet etching method. For example, an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid can be used. In particular, when a material containing copper is used for the conductive layer 112, an etchant containing phosphoric acid, acetic acid, and nitric acid can be suitably used.

[0412] Next, using the conductive layer 112 as a mask, a first element is supplied to the semiconductor layer 108 through the insulating layer 110 (FIG. 25C). The first element can be supplied by plasma processing, plasma ion doping, ion implantation, or the like. In FIG. 25C, the supply of the first element is indicated by arrows. By supplying the first element using the conductive layer 112 as a mask, a region 108i can be formed in the semiconductor layer 108 in a region overlapping with the conductive layer 112, and a region 108n can be formed in the semiconductor layer 108 in a region not overlapping with the conductive layer 112 in a self-aligned manner (FIG. 26A).

[0413] The first element can be preferably supplied by plasma treatment. When plasma treatment is used, the first element can be supplied by generating plasma in a gas atmosphere containing the first element to be supplied and performing the plasma treatment. As a device for generating plasma, a dry etching device, an ashing device, a plasma CVD device, a high density plasma CVD device, etc. can be used.

[0414] After the first element is supplied, the insulating layer 118 may be formed continuously without exposure to the air. For example, by using a plasma CVD apparatus to supply the first element and form the insulating layer 118, the insulating layer 118 can be formed continuously without exposure to the air after the first element is supplied. By performing the steps continuously, the productivity of the semiconductor device can be improved.

[0415] When performing plasma processing, a gas containing the first element can be used as a gas for supplying the first element. In particular, it is preferable to use a gas containing hydrogen, and the resistance value can be controlled by supplying hydrogen to the region 108n. For example, hydrogen (H2), ammonia (NH3), and silane (SiH4) can be suitably used as the gas containing the first element.

[0416] The substrate temperature during the plasma treatment is preferably from room temperature to 450° C., more preferably from 150° C. to 400° C., and even more preferably from 200° C. to 350° C. By setting the substrate temperature within the above range, the reaction between the material constituting the semiconductor layer 108 and the first element is promoted, and the resistance of the semiconductor layer 108 can be reduced. Note that the above upper and lower limits can be combined arbitrarily.

[0417] The pressure in the processing chamber during plasma processing is preferably 50 Pa or more and 1500 Pa or less, more preferably 100 Pa or more and 1000 Pa or less, more preferably 120 Pa or more and 500 Pa or less, and even more preferably 150 Pa or more and 300 Pa or less. Plasma can be generated stably by setting the pressure within the above range. The above upper limit value and lower limit value can be combined arbitrarily.

[0418] By appropriately selecting the conditions of the plasma treatment, the amount of the first element supplied to the semiconductor layer 108 can be adjusted to control the resistance value. In addition, since the first element is supplied to the semiconductor layer 108 through the insulating layer 110, the thickness of the insulating layer 110 may be adjusted so as to obtain a desired resistance.

[0419] Alternatively, the first element may be supplied by a process utilizing thermal diffusion caused by heating using a gas containing the first element.

[0420] Alternatively, the first element may be supplied by a plasma ion doping method or an ion implantation method. These methods allow the concentration profile in the depth direction to be controlled with high precision by the ion acceleration voltage, dose amount, etc. By using the plasma ion doping method, the productivity can be increased. Furthermore, by using the ion implantation method using mass separation, the purity of the supplied first element can be increased. Furthermore, as the first element, one or more of boron, phosphorus, aluminum, magnesium, and silicon can be preferably used.

[0421] In the supplying process of the first element, it is preferable to control the process conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 110, or at a portion close to the interface in the semiconductor layer 108, or at a portion close to the interface in the insulating layer 110. This makes it possible to supply the first element at an optimal concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0422] When using the plasma ion doping method or the ion implantation method, a gas containing the first element can be used as a gas for supplying the first element. When supplying boron, typically, B2H6 gas or BF3 gas can be used. When supplying phosphorus, typically, PH3 gas can be used. A mixed gas in which these raw material gases are diluted with a rare gas may also be used. Other examples of the gas for supplying the first element include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to gas, and a solid or liquid vaporized by heating may also be used.

[0423] The supply of the first element can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 110 and the semiconductor layer .

[0424] For example, when boron ions are supplied by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 5 kV to 100 kV, preferably 7 kV to 70 kV, and more preferably 10 kV to 50 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 That's it, 3 x 1016 ions / cm 2 It can be in the following range:

[0425] When phosphorus ions are supplied by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 10 kV to 100 kV, preferably 30 kV to 90 kV, and more preferably 40 kV to 80 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 More than 3×10 16 ions / cm 2 It can be in the following range:

[0426] In one embodiment of the present invention, the first element can be supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, damage to the semiconductor layer 108 during the supply of the first element can be reduced, and loss of crystallinity can be suppressed. Therefore, this is preferable in cases where electrical resistance increases due to a decrease in crystallinity.

[0427] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed to cover the insulating layer 110 and the conductive layer 112 (FIG. 26B). The insulating layer 118 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0428] When the insulating layer 118 is formed by the plasma CVD method, if the deposition temperature is too high, depending on the impurities contained in the region 108n, the impurities may diffuse to the surrounding area including the region 108i. As a result, the resistance of the region 108i may decrease, and the resistance of the region 108n may increase. The deposition temperature of the insulating layer 118 is preferably, for example, 150° C. to 400° C., preferably 180° C. to 360° C., and more preferably 200° C. to 250° C. By depositing the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0429] After the insulating layer 118 is formed, a heat treatment may be performed.

[0430] [Formation of Openings 141a, 141b, 341a, and 341b] Next, openings 141a and 141b reaching the region 108n are formed by removing parts of the insulating layer 118 and the insulating layer 110. Furthermore, openings 341a and 341b reaching the conductive layer 353a and the conductive layer 353b are formed by removing parts of the insulating layer 118, the insulating layer 110, and the insulating layer 137.

[0431] [Formation of Conductive Layer 120a, Conductive Layer 120b, Conductive Layer 320a, and Conductive Layer 320b] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a, 141b, 341a, and 341b, and the conductive film is processed to form the conductive layers 120a, 120b, 320a, and 320b (Figure 15A).

[0432] Through the above steps, the semiconductor device 600 can be manufactured.

[0433] <Components of Semiconductor Device> Next, components included in the semiconductor device of this embodiment will be described in detail.

[0434] 〔substrate〕 There are no significant limitations on the material of the substrate 102, but the substrate must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may be used as the substrate 102.

[0435] A flexible substrate may be used as the substrate 102, and the transistor 30 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 30 and the like. The peeling layer can be used to separate a semiconductor device that is partially or entirely completed thereon from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the transistor 30 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0436] [Semiconductor layer 108] A metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, is preferably used for the semiconductor layer 108. By using a metal oxide having an energy gap wider than that of silicon, the off-state current of the transistor can be reduced.

[0437] It is preferable to use a metal oxide having a low carrier concentration for the semiconductor layer 108. In the case of lowering the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. Note that examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0438] In particular, hydrogen contained in metal oxide reacts with oxygen that bonds with metal atoms to form water, which may cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region in the metal oxide, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms to generate electrons that serve as carriers. Therefore, transistors using metal oxides that contain a large amount of hydrogen tend to have normally-on characteristics.

[0439] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for a metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in a metal oxide, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide, instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration".

[0440] Therefore, it is preferable to reduce hydrogen in the metal oxide as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0441] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0442] The semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure, which will be described later. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC structure has the lowest density of defect states.

[0443] In the following, we explain about CAAC (c-axis aligned crystal). CAAC is an example of a crystal structure.

[0444] The CAAC structure is one of the crystal structures of thin films having multiple nanocrystals (crystal regions with a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films having a CAAC structure have the characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface on which it is formed, or the normal direction of the thin film surface.

[0445] CAAC-OS (Oxide Semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that the decrease in electron mobility caused by the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are resistant to heat and have high reliability.

[0446] Here, in crystallography, it is common to take a unit cell with a specific axis as the c-axis for the three axes (crystal axes) of the a-axis, b-axis, and c-axis that constitute the unit cell. In particular, in crystals having a layered structure, it is common to take two axes parallel to the plane direction of the layer as the a-axis and b-axis, and an axis intersecting the layer as the c-axis. A representative example of such a crystal having a layered structure is graphite, which is classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, a crystal of InGaZnO4 having a layered YbFe2O4 type crystal structure can be classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0447] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly identified in an image observed by TEM. The crystal parts included in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals having a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in an image observed by TEM, for example, in an nc-OS film, crystal grain boundaries may not be clearly identified.

[0448] The nc-OS film has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus using X-rays with a diameter larger than that of the crystal parts, no peak indicating a crystal plane is detected in the out-of-plane analysis. When the nc-OS film is subjected to electron beam diffraction (also called selected area electron beam diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal parts, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron diffraction (also known as nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (for example, 1 nm to 30 nm) that is close to or smaller than the size of the crystal part, a circular (ring-shaped) area of ​​high brightness is observed, and multiple spots may be observed within that area.

[0449] The nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film does not have regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier concentration and higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit high field-effect mobility.

[0450] The nc-OS film can be formed by lowering the oxygen flow rate ratio during film formation compared to the CAAC-OS film. Also, the nc-OS film can be formed by lowering the substrate temperature during film formation compared to the CAAC-OS film. For example, the nc-OS film can be formed at a relatively low substrate temperature (for example, 130°C or lower) or without heating the substrate, making it suitable for use on large glass substrates or resin substrates, and improving productivity.

[0451] An example of the crystal structure of a metal oxide will be described. In the following, a metal oxide film formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) will be described as an example. A metal oxide formed by a sputtering method using the above-mentioned target and with a substrate temperature of 100°C or higher and 130°C or lower is likely to have either a crystalline structure of nc (nano crystal) structure or a CAAC structure, or a structure in which these are mixed. On the other hand, a metal oxide formed by a sputtering method with a substrate temperature of room temperature (RT) is likely to have an nc crystalline structure. Note that room temperature (RT) here includes the temperature when the substrate is not heated.

[0452] [Metal oxide composition] A structure of a cloud-aligned composite (CAC)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described below.

[0453] In this specification, etc., the term CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be used. CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0454] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole has a function as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) that become carriers, and the insulating function is a function of not flowing electrons that become carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0455] CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0456] In the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

[0457] CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are caused to flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force in the on state of the transistor, that is, a large on-current and a high field effect mobility can be obtained.

[0458] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0459] The above is a description of the components.

[0460] <Laser processing equipment> Next, a laser processing apparatus that can be used in a manufacturing process of a semiconductor device according to one embodiment of the present invention will be described. The laser processing apparatus can irradiate a workpiece with laser light shaped into a linear beam.

[0461] The laser processing apparatus can be used for applications such as irradiating an amorphous film provided on a substrate with laser light to crystallize the amorphous film.

[0462] The laser processing device described here can also be used for separating a substrate by irradiating a structure formed on a substrate via a resin layer with a laser beam, or for a technique for peeling off a substrate, etc. Specifically, the laser beam can be transmitted through the substrate and irradiated onto the resin layer or a layer in the vicinity of the resin layer (e.g., an amorphous silicon layer or a metal layer, etc.).

[0463] For example, a resin layer such as polyimide is provided on a substrate, and a structure is formed on the resin layer. Then, by irradiating the resin layer or the vicinity of the resin layer with laser light that has been transmitted through the substrate, the bonding strength between the substrate and the resin layer is weakened, and the substrate can be separated.

[0464] 27A is a perspective view illustrating the main configuration of the laser processing device. The laser processing device has a moving mechanism 812, a moving mechanism 813, and a stage 815, which are components of an XY stage. In addition, the device has a laser oscillator 820 for forming a linear beam 827, an optical system unit 821, a mirror 822, a condenser lens 823, and the like.

[0465] The moving mechanism 812 and the moving mechanism 813 have a function of performing reciprocating linear motion in the horizontal direction. For example, a ball screw mechanism 816 driven by a motor can be used as a mechanism for powering the moving mechanism 812 and the moving mechanism 813. Since the moving directions of the moving mechanism 812 and the moving mechanism 813 intersect perpendicularly, the stage 815 fixed to the moving mechanism 813 can be freely moved in the X and Y directions.

[0466] The laser oscillator 820 may output light having a wavelength and intensity suitable for the purpose of the processing, and is preferably a pulsed laser, but may also be a CW laser (Continuous wave laser). Typically, an excimer laser capable of irradiating ultraviolet light with a wavelength of 351-353 nm (XeF) or 308 nm (XeCl) may be used. Alternatively, a second harmonic (515 nm, 532 nm, etc.) or third harmonic (343 nm, 355 nm, etc.) of a solid-state laser (YAG laser, fiber laser, etc.) may be used. Also, the laser oscillator 820 may be multiple.

[0467] The optical system unit 821 has, for example, a beam expander, a beam homogenizer, and a cylindrical lens, and can expand the laser light 825 output from the laser oscillator 820 while homogenizing the in-plane distribution of the energy of the laser light 825.

[0468] The mirror 822 may be, for example, a dielectric multilayer mirror, and is set so that the incident angle of the laser light is approximately 45°. The condenser lens 823 may be, for example, a cylindrical lens.

[0469] First, laser light 825 output from laser oscillator 820 enters optical system unit 821. Laser light 826 expanded into a rectangular shape by optical system unit 821 enters mirror 822.

[0470] The laser light 826 reflected by the mirror 822 enters a condenser lens 823 and forms a linear beam 827 at a desired position (height) on the workpiece 840. By moving the stage 815 in the horizontal direction while the linear beam 827 is irradiated onto the workpiece 840 in this manner, a desired area of ​​the workpiece 840 can be laser processed.

[0471] Next, the workpiece 840 and a method for processing it will be described.

[0472] 27B is a diagram illustrating a method of irradiating an amorphous film with a linear beam to crystallize the amorphous film. In FIG. 27B, a glass substrate 841 and an amorphous silicon layer 842 provided on the glass substrate 841 are shown as a workpiece 840.

[0473] The glass substrate 841 side is placed on the stage 815, with the amorphous silicon layer 842 side facing up. The height of the stage and the optical system are adjusted so that the laser light 826 incident on the condenser lens 823 forms a linear beam 827 on the surface on which the amorphous silicon layer 842 is formed or in the vicinity thereof.

[0474] The output of the laser oscillator 820 is set so that the energy density of the linear beam 827 is appropriate, and the stage is moved in the direction of the arrow while irradiating the laser light, whereby a polycrystalline silicon layer 843 can be formed.

[0475] Fig. 27C is a diagram illustrating a method of irradiating a resin layer with a linear beam through a substrate and separating the resin layer from the substrate. Fig. 27C shows a laminate of a glass substrate 845, a resin layer 846, and a structure 847 as a workpiece 840.

[0476] The structure 847 side is placed on the stage 815, with the glass substrate 845 side facing up. The height of the stage, the optical system, and the like are adjusted so that the laser light 826 incident on the condenser lens 823 passes through the glass substrate 845 and forms a linear beam 827 at or near the interface between the glass substrate 845 and the resin layer 846.

[0477] Note that the laser light is preferably a short-wavelength laser light having a relatively high transmittance through the glass substrate because the laser light is irradiated to the processing position through the glass substrate 845. For example, it is preferable to use a laser light having a wavelength in the range of 300 nm to 400 nm.

[0478] The output of the laser oscillator 820 is set so that the energy density of the linear beam 827 is appropriate, and a processed region 848 can be formed by moving the stage in the direction of the arrow while irradiating the laser light.

[0479] Here, in the processed region 848, the resin layer 846 is altered or decomposed due to light or heat at or near the interface between the resin layer 846 and the glass substrate 845. As a result of this phenomenon, the bonding strength between the resin layer 846 and the glass substrate 845 is weakened, and the resin layer 846 can be separated from the glass substrate 845. Note that, at the separation surface, a part of the resin layer 846 may remain on the glass substrate 845 side.

[0480] When the structure includes a display portion (display unit) or the like, a flexible substrate or the like may be further attached to the structure to form a flexible display device.

[0481] Although two applications of the linear beam have been described above, the laser processing device described in this embodiment can also be applied to other applications. The linear beam can be irradiated over a large area by moving it relatively in one axial direction. Therefore, the workpiece can be processed with high throughput.

[0482] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0483] (Embodiment 3) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[0484] <Configuration example> 28A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 bonded together with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided over the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0485] An FPC terminal portion 708 to which an FPC 716 (Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716 via the FPC terminal portion 708 and signal lines 710.

[0486] There may be a plurality of gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0487] The transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 can be the transistors that are the semiconductor device of one embodiment of the present invention.

[0488] Examples of the display element provided in the pixel unit 702 include a liquid crystal element and a light-emitting element. Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element. Examples of the light-emitting element include a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Examples of the light-emitting element include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, and a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type can also be used.

[0489] A display device 700A shown in FIG. 28B is an example of a display device in which a flexible resin layer 743 is applied instead of the first substrate 701 and which can be used as a flexible display.

[0490] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in region P1 in FIG. 28B, the pixel section 702 and the resin layer 743 have cutouts formed by cutting out parts of the pixel section 702 and the resin layer 743. A pair of gate driver circuit sections 706 are provided on both sides of the pixel section 702. The gate driver circuit sections 706 are provided at the corners of the pixel section 702 along the arc-shaped contour.

[0491] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. A portion of the resin layer 743 including the FPC terminal portion 708 can be folded back to the rear side in an area P2 in Fig. 28B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on an electronic device with the FPC 716 overlapping the rear side of the pixel portion 702, thereby saving space in the electronic device.

[0492] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. In this case, the source driver circuit unit 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

[0493] 28C is a display device that can be suitably used in electronic devices having a large screen. The display device 700B can be suitably used in, for example, a television device, a monitor device, a personal computer (including a notebook type or a desktop type), a tablet terminal, a digital signage, and the like.

[0494] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0495] The multiple source driver ICs 721 are each attached to an FPC 723. One terminal of each of the multiple FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0496] On the other hand, the gate driver circuit portion 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0497] With this configuration, a large-sized, high-resolution display device can be realized. For example, a display device with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more can be realized. Also, a display device with an extremely high resolution such as 4K2K or 8K4K resolution can be realized.

[0498] <Cross-section example> A configuration using liquid crystal elements as display elements and a configuration using EL elements will be described below with reference to Figs. 29 to 33. Figs. 29 to 32 are cross-sectional views taken along dashed line QR in Fig. 28A. Fig. 33 is a cross-sectional view taken along dashed line ST in display device 700A shown in Fig. 28B. Figs. 29 and 30 show configurations using liquid crystal elements as display elements, and Figs. 32 and 33 show configurations using EL elements.

[0499] [Description of common parts of the display device] 29 to 33 includes a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The pixel portion 702 includes a transistor 751 and a capacitor 790. The pixel portion 702 included in the display devices shown in FIGS. 32 and 33 further includes a transistor 750. The source driver circuit portion 704 includes a transistor 752. FIG. 30 illustrates a case where the capacitor 790 is not included.

[0500] The transistors 750, 751, and 752 can be any of the transistors described in Embodiment 1. For example, it is preferable that the transistor 751 be an OS transistor, and the transistors 750 and 752 be Si transistors.

[0501] The OS transistor used in this embodiment has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the OS transistor can be reduced. Thus, the retention time of an electric signal such as an image signal can be increased, and the interval between writing of the image signal can be set to be long. Thus, the frequency of a refresh operation can be reduced, which leads to an effect of reducing power consumption.

[0502] The Si transistor used in this embodiment has a relatively high field effect mobility, and therefore can be driven at high speed. For example, by using such a Si transistor capable of high speed driving in a display device, a switching transistor in a pixel section and a driver transistor used in a driving circuit section can be formed on the same substrate. That is, a configuration without using a driving circuit formed from a silicon wafer or the like is possible, and the number of components in the display device can be reduced. Also, by using a Si transistor capable of high speed driving in the pixel section, a high quality image can be provided.

[0503] 29, 31, 32, and 33 includes a lower electrode formed through the same process as the low-resistance region of the semiconductor layer of the transistor 752, and an upper electrode formed through the same process as the second gate electrode. A part of an insulating film functioning as a second gate insulating layer of the transistor 752 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. A wiring obtained by processing the same film as the source electrode and drain electrode of the transistor 752 is connected to the upper electrode.

[0504] Note that a capacitor that can be used in one embodiment of the present invention is not limited to the structure shown in the capacitor 790. The lower electrode and the upper electrode can be a combination of layers having any conductivity. Alternatively, one or a plurality of conductive layers may be provided as electrodes between the upper electrode and the lower electrode, and an insulating film may be provided between the electrodes.

[0505] A planarization insulating film 770 is provided over the transistor 751 , the transistor 752 , and the capacitor 790 .

[0506] The transistor 751 in the pixel portion 702 and the transistor 752 in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the above-described gate driver circuit portion 706 is similar to the source driver circuit portion 704.

[0507] The FPC terminal portion 708 includes a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed using the same conductive film as the source electrode and drain electrode of the transistor 752, and the like.

[0508] 29 to 33, a connection portion 711, a connection portion 713, and a connection portion 715 are shown.

[0509] The connection portion 711 is electrically connected to a first wiring formed by processing the same conductive film as the first gate electrode of the transistor 751 and a second wiring formed by processing the same conductive film as the second gate electrode through a wiring formed by processing the same conductive film as the source electrode and the drain electrode. The first wiring may be electrically connected to the first gate electrode of the transistor 751. The second wiring may be electrically connected to the second gate electrode of the transistor 751.

[0510] The connection portion 713 electrically connects a third wiring formed by processing the same conductive film as the first gate electrode of the transistor 752, a fourth wiring formed by processing the same conductive film as the second gate electrode, and wirings formed by processing the same conductive film as the source electrode and the drain electrode. The third wiring may be electrically connected to the first gate electrode of the transistor 750. The fourth wiring may be electrically connected to the second gate electrode of the transistor 750.

[0511] The connection portion 715 is electrically connected to a fifth wiring formed by processing the same conductive film as the second gate electrode of the transistor 752 and a wiring formed by processing the same conductive film as the source electrode and the drain electrode. The fifth wiring may be electrically connected to the second gate electrode of the transistor 751.

[0512] Note that a connection portion that can be used in one embodiment of the present invention is not limited to the structures shown in the connection portions 711, 713, and 715. The connection portions can be formed by combining any conductive layers.

[0513] A flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 752, etc.

[0514] On the second substrate 705 side, a light-shielding layer 738, a colored layer 736, and an insulating layer 734 in contact with these are provided.

[0515] [Example of the configuration of a display device using a liquid crystal element] A display device 700 shown in FIG. 29 includes a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 751. The conductive layer 772 is formed over a planarization insulating film 770 and functions as a pixel electrode.

[0516] A material that transmits or reflects visible light can be used for the conductive layer 772. For example, an oxide material containing indium, zinc, tin, or the like can be used as the light-transmitting material. For example, a material containing aluminum, silver, or the like can be used as the reflective material.

[0517] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich a liquid crystal element.

[0518] 30 shows an example of a display device 700 using a horizontal electric field (for example, FFS mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0519] 30, a storage capacitor can be formed using a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0520] 29 and 30, an alignment film may be provided in contact with the liquid crystal layer 776. In addition, optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0521] Thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. In addition, when the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0522] The liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0523] A scattering type liquid crystal using a polymer dispersed type liquid crystal or a polymer network type liquid crystal can also be used for the liquid crystal layer 776. In this case, a configuration for performing black and white display without providing the colored layer 736, or a configuration for performing color display using the colored layer 736 can also be used.

[0524] A time-division display method (also called a field sequential driving method) that performs color display based on a time-division additive color mixing method may be applied as a driving method for the liquid crystal element. In this case, the coloring layer 736 may not be provided. When the time-division display method is used, there is an advantage that the aperture ratio of the pixel can be improved and the resolution can be increased because there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue).

[0525] FIG. 31 shows an example in which a liquid crystal element 775 of a horizontal electric field mode (eg, FFS mode) is used, which is different from the display device 700 shown in FIG.

[0526] 31 includes a transistor 751, a transistor 752, a liquid crystal element 767, and the like between a first substrate 701 and a second substrate 705. The first substrate 701 and the second substrate 705 are attached to each other with a sealing layer 732.

[0527] The liquid crystal element 767 includes a conductive layer 761, a liquid crystal layer 765, and a conductive layer 733. The conductive layer 733 is provided over the first substrate 701. One or more insulating layers are provided over the conductive layer 733, and the conductive layer 761 is provided over the insulating layer. The liquid crystal layer 765 is located between the conductive layer 761 and the second substrate 705. The conductive layer 733 is electrically connected to a wiring 764 and functions as a common electrode. The conductive layer 761 is electrically connected to a transistor 751 and functions as a pixel electrode. A common potential is applied to the wiring 764.

[0528] 31 is a liquid crystal element to which a lateral electric field mode (for example, an FFS mode) is applied. The conductive layer 761 has a comb-like shape or a top surface shape having slits. In the liquid crystal element 767, the alignment state of the liquid crystal layer 765 is controlled by an electric field generated between the conductive layer 761 and the conductive layer 733.

[0529] A capacitor 790 functioning as a storage capacitor is formed by a stacked structure of the conductive layer 761, the conductive layer 733, and one or more insulating layers sandwiched between them. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0530] A material that transmits visible light or a material that reflects visible light can be used for the conductive layer 761 and the conductive layer 733. The light-transmitting material can be, for example, an oxide material containing indium, zinc, tin, or the like. The reflective material can be, for example, a material containing aluminum, silver, or the like.

[0531] When a reflective material is used for either or both of the conductive layer 761 and the conductive layer 733, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for both of the conductive layer 761 and the conductive layer 733, the display device 700 becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich a liquid crystal element.

[0532] 31 shows an example of a transmissive liquid crystal display device. A polarizing plate 755 and a light source 757 are provided on the outer side of a first substrate 701, and a polarizing plate 756 is provided on the outer side of a second substrate 705. The light source 757 functions as a backlight.

[0533] A light-shielding layer 738 and a colored layer 736 are provided on the surface of the second substrate 705 facing the first substrate 701. An insulating layer 734 functioning as a planarizing layer is provided to cover the light-shielding layer 738 and the colored layer 736. A spacer 727 is provided on the surface of the insulating layer 734 facing the first substrate 701.

[0534] The liquid crystal layer 765 is located between an alignment film 725 covering the conductive layer 761 and an alignment film 726 covering the insulating layer 734. Note that the alignment films 725 and 726 do not have to be provided if they are not necessary.

[0535] 31, optical members (optical films) such as a retardation film and an anti-reflection film, a protective film, an antifouling film, etc. may be appropriately provided outside the second substrate 705. Examples of the anti-reflection film include an AG (Anti Glare) film and an AR (Anti Reflection) film.

[0536] Thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 765. In addition, when the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0537] The liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0538] A scattering type liquid crystal using a polymer dispersed type liquid crystal, a polymer network type liquid crystal, or the like can be used for the liquid crystal layer 765. In this case, a configuration for performing black and white display without providing the colored layer 736, or a configuration for performing color display using the colored layer 736 can be used.

[0539] A time-division display method (also called a field sequential driving method) that performs color display based on a time-division additive color mixing method may be applied as a driving method for the liquid crystal element. In this case, the coloring layer 736 may not be provided. When the time-division display method is used, there is an advantage that the aperture ratio of the pixel can be improved and the resolution can be increased because there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue).

[0540] 31 has a structure in which an organic insulating film functioning as a planarizing layer is not provided on the formation surface side of the conductive layer 761 functioning as a pixel electrode and the conductive layer 733 functioning as a common electrode. In addition, the wiring 764 and the like can be manufactured in a common manufacturing process with the transistors, liquid crystal elements, and the like without adding a special process. With such a structure, the manufacturing cost can be reduced and the manufacturing yield can be increased, making it possible to provide a highly reliable display device at a low cost.

[0541] [Display device using light-emitting element] 32, a pixel portion 702 includes a transistor 750, a transistor 751, and a capacitor 790. A source driver circuit portion 704 includes a transistor 752.

[0542] The transistors 750, 751, and 752 can be any of the transistors described in Embodiment 1. For example, it is preferable that the transistor 751 be an OS transistor, and the transistors 750 and 752 be Si transistors.

[0543] The display device 700 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0544] Materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, etc. Materials that can be used for the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core-shell type quantum dot materials, core type quantum dot materials, etc.

[0545] 32, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element that has a light-transmitting conductive film 788. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0546] The colored layer 736 is provided at a position overlapping the light-emitting element 782, and the light-shielding layer 738 is provided at a position overlapping the insulating film 730 and in the source driver circuit section 704. The colored layer 736 and the light-shielding layer 738 are covered with an insulating layer 734. The space between the light-emitting element 782 and the insulating layer 734 is filled with a sealing layer 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when the EL layer 786 is formed by coloring, the colored layer 736 may not be provided.

[0547] A configuration of a display device that can be suitably applied to a flexible display is shown in Fig. 33. Fig. 33 is a cross-sectional view of the display device 700A shown in Fig. 28B taken along dashed line ST.

[0548] 33 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744, instead of the first substrate 701 shown in FIG. 32. A transistor 750, a capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.

[0549] The support substrate 745 is a substrate that contains an organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer that contains an organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are attached to each other by an adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0550] A display device 700A shown in Fig. 33 has a protective insulating layer 740 instead of the second substrate 705 shown in Fig. 32. The protective insulating layer 740 is attached to the sealing layer 732. A glass substrate, a resin film, or the like can be used as the protective insulating layer 740. In addition, an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be used as the protective insulating layer 740.

[0551] An EL layer 786 included in the light-emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By creating the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using the colored layer 736. A protective insulating layer 741 is provided to cover the light-emitting element 782. The protective insulating layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective insulating layer 741 is preferably an inorganic insulating film. In addition, a layered structure including one or more inorganic insulating films and one or more organic insulating films is more preferably used.

[0552] FIG. 33 shows a bendable region P2. In the region P2, in addition to the support substrate 745 and the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. By providing as little inorganic insulating film as possible in the bendable region P2 and by using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are laminated, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0553] [Example of configuration in which an input device is provided on a display device] An input device may be provided in the display devices shown in Figures 29 to 33. Examples of the input device include a touch sensor.

[0554] For example, the sensor may be of various types, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, a pressure sensitive type, etc. Alternatively, two or more of these types may be used in combination.

[0555] The touch panel may have a configuration such as an in-cell type touch panel in which an input device is formed between a pair of substrates, a so-called on-cell type touch panel in which an input device is formed on a display device, or an out-cell type touch panel in which the input device is attached to a display device.

[0556] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0557] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0558] (Embodiment 4) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0559] 34A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0560] The transistor of one embodiment of the present invention can be applied to the transistors in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0561] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0562] The driver circuit unit 504 has driver circuits such as a gate driver 504a that outputs scanning signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may have at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b may also be configured using a shift register.

[0563] The terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0564] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 34A is connected to various wirings such as the gate lines GL_1 to GL_X that are wirings between the gate driver 504a and the pixel circuit 501, or the data lines DL_1 to DL_Y that are wirings between the source driver 504b and the pixel circuit 501.

[0565] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel unit 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (e.g., a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0566] The pixel circuits 501 shown in FIG. 34A can have the configurations shown in FIGS. 34B and 34C, for example.

[0567] 34B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0568] The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the multiple pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0569] 34C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0570] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. A current flowing through the light emitting element 572 is controlled in accordance with a potential applied to the gate of the transistor 554, thereby controlling the light emission luminance of the light emitting element 572.

[0571] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0572] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0573] (Embodiment 5) In the following, a pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described. The transistors exemplified in the first embodiment can be applied to the transistors used in the pixel circuits exemplified below.

[0574] <Circuit configuration> 35A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0575] The transistor M1 has a gate connected to the wiring G1, one of its source and drain connected to the wiring S1, and the other of its source and drain connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of its source and drain connected to the wiring S2, and the other of its source and drain connected to the other electrode of the capacitor C1 and the circuit 401.

[0576] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be used.

[0577] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0578] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Also, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed according to the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0579] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistor M1 and the transistor M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period during which the potentials of the nodes are held is short (specifically, when the frame frequency is 30 Hz or more), a transistor including a semiconductor such as silicon may be used.

[0580] <Driving method example> Next, an example of an operation method of pixel circuit 400 will be described with reference to Fig. 35B. Fig. 35B is a timing chart relating to the operation of pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, threshold voltages of transistors, and the like will not be taken into consideration here.

[0581] 35B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0582] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supplies.

[0583] The node N1 is connected to a potential V ref The node N2 is supplied with a first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0584] [Period T2] In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0585] The node N1 receives a second data potential V data At this time, the second data potential V data In response to this, the potential of the node N2 changes by a potential dV. w The potential obtained by adding the second data potential V to the potential dV is input. Note that although the potential dV is shown to be a positive value in FIG. 35B, it may be a negative value. data is the potential V ref It may be lower.

[0586] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential becomes close to

[0587] In this manner, the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including a display element by combining two types of data signals. Therefore, it is possible to perform gray scale correction within the pixel circuit 400.

[0588] The pixel circuit 400 can generate a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. When a liquid crystal element is used, overdrive driving or the like can be realized.

[0589] <Application Examples> [Example using liquid crystal element] The pixel circuit 400LC shown in Fig. 35C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0590] The liquid crystal element LC has one electrode connected to the other electrode of the capacitance C1, the other electrodes of the source and drain of the transistor M2, and one electrode of the capacitance C2, and the other electrode is connected to a potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0591] The capacitor C2 functions as a storage capacitor. Note that the capacitor C2 can be omitted if not required.

[0592] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, it can, for example, realize high-speed display by overdrive driving, apply a liquid crystal material with a high driving voltage, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct the gradation according to the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0593] [Example using light-emitting element] The pixel circuit 400EL shown in Fig. 35D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0594] The transistor M3 has a gate connected to one electrode of the capacitance C2, and one of its source and drain connected to the potential V H The other electrode of the capacitor C2 is connected to a wiring to which a potential V com The light-emitting element EL has the other electrode connected to a wiring that is supplied with a potential V L Connect with the wiring given.

[0595] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if not required.

[0596] In this embodiment, the anode side of the light-emitting element EL is connected to the transistor M3, but the cathode side of the light-emitting element EL may be connected to the transistor M3. H and potential V L You can change the value as appropriate.

[0597] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, thereby realizing, for example, HDR display, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0598] It should be noted that the circuits are not limited to those illustrated in FIGS. 35C and 35D, and may be configured to include additional transistors, capacitors, and the like.

[0599] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0600] (Embodiment 6) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0601] A display module 6000 shown in FIG. 36A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0602] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0603] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately according to the size of the display device 6006.

[0604] The display device 6006 may have a function as a touch panel.

[0605] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0606] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0607] FIG. 36B is a cross-sectional schematic diagram of a display module 6000 with an optical touch sensor.

[0608] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. Also, in an area surrounded by an upper cover 6001 and a lower cover 6002, a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) are provided.

[0609] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guiding portion 6017a and a light guiding portion 6017b.

[0610] Light 6018 emitted from a light-emitting unit 6015 passes through a light-guiding unit 6017a, an upper portion of the display device 6006, and a light-guiding unit 6017b to reach a light-receiving unit 6016. When the light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected.

[0611] A plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. This makes it possible to obtain information on the position where a touch operation has been performed.

[0612] The light emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light receiving unit 6016 may be a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts it into an electric signal. Preferably, a photodiode that can receive infrared light may be used.

[0613] The light guiding portion 6017a and the light guiding portion 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, and it is possible to prevent external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, if a resin that absorbs visible light and transmits infrared light is used, it is possible to more effectively prevent the touch sensor from malfunctioning.

[0614] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0615] (Embodiment 7) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0616] The electronic device 6500 shown in FIG. 37A is a portable information terminal that can be used as a smartphone.

[0617] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0618] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0619] FIG. 37B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0620] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0621] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0622] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0623] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0624] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0625] (Embodiment 8) In this embodiment, electronic devices including a display device manufactured according to one embodiment of the present invention will be described.

[0626] The electronic devices exemplified below each have a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices have high resolution. In addition, the electronic devices can have both high resolution and a large screen.

[0627] The display portion of the electronic device according to one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0628] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0629] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0630] FIG. 38A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0631] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, a shutter button 8004, etc. In addition, a detachable lens 8006 is attached to the camera 8000.

[0632] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0633] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0634] The housing 8001 has a mount having electrodes, and can be connected to a strobe device and the like in addition to the finder 8100 .

[0635] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0636] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0637] The button 8103 has a function such as a power button.

[0638] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0639] FIG. 38B is a diagram showing the external appearance of the head mounted display 8200.

[0640] The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 includes a built-in battery 8206.

[0641] A cable 8205 supplies power from a battery 8206 to a main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes a camera and can use information on the movements of the user's eyeballs and eyelids as an input means.

[0642] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes capable of detecting a current flowing with the movement of the user's eyeball at positions that come into contact with the user. The wearing unit 8201 may also have a function of monitoring the user's pulse rate by the current flowing through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 according to the movement of the user's head.

[0643] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0644] 38C, 38D, and 38E are diagrams showing the external appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0645] A user can view the display on the display unit 8302 through the lens 8305. Note that it is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing another image displayed in a different area of ​​the display unit 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided, with one display unit being provided for each eye of the user.

[0646] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition, so that a user cannot see pixels even when the image is enlarged using a lens 8305 as in FIG. 38E, and a more realistic image can be displayed.

[0647] The electronic device shown in Figures 39A to 39G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0648] The electronic device shown in Fig. 39A to Fig. 39G has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded on a recording medium, etc. The functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have multiple display units. In addition, the electronic device may have a function of providing a camera or the like in the electronic device, taking still images and videos, and storing them in a recording medium (external or built-in to the camera), a function of displaying the taken images on the display unit, etc.

[0649] Details of the electronic device shown in FIGS. 39A to 39G will be described below.

[0650] 39A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

[0651] FIG. 39B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 39B shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, and phone calls, titles of e-mail and SNS, sender names, date and time, time, remaining battery level, and antenna reception strength. Alternatively, icons 9050 and the like may be displayed at the position where the information 9051 is displayed.

[0652] 39C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.

[0653] FIG. 39D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. The charging operation may be performed by wireless power supply.

[0654] 39E, 39F, and 39G are perspective views showing a foldable mobile information terminal 9201. FIG. 39E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 39G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 39F is a perspective view of a state in the middle of changing from one of FIG. 39E and FIG. 39G to the other. The mobile information terminal 9201 has excellent portability in a folded state, and has excellent viewability of the display due to a seamless wide display area in an unfolded state. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0655] 40A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0656] 40A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be appli...

Claims

1. a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer; the first transistor has a first semiconductor layer, a first gate insulating layer, a first gate electrode, a third gate insulating layer, and a third gate electrode; the first semiconductor layer comprises a metal oxide; the first gate electrode has a region overlapping with the first semiconductor layer via the first gate insulating layer; the third gate electrode has a region overlapping with the first semiconductor layer via the third gate insulating layer; the second insulating layer has a region overlapping with the third gate insulating layer via the third gate electrode; the first conductive layer has a region in contact with an upper surface of the first semiconductor layer; the second conductive layer has a region in contact with an upper surface of the first semiconductor layer, the third insulating layer has a region located above the first gate electrode; the first conductive layer has a region in contact with an upper surface of the third insulating layer; the second conductive layer has a region in contact with an upper surface of the third insulating layer; the second transistor has a second semiconductor layer, a second gate insulating layer, and a second gate electrode; the second semiconductor layer comprises crystalline silicon; the second gate electrode has a region overlapping with the second semiconductor layer via the second gate insulating layer; the first insulating layer has a region overlapping with the first transistor via the second insulating layer; the second insulating layer has a region overlapping with the second transistor via the first insulating layer; the first gate electrode has a region overlapping the second insulating layer via the first semiconductor layer; the third conductive layer has a region in contact with an upper surface of the second semiconductor layer, the fourth conductive layer has a region in contact with an upper surface of the second semiconductor layer, the fifth conductive layer is electrically connected to the third conductive layer; the sixth conductive layer is electrically connected to the fourth conductive layer; the fifth conductive layer has a region in contact with an upper surface of the third insulating layer, the sixth conductive layer has a region in contact with an upper surface of the third insulating layer, The second insulating layer has a film density higher than that of the first insulating layer.

2. In claim 1, the second semiconductor layer has a first region and a pair of second regions sandwiching the first region, the first region has a region overlapping with the second gate electrode, the third gate electrode comprises crystalline silicon; The second region and the third gate electrode each contain one or more elements selected from the group consisting of boron, aluminum, gallium, indium, phosphorus, arsenic, antimony, and bismuth.

Images