Data error correction circuit and data transmission circuit

Abstract

A data error correction circuit and a data transmission circuit are provided, the data error correction circuit comprising: a decoding module, an input terminal of which is connected to a data bus, configured to receive first data and a check code of the first data, and output an error correction code of the first data according to the check code; and an error correction latch module, a first input terminal of which is connected to the data bus and a second input terminal of which is connected to an output terminal of the decoding module, configured to latch the first data corresponding to the error correction code, and generate and output second data according to the error correction code and the corresponding first data. In an embodiment of the present invention, one data error correction circuit can perform verification and error correction on odd data and even data transmitted alternately.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on February 24, 2022, bearing application number 202210173543.8 and titled "Data Error Correction Circuit and Data Transmission Circuit", the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the technical field of electronic circuits, and more particularly to a data error correction circuit and a data transmission circuit capable of performing efficient data processing. [Background technology]

[0003] Data error correcting code (ECC) circuits are a technology that can check and correct data errors. By checking the target data using an ECC check code transmitted together with the target data, errors in data transmission as small as one bit can be corrected. Data error correcting circuits are widely used in circuits that must maintain accurate data transmission, such as memories. In a memory, data to be transmitted is usually divided into odd data and even data, which are transmitted alternately. The odd data is sampled with an odd clock and transmitted via an odd data signal line, and the even data is sampled with an even clock and transmitted via an even data signal line. The odd data signal line and the even data signal line are arranged in parallel, and the odd data and the even data are transmitted alternately, thereby avoiding crosstalk between the signal lines and improving the reliability of data transmission.

[0004] In some embodiments, when a data error correction circuit needs to be used to check and correct errors on data to be transmitted, the processing time of the data error correction circuit may be long, so that the even data check or error correction may not be completed before the odd data arrives, or the odd data check or error correction may not be completed before the even data arrives, so that it is necessary to provide a data error correction circuit on each of the odd data signal lines and the even data signal lines. However, the data error correction circuit occupies a relatively large area during layout, so that the area occupied by the entire data transmission circuit during layout is also large.

[0005] In addition, the information disclosed in the above background art section is intended to be used solely for the purpose of deepening understanding of the background of the present invention, and may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention [Problem to be solved by the invention]

[0006] In order to overcome at least to some extent the problem of a large layout area of ​​a data transmission circuit, the present invention aims to provide a data transmission circuit capable of saving layout area and a data transmission method applied to the data transmission circuit.

[0007] The present invention aims to provide a data error correction circuit and a data transmission circuit to overcome, at least to some extent, the problem that a single data error correction circuit cannot process odd and even data transmitted alternately due to limitations and shortcomings in the prior art. [Means for solving the problem]

[0008] According to a first aspect of the present invention, there is provided a data error correction circuit, comprising: a decoding module having an input terminal connected to a data bus, configured to receive first data and a check code of the first data, and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding module, configured to latch the first data corresponding to the error correction code, and to generate and output second data based on the error correction code and the corresponding first data.

[0009] In one exemplary embodiment of the present invention, the error correction latch module includes: a first latch unit, an input terminal of which is connected to the data bus and configured to latch the first data; an error correction unit, an output terminal of which is connected to the output terminal of the first latch unit and the output terminal of the decoding module, configured to perform error correction on the corresponding first data based on the error correction code, and output the error-corrected second data; and a second latch unit, an input terminal of which is connected to the output terminal of the error correction unit, configured to latch and output the second data.

[0010] In one exemplary embodiment of the present invention, the first data includes M-bit data, and the first latch unit includes N L-bit latches (N*L=M, N≧1).

[0011] In one exemplary embodiment of the present invention, N=1, L=M, the first latch unit is a serial output, the decoding module is a serial output, the error correction unit includes an error corrector, an input terminal of the error corrector is connected to an output terminal of the first latch unit, an enable terminal of the error correction unit is connected to an output terminal of the decoding module, and the output timing of the error correction code is the same as the data output timing of the first latch unit.

[0012] In one exemplary embodiment of the present invention, the first latch unit is a parallel output and includes M output terminals, the decoding module is a parallel output and includes M output terminals, the error correction unit includes M error correctors, an enable terminal of each of the error correctors is connected to one output terminal of the decoding module, and an input terminal of each of the error correction units is connected to one output terminal of the first latch unit.

[0013] In one exemplary embodiment of the present invention, the second latch unit includes one M-bit shift register, and the second latch unit is a serial input.

[0014] In an exemplary embodiment of the present invention, the second latch unit includes S (S≧1) K-bit shift registers (S*K=M), and the second latch unit is a parallel input.

[0015] In one exemplary embodiment of the present invention, the first latch unit is connected to a first control unit, and the second latch unit is connected to a second control unit, the first control unit is configured to control the first latch unit to start latching at a time point n+mt, n is a relative delay time, the start time point of the relative delay time is the time when the first data is transmitted to the decoding module, m is a natural number, t is a transmission interval of the first data, n is greater than 0 and less than t, and the second control unit is configured to control the second latch unit to start latching between n+mt and n+(m+1)t.

[0016] In one exemplary embodiment of the present invention, the error corrector comprises an inverter and a transmission tube connected in parallel, input terminals of the inverter and the transmission tube are connected as input terminals of the error corrector, output terminals of the inverter and the transmission tube are connected as output terminals of the error corrector, and enable terminals of the inverter and the transmission tube are both connected to the output terminal of the decoding module.

[0017] In one exemplary embodiment of the present invention, the first latch unit is a serial input or a parallel input.

[0018] In one exemplary embodiment of the present invention, the second latch unit is a serial output or a parallel output.

[0019] In one exemplary embodiment of the present invention, an input terminal of the second control unit is connected to an output terminal of the first control unit.

[0020] According to a second aspect of the present invention, there is provided a data transmission circuit comprising: an odd data signal line for transmitting odd data; and an even data signal line for transmitting even data, the even data and the odd data being transmitted alternately at a time interval, with a first time interval between an arrival time of the even data and an arrival time of the odd data; and a data error correction circuit according to any of the above aspects, having an input terminal connected to the odd data signal line and the even data signal line and an output terminal connected to an output bus, the output bus being electrically connected to a memory block, wherein the data error correction circuit is configured to perform error correction on the odd data or the even data when the odd data or the even data is written to the memory block.

[0021] In one exemplary embodiment of the present invention, the data error correction circuit includes a decoding module and an error correction latch module, the odd data or the even data enters the decoding module at a first time point, and the error correction latch module outputs error-corrected data at a second time point, and an interval between the first time point and the second time point is greater than the first time interval.

[0022] According to a third aspect of the present invention, there is provided a data transmission circuit comprising: a first data signal line for transmitting odd data and even data, the even data and the odd data being transmitted alternately at a time interval, with a first time interval between an arrival time of the even data and an arrival time of the odd data; and a data error correction circuit as in any of the above aspects, having an input terminal connected to the odd data signal line and the even data signal line and an output terminal connected to an output bus, the output bus being electrically connected to a memory block, wherein the data error correction circuit is configured to perform error correction on the odd data or the even data when the odd data or the even data is written to the memory block. Effect of the Invention

[0023] According to the embodiment of the present invention, the data error correction circuit is divided into two parts, a decoding module and an error correction latch module, so that the process of checking and correcting data can be divided into two parts, decoding and error correction, so that the current data can be decoded using the decoding module before the next data arrives, and when the next data is about to arrive, the processing process can be handed over to the error correction latch module, so that the arrival of the next data can avoid interrupting the processing process of the current data or losing the next data. In this way, the embodiment of the present invention realizes the sequential processing of odd data and even data transmitted alternately by one data error correction circuit, and when designing a data transmission circuit, it is possible to omit one channel of data error correction circuit, reduce the layout area occupied by the data transmission circuit, and reduce the power consumption of the entire data transmission circuit.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. [Brief description of the drawings]

[0025] [Figure 1A] FIG. 1 is a schematic diagram of the connections of a data error correction circuit in the prior art; [Figure 1B] 1B is a timing diagram of data processing in the data error correction circuit shown in FIG. 1A. [Diagram 2] FIG. 2 is a schematic diagram of a data error correction circuit structure in an exemplary embodiment of the present invention; [Diagram 3] FIG. 2 is a block diagram of an error correction latch module in one embodiment of the present invention. [Figure 4] FIG. 2 is a circuit diagram of an error correction latch module in one embodiment of the present invention. [Diagram 5] FIG. 13 is a circuit diagram of an error correction latch module in another embodiment of the present invention. [Figure 6] FIG. 4 is a timing diagram of a data latch in one embodiment of the present invention. [Figure 7] FIG. 2 is a schematic diagram of a first control unit and a second control unit in one embodiment of the present invention. [Figure 8] 1 is a schematic diagram of a data transmission circuit in one embodiment of the present invention. [Figure 9] FIG. 4 is a schematic diagram of a data transmission circuit according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The above drawings are incorporated in and constitute a part of this specification, illustrate embodiments in accordance with the present application, and are used together with this specification to explain the principles of the present application. Obviously, the above drawings are only some embodiments of the present invention, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.

[0027] Next, the exemplary embodiments will be described in more detail with reference to the drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as being limited to the examples described herein, but rather, by providing these embodiments, the present invention can be more comprehensive and complete, and the concept of the exemplary embodiments can be fully conveyed to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to fully understand the embodiments of the present invention. However, those skilled in the art will understand that the technical solutions of the present invention can be implemented without one or more specific details described, or can employ other methods, components, devices, steps, etc. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring each aspect of the present invention.

[0028] Furthermore, the drawings are merely schematic diagrams of the present invention, and the same reference numerals in the drawings indicate the same or similar parts, so that the repeated description thereof will be omitted. Some block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in the form of software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0029] Exemplary embodiments of the present invention will now be described in detail with reference to the drawings.

[0030] FIG. 1A is a schematic diagram of the connection relationship of a data error correction circuit in the prior art, and FIG. 1B is a timing diagram of data processing of the data error correction circuit shown in FIG. 1A.

[0031] 1A, in the prior art, odd data EvenData<127:0> and odd data ECC check code EvenParity<8:0> are transmitted on the odd data signal line, and error correction is performed by the odd data error correction unit 11 arranged on the odd data signal line to output the error correction data EvenDataWr<127:0>, and even data OddData<127:0> and even data ECC check code OddParity<8:0> are transmitted on the even data signal line, and error correction is performed by the even data error correction unit 12 arranged on the even data signal line to output the error correction data OddDataWr<127:0>. This is because, in the timing (see FIG. 1B), the transmission periods of the odd data EvenData<127:0> and even data OddData<127:0> are both T, and they are transmitted alternately, with a transmission interval of T / 2. However, since the error correction processing time of the odd data error correction unit 11 or the even data error correction unit 12 is both Tecc, and Tecc>T / 2, one error correction unit cannot process the odd data and even data that arrive alternately within T / 2 time, and two error correction units need to be arranged to process the odd data and the even data respectively.

[0032] FIG. 2 is a schematic diagram of the structure of a data error correction circuit in an exemplary embodiment of the present invention.

[0033] Referring to FIG. 2, the data error correction circuit 200 includes: a decoding module 21, whose input terminal is connected to the data bus, configured to receive the first data and a check code of the first data, and output an error correction code of the first data according to the check code; and an error correction latch module 22, the first input terminal of which is connected to the data bus and the second input terminal of which is connected to the output terminal of the decoding module 21, configured to latch first data corresponding to the error correction code, and generate and output second data based on the error correction code and the corresponding first data.

[0034] In one embodiment of the present invention, the first data is, for example, 128 bits (Bit) and is represented as Data<127:0>. Correspondingly, the check code of the first data may be an ECC check code. If the first data is 128 bits, the ECC check code of the first data may be represented as Parity<8:0>, and each bit of the ECC check code is an XOR result (i.e., row check value) of different row data of the first data, or an XOR result (i.e., column check value) of different column data of the first data. The decoding module 21 generates a corresponding row check value and column check value of the first data according to the ECC check logic, compares the generated row check value and column check value with the row check value and column check value recorded in the ECC check code, and determines a data bit of the first data where an anomaly occurs according to a check code position where the comparison result is inconsistent, and outputs an error correction code of the first data.

[0035] In an embodiment of the present invention, when the first data is 128 bits, the error correction code of the first data is 128-bit data, and each bit in the error correction code indicates whether the corresponding bit in the first data is erroneous or not. For example, when bit 6 of the first data is erroneous, the value of bit 6 in the error correction code is 1, and when bit 0 of the first data is correct, the value of bit 0 in the error correction code is 0. In this case, when the check result of the first data matches the ECC check code, the error correction code of the first data is all 0, and when the check result of the first data does not match the ECC check code, the corresponding bit of the error correction code of the first data is set to 1, and the error correction code takes a different value depending on the position where the error occurs. In another embodiment of the present invention, when the value of the corresponding bit in the first data is 1, it can be set to indicate that the bit is correct, and when the value of the corresponding bit in the first data is 0, it can be set to indicate that the bit is erroneous, and the present invention is not particularly limited thereto.

[0036] The error correction latch module 22 is configured to latch the first data, and perform error correction on the first data according to the error correction code of the first data. Note that the first data is cyclically transmitted within a transmission period corresponding to the first data, so that when the first data enters the decoding module 21 and is checked and calculated by the decoding module 21, if it can be guaranteed that the error correction latch module 22 can latch the first data in one transmission in the transmission period of the first data, the error correction latch module 22 can perform the latch on the first data with a delay, and continue to perform error correction on the currently processed data.

[0037] As can be seen from the above, by separating the error correction code generation step (check step) and the error correction step in data error correction, when the error correction latch module 22 performs error correction processing on the preceding data (either odd data or even data), the decoding module 21 can simultaneously perform checking and decoding on the subsequent data (the other of odd data or even data); in this way, when the subsequent data arrives, the error correction latch module 22 can continue the error correction processing on the preceding data, while the decoding module 21 can process the subsequent data in a timely manner, thereby avoiding the subsequent data being lost or the processing of the current data (preceding data) being interrupted due to the long time required for checking and correcting the error of the preceding data.

[0038] FIG. 3 is a block diagram of an error correction latch module in one embodiment of the present invention.

[0039] Referring to FIG. 3, in one embodiment, the error correction latch module 22 includes: A first latch unit 221, an input terminal of which is connected to the data bus and configured to latch first data; an error correction unit 222 connected to the output terminal of the first latch unit 221 and the output terminal of the decoding module 21, configured to perform error correction on the corresponding first data according to the error correction code, and output error-corrected second data; and a second latch unit 223, the input terminal of which is connected to the output terminal of the error correction unit 222 and configured to latch and output the second data.

[0040] In one embodiment, the first data includes M-bit data, and the first latch unit 221 includes N L-bit latches (N*L=M, N≧1), where M is the number of bits, and M=128 for 128-bit first data.

[0041] The first latch unit 221 may be realized by one or more latches or shift registers.

[0042] FIG. 4 is a circuit diagram of an error correction latch module in one embodiment of the present invention.

[0043] 4, in one embodiment, N=1, L=M, and the first latch unit 221 is implemented by one M-bit shift register. For example, if the first data is 128-bit data, M=128, and the first latch unit 221 is a 128-bit shift register. In this case, the first latch unit 221 is a serial input.

[0044] When the first latch unit 221 is a serial output, it has one output terminal, the data input terminal of the error correction unit 222 is one input terminal, the error correction unit 222 is a serial input, the decoding module 21 is a serial output, the error correction unit 222 is realized by one error corrector 2221, the input terminal of the error corrector 2221 is connected to the output terminal of the first latch unit 221, the enable terminal of the error correction unit 222 is connected to the output terminal of the decoding module 21, and the time when the error correction code Correct<127:0> outputs each bit (bit) data coincides with the time when the first latch unit 221 outputs each bit (bit) data in the data DataPre<127:0>. Furthermore, one set of error correction codes Correct<127:0> can be repeatedly transmitted within a transmission period t (equal to the transmission period t of the first data), and the time when the first latch unit 221 outputs data DataPre<127:0> must coincide with the transmission time of a set of error correction codes of the corresponding first data.

[0045] In the embodiment shown in FIG. 4, the error corrector 2221 comprises an inverter INV and a transmission tube SR connected in parallel, the input terminal of the inverter INV and the input terminal of the transmission tube SR are connected as input terminals of the error corrector 2221, the output terminal of the inverter INV and the output terminal of the transmission tube SR are connected as output terminals of the error corrector 2221, and the enable terminal of the inverter INV and the enable terminal of the transmission tube SR are both connected to the output terminal of the decoding module 21.

[0046] Each bit data in DataPre<127:0> output by the first latch unit 221 corresponds to the corresponding bit of the error correction code Correct<127:0>. When the data of the xth bit of the error correction code Correct<127:0> is 0, the inverter INV is off and the transmission tube SR is on, the xth bit of the output data DataPost<127:0> of the error corrector 2221 is equal to the xth bit of DataPre<127:0>, and no error correction is performed; when the data of the yth bit of the error correction code Correct<127:0> is 0, the inverter INV is on and the transmission tube SR is off, and the yth bit of the output data DataPost<127:0> of the error corrector 2221 is equal to the inverted data of the yth bit of DataPre<127:0>, thereby realizing the bit-wise error correction of DataPre<127:0>, that is, the first data Data<127:0>, where x and y are both natural numbers. The above data bit numbers are merely examples, and in practical applications, the data bit numbers are set according to processing requirements.

[0047] Therefore, when the error correction unit 222 is realized by one error corrector 2221 and has one output terminal, the second latch unit 223 includes one M-bit shift register, and the second latch unit 223 is a serial input. The second latch unit 223 may be a serial output or a parallel output according to the requirements of an external circuit.

[0048] In one embodiment, the first latch unit 221 is connected to a first control unit 224, and the second latch unit 223 is connected to a second control unit 225, where the first control unit 224 outputs a first control signal to control the latch of the first latch unit 221, and the second control unit 225 outputs a second control signal to control the latch of the second latch unit 223.

[0049] FIG. 5 is a circuit diagram of an error correction latch module in another embodiment of the present invention.

[0050] Referring to Fig. 5, in another embodiment, the first latch unit 221 may be parallel output and includes M output terminals, and correspondingly, the decoding module 21 is parallel output and includes M output terminals, and the error correction unit 222 includes M error correctors 2221, and the enable terminal of each error corrector 2221 is connected to one output terminal of the decoding module 21, and the input terminal of each error corrector 2221 is connected to one output terminal of the first latch unit 221. In addition, the second latch unit 223 is parallel input and has M input terminals. The second latch unit 223 can be realized by S K-bit shift registers, where S*K=M, S≧1. The error corrector 2221 is, for example, as shown in Fig. 4.

[0051] Furthermore, the first latch unit 221 may be a serial input or a parallel input, and the second latch unit 2231 may be a serial output or a parallel output.

[0052] Similar to the embodiment shown in FIG. 4, the first latch unit 221 is controlled by a first control signal output by the first control unit 224 to start latching, and the second latch unit 223 is controlled by a second control signal output by the second control unit 225 to start latching.

[0053] FIG. 6 is a timing diagram of a data latch in one embodiment of the present invention.

[0054] 6, in one embodiment, the first data Data<127:0> is odd data or even data that is alternately transmitted, the transmission interval between the odd data and the even data is t, and the transmission of the first data Data<127:0> is completed within the transmission interval t. As can be seen, the transmission interval t is equal to half the transmission period T of the odd data or even data shown in FIG. 1B.

[0055] The first control unit 224 is configured to control the first latch unit 221 to start latching the first data at the first time point T1, where T1 = n + mt, n is the relative delay time, the start point of the relative delay time is the time point T0 when the first data is transmitted to the decoding module 21, 0 < n < t, and m is a natural number. The second control unit 225 is configured to control the second latch unit 223 to start latching at a certain time point between the first time point T1 and the next first time point T1', and the next first time point T1' is T1' = n + (m + 1)t. In the embodiment shown in FIG. 6, m = 1.

[0056] The second latch unit 223 receives and outputs the error-corrected second data DataWr<127:0> from the second time point T2. The time from the time point T0 when the first data Data<127:0> is input to the decoding module 21 to the second time point T2 when the second data DataWr<127:0> is output is the time length Tecc for performing check and error correction on the first data, and Tecc is greater than the transmission period t of the first data. Referring to FIG. 6, before the second time point T2, after t hours have elapsed since the first data 61 arrived at the decoding module 21, that is, when reaching the third time point T3, the next first data 62 enters the decoding module 21, and the decoding module 21 starts to calculate the next first data 62. At this time (the third time point T3), the first latch unit 221 still latches the first data 61 (outputs DataPre<127:0>). After t hours have elapsed and reaching the next third time point T3', the first latch unit 221 latches the next first data 62. When the error correction unit 222 and the second latch unit 223 are serial input / output, more data processing time is required. Therefore, on the premise that the time for the first latch unit 221 to latch the first data 61 is controlled to t to ensure that the next first data 62 can be processed, sufficient data processing time can be given to the error correction unit 222.

[0057] It should be noted that the time when the decoding module 21 outputs the error correction code should be after the first time point T1 and before the third time point T3 when the transmission of the first data is completed (the time from T0 to T3 is t), that is, the time when the decoding module 21 performs checking and decoding does not exceed t at most, so as to ensure that each first data can undergo checking and decoding processing.

[0058] In one embodiment, the first control signal can be used to control the first time T1 at which the first latch unit 221 starts latching the first data to be aligned with the first bit data of the first data, and when the first latch unit 221 is a serial output, the timing at which the first latch unit 221 outputs the data DataPre<127:0> can be controlled to be the same as the timing at which the decoding module 21 outputs the error correction code (the time at which each bit is output). Meanwhile, the second control signal can be used to control the second time T2 at which the second latch unit 223 starts latching to be after the decoding module 21 outputs the error correction code, and in the extreme case, the second time T2 can be controlled to be equal to the time at which the error correction unit 222 starts outputting the data DataPost<127:0>. If the second latch unit 223 is a serial output, the time at which the second latch unit 223 starts latching must also be later than the time at which the decoding module 21 starts outputting the error correction code, because there is a certain delay between when the error correction unit 222 receives the error correction code and when it outputs a bit in DataPost<127:0>.

[0059] FIG. 7 is a schematic diagram of a first control unit and a second control unit in one embodiment of the present invention.

[0060] 7, in one embodiment, the input terminal of the second control unit 225 can be connected to the output terminal of the first control unit 224, the input terminal of the first control unit 225 is configured to receive a latch signal Catch, the first control unit 224 is configured to generate a first control signal according to the latch signal Catch, the second control unit 225 is configured to generate a second control signal according to the first control signal, the first control signal is used to control the first latch unit 221 to start latching, and the second control signal is used to control the second latch unit 223 to start latching. With the excitation of the first control signal and the second control signal, the first latch unit 221 starts latching at a first time point T1, and the second latch unit 223 starts latching between the first time point T1 and the next first time point T1'. Specifically, the first control unit 224 and the second control unit 225 are configured to delay input signals to obtain corresponding output signals, and by adjusting the delays of the first control unit 224 and the second control unit 225, the data output timing (time point when each bit is output) of the first latch unit 221 can be controlled to be the same as the timing (time point when each bit is output) of the decoding module 21 to output the error correction code, and the latch timing of the second latch unit 223 can be controlled to be the same as the timing of the error correction unit 222 to output the data DataPost<127:0>. That is, when the control signal Catch and the first data are input simultaneously, the delay time of the first control unit 224 may be equal to the decoding time of the decoding module 21, and the delay time of the second control unit 225 may be equal to the processing time of the error correction unit 222, i.e., the time difference between the data input and the data output of the error correction unit 222.

[0061] According to an embodiment of the present invention, a data error correction circuit divides the entire ECC operation with an operation time of Tecc into smaller time intervals, and performs checks and error corrections on data with a transmission interval of t (t < Tecc). As a result, using one data error correction circuit, checks and error corrections for alternately transmitted odd data and even data can be realized, and the setting of the data error correction circuit for one channel of the data transmission circuit can be reduced.

[0062] FIG. 8 is a schematic diagram of a data transmission circuit according to an embodiment of the present invention.

[0063] Referring to FIG. 8, in one embodiment, the data transmission circuit 800 includes an odd data signal line 81 for transmitting odd data, an even data signal line 82 for transmitting even data, wherein the even data and the odd data are alternately transmitted with a time interval, and there is a first time interval between the arrival time of the even data and the arrival time of the odd data, the even data signal line 82, a data error correction circuit 83 in the above embodiment, the input terminal of which is connected to the odd data signal line and the even data signal line, and the output terminal of which is connected to the output bus 84, and the output bus is electrically connected to the storage block 85. Here, the data error correction circuit 83 is configured to perform error correction on odd data or even data when the odd data or even data is written into the storage block 85.

[0064] In one embodiment, the data error correction circuit 83 includes a decoding module 831 and an error correction latch module 832. The odd data or even data enters the decoding module 831 at a first time point, and the error correction latch module 832 outputs the data corrected at a second time point. The interval between the first time point and the second time point is larger than the first time interval.

[0065] FIG. 9 is a schematic diagram of a data transmission circuit according to another embodiment of the present invention.

[0066] Referring to FIG. 9, in another embodiment, a data transmission circuit 900 includes: a first data signal line 91 for transmitting odd data and even data, the even data and the odd data being transmitted alternately at time intervals, with a first time interval between the arrival time of the even data and the arrival time of the odd data; The data error correction circuit 92 in the above embodiment may have an input terminal connected to a first data signal line 91 and an output terminal connected to an output bus 93, the output bus 93 being electrically connected to a memory block 94; Here, data error correction circuitry 92 is configured to perform error correction on odd or even data as it is written to storage block 94 .

[0067] The data error correction circuit 92 includes a decoding module 921 and an error correction latch module 922, where odd data or even data enters the decoding module 921 at a first time point, and the error correction latch module 922 outputs error-corrected data at a second time point, and the interval between the first time point and the second time point is greater than a first time interval.

[0068] It should be noted that, although the above detailed description describes several modules or units of an apparatus for performing operations, such division is not essential. In fact, according to an embodiment of the present invention, the features and functions of two or more of the above modules or units can be implemented by one module or unit. Conversely, the features and functions of one of the above modules or units can be further divided and implemented by multiple modules or units.

[0069] Those skilled in the art can easily conceive of other embodiments of the present application after studying the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, applications or adaptations of the present disclosure, which variations, applications or adaptations conform to the general principles of the present disclosure and include common knowledge or conventional technical means in the art that are not disclosed in the present disclosure. The specification and examples are merely exemplary, with the true scope and spirit of the present invention being pointed out in the appended claims. [Industrial Applicability]

[0070] According to the embodiment of the present invention, the data error correction circuit is divided into two parts, a decoding module and an error correction latch module, so that the process of checking and correcting data can be divided into two parts, decoding and error correction, so that the current data can be decoded using the decoding module before the next data arrives, and when the next data is about to arrive, the processing process can be handed over to the error correction latch module, so that the arrival of the next data can avoid interrupting the processing process of the current data or losing the next data. In this way, the embodiment of the present invention realizes the sequential processing of odd data and even data transmitted alternately by one data error correction circuit, and when designing a data transmission circuit, it is possible to omit one channel of data error correction circuit, reduce the layout area occupied by the data transmission circuit, and reduce the power consumption of the entire data transmission circuit.

Claims

1. 1. A data error correction circuit, comprising: a decoding module, the input terminal of which is connected to the data bus and configured to receive first data and a check code of the first data, and to output an error correction code of the first data based on the check code; an error correction latch module, the first input terminal of which is connected to the data bus and the second input terminal of which is connected to an output terminal of the decoding module, configured to latch the first data corresponding to the error correction code, and generate and output second data based on the error correction code and the corresponding first data; The error correction latch module includes: a first latch unit, an input terminal of which is connected to the data bus and configured to latch the first data; an error correction unit, connected to an output terminal of the first latch unit and an output terminal of the decoding module, configured to perform error correction on the corresponding first data according to the error correction code, and output the error-corrected second data; a second latch unit, the input terminal of which is connected to the output terminal of the error correction unit and configured to latch and output the second data; a first control unit connected to the first latch unit and a second control unit connected to the second control unit, the first control unit configured to control the first latch unit to start latching at a time point n+mt, n being a relative delay time, a start time point of the relative delay time being a time when the first data is transmitted to the decoding module, m being a natural number, t being a transmission interval of the first data, n being greater than 0 and less than t, and the second control unit configured to control the second latch unit to start latching between n+mt and n+(m+1)t.

2. The first data includes M-bit data, and the first latch unit includes N L-bit latches (N*L=M, N≧1).

2. The data error correction circuit of claim 1.

3. N=1, L=M, the first latch unit is a serial output, the decoding module is a serial output, the error correction unit includes an error corrector, an input terminal of the error corrector is connected to an output terminal of the first latch unit, an enable terminal of the error correction unit is connected to an output terminal of the decoding module, and an output timing of the error correction code is the same as a data output timing of the first latch unit; 3. The data error correction circuit of claim 2.

4. the first latch unit is a parallel output and includes M output terminals, the decoding module is a parallel output and includes M output terminals, the error correction unit includes M error correctors, an enable terminal of each of the error correctors is connected to one output terminal of the decoding module, and an input terminal of each of the error correction units is connected to one output terminal of the first latch unit; 3. The data error correction circuit of claim 2.

5. The second latch unit includes one M-bit shift register, and the second latch unit is a serial input.

4. The data error correction circuit of claim 3.

6. The second latch unit includes S (S≧1) K-bit shift registers (S*K=M), and the second latch unit has a parallel input.

5. The data error correction circuit of claim 4.

7. the error corrector comprises an inverter and a transmission gate connected in parallel, input terminals of the inverter and the transmission gate are connected as input terminals of the error corrector, output terminals of the inverter and the transmission gate are connected as output terminals of the error corrector, and enable terminals of the inverter and the transmission gate are both connected to an output terminal of the decoding module.

5. A data error correction circuit according to claim 3.

8. The first latch unit is a serial input or a parallel input.

2. The data error correction circuit of claim 1.

9. The second latch unit is a serial output or a parallel output.

9. A data error correction circuit according to claim 1 or 8.

10. an input terminal of the second control unit is connected to an output terminal of the first control unit; 2. The data error correction circuit of claim 1.

11. A data transmission circuit, an odd data signal line for transmitting odd data; an even data signal line for transmitting even data, the even data and the odd data being transmitted alternately at time intervals, and a first time interval being present between an arrival time of the even data and an arrival time of the odd data; and the data error correction circuit according to any one of claims 1 to 6 and 8, wherein an input terminal is connected to the odd data signal line and the even data signal line, and an output terminal is connected to an output bus, and the output bus is electrically connected to a memory block; The data transmission circuit, wherein the data error correction circuit is configured to perform error correction on the odd data or the even data when the odd data or the even data is written to the storage block.

12. The data error correction circuit includes a decoding module and an error correction latch module, the odd data or the even data enters the decoding module at a first time point, and the error correction latch module outputs error-corrected data at a second time point, and an interval between the first time point and the second time point is greater than the first time interval; The data transmission circuit according to claim 11.

13. A data transmission circuit, a first data signal line for transmitting odd data and even data, the even data and the odd data being transmitted alternately at time intervals, and a first time interval being present between the arrival time of the even data and the arrival time of the odd data; and the data error correction circuit according to any one of claims 1 to 6 and 8, having an input terminal connected to the first data signal line and an output terminal connected to an output bus, the output bus being electrically connected to a memory block; The data transmission circuit, wherein the data error correction circuit is configured to perform error correction on the odd data or the even data when the odd data or the even data is written to the storage block.

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