SENSE TIMING GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - Patent application

Abstract

To provide a sense timing generation circuit capable of performing highly reliable operation with reduced influence of a temperature and an increased reading margin, and a semiconductor storage device.SOLUTION: A sense timing generation circuit of an embodiment outputs, from an output terminal, a sense amplifier enable signal which turns a sense amplifier into an enable state based on a clock signal inputted from an input terminal. The sense timing generation circuit includes: a delay circuit part which has temperature characteristics in which a delay amount decreases as a temperature rises, has a plurality of kinds of delay circuits with different temperature characteristics, and delays the clock signal to output the signal as the sense amplifier enable signal; and a connection switching circuit which switches a connection state of the plurality of delay circuits in the delay circuit part extending from the input terminal to the output terminal.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] An embodiment of the present invention relates to a sense timing generation circuit and a semiconductor memory device. [Background technology]

[0002] In a semiconductor memory device, when data is read, the sense amplifier is activated after the bit line reaches a potential sufficient to determine the output of the sense amplifier. At this time, the timing at which the sense amplifier is activated (hereinafter referred to as sense timing) is set so as to absorb the characteristic variations of the transistors used in the sense amplifier and to reliably determine the level of the read signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-055673 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, the change in the potential of the read signal differs depending on the temperature, such as the ambient temperature. If the timing at which the sense amplifier is activated (hereinafter referred to as the sense timing) is the same, when the value of the memory cell is "0", the higher the temperature, the smaller the read margin (the difference between the level of the signal to be read and the level of the reference signal used for judgment), and when the value of the memory cell is "1", the lower the temperature, the smaller the data read margin.

[0005] An object of one embodiment of the present invention is to provide a sense timing generation circuit and a semiconductor memory device capable of generating sense timing that reduces the effect of temperature, increases a read margin, and enables highly reliable operation. [Means for solving the problem]

[0006] The sense timing generation circuit of the embodiment is a sense timing generation circuit that outputs a sense amplifier enable signal from an output terminal to enable a sense amplifier based on a clock signal input from an input terminal, and is equipped with a delay circuit section that has a temperature characteristic in which the amount of delay decreases as the temperature increases, has a plurality of types of delay circuits with different temperature characteristics, delays the clock signal and outputs it as a sense amplifier enable signal, and a connection switching section that switches the connection state of the plurality of delay circuits in the delay circuit section extending from the input terminal to the output terminal. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is an explanatory diagram of a schematic configuration of a semiconductor memory device according to an embodiment. [Diagram 2] FIG. 2 is an explanatory diagram of an example of the configuration of a main part of a sense amplifier circuit. [Diagram 3] FIG. 3 is an explanatory diagram of an example of a sense timing generation circuit. [Figure 4] FIG. 4 is an explanatory diagram of a configuration example of a delay circuit. [Diagram 5] FIG. 5 is an explanatory diagram of the conventional problems. [Figure 6] FIG. 6 is a diagram illustrating the operation of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the semiconductor memory device of the embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments.

[0009] FIG. 1 is an explanatory diagram of a schematic configuration of a semiconductor memory device according to an embodiment. The semiconductor device 10 is configured as a NOR type flash memory, and includes a memory cell array 11, a row decoder 12, a column decoder 13, a reference potential generating circuit 14, a sense amplifier circuit 15, a data output circuit 16, and a control circuit 17, as shown in FIG.

[0010] The memory cell array 11 includes a plurality of memory cells MC arranged in a grid pattern. The memory cell array also includes a plurality of word lines WL, a plurality of source lines SL, and a plurality of bit lines BL.

[0011] For ease of understanding, FIG. 1 shows only one memory cell MC in a selected state, and only the word line WL, source line SL, and bit line BL corresponding to that memory cell.

[0012] Here, the memory cell MC includes a memory cell transistor TR having a source terminal connected to a source line SL, a gate terminal connected to a word line WL, and a drain terminal connected to a bit line BL.

[0013] Under the control of the control circuit 17, the row decoder 12 enables the word line WL corresponding to the memory cell MC from which data is to be read. Under the control of the control circuit 17, the column decoder 13 enables the source line SL and bit line BL corresponding to the memory cell MC to be read.

[0014] The reference potential generating circuit 14 generates and supplies a reference potential to the sense amplifier circuit 15 . The sense amplifier circuit 15 compares the potential of the bit line corresponding to the memory cell MC in a selected state with a reference potential at a predetermined timing to determine the data of the memory cell MC and outputs the determination result to the data output circuit 16.

[0015] The data output circuit 16 outputs read data DOUT based on the output of the sense amplifier circuit 15 . The control circuit 17 controls the row decoder 12, the column decoder 13 and the sense amplifier circuit 15 to write, read or erase data to the corresponding memory cells MC based on a clock signal CLK, command data CMD and address data ADD from a host device (e.g., an MPU) not shown.

[0016] FIG. 2 is an explanatory diagram of an example of the configuration of a main part of a sense amplifier circuit. Next, the configuration of the sense amplifier circuit 15 will be described. The sense amplifier circuit 15 includes a plurality of sense amplifiers 151 and a plurality of sense timing generation circuits 152 corresponding to the bit lines BL. In this case, the sense timing generation circuit 152 can be shared by a plurality of sense amplifiers 151 .

[0017] The sense amplifier 151 receives an input signal IN from the source line SL of each block BLK at its non-inverting input terminal, a reference voltage Vref at its inverting input terminal, and outputs an output signal OUT at an “H” level when the sense amplifier enable signal SAE from the sense timing generation circuit 152 is in an enabled state and the input signal IN is a voltage higher than or equal to the reference voltage Vref.

[0018] Moreover, when the sense amplifier enable signal SAE from the sense timing generation circuit 152 is in an enable state, and the input signal IN has a voltage lower than the reference voltage Vref, the output signal OUT is at an "L" level.

[0019] Here, a configuration example of the sense timing generation circuit 152 will be described. FIG. 3 is an explanatory diagram of an example of a sense timing generation circuit. The sense timing generation circuit 152 includes a plurality of (six in the example of FIG. 4) first delay circuits DL1, a plurality of (six in the example of FIG. 4) second delay circuits DL2, and a selector SEL.

[0020] Here, the first delay circuit DL1 and the second delay circuit DL2 have different temperature characteristics and delay times, as will be described in detail later.

[0021] More specifically, the sense timing generation circuit 152 has an input end provided with three first delay circuits DL1 connected in series to which the clock signal CLK is input. The three first delay circuits DL1 are followed by three second delay circuits DL2. These six delay circuits function as a series-connected section in which a plurality of delay circuits are connected in series.

[0022] Furthermore, three first delay circuits DL1 connected in series and three second delay circuits DL2 connected in series are connected in parallel to the rear stage of the three second delay circuits DL2. These six delay circuits are connected to the series section and function as a parallel connection section in which multiple systems of delay circuits (two systems in the example of FIG. 3) are connected.

[0023] A selector SEL that functions as a connection switching unit is connected to the rear stage of the parallel connection unit, and each system is connected to each input terminal of the selector SEL, and an input signal of one of the input terminals is output as a sense amplifier enable signal SAE.

[0024] In the above explanation, the selector SEL functioning as a connection switching unit is connected downstream of the parallel connection unit. However, it is also possible to commonly connect the output terminals of each system of the parallel connection unit and provide the selector SEL as a connection switching unit between the series connection unit and the parallel connection unit. Alternatively, it is also possible to configure the parallel connection section to have a connection switching section connected in a subsequent stage, and the series connection section to be connected in a subsequent stage of the connection switching section.

[0025] Here, a detailed description will be given of an example of the configuration of the first delay circuit DL1 and the second delay circuit DL2. FIG. 4 is an explanatory diagram of a configuration example of a delay circuit. FIG. 4A is an explanatory diagram of an example of the circuit configuration of the first delay circuit DL1. FIG. 4B is an explanatory diagram of an example of the circuit configuration of the second delay circuit DL2. In the figures, similar parts are given the same reference numerals.

[0026] The first delay circuit DL1, as shown in FIG. 4(A), is roughly divided into a first inverter INV1 having an adjustable driving force and a negative temperature coefficient (negative temperature characteristic), a second inverter INV21 having an input terminal connected to the output terminal of the first inverter INV1 and having a positive temperature coefficient (positive temperature characteristic), and a second inverter INV22 having an input terminal connected to the output terminal of the second inverter INV21 and having a positive temperature coefficient (positive temperature characteristic).

[0027] In this case, the positive temperature characteristic means that the higher the temperature, the longer the delay time, and the negative temperature characteristic means that the lower the temperature, the longer the delay time. Moreover, the second inverter INV21 and the second inverter INV22 have the same configuration and the same temperature characteristics.

[0028] The first inverter INV1 includes a P-channel MOS transistor P11 having a gate terminal connected to the input terminal and a drain terminal connected to the output terminal, and a P-channel MOS transistor P12 having a drain terminal connected to the source terminal of the P-channel MOS transistor P11, a gate terminal to which the driving force control signal IREF_P is input, and a source terminal connected to the high potential power supply VDD.

[0029] Furthermore, the first inverter INV1 includes an N-channel MOS transistor N11 having a gate terminal connected to the input terminal of the first delay circuit DL1 and a drain terminal connected to the output terminal, and an N-channel MOS transistor N12 having a drain terminal connected to the source terminal of the N-channel MOS transistor N11, a gate terminal to which the driving force control signal IREF_N is input, and a source terminal connected to the low potential power supply VSS.

[0030] The second inverter INV21 includes a P-channel MOS transistor P21 having a gate terminal connected to the output terminal of the first inverter INV1, a source terminal connected to a high potential power supply VDD, and a drain terminal connected to the output terminal, and an N-channel MOS transistor N21 having a gate terminal connected to the input terminal, a drain terminal connected to the output terminal of the first delay circuit DL1, and a source terminal connected to a low potential power supply VSS.

[0031] Similarly, the second inverter INV22 includes a P-channel MOS transistor P21 having a gate terminal connected to the input terminal of the second inverter INV22, a source terminal connected to the high potential power supply VDD, and a drain terminal connected to the output terminal, and an N-channel MOS transistor N21 having a gate terminal connected to the input terminal, a drain terminal connected to the output terminal of the first delay circuit DL1, and a source terminal connected to the low potential power supply VSS.

[0032] The second delay circuit DL2, as shown in FIG. 4(B), is roughly divided into a first inverter INV11 having an adjustable driving force and a negative temperature coefficient (negative temperature characteristic), a first inverter INV12 having an adjustable driving force and a negative temperature coefficient (negative temperature characteristic) whose input terminal is connected to the output terminal of the first inverter INV12, and a second inverter INV2 having an input terminal connected to the output terminal of the first inverter INV12 and having a positive temperature coefficient (positive temperature characteristic).

[0033] In this case, the first inverter INV11 and the first inverter INV12 have the same configuration and the same temperature characteristics.

[0034] The first inverter INV11 includes a P-channel MOS transistor P11 having a gate terminal connected to the input terminal of the second delay circuit DL2 and a drain terminal connected to the output terminal, and a P-channel MOS transistor P12 having a drain terminal connected to the source terminal of the P-channel MOS transistor P11, a gate terminal to which the driving force control signal IREF_P is input, and a source terminal connected to the high potential power supply VDD.

[0035] Furthermore, the first inverter INV11 includes an N-channel MOS transistor N11 having a gate terminal connected to the input terminal of the second delay circuit DL2 and a drain terminal connected to the output terminal, and an N-channel MOS transistor N12 having a drain terminal connected to the source terminal of the N-channel MOS transistor N11, a gate terminal to which the driving force control signal IREF_N is input, and a source terminal connected to the low potential power supply VSS.

[0036] The first inverter INV12 includes a P-channel MOS transistor P11 having a gate terminal connected to the output terminal of the first inverter INV11 and a drain terminal connected to the output terminal of the first inverter INV12, and a P-channel MOS transistor P12 having a drain terminal connected to the source terminal of the P-channel MOS transistor P11, a gate terminal to which the driving force control signal IREF_P is input, and a source terminal connected to the high potential power supply VDD.

[0037] Furthermore, the first inverter INV12 includes an N-channel MOS transistor N11 having a gate terminal connected to the output terminal of the first inverter INV11 and a drain terminal connected to the output terminal, and an N-channel MOS transistor N12 having a drain terminal connected to the source terminal of the N-channel MOS transistor N11, a gate terminal to which the driving force control signal IREF_N is input, and a source terminal connected to the low potential power supply VSS.

[0038] The second inverter INV2 includes a P-channel MOS transistor P21 having a gate terminal connected to the output terminal of the first inverter INV12, a source terminal connected to the high potential power supply VDD, and a drain terminal connected to the output terminal, and an N-channel MOS transistor N21 having a gate terminal connected to the output terminal of the first inverter INV12, a drain terminal connected to the output terminal of the first delay circuit DL1, and a source terminal connected to the low potential power supply VSS.

[0039] In this embodiment, the first delay circuit DL1 and the second delay circuit DL2 are both delay circuits having negative temperature coefficients, but the second delay circuit DL2 is a delay circuit having a more negative temperature coefficient than the first delay circuit DL1.

[0040] That is, if the temperature coefficient of the first delay circuit DL1 is P1 and the temperature coefficient of the second delay circuit DL2 is P2, then: 0>P1>P2 It is as follows.

[0041] In other words, when the temperature rises by a certain amount, the decrease in the delay amount of the first delay circuit DL1 becomes smaller than the decrease in the delay amount of the second delay circuit DL2. Therefore, when a large number of second delay circuits DL2 are used as delay circuits constituting the sense timing generation circuit 152, the amount of delay decreases more in response to an increase in temperature than when a large number of first delay circuits DL1 are used, i.e., the transition to the sense amplifier enable state occurs more quickly.

[0042] In the above explanation, the first inverters INV1, INV11, and INV12 have negative temperature coefficients (negative temperature characteristics) and the second inverters INV2, INV21, and INV22 have positive temperature coefficients (positive temperature characteristics), but the opposite is also possible. In this case, the temperature characteristics of the first delay circuit DL1 and the temperature characteristics of the second delay circuit DL2 are naturally in an opposite state.

[0043] Next, the operation of the embodiment will be described. First, prior to the operation of the embodiment, problems with the conventional technology will be described. FIG. 5 is an explanatory diagram of the conventional problems. In a conventional sense timing generation circuit, the output timing of the sense amplifier enable signal is constant.

[0044] Incidentally, when reading from a flash memory compatible with a wide temperature range (for example, −40 to 175° C.), the fluctuation state of the read voltage differs depending on the value stored in the memory cell and the temperature.

[0045] More specifically, when the threshold voltage Vth of the memory cell transistor TR constituting the memory cell MC is high, even if the word line WL becomes "H" level, the memory cell transistor TR remains in the off state, and the potential of the bit line BL remains at approximately the power supply potential.

[0046] However, the potential of the bit line BL gradually decreases slightly due to the leakage current of the memory cell transistor TR. In general, the leakage current of the memory cell transistor TR tends to increase as the temperature increases, which means that the voltage of the bit line BL decreases faster when the value of 0 stored in the memory cell MC is read out as shown in FIG.

[0047] Therefore, the higher the operating temperature range, the less likely it is that the data read margin MG0 for the reference potential Vref will be sufficient, which may result in erroneous read data.

[0048] On the other hand, when the threshold voltage Vth of the memory cell transistor TR constituting the memory cell MC is low, when the word line WL becomes high level, the memory cell transistor TR turns on, an on-current flows from the bit line BL to the source line SL, and the potential of the bit line BL gradually decreases.

[0049] In general, the on-current of the memory cell transistor TR tends to decrease as the temperature decreases, so the lower the temperature, the slower the drop in the potential of the bit line BL becomes when reading the value = 1 stored in the memory cell MC, as shown in Figure 5.

[0050] Therefore, the lower the operating temperature range, the less likely it is that the data read margin MG1 for the reference potential Vref will be sufficient, which may result in erroneous read data.

[0051] Next, the operation of the embodiment will be described with reference again to FIG. In the sense timing generation circuit 152, the selector SEL is configured to select either one of the three first delay circuits DL1 connected in series that form a parallel connection section or the three second delay circuits DL2 connected in series that form a parallel connection section.

[0052] Therefore, when the selector SEL selects the upper row of three first delay circuits DL1 connected in series that already form a parallel connection section, the sense timing generation circuit 152 effectively has a configuration in which six first delay circuits DL1 and three second delay circuits DL2 are connected in series.

[0053] In the selector SEL, when the lower row of three second delay circuits DL2 connected in series that already form a parallel connection section is selected, the sense timing generation circuit 152 effectively has a configuration in which three first delay circuits DL1 and six second delay circuits DL2 are connected in series.

[0054] FIG. 6 is a diagram illustrating the operation of the embodiment. In this case, whether the upper row of three series-connected first delay circuits DL1 or the lower row of three series-connected second delay circuits DL2 is selected, the temperature coefficient is negative, so that the timing at which the sense amplifier enable signal SAE output from the sense timing generation circuit 152 becomes enabled differs between the case of a predetermined high temperature and the case of a predetermined low temperature, as shown in FIG. 6.

[0055] For example, in the case of a high temperature, the timing is indicated by the sense amplifier enable signal SAE(HT), and in the case of a low temperature, the timing is indicated by the sense amplifier enable signal SAE(LT).

[0056] Therefore, when reading the value = 0 stored in a memory cell, as shown by the signal waveform HT0 in Figure 6, even if the temperature is high and there is a large drop in the read voltage due to the current flowing between the drain and source of the transistor that constitutes the memory cell to be read, at the timing of the sense amplifier enable signal SAE (HT) when the sense amplifier enable signal SAE is enabled, a sufficiently large data read margin MGH from the reference voltage Vref can be secured, and the read data will not be erroneous.

[0057] Furthermore, when reading the value = 1 stored in the memory cell MC, even if the temperature is low and the drop in the read voltage due to the current flowing between the drain and source of the memory cell transistor TR that constitutes the memory cell MC to be read is small, as shown in signal waveform LT1 in Figure 6, the data read margin MGL from the reference voltage Vref can be secured to be sufficiently large, as shown in Figure 6, and the read data will not be erroneous.

[0058] However, if the temperature characteristic is too negative, when reading the value=1 stored in the memory cell at high temperature, the data read margin MGH1 decreases, and there is a risk that the read data will be erroneous.

[0059] For this reason, in this embodiment, the selector SEL is appropriately set to select a delay circuit with an appropriate temperature characteristic so that the data read margin MGH1 does not fall below the data read margin MGL1.

[0060] In other words, by setting the selector SEL so that the temperature characteristics when reading the value = 1 stored in the memory cell MC match the temperature characteristics of the delay circuit, it is possible to prevent the data read margin MGH1 from falling below the data read margin MGL1.

[0061] As described above, according to this embodiment, depending on the ambient temperature, when the temperature rises, the timing at which the sense amplifier enable signal SAE is enabled is shifted earlier, and when the temperature drops, the timing at which the sense amplifier enable signal SAE is enabled is shifted later. The amount of timing shift can be selected by a selector, so that the actual operation of the sense timing generation circuit 152 can be made more optimal.

[0062] In the above description, a case has been described in which two systems of delay circuit groups are provided as the parallel connection section, but it is also possible to provide three or more systems of delay circuit groups.

[0063] In the above explanation, a selector is provided as a connection switching section to switch between any of the systems, but it is also possible to commonly connect the input terminals of the delay circuit groups of multiple systems that make up the parallel connection section, and also commonly connect the output terminals, and to maintain the connection state of only one of the delay circuit groups by blowing fuses on the signal transmission circuits of the other delay circuit groups, or by physically disconnecting the delay circuit groups with a laser.

[0064] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0065] 10. Semiconductor memory device 11 Memory Cell Array 12 Row Decoder 13 Column Decoder 14 Reference potential generation circuit 15 Sense amplifier circuit 16 Data output circuit 17 Control circuit 151 Sense Amplifier 152 Sense timing generation circuit (delay circuit section) INV1, INV11, INV12 First inverter INV2, INV21, INV22 Second inverter N11, N12, N21 N-channel MOS transistors P11, P12, P21 P-channel MOS transistors BL bit line CLK Clock signal DL1 First delay circuit (delay circuit section) DL2 Second delay circuit (delay circuit section) IN Input signal IREF_P, IREF_N drive strength control signal HT0, HT1 signal waveform (at high temperature) LT0, LT1 signal waveform (at low temperature) MGL data read margin (at low temperature) MGH Data read margin (at high temperature) TR Memory Cell Transistor OUT Output signal SAE Sense amplifier enable signal SEL Selector (connection switching section) SL Source Line VDD High potential side power supply VSS Low potential side power supply Vref Reference voltage WL Word Line

Claims

1. A sense timing generation circuit that outputs from an output terminal a sense amplifier enable signal for enabling a sense amplifier based on a clock signal input from an input terminal, a delay circuit section having a temperature characteristic in which the delay amount decreases as the temperature increases, the delay circuit section having a plurality of types of delay circuits having different temperature characteristics, the delay circuit section delaying the clock signal and outputting the clock signal as the sense amplifier enable signal; a connection switching unit that switches a connection state of a plurality of delay circuits in the delay circuit unit extending from the input terminal to the output terminal; A sense timing generation circuit comprising:

2. Each of the plurality of types of delay circuits is a combination of an inverter having a positive temperature characteristic and an inverter having a negative temperature characteristic, the combination being connected in series, the connection switching unit switches the connection state as the delay circuit unit so as to provide a predetermined delay amount at a predetermined temperature; 2. The sense timing generation circuit according to claim 1.

3. the delay circuit unit includes a series connection unit in which one or more delay circuits are connected in series, and a parallel connection unit connected to the series connection unit in which a plurality of delay circuits are connected in parallel, the connection switching unit connects the series connection unit and the parallel connection unit in a state where one of the delay circuits in the plurality of parallel-connected systems is selected.

3. The sense timing generating circuit according to claim 1, further comprising:

4. The connection switching unit is provided between the series connection unit and the parallel connection unit or at a subsequent stage of the parallel connection unit.

4. The sense timing generation circuit according to claim 3.

5. A memory cell for storing data; a bit line for transmitting a signal read from the memory cell; a sense amplifier for detecting data stored in the memory cell based on a signal transmitted through the bit line; a sense timing generation circuit that controls a timing for outputting a sense amplifier enable signal for enabling the sense amplifier from an output terminal based on a clock signal input from an input terminal; the sense timing generation circuit has a temperature characteristic in which a delay amount decreases with an increase in temperature, and includes a delay circuit section having a plurality of types of delay circuits having different temperature characteristics, delaying the clock signal and outputting the delay signal as the sense amplifier enable signal, and a connection switching section switching a connection state of the plurality of delay circuits in the delay circuit section extending from the input terminal to the output terminal; Semiconductor memory device.

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