Secure Hardware Programmable Architecture

Abstract

The present invention relates to an electrical device comprising: (a) functional modules that can act as both transaction initiators and transaction targets, where a transaction initiating functional module may require a transaction target functional module to perform a function on its behalf; and (b) a first interconnect structure that connects the functional modules and provides communication between them, wherein the (electrical) device is configured such that a selected transaction initiating functional module temporarily has exclusive access to the transaction target functional module(s) that perform the function on its behalf, thereby ensuring that transaction initiating functional modules other than the selected transaction initiating functional module do not have uncontrolled access to the transaction target functional modules, and wherein the selected transaction initiating functional module is a hardware secure module.

Description

[Technical field]

[0001] The present invention is directed to the field of digital control of electrical systems, specifically (but not exclusively) to the control of the powertrain of the electrical systems (motors but also DC / DC converters etc.) of pure electric or hybrid vehicles, which require hard real-time and safety management. The present invention is concerned with providing the highest level of security features covering current and future security challenges applied to the above mentioned application fields, at the highest level of functional safety standards. The present invention combines current state of the art cryptographic and anti-hacking features with on-chip programmable hardware and accelerators. [Background technology]

[0002] The present invention is particularly suited to an electrical device (also referred to as FPCU) comprising a plurality of functional modules and an interconnect structure connecting the functional modules and providing communication between them, wherein one or more of the functional modules is a hardware programmable unit, that is a programmable logic matrix.

[0003] The invention relates to providing security by making available (in the long term) within such an FPCU type component (as a functional module) a specific secure subsystem characterized by state-of-the-art cryptographic and anti-hacking functions, essentially characterized by the following (among other functional modules): Several CPU cores with conventional on-chip program and data memory Subsystems featuring multiple peripherals around one or more flexible logic units, with optional task switching and spatial separation.

[0004] With the advent of connected vehicles, this type of application is increasingly subject to security concerns related to: -Protection against hackers taking control of the vehicle - Protection of the firmware update procedure when using "over-the-air" update scenarios · Protection of software IP running on the FPGA Checking firmware integrity (against electrical damage hacks)

[0005] Until recently, security management was managed by a central "bridge" that was the only system with direct contact with the outside world (e.g. connected to the cloud). This bridge was responsible for all secure scenarios, so all other electronic systems were hidden behind the bridge.

[0006] Currently, vehicle network architectures are moving towards a more decentralized approach, meaning that in some cases, every computing resource in the vehicle may have more or less direct contact with external networks (and therefore with more critical networks like the powertrain controller).

[0007] Therefore, it has become mandatory for any computing component to handle security scenarios.

[0008] As mentioned before, security is becoming more and more important in automotive applications, so the next generation of electronic components and devices must provide the necessary features to also address secure scenarios and secure attack countermeasures.

[0009] These elements are well covered by many commercial products that adequately address currently known security features.

[0010] However, the security domain is evolving rapidly. Hackers' techniques are becoming more sophisticated and cryptographic standards are evolving. As an example, some widely used cryptographic algorithms would theoretically require thousands of years of calculations to hack with current computers, but could be hacked in minutes with a future quantum computer. This is a critical issue in the automotive domain, where component life spans are much longer than in other domains (e.g. consumer electronics). This means that secure subsystems must be able to address new security challenges for a decade or more.

[0011] The present invention is specifically focused on FPCUs and is primarily targeted at hard real-time applications with the highest functional safety requirements (ASIC-D) and is designed to provide best-in-class levels in both real-time and safety domains.

[0012] State of the art solutions A typical answer to the previous challenge regarding flexibility of security features is to integrate the CPU cores into a secure subsystem, so that the secure functions can be upgraded by software updates.

[0013] However, this method has the following limitations that make it unacceptable for the target automotive applications: This method is not effective for products with long life spans because the required CPU power cannot be predicted correctly in advance, and therefore the device will end up with more CPU power than necessary, which will have a significant impact on the cost of the device. · Cryptographic algorithms require a lot of processing resources (hardware SHA processing time is 10 times longer than hardware processing time), and in the worst case, future cryptographic algorithms may not be able to run with the implemented processing resources. This approach is very restrictive in terms of the implementation of countermeasures, because the implementation of countermeasures often depends on hardware resources.

[0014] In relation to balancing safety and real-time capabilities with security, the conventional approach is to add some software stack that can synchronize the operation of both real-time and security systems, and to implement an arbitration policy that allows secure countermeasures while ensuring functional safety operation.

[0015] Again, response time is an issue.

[0016] In fact, the software required must know the current real-time state of the system so that it can make the right decisions at the right time.

[0017] However, in the considered best-in-class FPCU systems, the hard real-time algorithms are executed in a real-time processing subsystem (featuring several programmable and flexible hardware logic units) and are not finely synchronized with the CPU cores, and in any case the CPU is not fast enough to synchronize with the hardware operations. Summary of the Invention [Problem to be solved by the invention]

[0018] The aim of the present invention is to add a future-proof security subsystem to the above architecture, while avoiding a situation where this secure functionality may conflict with (best in class) real-time and / or safety requirements, if the secure subsystem interprets some safety-related failure (e.g. clock or power artifacts) as a security attack. Therefore, the secure subsystem may take some countermeasures to prevent hacking (e.g. blocking communication via CAN ports). Obviously, this can be a very risky decision.

[0019] The present invention relates to defining a specially adapted architecture within such FPCU type components, thereby providing the highest level of security features covering current and future security challenges at the highest functional safety standards. [Means for solving the problem]

[0020] The present invention therefore provides a means for efficiently expanding security, and in particular the capabilities of the secure subsystem, to enable the FPCU component to meet long-term security challenges, by enabling the (long-term) use (as a functional module) of a specific secure subsystem featuring state-of-the-art cryptographic and anti-hacking capabilities within such FPCU type components.

[0021] In a first aspect, the present invention provides an electrical apparatus comprising: (a) functional modules capable of acting as both transaction initiators or transaction targets, where a transaction initiating functional module may require a transaction target functional module to perform a function on its behalf; and (b) a first interconnect fabric connecting the functional modules and providing communication between them, the (electrical) apparatus being configured such that a selected transaction initiating functional module has temporarily exclusive access to the transaction target functional module(s) performing a function on its behalf, thereby ensuring that transaction initiating functional modules other than the selected transaction initiating functional module do not have uncontrolled access to the transaction target functional modules, the selected transaction initiating functional module being a hardware secure module.

[0022] In a second aspect, the present invention provides a secure transaction mechanism in which a transaction initiation functional module other than a selected transaction initiation functional module only accesses via a first interconnect structure after the other transaction initiation functional module has initiated a service request to said selected transaction initiation functional module by said other transaction initiation functional module for appropriately configuring a protection unit connected to such other transaction initiation functional module, subject to approval of the selected transaction initiation functional module.

[0023] In a third aspect, the present invention provides various interconnect structures and considerations related to the above. [Brief description of the drawings]

[0024] [Figure 1] FIG. 0100 shows a conventional FPCU architecture (without flexible hardware secure module). [Diagram 2] FIG. 2 shows an exemplary use of the concept of the present invention (0200). [Diagram 3] FIG. 1 illustrates a trigger hardware management architecture within the FPCU component in relation to specific considerations that must be taken to ensure safety in accordance with the present invention. [Figure 4] This is a diagram (0400) explaining a use case related to Figure 3 (0300). [Diagram 5] This is a diagram (0500) explaining the concept of a virtual boundary in relation to Figures 3 (0300) and 4 (0400). [Figure 6] FIG. 1 illustrates a typical interconnect structure in an FPCU, with specific considerations to be taken to ensure safety in accordance with the present invention. [Figure 7] FIG. 700 illustrates a further use case relating to a hardware secure module that utilizes peripheral resources. [Figure 8] In relation to Figure 7 (0700), this is a diagram (0800) introducing the concept of a virtual boundary. [Figure 9] A diagram illustrating the invention in the context of matrix switching and appropriate mechanisms for achieving security (0900). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The present invention relates to an (electrical) apparatus comprising: (a) a functional module capable of acting as both a transaction initiator or a transaction target, where a transaction initiating functional module may require a transaction target functional module to perform a function on its behalf; and (b) a first interconnect structure connecting the functional modules and providing communication between said functional modules, wherein the (electrical) apparatus is configured such that a selected transaction initiating functional module has (temporarily) exclusive access to the transaction target functional module(s) performing a function on its behalf to ensure that no transaction initiating functional module other than the selected transaction initiating functional module has uncontrolled access to the transaction target functional module (via the interconnect structure).

[0026] Typically, the selected transaction initiation function module is a hardware secure module (eg having cryptographic functionality).

[0027] The invention particularly relates to an (electrical) apparatus comprising (a) functional modules capable of playing both the role of transaction initiator or of transaction target, whereby a transaction initiating functional module may require a transaction target functional module to perform a function on its behalf, and (b) a first interconnect structure connecting the functional modules and providing communication between them, characterized in that protection means are provided to ensure that transaction initiating functional modules other than the selected transaction initiating functional module do not have uncontrolled access to the transaction target functional modules (via the interconnect structure) in order to ensure that a selected transaction initiating functional module has (temporarily) exclusive access to the transaction target functional module(s) performing a function on its behalf.

[0028] In one embodiment of the invention, the protection means comprises one or more protection units provided for each of the transaction target functional modules (between said modules and part of the first interconnect structure), whereby the configuration of said protection units is controlled (directly or indirectly) by the selected transaction initiation functional module (wherein said protection units provide transaction filtering).

[0029] In one embodiment of the present invention, transaction initiation functional modules other than the selected transaction initiation functional module only have access (and therefore access is controlled) via the first interconnect structure after a service request has been initiated by the other transaction initiation functional module to the selected transaction initiation functional module for appropriately configuring the associated protection unit in accordance with the authorization of the selected transaction initiation functional module.

[0030] In one embodiment of the present invention, in the (electrical) device, one or more protection units are further connected by a second interconnect structure for configuring the protection units, whereby a further protection unit is provided between the first interconnect structure and the second interconnect structure, and the configuration of the further protection unit is controlled (directly or indirectly) by the selected transaction initiation function module.

[0031] In an alternative embodiment of the invention in an (electrical) device, one or more protection units are further connected by one or more second interconnect structures for configuring the protection units, whereby one or more further protection units are provided between the first interconnect structure and the second interconnect structure, and the configuration of the further protection units is controlled (directly or indirectly) by the selected transaction initiation function module.

[0032] In one embodiment of the present invention, there is provided an (electrical) apparatus, in which a first interconnect structure connecting functional modules and providing communication between them comprises a third interconnect structure for exchanging task-specific trigger signals between the functional modules, the third interconnect structure comprising a trigger router module capable of routing any input trigger to any output trigger, the trigger router module being configured to ensure that no transaction initiating functional modules other than a selected transaction initiating functional module have uncontrolled access to the trigger router module via the third interconnect structure, preferably the trigger router module being configurable via the second interconnect structure (while a protection unit is provided for the remaining part of the first interconnect structure between the remaining part and the functional modules).

[0033] In one embodiment of the present invention, there is provided an (electrical) apparatus in which the first interconnection structure connecting functional modules and providing communication between those functional modules comprises a fourth interconnection structure comprising a direct connection between (part of) the functional modules, whereby the protection means ensures (by appropriately configuring protection units associated with those transaction initiation functional modules) that transaction initiation functional modules other than the selected transaction initiation functional module do not gain uncontrolled access via the fourth interconnection structure to a module(s) performing functions on behalf of the selected transaction initiation functional module.

[0034] The present invention will now be described based on a conventional FPCU architecture (without Flexible Hardware Secure Module) shown in FIG. 1 (0100), which comprises: (0101): One or more conventional processor cores. In such an FPCU component, the processor cores are dedicated to parts of the application that do not require hard real-time processing. (0102): One or more flexible logic unit matrices, each of which may optionally be task-switch capable. (0103): Multiple sensor / actuator and hardware accelerator peripherals. (0104): "Hardware Security Module" (Evita's term). This is a traditional security subsystem that is characterized by: ○Local processor core and associated secure firmware Multiple cryptographic hardware accelerators. ○Multiple mechanisms to protect against hacking attacks · (0105): This is the physical boundary of the security subsystem. This concept is important because it clearly specifies the communication channels between the secure world and the application world. Within this boundary, all hardware content is strictly reserved to the secure computing unit (e.g. CPU, but possibly FLU too) and cannot be accessed by other computing units (CPU or other) of the component. (0106): Any complex interconnection network that allows various kinds of communication between elements of the system (bus communication, interrupts, triggers, etc.)

[0035] As mentioned above, current software-based solutions do not adequately solve the problem.

[0036] The inventive concept therefore relates to exploiting the presence of flexible logic units and / or mathematical accelerators contained in the (so-called AxEC) subsystem in order to extend the "boundaries" of the HSM module. This resource allocation is intended to be done dynamically at run-time so that the use of AxEC resources can be adapted to the actual situation.

[0037] FIG. 2(0200) illustrates this concept in an example.

[0038] In this example: · Extending the functionality of a conventional security module (0201) by using a partition of the FLU (0202) and / or (preferably both) a hardware accelerator (0203). By a dedication mechanism (0204) (to be further explained) within the interconnect fabric, the above elements are dedicated to the use of the HSM, i.e. these resources remain "invisible" to any master in the SOC other than the HSM itself. Therefore, we extend the effective physical boundary (0205) of the secure subsystem and integrate some real-time computing power of the AxEC. This is the basic FHSM concept.

[0039] More generally, there is provided an electrical device comprising (a) a functional module (HSM, CPU, FLU, etc.) which may require another functional module (FLU, peripheral device) to (exclusively) perform (security) functions on its behalf.

[0040] As introduced above, the concept of FHSM is to virtually extend the boundary of the secure subsystem to the AxEC's computing resources (FLU, peripheral devices).

[0041] Further defined hardware mechanisms strictly guarantee that resources allocated to the HSM cannot be influenced by other parts of the SOC, i.e. communication channels where the resource is a "slave" (not the initiator of the communication) must be restricted so that only components that are part of the FHSM boundary can initiate communication on this channel, i.e. specific "isolation" hardware is required to achieve this goal.

[0042] Note: Communication channels for which the resource is the "master" do not require any special attention.

[0043] Depending on the type of communication channel, the mechanism of isolation may differ as will be further explained.

[0044] Below are the different types of communication channels: · System Bus: This type of channel relies on a bus transfer protocol (AXI, AHB, APB, OCP, etc.). This type of channel is a set of signals and vectors that work together according to a predefined protocol. Direct Data Bus: This type of channel is a simple vector of data, optionally associated with a dataValid / dataAck validation protocol. Trigger: This type of channel is a single bit wire. · Clock / Reset: This type of signal must be properly handled to avoid semi-invasive security attacks.

[0045] As mentioned above, the invention relates to providing security by making it possible to use (in the long term) specific secure subsystems (as functional modules) that are characterized by the current state of the art cryptographic and anti-hacking features, but are able to handle new security challenges, by defining a specially adapted architecture within the components of such a type of FPCU, and more specifically to making them future-proof by allowing the secure subsystems to depend (exclusively) on other resources within the device, and in particular the communication architecture requires attention.

[0046] Since, in essence, the invention relates to an (electrical) apparatus comprising (a) functional modules and (b) an interconnect structure connecting the functional modules and providing communication between them, for the above purposes the (electrical) apparatus must be configured in such a way that a selected functional module has (temporarily) exclusive access to another functional module(s) performing a function on its behalf, but prevents uncontrolled access (via the interconnect structure) to said other functional modules via protective means (attached to the communication architecture defined by the interconnect structure).

[0047] In the following, the various available communication mechanisms (which define the communication architecture) are described in more detail.

[0048] Trigger Mechanism Figure 3 (0300) illustrates the trigger hardware management architecture within the FPCU component. · (0301) A set of SOC modules can drive one or more triggers. A "module" here can be a FLU partition, an AxEC peripheral, or an AxEC computing accelerator. · (0302) A set of SOC modules can receive one or more triggers as inputs. Note that some modules can have both input and output triggers. (0303) A central trigger routing function capable of routing any input trigger to any output trigger based on a set of configuration registers accessed via a system bus slave configuration interface (0304).

[0049] Now consider the following case where some modules are selected for FHSM exclusive access as shown in Figure 4 (0400). In this case, it is important to ensure the following: Module #1 (0402) on the right side can receive a trigger from module #2 (0401) on the left side. This is not a security breach because both modules are within the virtual boundary of the FHSM. Module #1 (0402) on the right side cannot receive triggers from any module other than module #2 (0401) on the left side. Therefore, trigger information cannot pass through the virtual boundary of the FHSM.

[0050] As noted in Figure 3 (0300), configuration of the trigger router is accomplished through the system bus slave interface. As a result, the router must also be considered to be included within the virtual boundary of the FHSM, as conceptually illustrated in Figure 5 (0500). Therefore, the slave configuration interface must be managed to achieve this. A specific embodiment for achieving this is described further below.

[0051] This new virtual boundary allows the HSM module to determine the appropriate trigger routing and ensure the above conditions are met.

[0052] As a result of the edge effect, the HSM subsystem becomes responsible for configuring all triggers of the SOC, even those that are not part of security operations. This is not a problem: it is always possible for the application CPU to configure the necessary non-secure triggers. The only constraint is that the application CPU cannot do this directly by writing trigger router registers. Instead, the application CPU must send a specific request towards the HSM. This HSM can then check the secure side of this request and accept or reject the trigger routing request accordingly.

[0053] Generally speaking, an (electrical) apparatus in which a first interconnect structure connecting functional modules and providing communication between them comprises a (further) third interconnect structure for exchanging task-specific trigger signals between the functional modules, this third interconnect structure comprising a trigger router module capable of routing any input trigger to any output trigger, should be such that the trigger router module is configured to ensure that no functional modules other than the selected functional module have uncontrolled access to the trigger router module via the third interconnect structure.

[0054] Clock and Reset Management As mentioned before, the FPCU can have a variety of communication mechanisms available and these can be combined. Another FPCU (internal) communication mechanism is the clock and reset mechanism. As mentioned before, each communication mechanism needs to be adapted to ensure that safety and timing issues do not arise as a result of extending the security functionality to other modules.

[0055] Fortunately, the clock and reset management in the FHSM is very similar to the trigger management.

[0056] Therefore, the module(s) responsible for generating the clock and reset must be under the exclusive control of the HSM module (such as the trigger router in the previous section).

[0057] Thus, the configuration interface of the clock and reset manager(s) is managed as further described, and when the main CPU requires clock and reset operation, it issues a request to the HSM module, which checks the security validity of the request and ultimately performs the requested configuration.

[0058] Thus, as before, there is provided an (electrical) apparatus, in which a first interconnect structure connecting functional modules and providing communication between them comprises a (further) third interconnect structure relating to clocks and resets, this third interconnect structure comprising a clock and reset management module, the clock and reset management module being configured to ensure that no functional modules other than a selected functional module have uncontrolled access to the clock and reset management module via the third interconnect structure.

[0059] Slave Interface In a typical SOC architecture, such as that used in an FPCU, all functional modules are connected to an arbitrarily complex interconnect structure that allows bidirectional data transmission between the initiator and target of a transaction.

[0060] In the most general case, the memory mapping of target resources allows any initiator to potentially access any target. However, for reasons of software execution robustness and functional safety, the preferred architecture according to the invention features a multi-layer MPU (Memory Protection Unit) structure that allows fine-grained filtering of access rights of the interconnect memory map based on the following transaction characteristics: Initiator module identifier Access address · Access direction (read / write) ·Access security level, etc.

[0061] Therefore, the general interconnect structure in an FPCU as shown in FIG. 6(0600) can be summarized as follows: · (0601): Multiple MPU components are inserted into the interconnect socket. ○ On the initiator side, the functional safety requirement requires that the MPU be inserted unconditionally. On the target side, the MPU is optional. If the granularity of the memory-mapped regions of the initiator's MPU is too large, an MPU can be included anyway. Having a target-side MPU allows very fine-grained control over the protection of the memory map. · (0602): Each MPU features a configuration port which is itself a target socket in a subpart of the SOC interconnect structure (0603). This part of the interconnect itself is protected by the MPU (0604)

[0062] Now, assume that at runtime, the HSM module needs to use some computing resources in the AxEC, as shown in FIG. 7 (0700) (this is a concept introduced by this invention).

[0063] In the above example, the security requirement is that FLU#1 and peripheral device #2 cannot be accessed via the interconnect from any initiator other than the HSM subsystem.

[0064] That is, all MPUs present on the interconnect sockets of these modules must be configured with an HSM module.

[0065] That is, access to the configuration interfaces of those MPUs must be protected in the same way as the module interfaces.

[0066] That is, the MPU that controls access to the secure configuration interconnect must also be controlled by the HSM.

[0067] Therefore, in this architecture, all MPUs in the SOC must be configured with only the HSM subsystem, expanding the virtual boundary as shown in FIG. 8 (0800).

[0068] When the main CPU needs to configure some MPUs for non-secure reasons, it issues a service request to the HSM module, which checks the security validity of the request and then configures the MPUs accordingly.

[0069] Essentially, in the above architecture, the (communication) protection means mentioned above comprises one or more protection units provided (between the above module and part of the first interconnect structure), whereby the configuration of the above protection units is controlled (directly or indirectly) by the selected transaction initiation function module.

[0070] Use of a flexible logic unit in a flexible hardware secure mechanism So far we have discussed the communication mechanisms in SOC and the necessary adaptations for the flexible hardware approach (FHSM) according to the present invention. Advantageously, the FHSM concept takes advantage of the hardware computing resources of AxEC for security purposes.

[0071] We now describe the properties of the FLU that are necessary to make this concept possible.

[0072] First, we describe the base case where isolation and task switching features are not foreseen or used in the FLU.

[0073] If the FPCU component has one FLU matrix that does not provide task switching functionality, there are two possible cases: The embedded FPGA can support in-field partial reconfiguration. In this case, the HSM can reserve an area on the eFPGA for FHSM purposes and feed it a dedicated bitstream. However, this solution is not secure enough for the following reasons: ■ It is nearly impossible to demonstrate that there is no possible interaction between secure and insecure parts of the matrix. ■Management of the subpart's bitstream is handled by a software application whose level of security cannot be proven. Alternatively, the FLU is entirely dedicated to the FHSM or application at any one time. ○ From the perspective of security level, this is no problem. However, in target application areas where real-time computation cannot be interrupted, the FPCU component becomes almost unusable.

[0074] In conclusion, to implement the FHSM concept, an FPCU featuring one monotasking FLU matrix is ​​not a good candidate, even if it is technically possible in a fully dedicated case.

[0075] There is a concept where an FPCU component contains at least two FLU matrices that can optionally be used together as one big matrix. In this case the concept of FHSM is very important. · The application shall use a portion of the FLU matrix for real-time algorithms. The HSM may use the remaining free FLU matrix for security purposes (subject to the FHSM boundary management operations described above) · Allocation of FLU matrices to HSMs or applications can be done at runtime if required. This makes it easy to demonstrate the mutual independence of the secure and insecure parts of the FLU.

[0076] There is also the concept (which can be combined with the above concept) that the FPCU component contains at least one FLU matrix capable of performing task switching.

[0077] In this case the concept of FHSM is also relevant, but a bit more complicated to use. · The use of the FLU matrix shall be divided in time into two periodic time windows. ○One time window is reserved for real-time applications ○One time window is reserved in the HSM · The FLU is configured to switch tasks between both contexts. Microarchitectural principles make it possible to demonstrate the mutual independence of secure and insecure parts of the FLU.

[0078] The difficulty here is to properly handle the FHSM boundary as described, since the matrix must switch between secure and non-secure boundaries. This makes the switching procedure more complicated than switching between two application tasks. The mechanism to do this is shown in Figure 9 (0900). Naturally, for security reasons, all sequences must be managed exclusively by the HSM module. The previous sequence is technically possible. However, for real-time applications, the latency between the two FLU execution windows must be verified, due to the configuration of the MPU.

[0079] The electrical device described above, in which one or more of the above functional modules, which are essentially hardware programmable units that are programmable logic matrices, are configured to sequentially perform at least two tasks, and / or which comprises a plurality of flexible logic unit structures preferably arranged side by side and (at run time) physically connected or separated and configured to pair, and which describes the relationship switching mechanism, must be configured to properly handle the FHSM requirements.

[0080] Use Cases for FHSM Hardware Acceleration Using the FHSM concept, it is possible to dedicate some eFPGA resources and math accelerators to the secure subsystem, so that new cryptographic algorithms can be implemented.

[0081] Such an approach has the following advantages over a simple software implementation of the algorithm: · FPGA architectures offer massively parallel computing capabilities, making them particularly suitable for running cryptographic algorithms. The power fluctuation signature of FPGA operation is much noisier than the signature of a CPU core, making algorithmic operations more resistant to non-invasive security attacks. - The performance of cryptographic algorithms is higher when implemented in hardware.

[0082] Here, essentially, the electrical device according to the present invention is used in which one or more of the above functional modules, which are a hardware programmable unit (0202) that is a programmable logic matrix, are configured to at least partially perform an encryption method.

[0083] Safe Security Now consider a simple FPCU architecture featuring two FLU matrices. One is assigned to the real-time application The second one is assigned to FHSM

[0084] The first FLU content cannot access information from the second FLU content (FHSM boundary as described above)

[0085] However, it is not a security concern for the second FLU portion to access information in the first FLU portion, so the secure FLU content can have real-time information of the behavior of running applications.

[0086] This feature allows for tight synchronization between secure and application activities.

[0087] It is also possible to implement cryptographic algorithms in the FLU matrix and replicate reference algorithms implemented in the hard part of the FHSM or in software, allowing a lock-step implementation of security algorithms and the correctness of the execution of the replicated algorithms can be checked.

[0088] Several implementations are possible here. The algorithm replicated in the FLU is exactly the same as the reference algorithm (same RTL). In this case, spatial and temporal redundancy is ensured. The algorithm replicated in the FLU is different from the reference algorithm (same functionality, different RTL). In this case, spatial and temporal redundancy and correctness of results are guaranteed (two different algorithms produce the same result).

[0089] Secure Attack Detection (Digital Sensors) An eFPGA matrix such as the FLU can be configured to be able to detect invasive and semi-invasive attacks based on physical effects on internal propagation delays.

[0090] countermeasure Just as the FLU matrix is ​​intended for the implementation of new cryptographic algorithms, the FLU matrix of the FHSM can also implement some hardware countermeasures to improve the security level of the component against new attack methods.

[0091] For example, some random noise can be generated by the FLU to shuffle the power profile of the component and make it more resistant to side-channel attacks. [Item 1] An electrical device comprising: (1) functional modules (0101, 0102, 0103, 0104) capable of acting as both a transaction initiator or a transaction target, where a transaction initiation functional module may require a transaction target functional module to perform a function on behalf of the transaction initiation functional module; and (2) a first interconnect structure (0106) connecting the functional modules and providing communication between the functional modules, the electrical device being configured such that a selected transaction initiation functional module has temporary exclusive access to one or more transaction target functional modules performing a function on behalf of the selected transaction initiation functional module to ensure that transaction initiation functional modules other than the selected transaction initiation functional module do not have uncontrolled access to the transaction target functional module, the selected transaction initiation functional module being a hardware secure module (0105). The electrical device comprises: In order to ensure that a selected transaction initiation function module has temporarily exclusive access to one or more transaction target function modules which perform functions on behalf of the selected transaction initiation function module, protection means (0601, 0602) are provided for ensuring that transaction initiation function modules other than the selected transaction initiation function module do not have uncontrolled access to the transaction target function modules, the protection means comprises one or more protection units for each of the transaction target functional modules, the protection units being provided between the module and a portion of the first interconnect structure, the configuration of the protection units being controlled by the selected transaction initiation functional module; 1. An electrical device comprising: [Item 2] 2. The electrical device of claim 1, wherein the protection unit provides transaction filtering. [Item 3] 3. The electrical device of claim 1 or 2, wherein a transaction initiation function module other than the selected transaction initiation function module only accesses via the first interconnect structure after the other transaction initiation function module has initiated a service request to the selected transaction initiation function module by the other transaction initiation function module to appropriately configure protection units connected to such other transaction initiation function module, in accordance with the approval of the selected transaction initiation function module. [Item 4] The electrical device of item 1, wherein one or more protection units are further connected by one or more second interconnect structures (0603) to configure the protection units, thereby providing one or more additional protection units between the first interconnect structure and the second interconnect structure, and the configuration of the additional protection units is controlled by the selected transaction initiation function module. [Item 5] The electrical device of any one of items 1 to 4, wherein the first interconnect structure connecting the functional modules and providing communication between those functional modules comprises a third interconnect structure for exchanging task-specific trigger signals between the functional modules, the third interconnect structure comprising a trigger router module (0303) capable of routing any input trigger to any output trigger, the trigger router module being configured to ensure that no transaction initiation functional module other than the selected transaction initiation functional module has uncontrolled access to the trigger router module via the third interconnect structure. [Item 6] Item 6. The electrical device of item 5, wherein the trigger router module is configurable via the second interconnect structure. [Item 7] 7. The electrical device of any one of claims 1 to 6, wherein the first interconnect structure connecting the functional modules and providing communication between them comprises a fourth interconnect structure comprising direct connections between some of the functional modules, whereby the protection means ensures that transaction initiation functional modules other than the selected transaction initiation functional module do not have uncontrolled access via the fourth interconnect structure to the one or more modules performing functions on behalf of the selected transaction initiation functional module. [Item 8] 8. The electrical device of any one of claims 1 to 7, wherein accesses of a transaction initiating functional module to a transaction target functional module are partially organized via a system bus and an access unit, preferably supporting memory mapping, to filter said accesses based on transaction action characteristics. [Item 9] 9. The electrical device of claim 8, wherein the access unit functions as the protection unit. [Item 10] An electrical device according to any one of items 1 to 9, wherein one or more of the functional modules, which are hardware programmable units (0202) that are programmable logic matrices, are preferably configured to sequentially perform at least two tasks, and / or preferably comprise a plurality of flexible logic unit structures arranged side by side and configured to be physically connected or separated. [Item 11] 11. The electrical device of any one of claims 1 to 10, wherein one or more of the functional modules is optionally a peripheral hardware unit (0203) dedicated to electrical control unit hardware functions or mathematical accelerator functions. [Item 12] 12. The electrical device according to any one of claims 1 to 11, wherein one or more of the functional modules is a software programmable unit (0101), preferably a microprocessor core or a graphic processor core. [Item 13] The electrical device according to items 10 and 11, or items 10 and 12, or items 10, 11, and 12, which is a heterogeneous hardware system.

[0092] Drawing translation Figure 1 0101 CPU core(s) CPU core(s) 0102 FLU matrices FLU matrix 0103 AxEC Peripherals AxEC peripherals 0105 HSM boundary HSM boundary Figure 2 0203 Periph#2 Peripheral #2 0205 HSM boundary HSM boundary CPU core(s) CPU core(s) Periph#1 Peripheral #1 Periph#n Peripheral #n Figure 3 0301 module#1 0302 module#2 0303 Trigger router module System bus module#n module#n Figure 4 0401 module#1 0402 module#2 module#n module#n Trigger router module Figure 5 module#1 module#2 module#n module#n HSM boundary HSM boundary Trigger router module System bus Figure 6 0603 Secure configuration interconnect Other initiators System interconnect Periph#1 Peripheral #1 Figure 7 Other initiators System interconnect Periph#1 Peripheral #1 Secure configuration interconnect Figure 8 HSM boundary HSM boundary Other initiators System interconnect Periph#1 Peripheral #1 Secure configuration interconnect Figure 9 Task switching requested Stop FLU execution Re-configure MPUs Perform configuration and data context switch Resume FLU execution

Claims

1. An electrical device comprising: (1) a functional module capable of acting as both a transaction initiator or a transaction target, where a transaction initiation functional module may require a transaction target functional module to perform a function on behalf of the transaction initiation functional module; and (2) a first interconnect structure connecting the functional modules to provide communication between the functional modules, the electrical device being configured to ensure that transaction initiation functional modules other than the selected transaction initiation functional module do not have uncontrolled access to the transaction target functional modules by a selected transaction initiation functional module having temporary exclusive access to one or more transaction target functional modules performing functions on behalf of the selected transaction initiation functional module, the selected transaction initiation functional module being a hardware secure module. To ensure that a selected transaction initiation function module has temporarily exclusive access to one or more transaction target function modules performing functions on behalf of the selected transaction initiation function module, protection means are provided for ensuring that transaction initiation function modules other than the selected transaction initiation function module do not have uncontrolled access to the transaction target function modules; the protection means comprises one or more protection units for each of the transaction target functional modules, the protection units being provided between the functional modules and a portion of the first interconnect structure, the configuration of the protection units being controlled by the selected transaction initiation functional module; Electrical equipment.

2. The electrical device of claim 1 , wherein the protection unit provides transaction filtering.

3. 3. The electrical device of claim 1 or 2, wherein a transaction initiation function module other than the selected transaction initiation function module only accesses via the first interconnect structure after the other transaction initiation function module has initiated a service request to the selected transaction initiation function module for appropriately configuring protection units connected to such other transaction initiation function module, subject to approval by the selected transaction initiation function module.

4. 2. The electrical device of claim 1, wherein one or more protection units are further connected by one or more second interconnect structures to configure the protection units, thereby providing one or more additional protection units between the first interconnect structure and the second interconnect structure, and configuration of the additional protection units is controlled by the selected transaction initiation function module.

5. 5. The electrical device of claim 1, wherein the first interconnect structure connecting the functional modules and providing communication between them comprises a third interconnect structure for exchanging task-specific trigger signals between the functional modules, the third interconnect structure comprising a trigger router module capable of routing any input trigger to any output trigger, the trigger router module being configured to ensure that no transaction initiating functional module other than the selected transaction initiating functional module has uncontrolled access to the trigger router module via the third interconnect structure.

6. 6. An electrical device according to claim 5 when dependent on claim 4, wherein the trigger router module is configurable via the second interconnect structure.

7. 7. An electrical device as claimed in any one of claims 1 to 6, wherein the first interconnect structure connecting the functional modules and providing communication between them comprises a fourth interconnect structure comprising direct connections between some of the functional modules, whereby the protection means ensures that transaction initiation functional modules other than the selected transaction initiation functional module do not have uncontrolled access via the fourth interconnect structure to the one or more modules performing functions on behalf of the selected transaction initiation functional module.

8. 8. An electrical device as claimed in claim 1, wherein accesses of a transaction initiating functional module to a transaction target functional module are partly organised via a system bus and an access unit supporting memory mapping to filter said accesses based on transaction action characteristics.

9. The electrical device of claim 8 , wherein the access unit functions as the protection unit.

10. 10. The electrical device of claim 1, wherein one or more of the functional modules being hardware programmable units being programmable logic matrices are configured to sequentially perform at least two tasks and / or comprise a plurality of flexible logic unit structures arranged side by side and configured to be physically connected or separated.

11. 11. Electrical device according to any one of the preceding claims, wherein one or more of the functional modules is optionally a peripheral hardware unit dedicated to electrical control unit hardware functions or mathematical accelerator functions.

12. An electrical device according to any preceding claim, wherein one or more of the functional modules are software programmable units.

13. 13. An electrical device according to claim 10 and claim 11, or claim 10 and claim 12, or claim 10, claim 11 and claim 12, which is a heterogeneous hardware system.

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