Image Sensor

Abstract

To provide an image sensor with smaller wiring.SOLUTION: An image sensor includes a substrate with a first surface and a second surface that face each other, photoelectric conversion regions provided in the substrate, a separation pattern provided between the photoelectric conversion regions in the substrate, a conductive connection pattern disposed on the separation pattern and provided in a trench penetrating the first surface of the substrate, and a first impurity region disposed adjacent to the first surface of the substrate in the substrate. A first side wall of the conductive connection pattern is in contact with the first impurity region. The dopant included in the conductive connection pattern includes the same element as the impurity added to the first impurity region.SELECTED DRAWING: Figure 2B

Description

[Technical field]

[0001] The present invention relates to image sensors, and more particularly to electrical connections between components in a pixel region of an image sensor. [Background technology]

[0002] An image sensor is a device that converts an optical image into an electrical signal. Image sensors are classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. CMOS type image sensors are abbreviated as CIS (CMOS image sensor). CIS has multiple pixels arranged two-dimensionally. Each pixel contains a photodiode (PD). The photodiode converts incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,609,250 [Patent Document 2] U.S. Pat. No. 10,170,517 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide an image sensor having miniaturized wiring. [Means for solving the problem]

[0005] In order to achieve the above object, an image sensor according to one aspect of the present invention includes a substrate having a first surface and a second surface facing each other, a photoelectric conversion region provided in the substrate, an isolation pattern provided between the photoelectric conversion regions in the substrate, a conductive connecting pattern disposed on the isolation pattern and provided in a trench penetrating the first surface of the substrate, and a first impurity region disposed in the substrate adjacent to the first surface of the substrate, wherein a first sidewall of the conductive connecting pattern contacts the first impurity region, and a dopant contained in the conductive connecting pattern includes the same element as an impurity doped into the first impurity region.

[0006] According to another aspect of the present invention, an image sensor that has been made to achieve the above object includes a substrate having a first surface and a second surface facing each other, an isolation pattern penetrating the substrate to define a pixel region, a conductive connecting pattern provided on the isolation pattern and provided in a trench penetrating the first surface of the substrate, and an impurity region disposed within the substrate adjacent to the first surface of the substrate, the impurity region including a first impurity region in contact with a first sidewall of the conductive connecting pattern and a second impurity region in contact with a second sidewall opposite to the first sidewall of the conductive connecting pattern, and the conductive connecting pattern includes a doped semiconductor material.

[0007] According to another aspect of the present invention, there is provided an image sensor comprising: a substrate having a first surface and a second surface facing each other; an isolation pattern defining first and second pixel regions in the substrate; a photoelectric conversion region provided in each of the first and second pixel regions in the substrate; a first impurity region provided in the first pixel region of the substrate and adjacent to the first surface of the substrate; a second impurity region provided in the second pixel region of the substrate and adjacent to the first surface of the substrate; a conductive connection pattern disposed between the first impurity region and the second impurity region and provided in a trench penetrating the first surface of the substrate; and a conductive connection pattern provided on the first surface of the substrate. a gate pattern spaced apart from an electrical connecting pattern; a gate insulation pattern interposed between the substrate and the gate pattern; a wiring layer disposed on a first surface of the substrate and including an insulating layer and a wiring structure; a color filter disposed on a second surface of the substrate; and a microlens on the color filter, wherein the separation pattern includes an insulating separation pattern and a conductive separation pattern provided in the insulating separation pattern, the conductive connection pattern vertically overlapping the conductive separation pattern, the conductive connection pattern physically contacting the first impurity region and the second impurity region and electrically connected to the first impurity region and the second impurity region. Effect of the Invention

[0008] According to the present invention, a conductive connection pattern is provided between the impurity regions of two adjacent pixel regions and electrically connected to the impurity regions, so that the components of the image sensor are simplified, allowing for more flexible design and miniaturization of the image sensor. [Brief description of the drawings]

[0009] [Figure 1] 2 is a circuit diagram of a pixel of an image sensor according to an embodiment. [Figure 2A] FIG. 1 is a plan view illustrating a first example of an image sensor according to an embodiment. [Figure 2B]FIG. 2B is a cross-sectional view taken along line I-II in FIG. 2A. [Figure 2C] FIG. 2C is an enlarged view of region V in FIG. 2B. [Figure 2D] FIG. 2B is a cross-sectional view taken along line III-IV in FIG. 2A. [Figure 2E] 1 is a diagram illustrating a contact plug of an image sensor according to an embodiment; [Figure 3A] FIG. 4 is a plan view illustrating a second example of an image sensor according to an embodiment. [Figure 3B] FIG. 3B is a cross-sectional view taken along line I-II in FIG. 3A. [Figure 4A] FIG. 11 is a plan view illustrating a third example of an image sensor according to an embodiment. [Figure 4B] FIG. 4B is a cross-sectional view taken along line I-II in FIG. 4A. [Figure 5A] FIG. 11 is a plan view illustrating a fourth example of an image sensor according to an embodiment. [Figure 5B] FIG. 5B is a cross-sectional view taken along line I-II in FIG. 5A. [Figure 5C] FIG. 5B is a cross-sectional view taken along line VI-IV in FIG. 5A. [Figure 6A] FIG. 13 is a plan view illustrating a fifth example of an image sensor according to an embodiment. [Figure 6B] FIG. 6B is a cross-sectional view taken along line I-II in FIG. 6A. [Figure 6C] FIG. 7 is a cross-sectional view taken along line VII-VIII in FIG. 6A. [Figure 6D] FIG. 6B is a cross-sectional view taken along line VI-IV in FIG. 6A. [Figure 7A] FIG. 13 is a plan view illustrating a sixth example of an image sensor according to an embodiment. [Figure 7B] FIG. 7B is a cross-sectional view taken along line VI-IV in FIG. 7A. [Figure 8A] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 8B] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 8C] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 8D] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 8E] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 8F] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 8G] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 8H] 1A to 1C are diagrams illustrating an example of manufacturing an image sensor according to an embodiment. [Figure 9A] 11A to 11C are diagrams illustrating another example of manufacturing an image sensor according to an embodiment. [Figure 9B] 11A to 11C are diagrams illustrating another example of manufacturing an image sensor according to an embodiment. [Figure 9C] 11A to 11C are diagrams illustrating another example of manufacturing an image sensor according to an embodiment. [Figure 9D] 11A to 11C are diagrams illustrating another example of manufacturing an image sensor according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, specific examples of embodiments of an image sensor and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In this specification, the same reference numerals refer to the same elements throughout. An image sensor and a method for manufacturing the same according to an embodiment of the present invention will be described.

[0011] FIG. 1 is a circuit diagram of a pixel of an image sensor according to one embodiment.

[0012] 1, each pixel of the image sensor includes a photoelectric conversion region PD, a transfer transistor Tx, a source follower transistor Sx, a reset transistor Rx, and a selection transistor Ax. The transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax each include a transfer gate TG, a source follower gate SG, a reset gate RG, and a selection gate AG.

[0013] The photoelectric conversion region PD is a photodiode including an N-type impurity region and a P-type impurity region. The floating diffusion region FD functions as the drain of the transfer transistor Tx. The floating diffusion region FD functions as the source of a reset transistor Rx. The floating diffusion region FD is electrically connected to a source follower gate SG of a source follower transistor Sx. The source follower transistor Sx is connected to a selection transistor Ax. For example, the drain electrode / region of the source follower transistor Sx corresponds to the source electrode / region of the selection transistor Ax.

[0014] The operation of the image sensor will be described with reference to FIG. 1. First, when light is blocked, a power supply voltage V is applied to the drain of the reset transistor Rx and the drain of the source follower transistor Sx. DDWhen a voltage is applied to the source follower transistor Sx, the reset transistor Rx is turned on and the charge remaining in the floating diffusion region FD is released. Thereafter, when the reset transistor Rx is turned off and external light is incident on the photoelectric conversion region PD, electron-hole pairs are generated in the photoelectric conversion region PD. The holes move to the P-type impurity region of the photoelectric conversion region PD and the electrons move to the N-type impurity region and are stored there. When the transfer transistor Tx is turned on, these charges such as electrons and holes are transferred to and stored in the floating diffusion region FD. The gate bias of the source follower transistor Sx changes in proportion to the amount of stored charge, resulting in a change in the source potential of the source follower transistor Sx. At this time, when the selection transistor Ax is turned on, a signal V OUT is read out.

[0015] 1 illustrates a pixel having one photoelectric conversion region PD and four transistors (Tx, Rx, Ax, Sx), but the embodiment according to the present invention is not limited thereto. For example, a plurality of pixels may be provided, and the reset transistor Rx, the source follower transistor Sx, or the selection transistor Ax may be shared by adjacent pixels. This increases the integration density of the image sensor.

[0016] FIG 2A is a plan view showing a first example of an image sensor according to an embodiment. FIG 2B is a cross-sectional view taken along line I-II in FIG 2A. FIG 2C is an enlarged view of region V in FIG 2B. FIG 2D is a cross-sectional view taken along line III-IV in FIG 2A. Below, the contents overlapping with those described above will be omitted.

[0017] 2A to 2D, the image sensor 1 includes a substrate 100, an isolation pattern 210, an element insulating pattern 220, a conductive connecting pattern 310, a gate pattern 500, and a wiring layer 400. The substrate 100 has a plurality of pixel regions PX. The pixels described with reference to FIG. 1 are formed in the pixel regions PX of the substrate 100. For example, components of the pixels are provided on the pixel regions PX. The pixel regions PX include a first pixel region PX1 and a second pixel region PX2 in a plan view. The first pixel region PX1 is adjacent to the second pixel region PX2 and is spaced apart from the second pixel region PX2 in a first direction D1 or in a direction opposite to the first direction D1. The substrate 100 has a first surface 100a and a second surface 100b facing each other. The first surface 100a of the substrate 100 is a front surface, and the second surface 100b of the substrate 100 is a rear surface. For example, the substrate 100 is a semiconductor substrate or a silicon on insulator (SOI) substrate. The semiconductor substrate includes, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 includes impurities of a first conductivity type. For example, the impurities of the first conductivity type include P-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga). In this specification, the impurities refer to dopants.

[0018] The first direction D1 is parallel to the first surface 100a of the substrate 100. The second direction D2 is parallel to the first surface 100a of the substrate 100 and intersects the first direction D1. The third direction D3 is substantially perpendicular to the first direction D1 and the second direction D2. The third direction D3 corresponds to the depth direction of the image sensor 1.

[0019] The photoelectric conversion regions PD are each disposed in a pixel region PX within the substrate 100. The photoelectric conversion regions PD are disposed between the first surface 100a and the second surface 100b of the substrate 100. Each of the photoelectric conversion regions PD performs the same function and role as the photoelectric conversion region PD of FIG. 1. The photoelectric conversion regions PD are regions doped with impurities of a second conductivity type. The impurities of the second conductivity type have a conductivity type opposite to that of the impurities of the first conductivity type. The impurities of the second conductivity type include N-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. Each of the photoelectric conversion regions PD is disposed deep from the first surface 100a of the substrate 100.

[0020] An impurity region 111 is disposed in each pixel region PX. The impurity region 111 is disposed in the substrate 100 adjacent to the first surface 100a of the substrate 100. The bottom surface of the impurity region 111 is separated from the photoelectric conversion region PD. The impurity region 111 is a doped region. The impurity region 111 contains impurities of a first conductivity type. The impurity region 111 is a ground region. The impurity region 111 contains impurities of the same conductivity type as the substrate 100, for example, impurities of the first conductivity type. The impurity concentration of the impurity region 111 is greater than the impurity concentration doped into the substrate 100.

[0021] The impurity regions 111 of any two adjacent pixel regions PX are arranged symmetrically to each other. The impurity regions 111 include a first impurity region 111A and a second impurity region 111B. The first impurity region 111A is provided in the first pixel region PX1, and the second impurity region 111B is provided in the second pixel region PX2. The first impurity region 111A is arranged symmetrically to the second impurity region 111B. Each of the first impurity region 111A and the second impurity region 111B is a ground region. Each of the first impurity region 111A and the second impurity region 111B is a floating diffusion region.

[0022] The doped regions 112 are disposed in the pixel regions PX in the substrate 100. The doped regions 112 are disposed in the substrate 100 adjacent to the first surface 100a of the substrate 100. The bottom surfaces of the doped regions 112 are spaced apart from the photoelectric conversion regions PD. Each of the doped regions 112 includes impurities of a second conductivity type.

[0023] Each of the doping regions 112 is an active region. Here, the active region means a region for the operation of a transistor, and includes the floating diffusion region FD and the source / drain region of the transistor described with reference to Fig. 1. The transistor includes the transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, or the selection transistor Ax described with reference to Fig. 1.

[0024] A device insulation pattern 220 is provided in the substrate 100. The device insulation pattern 220 is provided in a first trench 229, and the first trench 229 is recessed from the first surface 100a of the substrate 100. The device insulation pattern 220 is a shallow device isolation STI film. A lower surface of the device insulation pattern 220 is provided in the substrate 100. The device insulation pattern 220 is disposed on one side of either the impurity region 111 or the doping region 112 in the substrate 100. The device insulation pattern 220 defines an active region or a ground region. Specifically, in each pixel region PX, the device insulation pattern 220 defines the impurity region 111 or the doping region 112, and the impurity region 111 is separated from the doping region 112 by the device insulation pattern 220. When a plurality of doping regions 112 are provided in at least one of the pixel regions PX, the doping regions 112 are separated from each other by the device insulation pattern 220. The device insulation pattern 220 includes, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0025] The isolation pattern 210 is provided in the substrate 100 to define the pixel region PX. For example, the isolation pattern 210 is provided between the pixel regions PX of the substrate 100. The isolation pattern 210 is provided in a second trench 219, which is recessed from the first surface 100a of the substrate 100. The second trench 219 penetrates the first surface 100a of the substrate 100. The isolation pattern 210 is a deep device isolation (Deep Trench Isolation) film. The lower surface of the isolation pattern 210 is disposed at a lower level than the lower surface of the device insulating pattern 220. The lower surface of the isolation pattern 210 is coplanar with the second surface 100b of the substrate 100 or adjacent to the second surface 100b of the substrate 100. For example, the isolation pattern 210 penetrates the second surface 100b of the substrate 100. The width of the upper surface of the isolation pattern 210 is greater than the width W of the lower surface of the isolation pattern 210. The width W of the lower surface of the separated pattern 210 is 0.03 μm to 0.08 μm. The separated pattern 210 is disposed in the substrate 100 between adjacent photoelectric conversion regions PD.

[0026] The isolation pattern 210 includes a first insulating isolation pattern 211, a second insulating isolation pattern 212, and a conductive isolation pattern 215. The first insulating isolation pattern 211 is provided along a sidewall of the second trench 219. The first insulating isolation pattern 211 does not extend to the top of the second trench 219. The first insulating isolation pattern 211 includes, for example, a silicon-based insulating material and / or a high-k material. In this specification, the silicon-based insulating material includes, for example, silicon nitride, silicon oxide, and / or silicon oxynitride. In this specification, the high-k material includes, for example, hafnium oxide and / or aluminum oxide. Although not shown, the first insulating isolation pattern 211 includes a plurality of layers, and the plurality of layers include different materials. The first insulating isolation pattern 211 has a lower refractive index than the substrate 100. Therefore, the crosstalk phenomenon between the pixel regions PX of the substrate 100 can be prevented / reduced.

[0027] The conductive isolation pattern 215 is provided within the first insulating isolation pattern 211. For example, a sidewall of the conductive isolation pattern 215 is surrounded by the first insulating isolation pattern 211. The first insulating isolation pattern 211 is interposed between the conductive isolation pattern 215 and the substrate 100. Thus, during operation of the image sensor 1, the conductive isolation pattern 215 is electrically isolated from the substrate 100. The conductive isolation pattern 215 includes a crystalline semiconductor material, for example, polysilicon. For example, the conductive isolation pattern 215 includes doped polysilicon. For example, the conductive isolation pattern 215 further includes a dopant, which is a first conductive type or a second conductive type dopant.

[0028] The second insulating isolation pattern 212 is provided in the second trench 219 on an upper surface of the first insulating isolation pattern 211 and an upper surface of the conductive isolation pattern 215. The second insulating isolation pattern 212 includes, for example, a silicon-based insulating material and / or a high dielectric material. The second insulating isolation pattern 212 has a lower refractive index than the substrate 100.

[0029] A conductive terminal 217 is provided on the second surface 100b of the substrate 100 and is connected to the conductive separation pattern 215. For example, the conductive terminal 217 is provided on any one of the pixel regions PX or outside any one of the pixel regions PX. Any one of the pixel regions PX is the outermost pixel region. The conductive terminal 217 is a terminal configured to receive a first voltage. The first voltage is, for example, a negative bias voltage. The first voltage is applied to the conductive separation pattern 215 through the conductive terminal 217. Thus, during operation of the image sensor 1, electrons (e.g., noise electrons) generated by interface defects between the separation pattern 210 and the substrate 100 are removed. The interface defects are formed, for example, on the sidewalls of the second trenches 219. The image quality of the image sensor 1 can be improved by removing the interface defects.

[0030] A conductive connecting pattern 310 is provided in the substrate 100. The conductive connecting pattern 310 is provided in a third trench 239, which is recessed from the first surface 100a of the substrate 100. The third trench 239 is disposed in the second insulating separation pattern 212 as shown in FIG. 2D. The upper surface of the conductive connecting pattern 310 is disposed at substantially the same level as the first surface 100a of the substrate 100 and the upper surfaces of the second insulating separation pattern 212. The width of the upper surface of the conductive connecting pattern 310 is greater than the width of the lower surface of the conductive connecting pattern 310. The length of the upper surface of the conductive connecting pattern 310 is greater than the length of the lower surface of the conductive connecting pattern 310. The conductive connecting pattern 310 is overlapped with the separation pattern 210 in a plan view as shown in FIG. 2A. The conductive connecting pattern 310 is overlapped vertically with the conductive separation pattern 215 as shown in FIG. 2B. The second insulating separation pattern 212 is interposed between the conductive separation pattern 215 and the conductive connecting pattern 310. The conductive connecting pattern 310 is electrically isolated from the conductive separating pattern 215 by the second insulating separating pattern 212 .

[0031] The conductive connecting pattern 310 is provided between the impurity regions 111 of two adjacent pixel regions PX and is electrically connected to the impurity regions 111. For example, the conductive connecting pattern 310 is interposed between a first pixel region PX1 and a second pixel region PX2. The conductive connecting pattern 310 has a first sidewall 310a and a second sidewall 310b facing each other as shown in FIG. 2C. The first sidewall 310a of the conductive connecting pattern 310 contacts the first impurity region 111A. The second sidewall 310b of the conductive connecting pattern 310 contacts the second impurity region 111B. The conductive connecting pattern 310 is electrically connected to the first impurity region 111A and the second impurity region 111B.

[0032] The conductive connecting pattern 310 includes a doped semiconductor material. The conductive connecting pattern 310 includes a crystalline semiconductor material and a dopant. As an example, the conductive connecting pattern 310 includes doped polysilicon. The dopant included in the conductive connecting pattern 310 has the same conductivity type as the impurity doped in the impurity region 111. The dopant included in the conductive connecting pattern 310 is the same element as the impurity doped in the impurity region 111. That is, the dopant included in the conductive connecting pattern 310 is the same element as the impurity doped in the first impurity region 111A and the impurity doped in the second impurity region 111B. The doping concentration of the conductive connecting pattern 310 may be the same as or different from the doping concentration of the impurity region 111. The doping depth of the conductive connecting pattern 310 is the same as the depth of the impurity region 111. Alternatively, the doping depth of the conductive connecting pattern 310 may be different from the depth of the impurity region 111. As another example, the conductive connecting pattern 310 includes a metal material.

[0033] A gate pattern 500 is disposed on the first surface 100a of the substrate 100. The gate pattern 500 does not overlap the separation pattern 210 in a plan view. The gate pattern 500 functions as a gate electrode of the transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, or the selection transistor Ax previously described in FIG. 1. For example, the gate pattern 500 includes a transfer gate TG, a source follower gate SG, a reset gate RG, or a selection gate AG. Although a single gate pattern 500 is illustrated as being disposed on each pixel region PX for simplification in FIGS. 2A to 2C, a plurality of gate patterns 500 are disposed on each pixel region PX. Hereinafter, a single gate pattern 500 will be described for simplification.

[0034] The gate pattern 500 has a buried gate structure. For example, the gate pattern 500 includes a first portion 500A and a second portion 500B as shown in FIG. 2C. The first portion 500A of the gate pattern 500 is disposed on the first surface 100a of the substrate 100. The first portion 500A of the gate pattern 500 extends in a direction parallel to the first surface 100a of the substrate 100. The second portion 500B of the gate pattern 500 protrudes into the substrate 100. The second portion 500B of the gate pattern 500 is connected to the first portion 500A. The gate pattern 500 includes a metal material, a metal silicide material, polysilicon, and a combination thereof. A gate insulating pattern 510 is interposed between the gate pattern 500 and the substrate 100. The gate insulating pattern 510 includes, for example, a silicon-based insulating material and / or a high dielectric material. The gate spacer 520 covers the sidewalls of the first portion 500A of the gate pattern 500 on the first surface 100a of the substrate 100. The gate spacer 520 includes a semiconductor nitride, such as silicon nitride, silicon carbonitride, or silicon oxynitride.

[0035] The wiring layer 400 is disposed on the first surface 100a of the substrate 100. The wiring layer 400 includes a first insulating layer 410, a second insulating layer 420, a third insulating layer 430, and a wiring structure 440. The first insulating layer 410 covers the first surface 100a of the substrate 100, the conductive connection pattern 310, and the gate spacer 520. The second insulating layer 420 is provided on the upper surface of the first insulating layer 410. The second insulating layer 420 is a multi-layer, or the second insulating layer 420 is omitted. The third insulating layer 430 is stacked on the second insulating layer 420. The first to third insulating layers (410, 420, 430) include silicon-based insulating materials, such as silicon oxide, silicon nitride, and / or silicon oxynitride. The wiring structure 440 includes vias and wiring. The wiring is interposed between the first to third insulating layers (410, 420, 430). The via is connected to the wiring by penetrating the second insulating layer 420 or the third insulating layer 430. Although not shown, the wiring structure 440 is electrically connected to at least one of the gate pattern 500, the impurity region 111, and the doping region 112.

[0036] The contact plugs 450 are provided in the first insulating layer 410 and penetrate the first insulating layer 410. The contact plugs 450 further penetrate the second insulating layer 420. The contact plugs 450 include a conductive material such as a metal. When the conductive connection pattern 310 is omitted, the plurality of contact plugs 450 are connected to the first impurity region 111A and the second impurity region 111B, respectively. That is, the total number of contact plugs 450 is the same as the total number of pixel regions PX. Here, the contact plugs 450 refer to contact plugs electrically connected to the impurity regions 111.

[0037] According to the present embodiment, the conductive connecting pattern 310, the first impurity region 111A, and the second impurity region 111B form a shared structure 300. A single contact plug 450 is disposed on any one of the first impurity region 111A, the second impurity region 111B, and the conductive connecting pattern 310. For example, the contact plug 450 is provided on the first impurity region 111A, and the contact plug 450 is not disposed on the second impurity region 111B and the conductive connecting pattern 310. The single contact plug 450 is provided as an electrical path between the first impurity region 111A, the second impurity region 111B, and the conductive connecting pattern 310. During operation of the image sensor 1, a second voltage is applied to the first impurity region 111A, the second impurity region 111B, and the conductive connecting pattern 310 through the contact plug 450. The second voltage is a ground voltage and is different from the first voltage. By providing the shared structure 300, the total number of contact plugs 450 becomes smaller than the total number of pixel regions PX. Therefore, the degree of freedom in arranging the contact plugs 450 increases, and the image sensor 1 is miniaturized. Here, the width W of the lower surface of the separation pattern 210 is 0.03 μm to 0.08 μm. If the width W of the lower surface of the separation pattern 210 is greater than 0.08 μm, it is difficult to miniaturize the image sensor 1. If the width W of the lower surface of the separation pattern 210 is less than 0.03 μm, the separation between the pixel regions PX is insufficient or the process of forming the separation pattern 210 becomes complicated.

[0038] 2E is a diagram illustrating a contact plug of an image sensor according to an embodiment, and corresponds to a cross section taken along line I-II in FIG. 2A. Hereinafter, the same content as that described above will be omitted.

[0039] 2E, a contact plug 450 of the image sensor 1 penetrates the first insulating layer 410 on the conductive connecting pattern 310. The contact plug 450 is directly connected to the conductive connecting pattern 310. The contact plug 450 is not disposed on the first impurity region 111A and the second impurity region 111B. A second voltage is applied to the first impurity region 111A and the second impurity region 111B through the single contact plug 450 and the conductive connecting pattern 310.

[0040] The substrate 100, the isolation pattern 210, the device insulating pattern 220, the conductive connecting pattern 310, the gate pattern 500, and the wiring layer 400 are substantially the same as those described with reference to FIGS. 2A to 2D.

[0041] 3A is a plan view of a second example of an image sensor according to an embodiment, and FIG 3B is a cross-sectional view taken along line I-II in FIG 3A. Hereinafter, the same content as that described above will be omitted.

[0042] 3A and 3B, the image sensor 2 includes a substrate 100, an isolation pattern 210, an element insulation pattern 220, a conductive connection pattern 310, a gate pattern 500, and a wiring layer 400. The substrate 100, the isolation pattern 210, the element insulation pattern 220, the conductive connection pattern 310, the gate pattern 500, and the wiring layer 400 are substantially the same as those described with reference to FIGS. 2A to 2D.

[0043] The impurity regions 111 are disposed in the pixel regions PX. The impurity regions 111 are disposed in the substrate 100 adjacent to the first surface 100a of the substrate 100. The impurity regions 111 are active regions. Each of the impurity regions 111 includes a floating diffusion region FD as described with reference to FIG. 1. The impurity regions 111 include impurities of a conductivity type opposite to that of the substrate 100. The impurity regions 111 include impurities of a second conductivity type (e.g., N-type impurities). The gate pattern 500 functions as a transfer gate TG as described with reference to FIG. 1, but is not limited thereto.

[0044] The conductive connecting pattern 310 is interposed between the first impurity region 111A and the second impurity region 111B and is electrically connected to the first impurity region 111A and the second impurity region 111B. The dopant in the conductive connecting pattern 310 contains the same element as the impurity doped in the first impurity region 111A and the impurity doped in the second impurity region 111B. The dopant in the conductive connecting pattern 310 has the second conductivity type. The conductive connecting pattern 310, the first impurity region 111A, and the second impurity region 111B form a shared structure 300.

[0045] 2A to 2E is not disposed on the shared structure 300. That is, no separate contact plug is provided on the conductive connecting pattern 310 and the impurity region 111.

[0046] FIG 4A is a plan view showing a third example of an image sensor according to an embodiment. FIG 4B is a cross-sectional view taken along line I-II in FIG 4A. Hereinafter, the same contents as those described above will be omitted. In the description of FIG 4A and FIG 4B, FIG 1 will be referred to.

[0047] 4A and 4B, the image sensor 3 includes a substrate 100, an isolation pattern 210, a conductive connecting pattern 310, a gate pattern 500, and a wiring layer 400. The substrate 100, the isolation pattern 210, the conductive connecting pattern 310, the gate pattern 500, and the wiring layer 400 are substantially the same as those described above. Although not shown, the image sensor 3 further includes an element insulating pattern 220 such as that described with reference to FIGS. 2A to 2D. The first impurity region 111A, the second impurity region 111B, and the conductive connecting pattern 310 form a shared structure 300.

[0048] The gate pattern 500 includes a first gate pattern 501 and a second gate pattern 502. The first gate pattern 501 is disposed on a first pixel region PX1 of the substrate 100, and the second gate pattern 502 is disposed on a second pixel region PX2 of the substrate 100. Each of the first gate pattern 501 and the second gate pattern 502 has substantially the same structure as the gate pattern 500 described with reference to FIGS. 2A to 2D. The first gate pattern 501 is a gate of a transistor having a different function from the second gate pattern 502. For example, one of the first gate pattern 501 and the second gate pattern 502 is a source follower gate SG, and the other of the first gate pattern 501 and the second gate pattern 502 is a selection gate AG. Hereinafter, for convenience of description, a case will be described in which the first gate pattern 501 is a source follower gate SG and the second gate pattern 502 is a selection gate AG, but the present embodiment is not limited thereto.

[0049] A first impurity region 111A and a second impurity region 111B are disposed in the substrate 100 adjacent to a first surface 100a of the substrate 100. The first impurity region 111A is a source / drain region of a source follower transistor. The second impurity region 111B is a source / drain region of a select transistor. The first impurity region 111A and the second impurity region 111B contain impurities of a conductivity type opposite to that of the substrate 100. The first impurity region 111A and the second impurity region 111B contain impurities of a second conductivity type (e.g., N-type impurities).

[0050] The positional relationship and electrical connection relationship between the conductive connecting pattern 310 and the impurity region 111 are substantially the same as those described in FIG. 2A to FIG. 2D. The conductive connecting pattern 310 is disposed between the first gate pattern 501 and the second gate pattern 502 in a plan view. The first impurity region 111A is disposed between the conductive connecting pattern 310 and the first gate pattern 501, and the second impurity region 111B is disposed between the conductive connecting pattern 310 and the second gate pattern 502 in a plan view. The conductive connecting pattern 310 is in physical contact with and electrically connected to the first impurity region 111A and the second impurity region 111B. However, the conductive connecting pattern 310 electrically connects the source / drain region of the source follower transistor and the source / drain region of the selection transistor. For example, the drain region of the source follower transistor is electrically connected to the source region of the selection transistor through the conductive connecting pattern 310. The dopant of the conductive connecting pattern 310 is the same element as the impurity doped into the first impurity region 111A and the second impurity region 111B.

[0051] By providing the shared structure 300, the components of the image sensor 3 are simplified and the image sensor 3 is miniaturized. For example, the first pixel region PX1 does not include a source region of a selection transistor, and the second pixel region PX2 does not include a drain region of a source follower transistor. According to the present embodiment, the components of the image sensor 3 can be designed more flexibly. The components include, for example, the impurity region 111, the doping region 112, the isolation pattern 210, the device insulation pattern 220, the gate pattern 500, and the wiring layer 400.

[0052] 2A to 2D is not disposed on the shared structure 300. That is, no separate contact plug is provided on the first impurity region 111A, the second impurity region 111B, and the conductive connecting pattern 310.

[0053] Fig. 5A is a plan view showing a fourth example of an image sensor according to an embodiment. Fig. 5B is a cross-sectional view taken along line I-II in Fig. 5A. Fig. 5C is a cross-sectional view taken along line VI-IV in Fig. 5A. Hereinafter, the contents overlapping with those described above will be omitted.

[0054] 5A to 5C, the image sensor 4 includes a substrate 100, an isolation pattern 210, an element insulation pattern 220, a conductive connection pattern 310, a gate pattern 500, and a wiring layer 400. The substrate 100, the isolation pattern 210, the gate pattern 500, and the wiring layer 400 are substantially the same as those described above.

[0055] The pixel region PX includes a first pixel region PX1, a second pixel region PX2, a third pixel region PX3, and a fourth pixel region PX4. The first pixel region PX1 and the second pixel region PX2 are adjacent to each other. The third pixel region PX3 is adjacent to the first pixel region PX1. The third pixel region PX3 is spaced apart from the first pixel region PX1 in the second direction D2 or in the opposite direction to the second direction D2. The third pixel region PX3 and the fourth pixel region PX4 are adjacent to each other. The fourth pixel region PX4 is spaced apart from the third pixel region PX3 in the first direction D1 or in the opposite direction to the first direction D1. The fourth pixel region PX4 is adjacent to the second pixel region PX2.

[0056] The impurity region 111 includes a first impurity region 111A, a second impurity region 111B, a third impurity region 111C, and a fourth impurity region 111D. The first impurity region 111A, the second impurity region 111B, the third impurity region 111C, and the fourth impurity region 111D are provided in the first pixel region PX1, the second pixel region PX2, the third pixel region PX3, and the fourth pixel region PX4, respectively. The first impurity region 111A is disposed symmetrically with respect to the second impurity region 111B and the third impurity region 111C, respectively. The second impurity region 111B and the fourth impurity region 111D are disposed symmetrically with respect to each other. The third impurity region 111C and the fourth impurity region 111D are disposed symmetrically with respect to each other.

[0057] The impurity regions 111 of the first to fourth pixel regions (PX1, PX2, PX3, PX4) are ground regions such as those described with reference to the impurity regions 111 of Figures 2A to 2D. The impurity regions 111 include a dopant of a second conductivity type (e.g., a P-type dopant).

[0058] The conductive connecting pattern 310 is in physical contact with and electrically connected to the impurity regions 111 of the first to fourth pixel regions (PX1, PX2, PX3, PX4), respectively. The dopant of the conductive connecting pattern 310 is the same element as the dopant contained in the impurity regions 111 of the first to fourth pixel regions (PX1, PX2, PX3, PX4).

[0059] The conductive connecting pattern 310 and the impurity regions 111 of the first to fourth pixel regions (PX1, PX2, PX3, PX4) form a shared structure 300. A single contact plug 450 is disposed on the conductive connecting pattern 310 and connected to the conductive connecting pattern 310. Unlike the illustrated example, the contact plug 450 may be disposed on any one of the first impurity region 111A, the second impurity region 111B, the third impurity region 111C, and the fourth impurity region 111D. A second voltage is applied to the first impurity region 111A, the second impurity region 111B, the third impurity region 111C, and the fourth impurity region 111D through the single contact plug 450.

[0060] Fig. 6A is a plan view showing a fifth example of an image sensor according to an embodiment. Fig. 6B is a cross-sectional view taken along line I-II in Fig. 6A. Fig. 6C is a cross-sectional view taken along line VII-VIII in Fig. 6A. Fig. 6D is a cross-sectional view taken along line VI-IV in Fig. 6A. Below, the contents overlapping with those described above will be omitted.

[0061] 6A to 6D, the image sensor 5 includes a wiring pattern 340 in addition to a substrate 100, an isolation pattern 210, an element insulating pattern 220, a conductive connecting pattern 310, a gate pattern 500, and a wiring layer 400. The substrate 100, the isolation pattern 210, the element insulating pattern 220, the conductive connecting pattern 310, the gate pattern 500, and the wiring layer 400 are substantially the same as those described above. A plurality of shared structures 300 are provided, and each shared structure 300 includes a conductive connecting pattern 310. Each conductive connecting pattern 310 is electrically connected to an adjacent impurity region 111. Each conductive connecting pattern 310 includes a first sidewall 310a, a second sidewall 310b, a third sidewall 310c, and a fourth sidewall 310d. The third sidewall 310c of each conductive connecting pattern 310 is adjacent to the first sidewall 310a and the second sidewall 310b. The fourth sidewall 310d of each of the conductive connecting patterns 310 faces the third sidewall 310c. The wiring pattern 340 is connected to the third sidewall 310c.

[0062] The wiring pattern 340 is provided in the fourth trench 249 as shown in FIG. 6C, and the fourth trench 249 is recessed from the first surface 100a of the substrate 100. The wiring pattern 340 has a major axis aligned in the second direction D2 in a plan view as shown in FIG. 6A. The wiring pattern 340 is connected to at least two shared structures 300. For example, the wiring pattern 340 is connected to the conductive connection pattern 310. Specifically, the wiring pattern 340 is connected to the third sidewall 310c and the fourth sidewall 310d of each of the conductive connection patterns 310 as shown in FIG. 6D. In FIG. 6D, the dotted lines are virtual lines for dividing the conductive connection pattern 310 and the wiring pattern 340, and are shown for convenience of explanation. The wiring pattern 340 includes the same material as the conductive connection pattern 310 and is connected to the conductive connection pattern 310 without an interface. For example, the wiring pattern 340 includes a crystalline semiconductor material and a dopant. As an example, the wiring pattern 340 includes doped polysilicon. The dopant included in the wiring pattern 340 has the same conductivity type as the dopant in the conductive connecting pattern 310. The dopant included in the wiring pattern 340 is the same element as the dopant in the conductive connecting pattern 310. However, the wiring pattern 340 is not limited thereto and may include various materials. For example, the wiring pattern 340 may include a metal such as copper, aluminum, titanium, and / or tungsten.

[0063] The wiring pattern 340 is superimposed on the separation pattern 210 in a plan view. As shown in FIG. 6C , the wiring pattern 340 and the conductive separation pattern 215 are vertically superimposed. The wiring pattern 340 is provided within the second insulating separation pattern 212. The second insulating separation pattern 212 is interposed between the wiring pattern 340 and the conductive separation pattern 215 and between the wiring pattern 340 and the substrate 100. The wiring pattern 340 is electrically separated from the conductive separation pattern 215 and the substrate 100 by the second insulating separation pattern 212.

[0064] A contact plug 450 penetrates the first insulating layer 410 on the wiring pattern 340 as shown in FIG. 6D. The contact plug 450 is directly connected to the wiring pattern 340. Unlike the illustrated example, the contact plug 450 is directly connected to one of the shared structures 300 rather than the wiring pattern 340. For example, the contact plug 450 is connected to one of the conductive connecting pattern 310 and the impurity regions 111. According to the present embodiment, since the wiring pattern 340 is provided, the single contact plug 450 is electrically connected to the impurity regions 111 of the multiple shared structures 300. A second voltage is applied to the impurity regions 111 of the first to fourth pixel regions (PX1, PX2, PX3, PX4) through the single contact plug 450.

[0065] Fig. 7A is a plan view illustrating a sixth example of an image sensor according to an embodiment. Fig. 7B is a cross-sectional view taken along line VI-IV in Fig. 7A. Figs. 7A and 7B will be described with reference to Figs. 6B and 6C.

[0066] 7A and 7B, the image sensor 6 includes a wiring pattern 340 in addition to a substrate 100, an isolation pattern 210, an element insulation pattern 220, a conductive connecting pattern 310, a gate pattern 500, and a wiring layer 400. The conductive connecting pattern 310 and the impurity regions 111 are substantially the same as those described with reference to Figures 5A to 5C. For example, the conductive connecting pattern 310 is in physical contact with and electrically connected to the impurity regions 111 of the first to fourth pixel regions (PX1, PX2, PX3, PX4).

[0067] 6A to 6D, except that the wiring pattern 340 includes a first wiring pattern 341 extending in a first direction D1 and a second wiring pattern 342 extending in a second direction D2. The second wiring pattern 342 is connected to the first wiring pattern 341. Unlike the illustrations, one of the first wiring pattern 341 and the second wiring pattern 342 may be omitted.

[0068] The wiring pattern 340 of the image sensor 5 of Figures 6A to 6D may include a first wiring pattern 341 and a second wiring pattern 342 as shown in Figures 7A and 7B. According to the present invention, the planar shape of the wiring pattern 340 is not limited to that of Figures 6A and 7A and may be modified in various ways.

[0069] In the image sensor 4 of Figures 5A to 5C, the image sensor 5 of Figures 6A to 6D, or the image sensor 6 of Figures 7A and 7B, the impurity region 111 is not limited to a ground region and may be modified in various ways. For example, each of the impurity regions 111 of the first to fourth pixel regions (PX1, PX2, PX3, PX4) functions as a floating diffusion region described with reference to the impurity region 111 of Figures 3 and 3B. In this case, the impurity region 111 of the pixel region PX includes impurities of a second conductivity type (e.g., N-type impurities).

[0070] As another example, each of the impurity regions 111 functions as a source / drain region as described with reference to the impurity region 111 of Figures 4A and 4B. In this case, the impurity region 111 of the pixel region PX includes impurities of a second conductivity type (e.g., N-type impurities).

[0071] Hereinafter, a method for manufacturing an image sensor according to an embodiment will be described. In the description of an example of manufacturing an image sensor, a pixel region is interpreted as including a region in which pixels are formed and a region for forming pixels, as described with reference to FIG.

[0072] Figures 8A to 8H are views for explaining an example of manufacturing an image sensor according to an embodiment, and correspond to cross sections taken along lines I-II and III-IV in Figure 2A. In the following description of Figures 8A to 8H, reference will be made to Figure 2A, and content that overlaps with that described above will be omitted.

[0073] Referring to FIG. 8A, a photoelectric conversion region PD is formed in a substrate 100. A first mask pattern 910 is formed on a first surface 100a of the substrate 100. The first mask pattern 910 includes a photoresist material. Forming the first mask pattern 910 includes applying a preliminary mask pattern (not shown) onto the substrate 100 and performing an exposure and development process on the preliminary mask pattern using a photomask (not shown). An etching process is performed on the substrate 100 using the first mask pattern 910 to form a first trench 229. The first trench 229 is a shallow trench. After the process of forming the first trench 229, the first mask pattern 910 is removed.

[0074] 8B, an insulating material is filled into the first trench 229 to form the device insulating pattern 220. The device insulating pattern 220 is localized within the first trench 229.

[0075] A second mask pattern 920 is formed on the first surface 100a of the substrate 100 to cover the first surface 100a of the substrate 100 and the device insulating pattern 220. The second mask pattern 920 includes a photoresist material. A second trench 219 is formed between the pixel regions PX in the substrate 100 by an etching process using the second mask pattern 920. The second trench 219 penetrates a portion of the substrate 100. The bottom of the second trench 219 is provided in the substrate 100. The second trench 219 is a deep trench. The depth of the second trench 219 is greater than the depth of the first trench 229. The second mask pattern 920 is then removed.

[0076] Referring to FIG. 8C, a first insulating isolation pattern 211 and a conductive isolation pattern 215 are formed in the second trench 219. The formation of the first insulating isolation pattern 211 and the conductive isolation pattern 215 includes forming a preliminary insulating isolation pattern (not shown) conformally covering the inner wall of the second trench 219, forming a preliminary conductive isolation pattern (not shown) on the preliminary insulating isolation pattern to partially fill the second trench 219, and performing a recess process on the preliminary conductive isolation pattern and the preliminary insulating isolation pattern. The recess process includes an etch-back process or a planarization process. The preliminary insulating isolation pattern and the preliminary conductive isolation pattern on the upper part of the second trench 219 are removed by the recess process. The preliminary insulating isolation pattern is recessed to form the first insulating isolation pattern 211. The preliminary conductive isolation pattern is recessed to form the conductive isolation pattern 215. The recess process is performed until the upper sidewall of the second trench 219 is exposed.

[0077] 8D, a second insulating isolation pattern 212 is formed on the first insulating isolation pattern 211 and the conductive isolation pattern 215 to fill the second trench 219. An upper surface of the second insulating isolation pattern 212 is provided at substantially the same level as the first surface 100a of the substrate 100. Thus, an isolation pattern 210 is formed. The isolation pattern 210 includes first and second insulating isolation patterns (211, 212) and a conductive isolation pattern 215.

[0078] 8E, a third mask pattern 930 is formed on the first surface 100a of the substrate 100 and the second insulating isolation pattern 212. The third mask pattern 930 exposes a portion of the second insulating isolation pattern 212. The portion of the second insulating isolation pattern 212 exposed by the third mask pattern 930 is removed to form a third trench 239. For example, a bottom surface of the third trench 239 is provided within the second insulating isolation pattern 212. The third trench 239 has a first sidewall 239a and a second sidewall 239b facing each other. The first sidewall 239a and the second sidewall 239b of the third trench 239 expose the substrate 100.

[0079] A preliminary conductive connecting pattern 310P is formed in the third trench 239. Forming the preliminary conductive connecting pattern 310P includes forming a semiconductor layer that fills the third trench 239. A recess process is further performed on the semiconductor layer to expose the first surface 100a of the substrate 100. The top surface of the preliminary conductive connecting pattern 310P is disposed at substantially the same level as the first surface 100a of the substrate 100 and the top surface of the second insulating isolation pattern 212. Then, the third mask pattern 930 is removed.

[0080] 8F, a fourth mask pattern 940 is formed on the first surface 100a of the substrate 100. The fourth mask pattern 940 includes a photoresist material. The fourth mask pattern 940 exposes the top surfaces of the preliminary conductive connection patterns 310P and a portion of the first surface 100a of the substrate 100.

[0081] Impurities are implanted into a portion of the first surface 100a of the substrate 100 and the preliminary conductive connecting pattern 310P to form the impurity region 111 and the conductive connecting pattern 310, respectively. The impurity region 111 includes a first impurity region 111A and a second impurity region 111B. The implantation of the impurities is performed using a fourth mask pattern 940. The impurities function as dopants in the conductive connecting pattern 310 and the impurity region 111. The shared structure 300 is formed by forming the impurity region 111 and the conductive connecting pattern 310. Since the impurity region 111 and the conductive connecting pattern 310 are formed in a single process, the dopant included in the conductive connecting pattern 310 includes the same element as the dopant of the impurity region 111. According to this embodiment, the process of forming the impurity region 111 and the conductive connecting pattern 310 is simplified. Thereafter, the fourth mask pattern 940 is removed.

[0082] 8G, impurities of a second conductivity type are implanted into substrate 100 to form doped region 112. Unlike what is shown, the formation of doped region 112 may be performed prior to or in a single step with the formation of impurity region 111 of FIG.

[0083] A gate insulating pattern 510 and a gate pattern 500 are formed in each pixel region PX. Gate spacers 520 are formed on the sidewalls of the gate pattern 500 on the first surface 100a of the substrate 100.

[0084] A first insulating layer 410 is formed on the first surface 100a of the substrate 100 to cover the upper surface of the impurity region 111, the upper surface of the doping region 112, the upper surface of the conductive connecting pattern 310, and the outer wall of the gate spacer 520. The first insulating layer 410 exposes the upper surface of the gate pattern 500. A second insulating layer 420 is formed on the first insulating layer 410 and the gate pattern 500. A contact plug 450 is formed to penetrate the first insulating layer 410 and the second insulating layer 420. As another example, the contact plug 450 does not penetrate the second insulating layer 420. A third insulating layer 430 is formed on the second insulating layer 420. A wiring is formed between the second insulating layer 420 and the third insulating layer 430. A via is formed in the third insulating layer 430. A wiring structure 440 is formed by forming the wiring and the via. The wiring structure 440 includes a via and a wiring. The steps of forming the wiring, the third insulating layer 430, and the vias are repeated, so that a plurality of stacked third insulating layers 430, a plurality of wirings, and a plurality of vias are formed.

[0085] 8H, a thinning process is performed on the second side 100b of the substrate 100. The thinning process may include a grinding process or a chemical mechanical polishing process. As a result of the thinning process, the isolation pattern 210 is exposed on the second side 100b of the substrate 100. As an example, the conductive isolation pattern 215 is exposed on the second side 100b of the substrate 100.

[0086] 2B and 2D, conductive terminals 217 are formed on the second surface 100b of the thinned substrate 100 and connected to the conductive separated pattern 215. A rear insulating layer 600 is formed on the second surface 100b of the thinned substrate 100 to cover the second surface 100b of the substrate 100 and the lower surface of the separated pattern 210. A color filter CF, a grid pattern 650, and a microlens 700 are formed on the lower surface of the rear insulating layer 600. According to the embodiment described above, the image sensor 1 described in FIGS. 2A to 2D is manufactured.

[0087] Unlike the above description, the impurity implantation process of Fig. 8F may include implanting impurities of the first conductivity type, and the process of forming contact plug 450 of Fig. 8G may not be performed. In this case, image sensor 2 described with reference to Figs. 3A and 3B or image sensor 3 described with reference to Figs. 4A and 4B may be manufactured.

[0088] 9A to 9D are views for explaining another example of manufacturing an image sensor according to an embodiment, and correspond to cross sections taken along lines I-II and III-IV in Fig. 2A. In the description of Figs. 9A to 9D, reference should be made to Fig. 2A, and content that overlaps with that described above will be omitted.

[0089] 9A, a photoelectric conversion region PD is formed in the substrate 100. A second mask pattern 920 is formed on a first surface 100a of the substrate 100. Forming the second mask pattern 920 includes applying a preliminary mask pattern (not shown) onto the substrate 100 and performing an exposure and development process using a photomask (not shown) on the preliminary mask pattern. A second trench 219 is formed between the pixel regions PX in the substrate 100 by an etching process using the second mask pattern 920. Thereafter, the second mask pattern 920 is removed.

[0090] 9B, a first insulating isolation pattern 211 and a conductive isolation pattern 215 are formed in the second trench 219. A second insulating isolation pattern 212 is formed on the first insulating isolation pattern 211 and the conductive isolation pattern 215 to fill the second trench 219. Thus, the isolation pattern 210 is formed. The methods of forming the first insulating isolation pattern 211, the conductive isolation pattern 215, and the second insulating isolation pattern 212 are substantially the same as those described above with reference to FIGS. 8C and 8D.

[0091] 9C, a third mask pattern 930 is formed on the first surface 100a of the substrate 100 and the second insulating isolation pattern 212. A portion of the second insulating isolation pattern 212 exposed by the third mask pattern 930 is removed to form a third trench 239. The third trench 239 exposes the second insulating isolation pattern 212 and an inner wall of the substrate 100. A preliminary conductive connecting pattern 310P is formed in the third trench 239. The formation of the third mask pattern 930, the third trench 239, and the preliminary conductive connecting pattern 310P is substantially the same as that described with reference to FIG. 8E.

[0092] 9D, a first mask pattern 910 is formed on the first surface 100a of the substrate 100, the second insulating isolation pattern 212, and the preliminary conductive connection pattern 310P. An etching process is performed on the substrate 100 using the first mask pattern 910 to form a first trench 229. The first mask pattern 910 is then removed. An insulating material is filled into the first trench 229 to form the device insulating pattern 220. The formation of the first mask pattern 910, the first trench 229, and the device insulating pattern 220 is substantially the same as that described with reference to FIGS. 8A and 8B.

[0093] 8F again, a fourth mask pattern 940 is formed on the first surface 100a of the substrate 100. An impurity implantation process using the fourth mask pattern 940 is performed on a portion of the first surface 100a of the substrate 100 and the preliminary conductive connecting pattern 310P to form impurity regions 111 and conductive connecting patterns 310. The formation of the impurity regions 111 and the conductive connecting patterns 310 forms the shared structure 300. Thereafter, the fourth mask pattern 940 is removed.

[0094] 8G, impurities of a second conductivity type are implanted into the substrate 100 to form doped regions 112. Unlike the example shown, the formation of the doped regions 112 may be performed before the formation of the impurity regions 111. A gate insulating pattern 510, a gate pattern 500, and a gate spacer 520 are formed in each pixel region PX.

[0095] A first insulating layer 410, a second insulating layer 420, a third insulating layer 430, and a wiring structure 440 are formed on the first surface 100a of the substrate 100 to form a wiring layer 400. A contact plug 450 is formed in the first insulating layer 410 and connected to one of the impurity regions 111 and the conductive connecting patterns 310.

[0096] Referring to FIG. 8H, a thinning process is performed on the second side 100b of the substrate 100 to expose the conductive isolation pattern 215 on the second side 100b of the substrate 100.

[0097] 2B, the conductive terminals 217, the rear insulating layer 600, the color filter CF, the grid pattern 650, and the microlenses 700 are formed on the second surface 100b of the substrate 100. According to the embodiments described above, the image sensor 1 described in FIGS. 2A to 2D is manufactured.

[0098] The impurity implantation process described in Fig. 8F includes a process of implanting impurities of the first conductivity type, and the process of forming contact plug 450 in Fig. 8G may not be performed. In this case, image sensor 2 described with reference to Figs. 3 and 3B or image sensor 3 described with reference to Figs. 4A and 4B is manufactured.

[0099] Although the implementation of the present invention has been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiment and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0100] 1, 2, 3, 4, 5, 6 Image Sensor 100 Substrates 100a, 100b 1st side, 2nd side 111 Impurity region 111A~111D 1st~4th impurity region 112 Doping Region 210 Separation Pattern 211, 212 First and second insulating isolation patterns 215 Conductive Separation Pattern 217 Conductive terminal 220 Element insulation pattern 229, 219, 239, 249 Trench No. 1 to 4 239a, 239b 1st and 2nd side walls 300 shared structures 310 Conductive connection pattern 310a~310d 1st~4th side wall 310P Spare conductive connection pattern 340 Wiring Pattern 341, 342 First and second wiring patterns 400 wiring layers 410, 420, 430 1st to 3rd insulating layers 440 Wiring structure 450 Contact Plug 500 Gate Pattern 500A, 500B 1st, 2nd part 501, 502 1st and 2nd gate patterns 510 Gate insulation pattern 520 Gate Spacer 600 Back insulation layer 650 Grid Pattern 700 Micro Lens 910, 920, 930, 940 1st to 4th mask patterns AG Selection Gate Ax selection transistor CF Color Filter FD Floating diffusion region PD Photoelectric conversion area PX Pixel Area PX1~PX4 1st to 4th pixel area RG Reset Gate SG Source Follower Gate Sx source follower transistor TG Transfer Gate Tx Transfer Transistor

Claims

1. a substrate having a first surface and a second surface opposed to each other; a photoelectric conversion region provided within the substrate; an isolation pattern provided between the photoelectric conversion regions in the substrate; a conductive connection pattern disposed on the isolation pattern and provided in a trench extending through the first surface of the substrate; a first impurity region disposed within the substrate adjacent to a first surface of the substrate; a second impurity region contacting a second sidewall of the conductive connecting pattern, the second sidewall being opposite to the first sidewall of the conductive connecting pattern; a first sidewall of the conductive connecting pattern contacts the first impurity region; the dopant included in the conductive connection pattern includes the same element as the impurity doped into the first impurity region; Each of the first impurity region and the second impurity region includes a floating diffusion region.

2. 2. The image sensor of claim 1, wherein the dopant included in the conductive connection pattern includes the same element as the impurity doped into the second impurity region.

3. the substrate has a first pixel area and a second pixel area defined by the separation pattern; the first impurity region is provided in a first pixel region of the substrate; 3. The image sensor of claim 2, wherein the second impurity region is provided in a second pixel region of the substrate.

4. a first gate pattern and a second gate pattern disposed on the first surface of the substrate in the first pixel region and the second pixel region, respectively; the conductive connecting pattern is interposed between the first gate pattern and the second gate pattern in a plan view; the first impurity region is disposed between the first gate pattern and the conductive connecting pattern, 4. The image sensor of claim 3, wherein the second impurity region is disposed between the second gate pattern and the conductive connecting pattern.

5. 3. The image sensor of claim 2, wherein the conductive connection pattern is electrically connected to the first impurity region and the second impurity region.

6. The separation pattern is A conductive separation pattern; an insulating isolation pattern on a sidewall and a top surface of the conductive isolation pattern; 2. The image sensor of claim 1, wherein the conductive connection pattern vertically overlaps the conductive separation pattern.

7. 7. The image sensor of claim 6, wherein the conductive connecting pattern is electrically isolated from the conductive isolating pattern.

8. 2. The image sensor of claim 1, wherein the width of the separation pattern on the second surface of the substrate is between 0.03 μm and 0.08 μm.

9. a substrate having a first surface and a second surface opposed to each other; an isolation pattern provided in the substrate defining pixel areas; a conductive connecting pattern provided on the isolation pattern and within a trench extending through the first surface of the substrate; an impurity region disposed within the substrate adjacent to the first surface of the substrate; The impurity region is a first impurity region contacting a first sidewall of the conductive connecting pattern; a second impurity region contacting a second sidewall of the conductive connecting pattern, the second sidewall being opposite to the first sidewall of the conductive connecting pattern; the conductive connection pattern includes a doped semiconductor material; Each of the first impurity region and the second impurity region includes a floating diffusion region.

10. 10. The image sensor of claim 9, wherein the dopant included in the conductive connection pattern includes the same element as the impurity doped into the first impurity region and the second impurity region.

11. the isolation pattern includes an insulating isolation pattern and a conductive isolation pattern provided within the insulating isolation pattern; 10. The image sensor of claim 9, wherein the conductive connection pattern vertically overlaps the conductive separation pattern.

12. a contact plug disposed on any one of the conductive connecting pattern, the first impurity region, and the second impurity region, 10. The image sensor of claim 9, wherein the contact plug is electrically connected to the conductive connection pattern, the first impurity region, and the second impurity region.

13. Further comprising a wiring pattern disposed on the separation pattern, the wiring pattern is connected to a third sidewall of the conductive connection pattern; The image sensor of claim 9 , wherein a third sidewall of the conductive connecting pattern is adjacent to the first sidewall and the second sidewall.

14. a substrate having a first surface and a second surface opposed to each other; an isolation pattern defining a first pixel area and a second pixel area within the substrate; a photoelectric conversion region provided in each of the first pixel region and the second pixel region within the substrate; a first impurity region provided in the first pixel region of the substrate and adjacent to the first surface of the substrate; a second impurity region provided in the second pixel region of the substrate and adjacent to the first surface of the substrate; a conductive connection pattern disposed between the first impurity region and the second impurity region and provided in a trench penetrating the first surface of the substrate; a gate pattern provided on a first surface of the substrate and spaced apart from the conductive connecting pattern; a gate insulating pattern interposed between the substrate and the gate pattern; a wiring layer disposed on a first surface of the substrate and including an insulating layer and a wiring structure; a color filter disposed on a second surface of the substrate; a microlens on the color filter; the isolation pattern includes an insulating isolation pattern and a conductive isolation pattern provided within the insulating isolation pattern; each of the first impurity region and the second impurity region includes a floating diffusion region; the conductive connection pattern is vertically overlapped with the conductive separation pattern, The image sensor according to claim 1, wherein the conductive connection pattern is in physical contact with the first impurity region and the second impurity region and is electrically connected to the first impurity region and the second impurity region.

15. 15. The image sensor of claim 14, wherein the conductive connection pattern comprises a doped semiconductor material.

16. 15. The image sensor of claim 14, wherein the dopant included in the conductive connection pattern includes the same element as the impurity doped into the first impurity region and the second impurity region.

17. the insulating isolation pattern is provided between the conductive connection pattern and the conductive isolation pattern, 15. The image sensor of claim 14, wherein the conductive connecting pattern is insulated from the conductive isolating pattern.

Images