Interconnection Between Quantum Computing Modules and Non-Quantum Processing Modules in a Quantum Computing System

Abstract

The technology disclosed in this patent document can be implemented to combine quantum computing, classical qubit control / readout, and classical digital computing in a scalable computing system based on superconducting qubits and a specialized interconnect design for connecting hardware components in a multi-stage cryogenic system to provide high-speed communication between quantum computing modules and their controllers while allowing efficient management of wiring with other modules.

Description

[Technical field]

[0001] Priority claims and related applications This patent document claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 091,455 (Attorney Docket No. 133858-8002.US00), filed on October 14, 2020, in the U.S. Patent and Trademark Office by Applicant SeeQC, Inc. and entitled “INTERCONNECTION BETWEEN QUANTUM COMPUTING MODULE AND NONQUANTUM PROCESSING MODULES IN QUANTUM COMPUTING SYSTEMS,” the entire disclosure of which is incorporated by reference into this patent document.

[0002] This patent document relates to computing or information processing systems that include quantum computing modules that use quantum states of quantum mechanical devices or circuits to perform information processing or computing. [Background technology]

[0003] Classical digital computers, including general-purpose digital computers and high-performance digital supercomputers, perform operations based on Boolean logic. Although Boolean logic-based computing techniques have revolutionized a wide range of industries and technologies over the last few decades, they also exhibit certain limitations in performing highly complex or numerous operations, such as molecular modeling of the structure and properties of chemical compounds or biological structures, cryptography, or modeling of complex systems for weather forecasting, climate change, and others. Various new computing techniques are being investigated to complement or replace Boolean logic-based digital computing.

[0004] Quantum mechanical systems can be used to build new computational systems for complex information processing. A quantum system suitable for quantum computing has an ensemble of subsystems in which the subsystems exhibit different quantum states that are correlated or "entangled" with each other due to quantum coherence, including long-range quantum coherence. In various implementations for quantum computers, each subsystem in the ensemble of subsystems may be a quantum system that exhibits two or more different quantum states to operate as an elementary quantum device, and information can be represented, stored, processed, and transmitted by the superposition and correlation of the quantum states of the different elementary quantum devices. One example of such an elementary quantum device is a two-state device known as a quantum bit ("qubit"). Some examples of qubit implementations include superconducting qubits based on superconducting Josephson junctions developed at IBM, Google, Intel, and others, ion-trapping devices based on electromagnetic trapping fields by laser beams developed at Honeywell and IonQ, semiconductor-based quantum dots, and other devices capable of quantum computing operations. Summary of the Invention [Means for solving the problem]

[0005] The technology disclosed in this patent document can be implemented to combine quantum computing and classical digital computing in a scalable computing system based on superconducting qubits using Josephson junctions, which exhibit low dissipation and long coherence times and can be fabricated using well-developed integrated circuit fabrication techniques. It is well known that quantum computers based on superconducting qubits are complex due to various requirements for providing and maintaining the superconducting qubit devices or systems, require complex and bulky cryogenic systems, and use special superconducting materials. In view of those technical complexities and challenges for scalable commercial applications, the disclosed technology provides a hybrid quantum-classical computing architecture and configuration that strategically partitions and combines hardware for quantum computing and hardware for classical digital computing, and places such hardware components in a multi-stage cryogenic system in a certain way, producing a scalable hybrid quantum-classical computing system for commercial applications. The disclosed technology can be implemented by using a special interconnect design for connecting the hardware components in the multi-stage cryogenic system.

[0006] In one aspect, the disclosed technology can be implemented to provide a system capable of information processing based at least in part on quantum computing using quantum states of qubits. The system includes a cryostat system structured to include different cryogenic stages operable to provide a low cryogenic temperature and a higher cryogenic temperature, and a quantum computing module surrounded by the cryostat system at the low cryogenic temperature, the quantum computing module comprising a first integrated chip structured to support a plurality of qubit circuits. Each qubit circuit is structured as a superconducting circuit at the low cryogenic temperature to exhibit a different quantum state as a quantum mechanical system and quantum mechanically interact with other qubit circuits through quantum entanglement, causing a superposition or correlation of the different quantum states of the qubit circuits. The system includes a quantum bit management circuit module surrounded by a cryostat system and located adjacent to the quantum computing module and coupled to be maintained at cryogenic temperatures, where the quantum bit control circuits are supported by a second integrated chip and are each structured to direct control signals to the quantum bit circuits for controlling the quantum bit circuits, and the quantum bit readout circuits are supported by the second integrated chip and are each structured to output a readout signal from the quantum bit circuits, the readout signals each representing a quantum state of the quantum bit circuits, the quantum bit control circuits and the quantum bit readout circuit include superconducting circuitry at low cryogenic temperatures and are structured to be operable to operate using the control signals and readout signals in a non-quantum classical manner based on digital processing, and the second integrated chip is engaged to the first integrated chip to form a multi-chip module and transfers the control signals and readout signals therebetween.The system further includes a circuit module surrounded by the cryostat system at a higher cryogenic temperature and structured to communicate with the quantum bit management circuit module in relation to control and readout signals, conductive bumps formed to interengage the first and second integrated chips, and conductive wires coupled between the quantum bit management circuit module and at least one of the circuit modules located in a higher temperature stage of the cryostat system to provide communication and transfer signals therebetween.

[0007] In another aspect, the disclosed technology can be implemented to provide a method for processing information processing based at least in part on quantum computing using quantum states of qubits. The method includes operating a quantum computing module including a plurality of qubit circuits, the qubit circuits being operable to exhibit different quantum states as a quantum mechanical system and to cause quantum mechanical interactions between the qubit circuits and to cause superposition or correlation of the different quantum states of the qubit circuits; directing qubit control circuits to the qubit circuits, respectively, control signals for controlling the qubit circuits; and operating the qubit readout circuits to output readout signals from the qubit circuits, respectively, the readout signals representing the quantum states of the qubit circuits; and controlling the qubit circuits, the qubit control circuits, and the qubit readout circuits to output readout signals from the qubit circuits, respectively, the readout signals representing the quantum states of the qubit circuits. the quantum bit control circuit and the quantum bit readout circuit to a common cryogenic stage; coupling the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit via capacitive or inductive coupling, respectively, applying a control signal from the quantum bit control circuit to the quantum bit circuit; and transmitting information using conductive wires coupled between the quantum bit management circuit module and one or more circuit modules at a temperature one degree or more higher than the temperature of the common cryogenic stage coupled to the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit in association with operating the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit.

[0008] In yet another aspect, the disclosed technology can be implemented to provide a system capable of information processing based at least in part on quantum computing using quantum states of qubits. The system includes a cryostat system structured to include different cryogenic stages operable to provide low and higher cryogenic temperatures, and a quantum computing module surrounded by the cryostat system at the low cryogenic temperature. The quantum computing module includes a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit being structured as a superconducting circuit at the low cryogenic temperature to exhibit a different quantum state as a qubit and to quantum-mechanically interact with other qubit circuits to cause correlation (superposition or entanglement) of the different quantum states and portions of the qubit circuits. The system includes a quantum bit management circuit module surrounded by a cryostat system and located adjacent to the quantum computing module and coupled thereto so as to be maintained at the same low cryogenic temperature as the quantum computing module, the quantum bit management circuit module being structured to include a second integrated chip, quantum bit control circuits supported by the second integrated chip and each structured to direct control signals to the quantum bit circuits for controlling the quantum bit circuits, and quantum bit readout circuits supported by the second integrated chip and each structured to output a readout signal from the quantum bit circuits, the readout signals each representing a quantum state of the quantum bit circuits, the quantum bit control circuits and the quantum bit readout circuits including superconducting circuits at the low cryogenic temperature and structured to be operable to operate with the control signals and readout signals in a non-quantum classical manner based on digital processing, and the second integrated chip is engaged to the first integrated chip to form a multi-chip module and transfers the control signals and readout signals therebetween.The system further includes a circuit module surrounded by the cryostat system at a higher cryogenic temperature and structured to communicate with the quantum bit management circuit module in relation to control and readout signals; conductive bumps formed to connect with the first and second integrated chips, at least some of which form conductive paths between the quantum bit management circuit module and the quantum computing module for transferring some of the control and readout signals without using other wiring between the quantum bit management circuit module and the quantum computing module; and conductive wires coupled between the quantum bit management circuit module and at least one of the circuit modules to provide communication and transfer signals therebetween.

[0009] This and other aspects and their implementations are described in more detail in the drawings, description, and claims. The present invention provides, for example, the following: (Item 1) 1. A system capable of information processing based, at least in part, on quantum computing using quantum states of qubits, comprising: a cryostat system structured to include different cryogenic stages operable to provide a lower cryogenic temperature and a higher cryogenic temperature; a quantum computing module surrounded by the cryostat system at the low cryogenic temperature, the quantum computing module comprising a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit being structured as a superconducting circuit at the low cryogenic temperature such that, as a quantum mechanical system, each qubit circuit exhibits a different quantum state and quantum mechanically interacts with other qubit circuits via quantum entanglement, causing a superposition or correlation of the different quantum states of the qubit circuits; a quantum bit management circuit module surrounded by the cryostat system and located adjacent to the quantum computing module and coupled to be maintained at a cryogenic temperature, quantum bit control circuits supported by a second integrated chip and each configured to direct control signals to the quantum bit circuits for controlling the quantum bit circuits, quantum bit readout circuits supported by the second integrated chip and each configured to output a readout signal from the quantum bit circuits, the readout signals each representing a quantum state of the quantum bit circuits, the quantum bit control circuits and quantum bit readout circuits including superconducting circuitry at the low cryogenic temperature and configured to be operable to operate using the control signals and readout signals in a non-quantum classical manner based on digital processing, and the second integrated chip is engaged to the first integrated chip to form a multi-chip module for transferring control signals and readout signals therebetween; a circuit module that is surrounded by the cryostat system at the higher cryogenic temperature and that is structured to communicate with the quantum bit management circuit module in association with the control and readout signals; conductive bumps formed to interlock the first and second integrated chips; an electrically conductive wire coupled between the quantum bit management circuit module and at least one of the circuit modules located in a hotter stage of the cryostat system to provide communication and transfer signals therebetween; and A system comprising: (Item 2) the conductive bumps are for providing a mechanical engagement between the first integrated chip and the second integrated chip and are not electrically connected to circuitry in either the first integrated chip or the second integrated chip; the quantum computing module and the quantum bit management circuit module are coupled to each other and exchange information via conductive or inductive coupling; Item 1. The system according to item 1. (Item 3) 2. The system of claim 1, wherein the conductive bumps are connected to form a conductive path between the quantum bit management circuit module and the quantum computing module, at least in part, for transfer of some of the control and readout signals without using other wiring between the quantum bit management circuit module and the quantum computing module. (Item 4) Item 2. The system of item 1, wherein the conductive bumps include conductive insulating bumps positioned to form an insulating fence separating the conductive wires and reduce crosstalk between the conductive wires. (Item 5) Item 2. The system of item 1, wherein the quantum computing module includes conductive insulating bumps positioned to form an insulating fence separating the qubit circuits, reducing crosstalk therebetween, and reducing decoherence of the qubit circuits. (Item 6) Item 10. The system of item 1, further comprising a conductive insulating wall positioned to form an insulating wall separating the conductive wires and reduce crosstalk between the conductive wires. (Item 7) 2. The system of claim 1, wherein the quantum computing module includes a conductive insulating wall separating the qubit circuits to reduce crosstalk therebetween and reduce decoherence of the qubit circuits. (Item 8) 2. The system of claim 1, wherein the quantum bit management circuit module and quantum computing module include capacitive coupling circuitry to enable capacitive coupling between the quantum bit management circuit module and the quantum computing module and are structured to provide signal transmission separate from the conductive paths formed by conductive bumps. (Item 9) 2. The system of claim 1, wherein the quantum bit management circuit module and quantum computing module include a magnetic coupling circuitry to enable magnetic inductive coupling between the quantum bit management circuit module and the quantum computing module and are structured to provide signal transmission separate from the conductive paths formed by conductive bumps. (Item 10) Item 1, the system of item 1 further comprising a flexible non-conductive material on which the conductive wires are formed and separated from one another, whereby the flexible non-conductive material and the conductive wires form a flexible ribbon connecting at least one of the circuit module and the quantum bit management circuit module. (Item 11) 2. The system of claim 1, wherein each quantum bit circuit includes a superconducting Josephson junction circuit at the low cryogenic temperature. (Item 12) 2. The system of claim 1, wherein the quantum bit management circuit module includes a superconducting switching circuit that is different from a Josephson junction circuit. (Item 13) 2. The system of claim 1, wherein the quantum bit management circuit module includes a Josephson junction circuit. (Item 14) 2. The system of claim 1, wherein the quantum bit management circuit module includes a single flux quantum (SFQ) logic circuit. (Item 15) 2. The system of claim 1, wherein the quantum bit management circuit module includes a quantum flux parametron circuit. (Item 16) Item 2. The system of item 1, wherein the quantum bit management circuit module includes a nanowire switch. (Item 17) Item 2. The system of item 1, wherein the quantum bit management circuit module includes a superconducting ferromagnetic transistor. (Item 18) 10. The system of claim 1 , wherein the quantum bit management circuit module comprises a superconducting spintronic device. (Item 19) 2. The system of claim 1, wherein the quantum bit management circuit module includes a field effect superconducting device. (Item 20) 2. The system of claim 1, further comprising an optical transmitter and receiver device to enable transmission and reception of optical signals between the cryogenic stage located at the highest temperature of the cryostat system and room temperature electronics to provide communication therebetween. (Item 21) 2. The system of claim 1, wherein the quantum bit management circuit module and the quantum computing module are maintained at the same low cryogenic temperature. (Item 22) the quantum computing module further comprises a plurality of readout resonators supported by the first integrated chip and each configured to interact with the plurality of qubit circuits and produce a qubit circuit readout signal; the quantum bit readout circuits are supported by the second integrated chip and are each configured to interact with the plurality of readout resonators supported by the first integrated chip, each to receive a quantum bit circuit readout signal, and each to output the readout signal; Item 1. The system according to item 1. (Item 23) the quantum bit readout circuit supported by the second integrated chip is structured to include a plurality of readout resonators supported by the second integrated chip, each configured to interact with the plurality of quantum bit circuits supported by the first integrated chip and to produce a quantum bit circuit readout signal; the quantum bit readout circuits supported by the second integrated chip are each configured to interact with the plurality of readout resonators, each to receive a quantum bit circuit readout signal, and each to output the readout signal. Item 1. The system according to item 1. (Item 24) 1. A method for processing information based, at least in part, on quantum computing using quantum states of qubits, comprising: operating a quantum computing module as a quantum mechanical system, the quantum computing module comprising a plurality of qubit circuits operable to exhibit different quantum states and to cause quantum mechanical interactions between the qubit circuits and to cause a superposition or correlation of the different quantum states of the qubit circuits; causing quantum bit control circuits to respectively direct control signals to the quantum bit circuits for controlling the quantum bit circuits; operating a qubit readout circuit to output a readout signal from each of the qubit circuits, each of the readout signals representing a quantum state of the qubit circuit; thermally coupling the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit to a common cryogenic stage; coupling the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit via capacitive coupling or inductive coupling, and applying the control signal from the quantum bit control circuit to the quantum bit circuit, respectively; transmitting information using conductive wires coupled between a quantum bit management circuit module and one or more circuit modules at a temperature that is 1 degree or more higher than a temperature of the common cryogenic stage coupled to the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit in association with operating the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit; A method comprising: (Item 25) 25. The method of claim 24, comprising one or more operating steps in operating a system as recited in one of claims 1-23. [Brief description of the drawings]

[0010] [Figure 1A] 1A, 1B, 1C, 1D, and 1E show examples of quantum computing systems based on the disclosed techniques and interconnect designs for connecting different hardware modules in a multi-stage cryogenic system. [Figure 1B] 1A, 1B, 1C, 1D, and 1E show examples of quantum computing systems based on the disclosed techniques and interconnect designs for connecting different hardware modules in a multi-stage cryogenic system. [Figure 1C] 1A, 1B, 1C, 1D, and 1E show examples of quantum computing systems based on the disclosed techniques and interconnect designs for connecting different hardware modules in a multi-stage cryogenic system. [Figure 1D] 1A, 1B, 1C, 1D, and 1E show examples of quantum computing systems based on the disclosed techniques and interconnect designs for connecting different hardware modules in a multi-stage cryogenic system. [Figure 1E] 1A, 1B, 1C, 1D, and 1E show examples of quantum computing systems based on the disclosed techniques and interconnect designs for connecting different hardware modules in a multi-stage cryogenic system.

[0011] [Diagram 2] 2, 3A, 3B, and 3C show examples of interconnect wires and electrical isolation structures. [Figure 3A] 2, 3A, 3B, and 3C show examples of interconnect wires and electrical isolation structures. [Figure 3B] 2, 3A, 3B, and 3C show examples of interconnect wires and electrical isolation structures. [Figure 3C] 2, 3A, 3B, and 3C show examples of interconnect wires and electrical isolation structures.

[0012] [Figure 4A] 4A, 4B, and 4C show example sections of an MCM structure with a qubit management circuit module and a quantum computing module mechanically and electrically connected via superconducting bumps. [Figure 4B] 4A, 4B, and 4C show example sections of an MCM structure with a qubit management circuit module and a quantum computing module mechanically and electrically connected via superconducting bumps. [Figure 4C] 4A, 4B, and 4C show example sections of an MCM structure with a qubit management circuit module and a quantum computing module mechanically and electrically connected via superconducting bumps.

[0013] [Figure 4D] FIG. 4D shows an example of a plot showing the results of simulated coupling between striplines for each of the three (curves 1-3, respectively) depicted in FIGS. 4A, 4B, and 4C.

[0014] [Figure 5A] FIG. 5A illustrates an example of an MCM device, showing a more detailed layout of the qubit management circuitry module and quantum computing module with asymmetric flux bias supply lines.

[0015] [Figure 5B] FIG. 5B illustrates an example of an MCM device, showing a more detailed layout of the qubit management circuitry module and quantum computing module, along with symmetric flux bias supply lines.

[0016] [Figure 5C] FIG. 5C shows another example for implementing an MCM module in relation to a quantum bit management circuit module and a quantum computing module, in which a readout resonator for each qubit is located on the quantum bit management circuit module.

[0017] [Figure 6] 6 and 7 show an embodiment of the JPM-SFQ comparator MCM. [Figure 7] 6 and 7 show an embodiment of the JPM-SFQ comparator MCM.

[0018] [Figure 8] FIG. 8 shows an example of capacitive coupling between a qubit and a SFQ chip via a passive transmission line (PTL) and overlapping capacitors.

[0019] [Figure 9] FIG. 9 shows an example of capacitive coupling between a qubit and an SFQ chip. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The techniques disclosed herein for computing or information processing systems involving superconducting-based quantum computing modules (e.g., superconducting Josephson junctions) can be implemented by combining quantum computing modules or devices with classical digital computing modules or devices in a manner that allows the system to be scalable for complex computing applications, and by strategically partitioning such systems into different quantum and classical digital computing modules, devices, or components in various cryogenic stages at different cryogenic temperatures and achieving superconducting conditions in those cryogenic stages. Such implementations of the disclosed techniques can be used to simplify and reduce the complex and bulky cryogenic systems commonly used in various quantum computer systems that use superconducting quantum computing devices, and to reduce the use, or level of use, of complex superconducting cable systems to link different computing or processing modules. Implementations of the disclosed techniques can be devised to enable commercially scalable fabrication using integrated circuit (IC) fabrication processes and equipment in manufacturing modules or devices based on superconducting Josephson junctions that will be key for quantum computer systems. The technology disclosed in this patent document provides a specialized interconnect design for connecting hardware components in a multi-stage cryogenic system while allowing efficient management of wiring with other modules, and can be implemented to provide high speed communication between the quantum computing modules and their controllers.

[0021] 1A, 1B, 1C, 1D, and 1E show examples for implementing a quantum computing system based on the disclosed techniques and an interconnect design for connecting different hardware modules in a multi-stage cryogenic system.

[0022] 1A illustrates an example of a quantum computing system 110 for producing a scalable hybrid quantum-classical computing system for commercial applications. The quantum computing system 110, as its name implies, includes multiple qubit circuits, performs computing operations based on the quantum states of the qubit circuits, and communicates with external computers or computing systems 130 via communication links or networks 120. The communication links and networks 120 may include circuits in which signals are transferred in the form of electromagnetic signals, including electrical signals carried, for example, by conductive wires and / or optical signals. In operation, the quantum computing system 110 receives computational requests or tasks from one or more external computers or computing systems 130, performs the requested computational operations, and transmits computational results back to the one or more requesting external computers or computing systems 130. Communications and / or interactions between quantum computing system 110 and external computer or computing system 130 are via communications links or networks 120, which may constitute the longest communication cycles in time in the operation of quantum computing system 110 and are labeled as long communications links or loops. As explained further below, quantum computing system 110 is structured to partition different internal computing modules whereby those internal computing modules communicate via internal shorter communications links or loops, such as medium communications links or loops, with medium latency in time, and high speed communications links or loops, with the shortest latency in time.

[0023] Quantum computing system 110 includes a multi-stage cryogenic system to provide different cryogenic stages at different locations and maintain different modules or devices at different cryogenic temperatures to keep them at their respective desired temperatures (e.g., T1, T2, T3, and T4 as shown). In some implementations, the different cryogenic stages may be designed to produce temperatures from millikelvin to tens of kelvins. This exemplary system 110 includes a quantum computing module 102 that includes multiple qubit circuits or devices as a quantum qubit ensemble to perform desired quantum computing operations via their respective qubit states. In many implementations, quantum computing module 102 is engaged or coupled to a cryogenic stage at a low cryogenic temperature T1 to ensure that the qubit circuits or devices are under acceptable quantum computing operating conditions under the desired superconducting state and with sufficiently low noise and interference levels. The qubit management circuitry module 104 is provided to communicate with the quantum computing module 102, provide control signals to and read out from the individual qubit circuits or devices of the quantum computing module 102, and may be implemented by using non-quantum mechanical processing circuitry, such as digital or analog circuitry or a combination of digital and analog circuitry. The qubit management circuitry module 104 may be implemented with superconducting circuitry and is coupled to a cryogenic stage at a cryogenic temperature T2, which in some implementations may be different from the lower cryogenic temperature T1 or, in other implementations, may be the same as temperature T1. As discussed further below, in some designs, the quantum computing module 102 and the qubit management circuitry module 104 may be mated to share a common cryogenic stage such that both modules are kept at the same cryogenic temperature.Quantum bit management circuit module 104 can be structured to include (1) qubit control circuits for directing control signals to the qubit circuits, respectively, to control the qubit circuits, and (2) qubit readout circuits for outputting readout signals from the qubit circuits, respectively. In this embodiment, quantum computing module 102 and qubit management circuit module 104 together form the "heart" or "core" of quantum computing system 110, in part because quantum computing operations are performed within quantum computing module 102 based on control signals to the qubit circuits from qubit management circuit module 104, and readout of the qubit circuits is performed by qubit management circuit module 104. Communication between quantum computing module 102 and qubit management circuit module 104 is essential to quantum computing operations, in terms of the quality and speed of such communication. Thus, in an implementation, the quantum computing module 102 and the qubit management circuit module 104 may be installed or positioned in close physical proximity or adjacent to one another to shorten the signal path between the two modules 102, 104 and reduce any interference or noise to such communications. In addition, the functions or operations of the qubit management circuit module 104 may be limited by intentional design to certain core functions or operations in connection with the quantum operations performed by the quantum computing module 102, such that the qubit management circuit module 104 can achieve short or fast response or processing times and ensure fast input / output signal transfer in the quantum computing module 102.This intentionally reduced functionality design consideration for the qubit management circuitry module 104 is also based on the power consumption and energy dissipation by the qubit management circuitry module 104 into its surroundings in light of its close proximity to the quantum computing module 102, the desire to reduce noise or interference by the qubit management circuitry module 104 to the quantum computing module 102, and the need to maintain suitable cryogenic conditions in both the qubit management circuitry module 104 and the adjacent quantum computing module 102. Based on these and other considerations, the interconnects and signal paths between the two modules 102 and 104 are designed to form a high-speed communications link or loop with minimal delay in time to the quantum computing system 110. For example, in some implementations, the quantum computing module 102 may include at least one integrated chip supporting one or more qubit circuits, and the qubit management circuitry module 104 may be formed on another integrated chip that is mechanically and electrically coupled as a multi-chip module directly to the integrated chip with the qubit circuits via superconducting bumps, capacitive coupling, or magnetic coupling via vacuum, and may transfer control and readout signals therebetween. This multi-chip module formed by the two modules 102 and 104 can be coupled to the same cryogenic stage at low cryogenic temperature T1. This design may be commercially important because the chip fabrication for the multi-chip module formed by the two modules 102 and 104 is a scalable platform to allow a wide range of qubit circuits to be fabricated and included in the quantum computing module 102, and similarly, the qubit management circuitry module 104 may also be scaled based on the number of qubit circuits present.

[0024] 1A further includes a digital processing module 108 that provides certain signal and data processing functions or operations for the quantum computing system 110 in connection with the quantum operations performed by the quantum computing module 102 via the qubit management circuitry module 104. In this regard, the digital processing module 108 forms the core processing module for the non-quantum operations and / or processing functions within the quantum computing system 110, and is therefore designed with much more complex circuitry and higher processing power than the qubit management circuitry module 104. In particular, certain functions and / or processing operations may be included within the circuitry of the digital processing module 108 that may not be built into the qubit management circuitry module 104. In addition, the digital processing module 108 also serves as an interface between the quantum computing system 110 and one or more external computers or computing systems 130 via a communication link or network 120. Thus, the digital processing module 108 is designed to further include processing functions associated with communication and interaction between the quantum computing system 110 and the external computer or computing system 130. Thus, unlike the installation and design of the qubit management circuitry module 104, the digital processing module 108 is designed to be complex and capable of being a classical counterpart and co-processor of the quantum computing module 102 of the quantum computing system 110. The increase in functionality and / or processing operations and processing power packed into the digital processing module 108 adds to the complexity and size of the circuitry of the digital processing module 108, further increasing the power consumption and energy dissipation of the digital processing module 108. Thus, it is desirable to install the digital processing module 108 physically away from the quantum computing module 102 and its adjacent neighboring qubit management circuitry modules 104 to reduce noise and interference that the digital processing module 108 may impose on the quantum computing module 102.Digital processing module 108 may be designed with various functions and capabilities, including, for example, error correction functions for quantum computing system 110, and non-quantum operational and / or processing functions within quantum computing system 110, including, for example, functions associated with control and readout of quantum computing module 102, performed by qubit management circuitry module 104, and management of data for quantum operations, performed by quantum computing module 102. In some implementations, digital processing module 108 may be coupled to a cryogenic stage at a higher temperature T4 than for quantum computing module 102 (at T1) and qubit management circuitry module 104 (at T1 or T2). Digital processing module 108 may be designed to include superconducting circuitry and is enclosed within the multi-stage cryogenic system of quantum computing system 110.

[0025] The deliberate design to locate the digital processing module 108 away from the qubit management circuit module 104 leads to longer signal paths or links between the digital processing module 108 and the qubit management circuit module 104. Within the enclosure of the multi-stage cryogenic system, such signal paths or links may be formed by using superconducting wires or cables. Notably, the long length of such signal paths or links may cause a degree of signal degradation, and one option to address this is to add one or more interconnect repeaters or signal conditioning circuits 106 between the digital processing module 108 and the qubit management circuit module 104 to condition the signals. As with other modules in a multi-stage cryogenic system, each interconnect repeater or signal conditioning circuit 106 may be engaged or coupled to a cryogenic stage at a temperature T3 that is higher than the temperature of the qubit management circuit module 104 (at T1 or T2) and lower than the temperature of the digital processing module 108 (at T4). For example, the digital signal conditioning circuit module 106 may include superconducting circuits that condition the control or readout signals.

[0026] In some implementations, the quantum computing system 110 may further include a digital processing subsystem 109, outside the multi-stage cryogenic system or cryostat system, in communication with the digital processing module 108 and performing operations associated with supporting the execution of quantum or quantum-classical algorithms and / or communication with one or more other computers or networks 130. This is shown in the example of Figures 1C and 1D. This digital processing subsystem 109, outside the cryostat system, may include one or more CMOS digital processors, one or more field programmable gate arrays (FPGAs), or one or more application specific integrated circuits (ASICs), or one or more central processing units (CPUs).

[0027] Quantum processing performed by quantum computing module 102 is the core of quantum computing system 110, and signaling and communication between quantum computing module 102 and the rest of system 110 plays a key role in the overall computing speed and performance of system 110. The latency in signaling and communication between quantum computing module 102 and the rest of system 110 is a key parameter to optimize in order to achieve a scalable hybrid quantum-classical computing system for commercial applications. During operation, information is passed between quantum computing module 102, other processing modules, and computing entities involved in the operations performed in quantum computing system 110. As shown, different communication links and / or feedback loops are formed between quantum computing module 102, non-quantum modules, and other modules in system 110. The fastest link / loop, labeled as the short loop in FIG. 1A, exists between quantum computing module 102 and qubit management circuit module 104. This link / loop is compared to the communication link / loop formed between quantum computing module 102 and digital processing module 108, which may incur longer latency 1) because communication between these modules must traverse a longer distance, including passing through qubit management module 104, which may perform its own operations on the data circulation between quantum computing module 102 and digital processing module 108, and 2) because digital processing module 108 generally performs more complex processing operations. Thus, in FIG. 1A , the communication between 102 and 108 is labeled as a medium communication link / loop.Even longer latency occurs between the quantum computing module 102 and the external computer or computing system 130, again labeled in FIG. 1A as a long communications link / loop due to the increased distance and complexity of processing operations (which encompasses both the communications path and possible operations of short and medium loops in addition to the communications link or network 120) compared to the medium link / loop.

[0028] Thus, the embodiment of quantum computing system 110 of FIG. 1A includes special design features to provide a hybrid computing environment that combines processing functions and / or operations by quantum computing portions (e.g., quantum computing module 102) and non-quantum classical processing portions (e.g., qubit management circuitry module 104 and digital processing module 108), strategically partitioning and allocating different amounts and types of processing functions and / or operations of the non-quantum classical processing portions between qubit management circuitry module 104 and digital processing module 108 in light of the intentional design to position qubit management circuitry module 104 such that it is located in close physical proximity to quantum computing module 102, while keeping quantum computing module 102 away from digital processing module 108.

[0029] In some implementations, the digital processing module 108 may include two or more different processing modules and be designed to optimize the computational speed and performance of the digital processing module 108. For example, the digital processing module 108 may be further divided into a series of modules, as shown in FIG. 1B, with different temperature stages of the cryogenic system housing one or more such modules. In general, the design of the quantum computing system 110 of FIG. 1A allows for optimization of the placement of each module within the cryogenic system to balance its particular need for low latency (weighting close proximity to the quantum module 102) with the ability to efficiently utilize the volume of the cryogenic system as well as manipulate dissipation during processing operations (weighting higher temperature stages placed further away from the quantum module 102).

[0030] 1C shows an example for performing certain processing operations in different modules in system 110 of FIG. 1A, specifically, processing operations in digital processing module 108, additional digital processing module 109, which is operated at a higher temperature than that of digital processing module 108, and processing operations in qubit management circuit module 104. As a specific example, FIG. 1C shows that a desired quantum gate sequence produced by additional digital processing module 109 based on information from digital processing module 108 in light of a qubit readout from qubit management circuit module 104 is transmitted to and processed by digital processing module 108 to generate an SFQ control pulse pattern. Qubit management circuit module 104 receives such SFQ control pulse pattern and applies the received SFQ control pulse pattern and / or a flux bias to quantum module 102 to set the associated qubit into the quantum gate sequence. This is an example for implementing the medium communication loop of FIG. 1A , i.e., communication between quantum computing module 102 and digital processing module 108, including a link with qubit management module 104, or any interconnection module 106 between modules 102 and 108. FIG. 1C further shows an example for implementing a short communication loop between qubit management module 104 and quantum computing module 102, in which qubit readouts obtained from reading out quantum computing module 102 are digitally processed by qubit management module 104, and the processed information is further used by qubit management circuitry module 104 to apply SFQ control pulse patterns and / or flux biases to quantum module 102.

[0031] In various implementations, the quantum computing module 102 and the non-quantum classical processing portions (e.g., the qubit management circuitry module 104 and the digital processing module 108) are structured to include superconducting circuits or devices that are coupled to different cryogenic stages of a multi-stage cryogenic system, and the superconducting interconnect wires 112, 114, and 116 are provided and maintained at temperatures at different locations to transfer signals between the different modules or stages. The multi-stage cryogenic system for the quantum computing system 110 may be implemented in various configurations, including a multi-stage dilution refrigerator, the operating principle of which is based on mixing helium-3 and helium-4 to provide different cryogenic stages at different graded cryogenic temperatures. In some implementations, the cryostat system may include a nuclear demagnetization refrigerator or an adiabatic demagnetization refrigerator.

[0032] The modules in quantum computing system 110 may be implemented in various configurations. For example, each qubit circuit for a qubit in quantum computing module 102 may include a superconducting Josephson junction circuit, or a switched superconducting circuit different from a Josephson junction circuit. For example, qubit management circuit module 104 may be implemented to include a superconducting Josephson junction circuit, or a single flux quantum (SFQ) logic circuit, or a quantum flux parametron circuit such as an adiabatic quantum flux parametron circuit, or a nanowire switch, or a superconducting ferromagnetic transistor, or a superconducting spintronic device, or a field effect superconducting device. Digital processing module 108 may be implemented to include SFQ circuitry, a field programmable gate array (FPGA), or one or more application specific integrated circuits (ASICs).

[0033] In the system of FIG. 1A, an optical communication link may be used for the transfer of signals, either as a replacement for certain conductive wires or cables, or as an additional link in combination with conductive wires or cables. The optical communication link may provide faster data transmission and increase communication bandwidth. For example, optical communication may be used between a cryogenic stage with the highest temperature stage (e.g., module 108 of FIG. 1A) and a room temperature stage. In implementations, optical transmitter and receiver devices are provided in such stages or circuit modules to enable transmission and reception of optical signals between the cryogenic stage, which is placed at the highest temperature of the cryostat system, and room temperature electronics to provide communication therebetween. In some implementations, such an optical communication link may be implemented between module 108 and a CMOS FPGA subsystem.

[0034] FIG. 1D illustrates an example of a quantum computing system capable of processing information based on quantum computing using quantum states of qubits, based at least in part on the design of FIG. 1A. The cryostat system in this example is structured and operable to provide different cryogenic stages at different temperatures of 20 mK, 0.1 K, 0.7 K, and 3 K. The different circuit modules in the different cryogenic stages are interconnected by superconducting wires, such as NbTi / Kapton (NbTi / polyamide) strips. The quantum computing module, surrounded by the cryostat system, includes a first integrated chip structured to support qubit circuits. Each qubit circuit is structured as a superconducting circuit, exhibits a different quantum state as a qubit, and quantum-mechanically interacts with other qubit circuits through quantum entanglement, causing a superposition or correlation of the different quantum states of the qubit circuits. The qubit management circuit 104 module is located adjacent to the quantum computing module 102 and is coupled to be maintained at the same low cryogenic temperature as the quantum computing module. The quantum bit management circuit includes a second integrated chip, a quantum bit control circuit supported by the second integrated chip and configured to direct control signals to the quantum bit circuits, respectively, for controlling the quantum bit circuits, and a quantum bit readout circuit supported by the second integrated chip and configured to output a readout signal from the quantum bit circuits, respectively. In operation, the readout signals each represent a quantum state of the quantum bit circuits, and the quantum bit control circuit and the quantum bit readout circuit include superconducting circuitry and are configured to be operable to operate with the control signals and readout signals in a non-quantum classical manner based on digital processing. In particular, the second integrated chip is mated to the first integrated chip to form a multi-chip module (MCM) and transfers the control signals and readout signals.

[0035] Figure 1E shows an example for implementing an interconnect linking different hardware components of classical and quantum circuits in the example of Figure 1A, 1C, or 1D. The example system of Figure 1E includes at least one classical non-quantum digital processing module 108, labeled as a "classical processor chip," at least one SFQ repeater as part of the interconnect circuitry or module 106, and at least one classical superconducting controller as part of a qubit management circuit module 104 that controls a quantum computing processor or module 102 with multiple qubit circuits or devices.

[0036] The interconnect of FIG. 1E is designed to include superconducting connection nodes or pads 140 and superconducting connection cables 150 for connecting the classical circuits 104, 106, and 108 with the quantum computing processor or module 102. As shown, the superconducting connection nodes or pads 140 may be implemented as superconducting bumps in direct contact with one or more hardware components (102, 104, 106, 108) to be connected and can be used to provide connections between the hardware components and the superconducting cables. As described with reference to FIG. 1A, the quantum computing module 102 and the qubit management circuit module 104 can be placed adjacent to each other to enable short connection paths between them for fast inter-module communication, and can be thermally coupled to the same cryogenic stage at the same low cryogenic temperature. In particular, the communication link or loop between the classical superconducting controller as part of the qubit management circuitry module 104 and the quantum processor chip 102 should be a high-speed communication link or loop, and superconducting bumps can be used to interconnect the two modules 102 and 104 to enable high-speed exchange of information for quantum computing operations and readout. In some implementations, the qubit management circuitry module 104, containing the classical controller chip, can be positioned on the cold plate of a cryocooler directly above or below the quantum computing module 102 to reduce noise and interference to quantum computing operations by qubit circuits or devices inside the quantum computing module 102. In some implementations, the superconducting bumps can be configured or used in the form of strip or microstrip lines, or other on-chip transmission lines, to reduce mutual crosstalk between superconducting electronic elements or systems, and to improve the quality factor of the resonators, to produce fences or walls that separate qubits or systems of multiple qubits from each other.

[0037] In addition to direct electrical connections between the quantum computing module 102 and the quantum bit management circuit module 104, non-contact connections may be used to achieve high speed communication, including, for example, differential capacitive coupling and magnetic coupling between the qubits and passive transmission lines, both of which provide a communication link without a direct connection and allow compensation for geometric mismatches between the modules 102 and 104 and other components as a result of fabrication processes.

[0038] Unlike classical computers based on deterministic Turing machines and Boolean bits of "0" and "1" states, quantum computing operations by qubit circuits or devices inside quantum computing module 102 use quantum mechanical phenomena such as superposition of "0" and "1" qubit states, entanglement between qubits, and interference between probability amplitudes of non-deterministic measurement outcomes to perform computing operations. The superconducting qubits inside quantum computing module 102 can be implemented by superconducting Josephson junctions. Josephson junctions are systems of weakly coupled superconductors that exhibit correlated or coherent states and behave similarly to nonlinear inductors, allowing the construction of quantum non-harmonic oscillators. The two discrete energy level states of this non-harmonic oscillator and their quantum superposition are used to create the qubits. Using Josephson junctions, several versions of superconducting qubits can be constructed, such as transmons, exmons, quantroniums, and fluxoniums.

[0039] The state of the qubits is controlled by applying microwave signals to the qubits. In various implementations, the microwave signal generator may be a room temperature device, but the quantum circuit comprising the qubits operates at very low cryogenic temperatures to reduce undesired decoherence of the qubits. In particular, the wiring required to provide the microwave signals to the qubit circuits may involve different compartments maintained at different temperatures from room temperature to the lowest temperature in the cryogenic stage in which the quantum circuit is placed, and thus may cause or introduce undesired electrical noise or excessive heat load. Such wiring for a significant number of qubit circuits may occupy a lot of space. These factors may lead to undesired decoherence of the qubit quantum states, posing a significant problem for the scale-up of quantum computers.To overcome this problem, various techniques may be used to control qubits in a fully integrated cryogenic and hybrid quantum-classical processor as shown in FIGS. 1A-1E, such as the integration of superconducting qubits with classical superconducting digital logic families such as reciprocal quantum logic (RQL) as disclosed by Quentin P. Herr and Anna Y. Herr in the paper titled “Ultra-low-power superconductor logic” J. Appl. Phys. 109, 103903 (2011), and the integration of superconducting qubits with classical superconducting digital logic families such as reciprocal quantum logic (RQL) as disclosed by O. Chen, R. Cai, Y. Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi, and N. in the paper titled “Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems” Sci. Rep. 9, 10514 (2019). or the use of single flux quantum (SFQ) technology as disclosed by OA Mukhanov in a paper entitled "Energy-Efficient Single Flux Quantum Technology" IEEE Trans. Appl. Supercond. 21, 760 (2011). As part of the interconnect design for the systems in Figures 1A-1E, control of qubits can be implemented via a SFQ system to control the state of the qubits by applying a sequence of SFQ pulses without the traditional use of microwave signals as disclosed in U.S. Patent No. 9,425,804.Techniques for applying magnetic flux to a quantum-coherent superconducting circuit in U.S. Patent Application Publication No. 2015 / 0263736A1, by inventors Quentin P. Herr, Ofer Naaman, and Anna Y. Herr, and assignee Northrop Grumman Systems, for "Systems and methods for applying flux to a quantum-coherent superconducting circuit," may also be implemented. Qubit readout may be implemented by quantum electrodynamic measurements as disclosed in U.S. Patent No. 9,692,423, by Robert Francis McDermott et al., and applicants Universitaet des Saarlandes, Syracuse University, and Wisconsin Alumni Research Foundation, for "System and method for circuit quantum electrodynamics measurement." CryoCMOS techniques may also be implemented in the systems of FIGS. 1A-1E to control superconducting qubits.See the embodiments disclosed by E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song, and RM Incandela. in their paper entitled "Cryo-CMOS for quantum computing" in Technical Digest - International Electron Devices Meeting, IEDM (2017), pp. 1-13. (doi: 10.1109 / IEDM.2016.7838410), and by JC Bardin et al. in their paper entitled "A 28nm Bulk-CMOS 4-to-8GHz 2mW Cryogenic Pulse Modulator for Scalable Quantum Computing" IEEE J. Solid-St. Circuits 54, 3043-3060 (2019), all of which are incorporated by reference as part of the disclosure of this patent document.

[0040] The practical implementation of the system of FIGS. 1A - 1E requires careful design of the interconnection or interface between the quantum circuit of the quantum computing module 102, which is placed at a low cryogenic temperature (e.g., a few millikelvin), and the classical processing circuit, which is placed at a higher temperature (including liquid helium temperature). The interconnection in the embodiment of FIG. 1E involves placing the quantum computing module 102 and the qubit management circuit module 104 adjacent to each other on the same cryogenic stage of the dilution refrigerator without using any superconducting cable or wire 150 between the modules 102 and 104. Instead, superconducting bumps or pads 140 are used to physically bond or join the two modules 102 and 104 together. The signal path between the two modules 102 and 104 can be implemented in various ways, including signal transmission through a conductive path formed through the superconducting bumps or pads 140 between the modules 102 and 104, or signal transmission through capacitive and / or magnetic coupling between the modules 102 and 104. The signal path between the two modules 102 and 104 is designed to minimize the signal transmission time (e.g., by reducing or eliminating the amount of wiring between the modules 102 and 104) and to form a high-speed communication link or loop within the system as described above with respect to FIG. 1A.

[0041] In implementations where the two modules 102 and 104 are supported by two IC chips, the two chips may be bonded as an integrated unit to the same low temperature cryogenic stage and thus stacked and bonded over one another to form a multi-chip module (MCM) where both modules 102 and 104 are operated under the same low cryogenic temperature. Superconducting bumps or pads 140 may be used as part of the bond between the two IC chips or modules 102 and 104. The interconnect in the embodiment of FIG. 1E also implements a combination of superconducting bumps or pads 140 and superconducting cables or wires 150, where the superconducting bumps or pads 140 are used at the terminals of the superconducting cables or wires 150 to connect the wire terminals to a device. 1E shows that a qubit management circuit module 104 is connected to an interconnection network or module 106, such as a digital signal conditioning circuit module, via superconducting cables or wires 150, with two sets of superconducting bumps or pads 140 used to splice two end terminals of each superconducting cable or wire 150 to contact points on the qubit management circuit module 104 and the corresponding interconnection network or module 106. This use of superconducting bumps or pads 140 and superconducting cables or wires 150 can be applied to connections between a digital processing module 108 and a corresponding interconnection network or module 106, as well as connections to other modules, such as connections between different stages of an interconnection network or module 106 or between digital signal conditioning circuit modules. As shown, such superconducting cables or wires 150 with superconducting bumps or pads 140 constitute part of an internal communication link and loop, as described above with respect to FIG. 1A.

[0042] FIG. 2 shows an example of a portion of a flexible ribbon cable 200 having superconducting striplines and superconducting contact bumps in one implementation of the interconnect 150 shown in FIG. 1E. This exemplary flexible ribbon cable 200 includes a conductive cable 210, either a superconducting stripline or a microstripline (e.g., made from Nb or NbTi, among other suitable conductive metallic materials), supported by or engaged with a flexible non-conductive flexible substrate or tape 220, such as Kapton tape. The superconducting cable 200 further includes a conductive bump 212, which in FIGS. 1A-1E serves to connect the cable 210 to electronic circuits placed on the solid-state (typically Si) chips or modules 102, 104, 106, and 108. This bump 212 corresponds to the bump 140 in FIG. 1E. The superconducting cable 200 further includes a superconducting metallization 230, which typically serves as a ground electrode. The use of high bandwidth superconducting cables may allow the transmission of microwave signals and single flux quantum (SFQ) pulses between different temperature stages (e.g., between 3K and 20mK stages in a dilution refrigerator) with minimal thermal conductivity. Specifically, NbTi has a very low thermal conductivity, and the estimated heat load is about 40μW when using a 50μm wide microstrip line. It is known that SFQ pulses will not be able to remain intact over large distances between the highest and lowest temperature stages due to dispersion and attenuation in the cable. Therefore, typically shorter cable sections between the 3K, 700mK, 100mK, and 20mK stages present in a dilution refrigerator will be used, namely cable section #1 from 3K to 700mK, cable section #2 from 700mK to 100mK, and cable section #3 from 100mK to 20mK. A combination of superconducting cables and intermediate repeaters may be used to achieve a significant increase in wiring density, and therefore advantageously reduce the volume or space required for such wiring within the cryostat.

[0043] Additional examples of superconducting cables suitable for implementing the disclosed technology include pin-chip bonding to provide fully vertical interconnects using rectangular coaxial ribbon cables for large arrays of superconducting qubits fabricated on a single Si or sapphire chip at both room temperature and cryogenic temperatures down to about 10 mK for signal transmission from DC to about 10 GHz. One example for implementing such pin-chip bonding can be found in the 8-page document "High-Density Qubit Wiring: Pin-Chip Bonding for Fully Vertical Interconnects" by M. Mariantoni and AV Bardysheva, in Quantum Physics, 2020 (arxiv.org / pdf / 1810.08580.pdf and arxiv.org / abs / 1810.08580), which is incorporated by reference as part of the disclosure of this patent document.

[0044] To minimize dispersion and attenuation within the cable sections as shown in FIG. 2 and other cable implementations, each cable section can be bump-bonded using superconducting contact pads or bumps to circuit modules or chips with electronic superconducting circuits, such as the qubit management circuit module 104 and the interconnect circuit or classical control circuitry in module 106 (including, for example, SFQ pulse regenerators / repeaters). The classical controller chip for the qubit management module 104 and the quantum chip 102 may be placed in the cold stage of a dilution refrigerator and directly bump-bonded via superconducting contact pads (bumps) on both chips using MCM techniques. The superconducting contact pads (bumps) may be structured to contain indium, which is mechanically soft and has a superconducting transition temperature of 3.4 K. Alternatively, non-superconducting bump bonds may also be used to couple the classical controller chip 104 and the quantum chip 102, and the classical chip 104 may be further connected to other classical chips via superconducting or non-superconducting cables (coaxial or ribbon cables).

[0045] In some implementations, the ribbon cables can be connected by connecting to a special impedance transformer wafer or chip (e.g., 50-20 ohms), which is in turn bump bonded to the classical chip. Quantum chips can be connected to other quantum chips using microwave waveguides or other types of quantum links without destroying the quantum coherence between the chips. Both surfaces of each chip (quantum and classical) can be used to form circuits. These circuits can be interconnected using (e.g., superconducting) through-silicon vias (TSVs) and bump bonds.

[0046] The aforementioned direct bump bonding has several advantages and serves the following purposes: (1) to establish a mechanical connection between the quantum chip 102 and the classical controller chip 104; (2) to minimize the effects of noise on the quantum chip 102 and to minimize communication time between the classical controller chip 104 and the quantum chip 102; (3) to set a defined uniform distance (the same distance across the chips) between the chips 102 and 104 to establish a repeatable and invariant coupling capacitance and mutual inductance between the circuits on both chips during operation; (4) to provide a galvanic connection between the grounds on both chips 102 and 104 to form a common ground between them; and (5) to provide a galvanic connection of the signal lines to form a superconducting lossless loop between the chips 102 and 104. These loops can be used to provide flux bias for the qubits and the couplers between the qubits, (6) provide galvanic connections between the chips to transmit SFQ pulses between the chips, and (7) provide galvanic connections to deliver constant or switchable currents, including currents to form a single superconducting circuit with elements on both chips.

[0047] The placement and design of the common ground and superconducting bumps 140 can be done in an array, fence, wall, etc. Referring to Figure 3A, shown is a schematic perspective view of a portion of a chip 1000 (typically made from Si) with a transmission line structure 1001 and bumps 140 residing on metallization 1002. Some of the metallizations 1002 may be connected to the ground plane of the chip 1000, while others may be connected to other parts of the circuitry on the chip 1000. In still other applications, including applications using TSV and bump bonding, the metallizations 1002 may not be present.

[0048] The bumps 140 create a fence 140' that improves electromagnetic isolation between the transmission line structures 1001 and reduces crosstalk between them. In some implementations, instead of multiple bumps 140, the fence can be made as a continuous wall 140'', as shown diagrammatically in FIG. 3B for the same type of transmission line structure. Also, in various implementations, the fence 140'' or wall 140'' can be positioned on either the quantum chip 102 or the classical chip 104.

[0049] FIG. 3C shows an example in which superconducting fences 140′ or walls 140″ are used to form 3D compartments 300, each comprising one or more qubits, classical circuitry 203, and superconducting metallization 201′, which is shown diagrammatically in FIG. 3C as a cross-section of a portion of an MCM structure. Such a setup results in better electromagnetic isolation of the qubits from each other (in other words, reducing crosstalk) and increases the quality factor of the resonators incorporating or connected to the qubits. This is further illustrated through simulation results presented in FIG. 4D.

[0050] FIG. 4A shows a schematic cross-section of a section of an example of a preferred MCM structure with two chips 301 and 302, which are mechanically and electrically connected via bumps 140. The top chip 301 has a metallization 201′ in the form of a superconducting thin film. The bottom chip 302 has a transmission line 202 and a section of the metallization 201′ that serves as a ground plane for the transmission line 202. The transmission line 1001 in FIGS. 3A-3C and the transmission line 202 in FIGS. 4A-4C are shown as examples, and in general other circuits (both classical and quantum) or circuit elements can be represented by the sections 1001 and 202. A central section of the metallization 201′ separates the two transmission lines 202 and is connected via bumps 140 to the metallization 201′ on the top chip.

[0051] Figure 4B shows another embodiment with a structure similar to Figure 4A, but with modifications, in which the bumps 140 that connect the central section of the metallization 201' on the bottom chip to its counterpart 201' on the top chip are absent. Figure 4C shows a cross section of a section of the bottom chip with the transmission lines 202 and metallization 201' without any bumps 140.

[0052] Figure 4D shows the results of simulated coupling between the transmission lines 202 for each of the three cases described above. Curves 1-3 in Figure 4D correspond to the cases depicted in Figures 4A, 4B, and 4C, respectively. From these plots it can be inferred that the minimum coupling (best result) is obtained for the structure shown in Figure 4A, where the transmission lines 202 are separated from each other by a fence created by bumps 140. A similar situation, i.e., reduction of crosstalk, will be realized in more complex circuits, in particular when the quantum circuits are separated from each other by a fence 140' or a continuous wall 140''.

[0053] The aforementioned coupling of the classical controller chip 104 and the quantum chip 102 in the form of an MCM may be advantageous in some implementations for one or more of the following reasons: (i) the above-mentioned chip-to-chip bonding allows the classical control chip 104 and the quantum chip 102 to be fabricated using different technologies that may not be fully compatible with each other. The separate fabrication of these chips 104 and 102 allows the chips 104 and 102 to be fabricated individually with high quality and using state-of-the-art fabrication techniques. (ii) It is experimentally determined that if both the classical control circuitry 104 and the quantum circuitry 102 are fabricated on the same chip, the quantum chip 102 may suffer from quasiparticle poisoning from the classical control chip 104, which leads to enhanced decoherence. (iii) Input / output signals between room temperature electronics and the MCM or between the repeater and the MCM are accomplished via connecting appropriate cables to the classical control chip 104, which may reduce the effect of electrical noise from the hotter stages of the setup on the quantum chip 102.

[0054] An example for implementing such an MCM is shown in Figures 5A and 5B for chips 102 and 104. As shown, the top quantum chip 102 contains the qubit circuitry and readout resonators. The bottom classical chip 104 includes the SFQ circuitry and power lines for coupling to the qubit resonators for each qubit. The current bias lines I BQ or I F is used to provide a flux bias current to each qubit. This flux bias current is provided by the current bias line I BQ Alternatively, the current bias line can be provided through inductive coupling across the gap between the classical chip and the quantum chip 102, as illustrated by the current bias line I FAs illustrated by the current bias line I, an inductor may reside on the quantum chip 102 with the qubits that extends from the classical chip 104 through the bump 140 to the quantum chip 102, thereby coupling to the qubits to provide a flux bias. F can be configured asymmetrically, as shown in Figure 5A, or symmetrically, as shown in Figure 5B. Superconducting indium bumps 140 also connect the ground planes of the two chips 102 and 104. Other configurations of the MCM module are also possible.

[0055] 5C shows another example for implementing the MCM assembly for chips 104 and 102, where a per-qubit readout resonator is located on classical chip 104, in contrast to the configuration described above in which the qubit and readout resonator are integrated together on quantum chip 102. In various implementations, a superconducting qubit can be coupled to an electromagnetic resonator for readout based on the state of the qubit (ground or excited) inducing a shift in the resonant mode of the electromagnetic resonator. Both the qubit and readout resonators are planar and can be fabricated on the same chip as disclosed in the paper entitled "Strong coupling of a single photon to a superconducting qubit using circuit quantum electrodynamics" by Wallraff, A., Schuster, DI, Blais, A., Frunzio, L., Huang, RS, Majer, J., Kumar, S., Girvin, SM, and Schoelkopf, RJ, in Nature, 431(7005), 162-167 (2004).Alternatively, various quantum circuit designs seek to take advantage of having as much electromagnetic field density as possible within a loss-free vacuum by coupling qubits to 3D resonant modes, such as those within a 3D cavity or resonator, as described in the paper entitled "Observation of High Coherence in Josephson Junction Qubits Measured in a Three-Dimensional Circuit QED Architecture" by Paik, H., Schuster, DI, Bishop, LS, Kirchmair, G., Catelani, G., Sears, AP, Johnson, BR, Reagor, MJ, Franzio, L., Glazman, LI, Girvin, SM, Devoret, MH, and Schoelkopf, RJ, in Physical Review Letters, 107(24), 240501 (2011).

[0056] One way to implement the design of FIG. 5C is to design both the qubits and readout resonators in a planar, two-dimensional (2D) configuration per circuit, while fabricating each qubit and its corresponding readout resonator on a different substrate and packaging and stacking them in an MCM such that they lie in different XY planes and are separated by a chip-to-chip distance d along the Z axis. In this design, the individual elements (e.g., each qubit and its corresponding readout resonator) are 2D components that each reside entirely on their own substrate, but the integration density of the device or module is increased by coupling different 2D components or circuits in a three-dimensional (3D) fashion such that the mode coupling is out-of-plane coupling between the planar qubit circuit to the matching planar readout resonator. This configuration combines 2D components stacked in a 3D configuration, and thus may be referred to as a "2.5D" architecture. Under the present "2.5D" design, the planar readout resonator resides entirely on the classical chip and therefore exhibits 2D modes in the plane of the classical chip, independent of the quantum chip containing the corresponding qubits. When the planar readout resonator is brought close to the quantum chip, as in an MCM, there is a small out-of-plane component that provides coupling between the qubits and their corresponding readout resonators, but the majority of the readout resonator modes are still 2D in the plane of the classical chip. The present design is advantageous due to the simplicity of fabrication of 2D circuits or components, design flexibility, and / or increased integration density.

[0057] Specifically, the embodiment of FIG. 5C illustrates diagrammatically that a transmon qubit in the quantum qubit chip 102 is capacitively coupled to a corresponding readout resonator in the classical chip 104; in this case, the coupling occurs between two capacitor pads separated by the chip-to-chip distance d. The readout resonator may be implemented, for example, as a serpentine coplanar waveguide (CPW) resonator or a lumped element resonator. Other qubits are also diverse, such as flaxonium, C-shunt flux qubits (CSFQ), Cooper pair boxes, or other qubits along the charge / flux spectrum. In addition, the coupling across the gap may be capacitive or inductive in nature.

[0058] The two substrates, supporting the qubits in chip 102 and the readout resonator in chip 104, respectively, may be connected by bump bonds 140. In implementations where the coupling between the qubits and the readout resonator is via capacitive or inductive coupling, these bonds 140 may be implemented to provide a purely mechanical connection or engagement, meaning that the qubits are electrically isolated from the resonator ground plate, and thus are referred to as "floating qubits". Alternatively, the bump bonds may provide a superconducting connection between the ground plates on both substrates, such that each qubit is a "grounded qubit". In various implementations, the classical controller chip 104 may include electronic circuitry suitable for high-speed exchange of information between the chip 104 and the quantum chip 102. FIG. 6 shows an example of an MCM containing a classical controller chip 104 and a quantum chip 102. In FIG. 6, the qubits and readout resonator are fabricated on the top quantum chip 102. A Josephson photomultiplier (JPM) and a reflectance measurement port are fabricated on the bottom classical controller chip 104. The JPM is coupled to an SFQ comparator with a digital trigger in and a digital result out. For example, the comparator may be implemented as a standard SFQ circuit element, primarily used in SFQ analog-to-digital converters. All flux lines for the JPM and qubits are present on the classical controller chip 104. A readout (RO) port is also added to measure the readout resonator using microwaves. A more detailed layout of the JPM-SFQ comparator circuit is shown in the example of FIG. 7. As shown by the right side of FIG. 7, a loop is made from the junction of the bottom comparator to convert the magnetic flux into a current. This loop is connected to the mutual inductance M c Another small junction J Q is added to the loop to eliminate any residual magnetic flux left in the loop as a result of switching. B1 and I B2 Two bias currents from are used to adjust the phase of the junctions of the two comparators.

[0059] Figure 8 shows an example of a circuit design for improving the capacitive coupling between the classical SFQ chip 104 and the qubits belonging to the quantum chip 102. Figure 8 shows the capacitive coupling as described above in schematic form. The SFQ signal from the classical chip 104 is delivered to the qubit via a driver 401, a passive transmission line (PTL) 402, and a capacitor 500 created by the overlapping area A of a portion of the PTL and a portion of the qubit 202. The capacitance C m is proportional to the area A and thus to the distance d that the PTL 402 extends into the appropriate portion of the qubit. Due to non-ideal reproducibility of the technological conditions, this distance d may vary from process to process, which is related to the coupling capacitance δC m This results in an undesirable variation of ∝δd.

[0060] Figure 9 shows an alternative implementation to Figure 8 to overcome the above-mentioned shortcomings in the design of Figure 8. The design of Figure 9 uses two passive transmission lines (PTLs) 402 to provide capacitive coupling and reduce variations in capacitive coupling caused by mismatch between the PTLs 402 and the appropriate portion of the qubit in the design of Figure 8. Figure 9 uses capacitive coupling with two capacitors formed by overlapping areas A1 and A2. For the two PTLs 402 with a conductive plane in the quantum chip 202, the total coupling capacitance C m is the sum of the two capacitors, represented by the overlapping areas A1 and A2, and hence the following relationship is satisfied: C m ∝ A1+A2∝ d1+d2;δC m will be preserved regardless of the actual positioning d1, d2 due to ∝ δ(d1+d2)=0. An advantage of the coupling design in Fig. 9 is the reproducibility of the coupling capacitance for devices fabricated at different steps, which is important for establishing reproducible qubit control.

[0061] The above embodiments of the disclosed quantum computing system provide unique interconnection designs for different modules, allowing practical and scalable implementations based on new system designs and new interconnection designs that reduce or eliminate direct wiring connections between room temperature and the cryostage where the quantum chips are placed. Multiplexing and demultiplexing circuits are placed on the qubit management modules and digital processing modules, allowing each signal line to carry signals to / from multiple qubits in the quantum array, thus reducing the amount of wiring required between modules. The disclosed system designs and interconnections will allow the quantum computing system to be scaled with different quantum computing powers for different applications. In the implementation, qubit control can be implemented by placing an SFQ control chip in close proximity to the quantum circuit chip with suitable interconnects that operate with SFQ control and at different cryogenic temperatures, for example, from liquid He temperatures for classical non-quantum processing circuits or modules to millikelvin temperatures for one or more quantum circuits or processors.

[0062] Implementation of various features disclosed in this patent document may be based on what is disclosed in this patent document in light of various technical features in the following published references, which are incorporated by reference as part of the disclosure of this patent document: 1. “Energy-Efficient Single Flux Quantum Technology” by Oleg A. Mukhanov in IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 21, NO. 3, JUNE 2011. 2. “Cryo-CMOS for Quantum Computing” by Charbon et al. in IEEE, 2016. 3. “Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less Than 2 mW at 3 K” by Leonard Jr. et al., in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 11, NOVEMBER 2019. 4. “Digital Coherent Control of a Superconducting Qubit” by Bardin et al., in PHYSICAL REVIEW APPLIED 11, 014009 (2019).

[0063] Although this patent document contains many details, these should not be interpreted as limitations on any subject matter or the scope of what may be claimed, but rather as descriptions of features that may be specific to certain embodiments of a particular technique. Certain features described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Also, although features may be described above as acting in a combination and may be initially claimed as such, in some cases one or more features from a claimed combination may be excluded from the combination, and the claimed combination may also be subject to subcombinations or variations of the subcombination.

[0064] Although only a few implementations and examples are described, other implementations, improvements, and variations can be made based on what is described and illustrated in this patent document.

Claims

1. A system capable of information processing based at least in part on quantum computing using a plurality of quantum states of a plurality of quantum bits, the system comprising: a cryostat system structured to include a plurality of different cryogenic stages operable to provide a low cryogenic temperature and a plurality of higher cryogenic temperatures; a quantum computing module surrounded by the cryostat system at the low cryogenic temperature, the quantum computing module comprising a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit being structured as a superconducting circuit at the low cryogenic temperature such that, as a quantum mechanical system, each qubit circuit exhibits a plurality of different quantum states and quantum mechanically interacts with other qubit circuits via quantum entanglement to cause a superposition or correlation of the plurality of different quantum states of the plurality of qubit circuits; a quantum bit management circuit module surrounded by the cryostat system, the quantum bit management circuit module disposed adjacent to the quantum computing module and coupled to be maintained at cryogenic temperatures; a plurality of quantum bit control circuits supported by a second integrated chip and configured to direct a plurality of control signals to the plurality of quantum bit circuits, respectively, to control the plurality of quantum bit circuits; and a plurality of quantum bit readout circuits supported by the second integrated chip and configured to output a plurality of readout signals, respectively, from the plurality of quantum bit circuits. a quantum bit management circuit module, the quantum bit control circuits and the quantum bit readout circuits being structured to include superconducting circuits at the low cryogenic temperature and operable to operate with the control signals and the readout signals in a non-quantum classical manner based on digital processing, the second integrated chip being mated to the first integrated chip to form a multi-chip module to transfer the control signals and the readout signals between the first integrated chip and the second integrated chip; a plurality of circuit modules enclosed by the cryostat system at the higher cryogenic temperatures, the plurality of circuit modules structured to communicate with the quantum bit management circuit module in relation to the plurality of control signals and the plurality of readout signals; a plurality of conductive bumps formed to mechanically and electrically engage the first integrated chip and the second integrated chip with one another, the plurality of conductive bumps being structured to separate different qubit circuits on the first integrated chip and separate different transmission lines on the second integrated chip; a plurality of conductive wires coupled between the quantum bit management circuit module and at least one of the plurality of circuit modules in a plurality of higher temperature stages of the cryostat system to provide communications and transfer signals between the quantum bit management circuit module and the at least one of the plurality of circuit modules; a plurality of communication links for performing the information processing at a plurality of different rates during operation of the system, the plurality of communication links including one or more first communication links formed between the quantum computing module and the quantum bit management circuit module, one or more second communication links formed between the quantum computing module and at least one of the plurality of circuit modules, and one or more third communication links formed between the quantum computing module and one or more processors disposed outside the cryostat system, each of the one or more first communication links configured to provide communication with a first communication delay, each of the one or more second communication links configured to provide communication with a second communication delay longer than the first communication delay, and each of the one or more third communication links configured to provide communication with a third communication delay longer than the second communication delay; A system comprising:

2. the plurality of conductive bumps are for providing a mechanical engagement between the first integrated chip and the second integrated chip, the plurality of conductive bumps are not electrically connected to circuitry on either the first integrated chip or the second integrated chip; 10. The system of claim 1 , wherein the quantum computing module and the quantum bit management circuitry module are coupled to each other to exchange information via conductive or inductive coupling.

3. 2. The system of claim 1 , wherein the plurality of conductive bumps are connected such that at least a portion of the plurality of conductive bumps form a conductive path between the quantum bit management circuit module and the quantum computing module for transfer of the plurality of control signals and a portion of the plurality of readout signals without using other wiring between the quantum bit management circuit module and the quantum computing module.

4. 2. The system of claim 1, wherein the plurality of conductive bumps comprises a plurality of conductive insulating bumps arranged to reduce crosstalk between the plurality of conductive wires by forming a plurality of insulating fences separating the plurality of conductive wires.

5. 10. The system of claim 1, wherein the quantum computing module includes a plurality of conductive insulating bumps arranged to form a plurality of insulating fences separating the plurality of qubit circuits to reduce crosstalk between each of the plurality of qubit circuits and to reduce decoherence of the plurality of qubit circuits.

6. The system of claim 1, further comprising a plurality of conductive insulating walls arranged to reduce crosstalk between the plurality of conductive wires by forming a plurality of insulating walls separating the plurality of conductive wires.

7. 10. The system of claim 1, wherein the quantum computing module includes a plurality of conductive insulating walls that separate the plurality of qubit circuits to reduce crosstalk between each of the plurality of qubit circuits and to reduce decoherence of the plurality of qubit circuits.

8. 2. The system of claim 1, wherein the quantum bit management circuitry module and the quantum computing module are structured to include a capacitive coupling network to enable capacitive coupling between the quantum bit management circuitry module and the quantum computing module to provide signal transmission separate from the conductive path formed by the plurality of conductive bumps.

9. 2. The system of claim 1, wherein the quantum bit management circuitry module and the quantum computing module are structured to include a magnetic coupling network to enable magnetic inductive coupling between the quantum bit management circuitry module and the quantum computing module to provide signal transmission separate from the conductive path formed by the plurality of conductive bumps.

10. The system of claim 1, further comprising a flexible non-conductive material on which the plurality of conductive wires are formed and separated from one another, the flexible non-conductive material and the plurality of conductive wires forming a flexible ribbon connecting at least one of the plurality of circuit modules and the quantum bit management circuit module.

11. 10. The system of claim 1 , wherein each qubit circuit comprises a superconducting Josephson junction circuit at the low cryogenic temperature.

12. 10. The system of claim 1 , wherein the quantum bit management circuit module includes superconducting switching circuitry distinct from Josephson junction circuitry.

13. 10. The system of claim 1 , wherein the quantum bit management circuit module comprises a Josephson junction circuit.

14. 10. The system of claim 1 , wherein the quantum bit management circuit module comprises a single flux quantum (SFQ) logic circuit.

15. 10. The system of claim 1 , wherein the quantum bit management circuit module comprises a quantum flux parametron circuit.

16. 10. The system of claim 1 , wherein the quantum bit management circuit module includes a nanowire switch.

17. 10. The system of claim 1 , wherein the quantum bit management circuit module comprises a superconducting ferromagnetic transistor.

18. 10. The system of claim 1 , wherein the quantum bit management circuit module comprises a superconducting spintronic device.

19. 10. The system of claim 1 , wherein the quantum bit management circuit module comprises a field effect superconducting device.

20. The system of claim 1, further comprising an optical transmitter device and receiver device providing communication between the multiple cryogenic stages located at the highest temperature of the cryostat system and the multiple room-temperature electronics by enabling transmission and reception of optical signals between the multiple cryogenic stages and the multiple room-temperature electronics.

21. 10. The system of claim 1 , wherein the quantum bit management circuitry module and the quantum computing module are maintained at the same low cryogenic temperature.

22. the quantum computing module further comprising a plurality of readout resonators supported by the first integrated chip and configured to respectively interact with the plurality of qubit circuits to generate a plurality of qubit circuit readout signals; 2. The system of claim 1, wherein the plurality of quantum bit readout circuits are supported by the second integrated chip and are structured to receive the plurality of quantum bit circuit readout signals respectively and output the plurality of readout signals respectively by interacting with the plurality of readout resonators respectively supported by the first integrated chip.

23. the plurality of quantum bit readout circuits supported by the second integrated chip are structured to include a plurality of readout resonators supported by the second integrated chip and are structured to generate a plurality of quantum bit circuit readout signals by respectively interacting with the plurality of quantum bit circuits supported by the first integrated chip; 2. The system of claim 1, wherein the plurality of quantum bit readout circuits supported by the second integrated chip are structured to receive the plurality of quantum bit circuit readout signals and output the plurality of readout signals respectively by interacting with the plurality of readout resonators respectively.

24. A method for information processing based at least in part on quantum computing using a plurality of quantum states of a plurality of qubits, the method comprising: operating a quantum computing module comprising a first integrated chip structured to support a plurality of qubit circuits, the plurality of qubit circuits exhibiting a plurality of different quantum states as a quantum mechanical system and operable to induce quantum mechanical interactions among the plurality of qubit circuits to induce a superposition or correlation of the plurality of different quantum states of the plurality of qubit circuits; causing a plurality of quantum bit control circuits supported by a second integrated chip to control, respectively, the plurality of quantum bit circuits by directing a plurality of control signals to the plurality of quantum bit circuits, respectively; operating a plurality of quantum bit readout circuits to output a plurality of readout signals from the plurality of quantum bit circuits, the plurality of readout signals representing a plurality of quantum states of the plurality of quantum bit circuits, respectively; thermally coupling the plurality of quantum bit circuits, the plurality of quantum bit control circuits, and the plurality of quantum bit readout circuits to a common cryogenic stage; applying the control signals from the quantum bit control circuits to the quantum bit circuits, respectively, by coupling the quantum bit circuits, the quantum bit control circuits, and the quantum bit readout circuits via conductive bumps that mechanically and electrically engage with each other on the first integrated chip and the second integrated chip, the conductive bumps being structured to separate different quantum bit circuits on the first integrated chip and separate different transmission lines on the second integrated chip; transmitting information in connection with operating the plurality of quantum bit circuits and the plurality of quantum bit control circuits and the plurality of quantum bit readout circuits by using a plurality of conductive wires coupled between a quantum bit management circuit module and one or more circuit modules at one or more elevated temperatures that are greater than a temperature of the common cryogenic stage coupled to the plurality of quantum bit circuits and the plurality of quantum bit control circuits and the plurality of quantum bit readout circuits; using a plurality of communication links to perform the information processing at a plurality of different speeds, the plurality of communication links including one or more first communication links formed between the quantum computing module and the quantum bit management circuit module, one or more second communication links formed between the quantum computing module, at least one of the plurality of quantum bit control circuits and the plurality of quantum bit readout circuits, and one or more third communication links formed between the quantum computing module and one or more processors, each of the one or more first communication links configured to provide communication with a first communication delay, each of the one or more second communication links configured to provide communication with a second communication delay longer than the first communication delay, and each of the one or more third communication links configured to provide communication with a third communication delay longer than the second communication delay; A method comprising:

25. The method according to claim 24, the method comprising one or more operating steps when operating a system described in any one of claims 1 to 23.

26. The system described in claim 1, wherein the plurality of conductive bumps includes a plurality of conductive superconducting bumps.

27. ​​The system described in claim 26, wherein the quantum computing module and the quantum bit management circuit module are coupled to each other using the plurality of conductive superconducting bumps to provide signal transmission between the quantum computing module and the quantum bit management circuit module via a conductive path formed between the quantum computing module and the quantum bit management circuit module, or via a capacitive coupling formed between the quantum computing module and the quantum bit management circuit module, or via a magnetic coupling formed between the quantum computing module and the quantum bit management circuit module.

28. The method of claim 24, wherein the plurality of conductive bumps includes a plurality of conductive superconducting bumps.

29. The method of claim 28, wherein the quantum computing module and the quantum bit management circuit module are coupled to each other using the plurality of conductive superconducting bumps to provide signal transmission between the quantum computing module and the quantum bit management circuit module via a conductive path formed between the quantum computing module and the quantum bit management circuit module, or via a capacitive coupling formed between the quantum computing module and the quantum bit management circuit module, or via a magnetic coupling formed between the quantum computing module and the quantum bit management circuit module.

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