Driving circuit, driving method thereof, and display device

Abstract

The present embodiment provides a driving circuit, a driving method thereof, and a display device, which relate to the display technology field. The driving circuit is for driving a waiting-to-drive element and includes a driving element. The driving element and the waiting-to-drive element are connected in series between a first operating voltage terminal and a second operating voltage terminal. The driving element includes a driving sub-circuit, a writing sub-circuit, and a grayscale control sub-circuit. The writing sub-circuit writes a first data voltage provided from the first data signal terminal to the driving sub-circuit. The grayscale control sub-circuit transmits the first operating voltage provided by the first operating voltage terminal to the driving sub-circuit. The driving sub-circuit generates a driving current. The grayscale control sub-circuit further controls the on-time of the current path.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to Chinese Patent Application No. 201810696655.5, filed on June 29, 2018, the contents of which are incorporated herein by reference. [Technical field]

[0002] The present application relates to the field of display technology, and in particular to a driving circuit and a driving method thereof, and a display device. [Background technology]

[0003] Regarding OLED (Organic Light Emitting Diode) display devices, micro light emitting diode display devices (such as Micro LED display devices or μLED display devices) have the advantages of low driving voltage, long life, wide temperature resistance, etc., and are gradually being applied to the mobile terminal field. Summary of the Invention [Means for solving the problem]

[0004] In one aspect, the present application provides a drive circuit including a drive element that drives a drive waiting element, the driving element and the waiting-to-drive element are connected in series between a first operating voltage terminal and a second operating voltage terminal, and the driving element provides a driving signal to the waiting-to-drive element to control an on-time of a signal path between the first operating voltage terminal and the second operating voltage terminal; The driving element includes a driving sub-circuit, a writing sub-circuit, and a grayscale control sub-circuit; the write sub-circuit is connected to a first scan signal terminal, a first data signal terminal and the drive sub-circuit, and the write sub-circuit writes a first data voltage provided from the first data signal terminal to the drive sub-circuit under the control of the first scan signal terminal; The gray scale control sub-circuit is connected to a driving control signal terminal, a second scanning signal terminal, a second data signal terminal and the driving sub-circuit; The grayscale control sub-circuit provides a first operating voltage provided by the first operating voltage terminal to the driving sub-circuit under control of the driving control signal terminal; the drive subcircuit generates the drive signal based on the first data voltage and the first actuation voltage; The grayscale control subcircuit further provides a drive circuit for controlling an on-time of the current path under control of the drive control signal terminal, the second scan signal terminal and the second data signal terminal.

[0005] According to an embodiment of the present application, the grayscale control sub-circuit includes a first control sub-circuit and a second control sub-circuit; the first control subcircuit is connected to the drive control signal terminal, the drive subcircuit, and the second control subcircuit, and the first control subcircuit transmits a first operating voltage provided by the first operating voltage terminal to the drive subcircuit under control of the drive control signal terminal; the first control subcircuit further transmits a drive current generated by the drive subcircuit to the second control subcircuit under control of the drive control signal terminal to control an on-time of the current path; The second control sub-circuit is further connected to the second scan signal terminal and the second data signal terminal, and the second control sub-circuit controls the on-time of the current path under the control of the second scan signal terminal and the second data signal terminal.

[0006] According to an embodiment of the present application, the driving circuit further includes a compensation sub-circuit; The compensation sub-circuit is connected to the first scan signal terminal and the driving sub-circuit, and the compensation sub-circuit compensates a threshold voltage of the driving sub-circuit under control of the first scan signal terminal.

[0007] According to an embodiment of the present application, the driving circuit further comprises a reset sub-circuit, The reset subcircuit is connected to a reset voltage terminal, a reset control signal terminal and the drive subcircuit, and the reset subcircuit transmits a reset voltage provided by the reset voltage terminal to the drive circuit under the control of the reset control signal terminal.

[0008] According to an embodiment of the present application, the first control sub-circuit includes a first transistor and a second transistor; an anode of the waiting-to-be-driven element is connected to the second control subcircuit, a cathode of the waiting-to-be-driven element is connected to the second operating voltage terminal, a gate of the first transistor is connected to the operating control signal terminal, a first pole is connected to the first operating voltage terminal, and a second pole is connected to the driving subcircuit; The second transistor has a gate connected to the drive control signal terminal, a first pole connected to the drive sub-circuit, and a second pole connected to the second control sub-circuit.

[0009] According to an embodiment of the present application, the first control sub-circuit includes a first transistor and a second transistor; an anode of the waiting-to-be-driven element is connected to the first operating voltage terminal, a gate of the first transistor is connected to the driving control signal terminal, a first pole is connected to the cathode of the waiting-to-be-driven element, and a second pole is connected to the driving sub-circuit; The second transistor has a gate connected to the drive control signal terminal, a first pole connected to the drive sub-circuit, and a second pole connected to the second control sub-circuit.

[0010] According to an embodiment of the present application, the second control sub-circuit is further connected to a first voltage terminal, the second control sub-circuit comprising a third transistor, a fourth transistor, and a first capacitor; a gate of the third transistor is connected to the second scan signal terminal, a first electrode is connected to the second data signal terminal, and a second electrode is connected to the gate of the fourth transistor; one end of the first capacitor is connected to the second pole of the third transistor, and the other end of the first capacitor is connected to the first voltage terminal; The cathode of the ready-to-drive element is connected to the second operating voltage terminal, the first pole of the fourth transistor is connected to the first control sub-circuit, and the second pole is connected to the anode of the ready-to-drive element.

[0011] According to an embodiment of the present application, the second control sub-circuit is further connected to a first voltage terminal, the second control sub-circuit comprising a third transistor, a fourth transistor, and a first capacitor; a gate of the third transistor is connected to the second scan signal terminal, a first electrode is connected to the second data signal terminal, and a second electrode is connected to the gate of the fourth transistor; one end of the first capacitor is connected to the second pole of the third transistor, and the other end of the first capacitor is connected to the first voltage terminal; The anode of the waiting-to-drive element is connected to the first operating voltage terminal, the cathode of the waiting-to-drive element is connected to the first control sub-circuit, and the first pole of the fourth transistor is connected to the first control sub-circuit and the second pole is connected to the second operating voltage terminal.

[0012] According to an embodiment of the present application, the driving sub-circuit is further connected to a second voltage terminal, the driving sub-circuit further comprising a driving transistor; The gate of the drive transistor is connected to the second voltage terminal, a first pole is connected to the writing sub-circuit, and a second pole is connected to the grayscale control sub-circuit.

[0013] According to an embodiment of the present application, the driving sub-circuit is further connected to a second voltage terminal, the driving sub-circuit comprising a driving transistor and a second capacitor; A gate of the driving transistor is connected to one end of the second capacitor, a first pole of the second capacitor is connected to the writing sub-circuit, and a second pole of the second capacitor is connected to the grayscale control sub-circuit; The other end of the second capacitor is connected to the second voltage terminal.

[0014] According to an embodiment of the present application, the write sub-circuit includes a fifth transistor; The fifth transistor has a gate connected to the first scan signal terminal, a first pole connected to the first data signal terminal, and a second pole connected to the driving sub-circuit.

[0015] According to an embodiment of the present application, the compensation sub-circuit includes a sixth transistor; The gate of the sixth transistor is connected to the first scan signal terminal, and a first pole and a second pole are both connected to the driving sub-circuit.

[0016] According to an embodiment of the present application, the reset sub-circuit comprises a seventh transistor; The seventh transistor has a gate connected to the reset control signal terminal, a first pole connected to the reset voltage terminal, and a second pole connected to the drive sub-circuit.

[0017] In another aspect, the present application provides a drive circuit comprising first to seventh transistors, a first capacitor, a second capacitor, a drive transistor, a reset control signal terminal, a drive control signal terminal, a first data signal terminal, a second data signal terminal, a first scanning signal terminal, a second scanning signal terminal, a first operating voltage terminal, a first voltage terminal, and a second voltage terminal, the drive circuit driving a drive waiting element to operate it, the drive control signal terminal is connected to the gate of the first transistor and the gate of the second transistor; the first data signal terminal is connected to a first pole of the fifth transistor; the second data signal terminal is connected to a first pole of the third transistor; the first scanning signal terminal is connected to a gate of a fifth transistor and a gate of a sixth transistor; the second scanning signal terminal is connected to the gate of the third transistor; the first operating voltage terminal is connected to a first pole of the first transistor; the first voltage terminal is connected to one end of the first capacitor; the second voltage terminal is connected to one end of the second capacitor; the reset control signal terminal is connected to the gate of the seventh transistor; the reset voltage terminal is connected to a first pole of the seventh transistor; a second pole of the first transistor and a second pole of the fifth transistor are connected to a first pole of the drive transistor; the other end of the second capacitor, a second electrode of the sixth transistor, and a second electrode of the seventh transistor are connected to a gate of the drive transistor; a first pole of the second transistor and a first pole of the sixth transistor are connected to a second pole of the drive transistor; a second electrode of the second transistor is connected to a first electrode of the fourth transistor; the other end of the first capacitor and the second electrode of the third transistor are connected to the gate of the fourth transistor; A drive circuit is provided in which the second pole of the fourth transistor is connected to a drive waiting element.

[0018] In another aspect, the present application provides a drive circuit comprising first to seventh transistors, a first capacitor, a second capacitor, a drive transistor, a reset control signal terminal, a drive control signal terminal, a first data signal terminal, a second data signal terminal, a first scanning signal terminal, a second scanning signal terminal, a power supply voltage terminal, a first voltage terminal, and a second voltage terminal, the drive circuit driving and operating a drive waiting element, the drive control signal terminal is connected to a gate of the first transistor and a gate of the second transistor; the first data signal terminal is connected to a first pole of the fifth transistor; the second data signal terminal is connected to a first pole of the third transistor; the first scanning signal terminal is connected to a gate of a fifth transistor and a gate of a sixth transistor; the second scanning signal terminal is connected to the gate of the third transistor; the power supply voltage terminal is connected to the second electrode of the fourth transistor; the first voltage terminal is connected to one end of the first capacitor; the second voltage terminal is connected to one end of the second capacitor; the reset control signal terminal is connected to the gate of the seventh transistor; the reset voltage terminal is connected to a first pole of the seventh transistor; a second pole of the first transistor and a second pole of the fifth transistor are connected to a first pole of the drive transistor; the other end of the second capacitor, a second electrode of the sixth transistor, and a second electrode of the seventh transistor are connected to a gate of the drive transistor; a first pole of the second transistor and a first pole of the sixth transistor are connected to a second pole of the drive transistor; a second electrode of the second transistor is connected to a first electrode of the fourth transistor; the other end of the first capacitor and the second electrode of the third transistor are connected to the gate of the fourth transistor; A drive circuit is provided in which a first pole of the first transistor is connected to the drive-ready element.

[0019] In another aspect, the present application provides a display device comprising a substrate, a plurality of sub-pixels in a display region of the display substrate, and a driving circuit and a drive-waiting element according to an embodiment of the present application within at least one of the sub-pixels, the driving circuit supplying a drive signal to the drive-waiting element.

[0020] In another aspect, the present application provides a method for driving a driving circuit having a plurality of scanning periods within one image frame, the grayscale control subcircuit having a first control subcircuit and a second control subcircuit, and in one of the scanning periods, the driving method of the driving circuit includes: providing a first scan signal to the first scan signal terminal and a first data voltage to the first data signal terminal, the first data voltage being written to a drive sub-circuit via a write sub-circuit; providing a second scan signal to a second scan signal terminal and a second data voltage to the second data signal terminal, such that a second control sub-circuit opens or closes under control of the second scan signal and the second data voltage; providing a drive control signal to a drive control signal terminal; providing a first operating voltage to the first operating voltage terminal; and transmitting the first operating voltage to a drive sub-circuit via a first control sub-circuit, under control of the drive control signal, the first scanning signal, the second scanning signal and the second data voltage, so that the waiting-to-be-driven element operates based on the first data voltage and the first operating voltage.

[0021] According to an embodiment of the present application, the method further comprises: The time at which the second scanning signal terminal outputs an active signal is later than the time at which the first scanning signal terminal outputs an active signal within one scanning period.

[0022] According to an embodiment of the present application, the driving circuit further includes a reset sub-circuit, and provides a first scanning signal to the first scanning signal terminal and a first data voltage to the first data signal terminal, and before the first data voltage is written to the driving sub-circuit via the write sub-circuit, the driving method of the driving circuit further includes: providing a reset control signal to a reset control signal terminal and providing a reset voltage to a reset voltage terminal, the reset voltage being transmitted through the reset sub-circuit to the drive sub-circuit.

[0023] According to an embodiment of the present application, the driving sub-circuit includes a driving transistor and a second capacitor, a gate of the driving transistor is connected to one end of the second capacitor, the other end of the second capacitor is connected to a second voltage terminal, and the voltages input to the second voltage terminal and the first operating voltage terminal are the same.

[0024] In order to more clearly explain the technical solutions of the embodiments of the present application or the prior art, the drawings used in the practical examples or the prior art are briefly described below. The drawings described below are only some embodiments of the present application, and it is obvious to those skilled in the art that other drawings can be derived from these drawings without exerting creative efforts. [Brief description of the drawings]

[0025] [Figure 1] FIG. 2 is a structural conceptual diagram of a driving circuit provided in some embodiments of the present application. [Diagram 2] FIG. 2 is a structural conceptual diagram of another driving circuit provided by some embodiments of the present application. [Diagram 3] FIG. 2 is a conceptual diagram showing a specific structure of the drive circuit shown in FIG. [Figure 4] FIG. 3 is a conceptual diagram showing a specific structure of the drive circuit shown in FIG. 2. [Diagram 5] 4 is a conceptual diagram showing a specific structure of each sub-circuit in the drive circuit shown in FIG. 3. [Figure 6] 5 is a conceptual diagram showing a specific structure of each sub-circuit in the drive circuit shown in FIG. 4. [Figure 7] FIG. 2 is a structural conceptual diagram of another driving circuit provided by some embodiments of the present application. [Figure 8] FIG. 2 is a structural conceptual diagram of another driving circuit provided by some embodiments of the present application. [Figure 9] FIG. 2 is a timing signal diagram provided by some embodiments of the present application. [Figure 10] 1 is a structural schematic diagram of a display panel provided by some embodiments of the present application; [Figure 11]2 is a flowchart of a driving method for a driving circuit provided in some embodiments of the present application; [Figure 12] FIG. 4 is another timing signal diagram provided by some embodiments of the present application. [Figure 13] FIG. 11 is a conceptual diagram showing a specific structure of each sub-circuit in a driving circuit according to another embodiment. [Figure 14] FIG. 11 is a conceptual diagram showing a specific structure of each sub-circuit in a driving circuit according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The following will clearly and comprehensively describe the technical solutions in the embodiments of the present application in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present application without exerting their creative efforts are all within the scope of the claims of the present application.

[0027] Some embodiments of the present application provide a driving circuit 01, which includes a driving element 100 and a waiting-to-be-driven element L, as shown in FIG. The driving element 100 and the drive-waiting element L are connected in series between a first operating voltage terminal VL1 and a second operating voltage terminal VL2. For example, as shown in FIG. 1, the driving element 100 is connected between a first operating voltage terminal VL1 and an anode of a waiting-to-be-driven element L, and the cathode of the waiting-to-be-driven element L is connected to a second operating voltage terminal VL2. Alternatively, for example, as shown in FIG. 2, the driving element 100 is connected between the second operating voltage terminal VL2 and the cathode of the waiting-to-be-driven element L, and the anode of the waiting-to-be-driven element L is connected to the first operating voltage terminal VL1.

[0028] The waiting-to-drive element L may be a light-emitting element such as a micro light-emitting diode, μLED, or Micro LED. The size level of μLED or Micro LED is at the micron (μm) level. In the embodiment of the present application, the waiting-to-drive element L is used as the light-emitting element, and the driving circuit 01 is used as the driving circuit. The waiting-to-drive element L may be other flow control type electronic components. In the present embodiment, the driving element 100 provides a driving current I and controls the on-time of a current path between a first operating voltage terminal VL1 and a second operating voltage terminal VL2. When the current path is on, the first operating voltage VDD output from the first operating voltage terminal VL1 and the second operating voltage VSS output from the second operating voltage terminal VL2 provide a potential difference to the current path, causing the driving current I to be transmitted to the light-emitting element L along the current path. Alternatively, the first operating voltage VDD may be at a constant high level, and the second operating voltage VSS may be at a constant low level. The light emitting element L receives the driving current I through the current path and emits light.

[0029] As shown in FIG. 3 or FIG. 4, the driving element 10 includes a driving sub-circuit 10, a writing sub-circuit 20, and a gradation control sub-circuit 30. The driving sub-circuit 10 includes a driving sub-circuit 20, a writing sub-circuit 20, and a gradation control sub-circuit 30. The write sub-circuit 20 is connected to the first scanning signal terminal G_A, the first data signal terminal D_A, and the drive sub-circuit 10. The write sub-circuit 20 writes a first data voltage Vdata_A provided from the first data signal terminal D_A to the drive sub-circuit 10 under the control of the first scanning signal terminal G_A. The gradation control sub-circuit 30 is connected to a light emission control signal terminal EM serving as a drive control signal terminal, a second scanning signal terminal G_B, a second data signal terminal D_B, and the drive sub-circuit 10.

[0030] When the driving circuit 01 has the structure shown in Fig. 1, the gradation control subcircuit 30 in the driving circuit 01 can be directly connected to the first operating voltage terminal VL1 and can be connected to the second operating voltage terminal VL2 via the light-emitting element L, as shown in Fig. 3. Alternatively, when the driving circuit 01 has the structure shown in Fig. 2, the gradation control subcircuit 30 in the driving circuit 01 can be connected to the first operating voltage terminal VL1 via the light-emitting element L and can be directly connected to the second operating voltage terminal VL2, as shown in Fig. 4. In the driving circuit 01 shown in Fig. 3, the gradation control subcircuit 30 transmits the first operating voltage VDD provided from the first operating voltage terminal VL1 to the driving subcircuit 10 under the control of the light-emitting control signal terminal EM. The driving sub-circuit 10 generates a driving current I based on a first data voltage Vdata_A and a first operational voltage VDD. The grayscale control subcircuit 30 is further used to control the on-time of the current path under the control of the emission control signal terminal EM, the second scanning signal terminal G_B and the second data signal terminal D_B.

[0031] From the above, the write subcircuit 20 can output the first data voltage Vdata_A related to the display gradation to the drive subcircuit 10, and the drive subcircuit 10 can generate the drive current I that causes the light-emitting element L to emit light. In addition, the gradation control subcircuit 30 can control the light-emitting time of the light-emitting element L by controlling the on-time of the current path formed in the process in which the drive current I flows into the light-emitting element L. Since the magnitude of the drive current I and the light-emitting time affect the effective luminance of the light-emitting element L, the effective light-emitting luminance of the light-emitting element L can be controlled by the magnitude of the first data voltage Vdata_A and the gradation control subcircuit 30 within one scanning period, thereby achieving the purpose of adjusting the display gradation. According to the embodiment of the present application, each of the driving circuits 01 is provided with a grayscale control subcircuit 30, and each of the driving circuits corresponding to the subpixels in the same row includes a grayscale control subcircuit 30 that is connected to different data signal lines (i.e., controlled by second data voltages Vdata_B that are independent of each other), so that the driving circuit 01 provided by the embodiment of the present application can individually control the brightness of the light-emitting element L (e.g., μLED) in the driving circuit 01. In addition, the driving circuit 01 provided by the embodiment of the present application is manufactured on a glass substrate or a transparent resin substrate in a display panel of a display device through a patterning process. When the light-emitting element is a μLED, a method for realizing a μLED display device that is low-cost, has a simple manufacturing process, and can be mass-produced can be provided.

[0032] The structure of each sub-circuit in the driver circuit 01 will now be described in detail. Taking the structure shown in FIG. 3 as an example, the grayscale control sub-circuit 30 may include a first control sub-circuit 301 and a second control sub-circuit 302, as shown in FIG.

[0033] 5, the first control sub-circuit 301 is connected to the light emission control signal terminal EM, the driving sub-circuit 10 and the second control sub-circuit 302. The first control sub-circuit 301 is used to transmit the first operating voltage VDD provided from the first operating voltage terminal VL1 to the driving sub-circuit 10 under the control of the light emission control signal terminal EM. The first control sub-circuit 301 is further used for transmitting the driving current I generated by the driving sub-circuit 10 to the second control sub-circuit 302 under the control of the emission control signal terminal EM, and controlling the on-time of the current path. The second control sub-circuit 302 is further connected to the second scan signal terminal G_B and the second data signal terminal D_B. The second control sub-circuit 302 is used to control whether the current path is turned on in one scan period and the total on-time in multiple scan periods under the control of the second scan signal terminal G_B and the second data signal terminal D_B.

[0034] As can be seen from the above, the current path can be turned on only when both the first control subcircuit 301 and the second control subcircuit 302 are in the on state, and the driving current I generated by the driving subcircuit 10 is output via the current path to the light-emitting element L. As a result, the effective light-emitting luminance of the light-emitting element L is subject to coordinated control of the driving current I, the first control subcircuit 301, and the second control subcircuit 302, increasing the number of factors that affect the effective light-emitting luminance of the light-emitting element L, and making the gradation values ​​that can be displayed by the subpixel having the driving circuit 01 more diverse.

[0035] According to an embodiment of the present application, as shown in FIG. 5, the first control sub-circuit 301 may include a first transistor T1 and a second transistor T2. Fig. 5 explains the structure of each sub-circuit in Fig. 3 by taking the structure shown in Fig. 3 as an example. In this case, as shown in Fig. 5, the cathode of the light-emitting element L is connected to the second operating voltage terminal VL2. The first transistor T1 has a gate connected to the emission control signal terminal EM, a first pole connected to the first operating voltage terminal VL1, and a second pole connected to the driving sub-circuit 10. The gate of the second transistor T2 is connected to the emission control signal terminal EM, a first pole is connected to the driving sub-circuit 10, and a second pole is connected to the second control sub-circuit 302. Additionally, the second control sub-circuit 302 is further connected to a first voltage terminal V1, which may be a ground terminal GND. The second control sub-circuit 302 comprises a third transistor T3, a fourth transistor T4 and a first capacitor C1. The third transistor T3 has a gate connected to the second scanning signal terminal G_B, a first electrode connected to the second data signal terminal D_B, and a second electrode connected to the gate of the fourth transistor T4. One end of the first capacitor C1 is connected to the second pole of the third transistor T3, and the other end of the first capacitor C1 is connected to the first voltage end V1.

[0036] As shown in FIG. 5, when the anode of the light-emitting element L is connected to the second control sub-circuit 302 and the cathode of the light-emitting element L is connected to the second operating voltage terminal VL2, the first pole of the fourth transistor T4 is connected to the first control sub-circuit 301 and the second pole is connected to the anode of the light-emitting element L. When the structure of the first control subcircuit 301 is as described above, the first pole of the fourth transistor T4 is connected to the second pole of the second transistor T2. According to another embodiment of the present application, the structure of each sub-circuit in FIG. 4 will be described by taking the structure shown in FIG. 4 as an example.

[0037] Fig. 6 is a structural conceptual diagram of each sub-circuit in Fig. 4, which is similar to the structure of each sub-circuit in Fig. 5, except that the connection manner of the light-emitting element L, the first control sub-circuit, and the second control sub-circuit is different. Specifically, referring to Fig. 4 and Fig. 6, the anode of the light-emitting element L is connected to the first operating voltage terminal VL1, and the cathode of the light-emitting element L is connected to the first pole of the first transistor T1. The first pole of the fourth transistor T4 is connected to the first control sub-circuit 301, and the second pole is connected to the second operating voltage terminal VL2.

[0038] According to an embodiment of the present application, as shown in Fig. 7, the driving sub-circuit 10 includes a driving transistor Td and a second capacitor C2, the gate of the driving transistor Td is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to a second voltage terminal V2. The second voltage terminal V2 may be the same as the first voltage terminal V1, and both are ground terminals GND. Alternatively, since the second voltage terminal V2 is close to the position of the first operating voltage terminal VL1, in order to make the layout design easier, the second voltage terminal V2 may be connected to the first operating voltage terminal VL1 and receive the first operating voltage VDD output from the first operating voltage terminal VL1. The gate of the driving transistor Td is connected to one end of the second capacitor C2, the first pole is connected to the writing sub-circuit 20, and the second pole is connected to the gradation control sub-circuit 30. When the gradation control sub-circuit 30 has the structure as described above, the second pole of the driving transistor Td is connected to the first pole of the second transistor T2.

[0039] According to an embodiment of the present application, the write sub-circuit 20 comprises a fifth transistor T5. The gate of the fifth transistor T5 is connected to the first scanning signal terminal G_A, the first pole is connected to the first data signal terminal D_A, and the second pole is connected to the driving sub-circuit 10. When the structure of the driving sub-circuit 10 is as described above, the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor Td. When the drive transistor Td in the drive sub-circuit 10 operates in the saturation region, the drive transistor Td can generate a drive current I according to its gate voltage and source voltage. The drive current formula is I=K(Vgs-Vth). 2It can be seen that the driving current I is affected by the threshold voltage Vth of the driving transistor Td. The threshold voltage Vth of the driving transistor Td drifts during operation, and the drift amounts of the threshold voltages Vth of the driving transistors Td located in different subpixels are not necessarily the same, so that when displaying the same gray scale data, the driving currents I generated by the driving transistors Td of different subpixels are different, which causes the brightness of the light-emitting elements L of different subpixels to be non-uniform, affecting the display effect.

[0040] To solve the above problem, the driving circuit 01 provided in the embodiment of the present application further includes a compensation sub-circuit 40, as shown in FIG. The compensation sub-circuit 40 is connected to the first scanning signal terminal G_A and the driving sub-circuit 10. The compensation sub-circuit 40 compensates the threshold voltage of the driving sub-circuit 10 under the control of the first scanning signal terminal G_A. When the driving sub-circuit 10 has the above structure, the compensation sub-circuit 40 can compensate the threshold voltage Vth of the driving transistor Td. The specific procedure for compensating the threshold voltage Vth will be described later.

[0041] Illustratively, the compensation subcircuit 40 may include a sixth transistor T6. The gate of the sixth transistor T6 is connected to the first scanning signal terminal G_A, and the first pole and the second pole are both connected to the driving sub-circuit 10. When the driving sub-circuit 10 has the above structure, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor Td, and the second pole of the sixth transistor T6 is connected to the gate of the driving transistor Td. In addition, since the signal remaining in the driving sub-circuit 10 from the previous image frame affects the display screen of the next image frame, the driving sub-circuit 01 provided in the embodiment of the present application further includes a reset sub-circuit 50, as shown in FIG. 7. The reset subcircuit 50 is connected to a reset voltage terminal VINT, a reset control signal terminal RS, and the driving subcircuit 10. The reset subcircuit 50 is used to transmit a reset voltage provided from the reset voltage terminal VINT to the driving subcircuit 10 under the control of the reset control signal terminal RS.

[0042] The reset subcircuit 50 includes a seventh transistor T7. The seventh transistor T7 has a gate connected to the reset control signal terminal RS, a first pole connected to the reset voltage terminal VINT, and a second pole connected to the driving sub-circuit 10. When the driving sub-circuit 10 has the structure as described above, the first pole of the seventh transistor T7 is connected to the gate of the driving transistor Td.

[0043] Note that Fig. 7 illustrates that the driving element 100 and the light-emitting element L adopt the connection method shown in Fig. 1. When the driving element 100 and the light-emitting device L adopt the connection method as shown in Fig. 2, the specific structures and connection method of the compensation sub-circuit 40 and the reset sub-circuit 50 are as described above, and the structure of the driving circuit 01 having the driving sub-circuit 10, the writing sub-circuit 20, the gradation control sub-circuit 30, the compensation sub-circuit 40 and the reset sub-circuit 50 is as shown in Fig. 8.

[0044] 5 to 8, a case where each transistor is a P-type transistor will be described as an example. In some embodiments of the present application, the transistor of each sub-circuit may be an N-type transistor. The first pole of the transistor may be the source and the second pole may be the drain, or the first pole may be the drain and the second pole may be the source.

[0045] Hereinafter, taking the structure of the driving circuit 01 shown in FIG. 7 as an example, the operation process of the driving circuit 01 within one image frame will be described in detail. In some embodiments of the present application, in order to enable a sub-pixel equipped with a driving circuit 01 to display more gray scale values ​​and improve the display effect, the driving circuit 01 can have multiple scanning periods S in one image frame. For example, as shown in FIG. 9, an image frame having three scanning periods S1, S2 and S3 is taken as an example.

[0046] Each scanning period can be divided into three phases: a first phase t1, a second phase t2, and a third phase t3. Taking the first scanning period S1 as an example, in the first stage t1, a low level is input to the reset control signal terminal RS, the seventh transistor T7 is turned on, and the reset voltage provided by the reset voltage terminal VINT is transmitted to the gate of the driving transistor Td through the seventh transistor T7 to reset the gate of the driving transistor Td, so as to prevent the voltage remaining in the driving transistor Td in the previous image frame from affecting the display of the current image frame. At this time, the voltage of the node N1 is the reset voltage provided by the reset voltage terminal VINT.

[0047] According to the embodiment of the present application, the reset voltage may be at a low level, and the driving transistor Td is close to being turned on but not turned on, thereby preparing to charge the gate of the driving transistor Td during the next data write step, and the first data voltage Vdata_A can be charged to the gate of the driving transistor Td faster. Therefore, when different data voltages are input to the driving transistors in the subsequent data write step, the write time of the data voltage can be shortened, so that the response times of all the driving transistors Td are approximately the same in all the driving circuits of the entire display panel, and the write times of the data voltages are approximately the same, and this installation method makes the display effect of the entire display panel more uniform.

[0048] The first phase t1 can be called the reset phase. In the second stage t2, a low level is input to the first scanning signal terminal G_A and the second scanning signal terminal G_B. Under the control of the first scanning signal terminal G_A, the fifth transistor T5 and the sixth transistor T6 are turned on. The first data voltage Vdata_A provided from the first data signal terminal D_A is transmitted to the first pole of the driving transistor Td through the fifth transistor T5.

[0049] After the sixth transistor T6 is turned on, the gate and the second pole of the driving transistor Td are electrically connected, so that the driving transistor Td becomes a diode. At this time, the first data voltage Vdata_A charges the gate of the driving transistor Td until the driving transistor Td is turned off. When the driving transistor Td is turned off, the gate-source voltage Vgs of the driving transistor Td is Vth, that is, Vg-Vs=Vth. At this time, the gate-source voltage (voltage at the N1 node) of the driving transistor Td is Vg=Vs+Vth=Vdata_A+Vth. In this case, the first data voltage Vdata_A is input to the gate of the driving transistor Td. Also, under the control of the second scanning signal terminal G_B, the third transistor T3 is turned on, and the second data voltage Vdata_B provided from the second data signal terminal D_B is transmitted to the gate of the fourth transistor T4 via the third transistor T3. The voltage of the node N2 is Vdata_B.

[0050] Under the action of the first capacitor C1 and the second capacitor C2, the potentials of the nodes N1 and N2 do not change before the first scanning signal terminal G_A and the second scanning signal terminal G_B output a low level again. The second phase t2 may be a data writing phase. In the third stage t3, as shown in FIG. 9, the emission control signal terminal EM provides a low level, and the first transistor T1 and the second transistor T2 are turned on.

[0051] In addition, the second data voltage Vdata_B output from the second data signal terminal D_B has two patterns, a high level (VGH) and a low level (VGL). The fourth transistor T4 may be set so that when the gate of the fourth transistor T4 receives a high level, the fourth transistor T4 is turned off, and when the gate of the fourth transistor T4 receives a low level, the fourth transistor T4 is turned on.

[0052] 9, in the third stage t3, the second data voltage Vdata_B is at a low level, and at this time, the second scanning signal terminal G_B changes from a low level to a high level, and the third transistor T3 is turned off. However, due to the presence of the first capacitor C1, the potential of the node N2 is maintained at a high level even in the second stage t2, so the fourth transistor T4 is turned off, and the light-emitting element L does not emit light at this time. By controlling the light-emitting element L to a non-emitting state in the scanning period, the light-emitting stage of the light-emitting element in one image frame can be shortened overall.

[0053] 9, by setting Vdata_B to a low level in the second stage t2, the fourth transistor t4 may be turned on in the third stage t3, in which case the current path between the first operating voltage terminal VL1 and the second operating voltage terminal VL2 is turned on. At this time, the driving current I generated by the driving transistor Td operating in the saturation region is transmitted to the light-emitting element L through the current path, causing the light-emitting element L to emit light. Drive current I=K(Vgs-Vth) 2 = K(Vg-Vs-Vth) 2 = K(Vdata_A + Vth-VDD-Vth) 2 =K(Vdata_A-VDD) 2 . In the formula, K=1 / 2Cox(μW / L), Cox is the channel capacitance per unit area of ​​the driving transistor Td, μ is the channel transition rate, W is the channel width, and L is the channel length. Therefore, K is a constant. As can be seen from the equation for the drive current I, the drive current I is independent of the threshold voltage Vth of the drive transistor Td. Therefore, the magnitude of the drive current I does not change with the transition of the threshold voltage Vth of the drive transistor Td. The third stage t3 may be a light emitting stage.

[0054] The operation process of the drive circuit 01 in the first scanning period S1 will be described below. The operation process of the drive circuit 01 in the remaining scanning periods is as described above, so a detailed description will be omitted here. The difference is that the magnitude of the driving current I flowing through the light-emitting element L can be changed by changing the magnitude of the first data voltage Vdata_A provided from the first data signal terminal D_A. Meanwhile, the magnitude of the second data voltage Vdata_B provided from the second data signal terminal D_B can also be changed. For example, referring to FIG. 9, Vdata_B is set to a low level in the second stage t2 of the second scanning period S2, so that the fourth transistor T4 is turned on in the second scanning period S1, and the light-emitting element L emits light in the second scanning period S2, and the effective light emission luminance of the light-emitting element L in one image frame changes. Therefore, Vdata_B can determine when to transmit the driving current I to the light-emitting element L. In addition, the time of the low level provided by the light-emitting control signal terminal EM can be controlled, and the on-time of the first transistor T1 and the second transistor T2 can be controlled by controlling the signal duty ratio provided by the light-emitting control signal terminal EM, thereby controlling the on-time of the current path through which the driving current I flows.

[0055] As described above, the effective light emission brightness of the light-emitting element L in the driving circuit 01 within one image frame is determined by multiple factors, namely, the number of scanning cycles within one image frame, the time per scanning cycle, the first data voltage Vdata_A, the second data voltage Vdata_B, and the light emission control signal provided from the light emission control signal terminal EM, so that the gradation value of the sub-pixel display with the driving circuit 01 can be increased, and the screen displayed on the display panel can be made richer and more delicate.

[0056] 7, the gates of the fifth transistor T5 and the sixth transistor T6 are connected to the first scanning signal terminal G_A, and the gate of the third transistor T3 is connected to the second scanning signal terminal G_B. In FIG 9, a case where the same signal is input to the first scanning signal terminal G_A and the second scanning signal terminal G_B will be described as an example.

[0057] In some embodiments of the present application, as shown in FIG. 12, there may be a delay in the active signal input to the second scanning signal terminal G_B within one scanning period S, for example, in the second stage t2, the active signal input to the second scanning signal terminal G_B is slower than the active signal input to the first scanning signal terminal G_A. The active signal is a level signal that can turn on the sub-circuit that receives the active signal, for example, a low level. In this case, the on time of the gradation control sub-circuit 30 that receives the active signal input to the second scanning signal terminal G_B is longer than the on time of the writing sub-circuit 20 that receives the active signal input to the first scanning signal terminal G_A.

[0058] Also, when the subcircuit includes a transistor, the active signal refers to a level signal that can turn on the transistor controlled by the active signal. For example, when the grayscale control subcircuit 30 includes the third transistor T3, the writing subcircuit 20 includes the fifth transistor T5, and the compensation subcircuit 40 includes the sixth transistor T6, the on-time of the fifth transistor T5 and the sixth transistor T6 controlled by the first scanning signal terminal G_A has priority over the on-time of the third transistor T3 controlled by the second scanning signal terminal G_B. When the transistor is a P-type transistor, the active signal is a low level.

[0059] In this way, the on-time of the fourth transistor T4 can be delayed, and it is possible to prevent the leakage current generated by the second transistor T2 from flowing through the fourth transistor T4 to the light-emitting element L to cause erroneous light emission. That is, according to the embodiment of the present application, after the state in which the first data voltage Vdata_A provided from the first data signal terminal D_A is written to the driving transistor Td is stabilized, and after the driving current I generated by the driving transistor Td is stabilized, the third transistor T3 is turned on again and the fourth transistor T4 is controlled to be turned on, thereby transmitting the stable driving current I to the light-emitting element L and stabilizing the light emission luminance of the light-emitting element L. The above has been described taking the structure shown in FIG. 7 as an example, but the operation process of the driving circuit 01 shown in FIG. 8 is the same as that described above, so a detailed description will be omitted here.

[0060] In some embodiments of the present application, a display device is provided that includes a display panel, the display area of ​​the display panel includes a plurality of subpixels 02 as shown in FIG. 10, and at least one of the subpixels 02 includes any one of the driving circuits 01 described above. Subpixels 02 are defined by the intersection of a first scanning signal line G_A and a first data signal line D_A, which cross each other vertically and horizontally. A second scanning signal line G_B is arranged parallel to the first scanning signal line G_A, and a second data signal line D_B is arranged parallel to the first data signal line D_A.

[0061] 10, sub-pixels located in the same row have the first transistors T1 in their drive circuits 01 connected to the same emission control signal terminal EM. In this case, when an active signal, for example, a low level as shown in FIG. 9, is provided from the emission control signal terminal EM, the first transistors T1 and second transistors T2 located in the same row are both turned on.

[0062] Based on this, in order to individually control the emission brightness of different sub-pixels in the same row, the third transistor T3 is controlled to be turned on via an active signal input to the second scanning signal terminal G_B, and after the third transistor T3 is turned on, when the second data voltage Vdata_B provided by the second data signal terminal D_B is an active signal, the fourth transistor T4 is turned on, thereby controlling the current path between the first operating voltage terminal VL1 and the second operating voltage terminal VL2 to be on.

[0063] The driving current I generated by the driving transistor Td is transmitted to the light-emitting element L via a current path. The longer the time that the current path is on, the higher the effective light emission luminance of the light-emitting element L in one scanning period S. In addition, the magnitude of the driving current I can also be adjusted by adjusting the magnitude of the first data voltage Vdata_A provided from the first data signal terminal D_A. The larger the driving current I, the higher the effective light emission luminance of the light-emitting element L in one scanning period S.

[0064] According to an embodiment of the present application, as shown in FIG. 9, there are three scanning periods S1, S2, and S3 in one image frame. The third stage t3 in the three scanning periods is different from each other. Therefore, one or more corresponding scanning periods can be selected according to the desired light emission time of the light emitting element, and the light emitting element can be made to emit light in the third stage t3 in the one or more scanning periods, thereby obtaining eight different gradation brightness levels. According to another embodiment of the present application, the third stages of the multiple scanning periods in one image frame can be the same. Therefore, one or more scanning periods can be selected according to the desired light emission time of the light emitting element, and the light emitting element can be made to emit light in the third stage t3 in the one or more scanning periods, thereby obtaining four different gradation levels.

[0065] As can be seen from this, when there are multiple scanning cycles within one image frame and the lengths of the scanning cycles are different, the adjustable range of the light-emitting time and effective brightness of the light-emitting element can be expanded, and the number of gray levels that can be displayed by the display panel can be increased. In light of the above, in the related art, it is possible to simultaneously cause all sub-pixels in one row of the drive circuit 01 to emit light under control of the light emission control signal provided from the light emission control signal terminal EM, but it is not possible to individually control the light emission luminance and light emission time of each sub-pixel. However, according to the drive circuit provided by the present application, it is possible to adjust the light emission luminance of a single sub-pixel by coordinating the light emission control signal terminal EM, the first scanning signal terminal G_A, the second scanning signal terminal G_B, the first data signal terminal D_A, and the second data signal terminal D_B.

[0066] It should be noted that the display device may be any product or component having a display function, such as a display, a television, a digital photo frame, a mobile phone, a tablet PC, etc. Among them, the display device has the same technical effect as the driving circuit 01 provided in the above embodiment, so a detailed description is omitted here.

[0067] Some embodiments of the present application provide a method for driving such a driving circuit 01, in which the driving circuit has multiple scanning periods within one image frame. The gradation control sub-circuit 30 in the drive circuit 01 has a first control sub-circuit 301 and a second control sub-circuit 302 . The method of driving the drive circuit in one scanning period S (for example, the first scanning period S1) includes steps S100 to S103 as shown in FIG.

[0068] Step S101 includes providing a first scanning signal to a first scanning signal terminal G_A, providing a first data voltage Vdata_A to a first data signal terminal D_A, and the first data voltage Vdata_A being written to the driving sub-circuit 10 by the writing sub-circuit 20.

[0069] 9, in one scanning period S, the signal provided by the first scanning signal terminal G_A has two states, high level and low level, and in the embodiment of the present application, when the first scanning signal terminal G_A inputs a low level, it can be used as an active signal to turn on the write sub-circuit 20. When the first scanning signal terminal G_A inputs a high level, the write sub-circuit 20 is closed.

[0070] Step S102 includes providing a second scanning signal to the second scanning signal terminal G_B, providing a second data voltage Vdata_B to the second data signal terminal D_B, and the second control sub-circuit 302 being opened or closed under the control of the second scanning signal and the second data voltage Vdata_B.

[0071] By controlling the open time of the first control sub-circuit 301 and the second control sub-circuit 302, the purpose of controlling the on time of the current path can be achieved. 9, the second scanning signal terminal G_B and the second data voltage terminal D_B have two states, a high level and a low level, and in the embodiment of the present application, when a low level is input to the second scanning signal terminal G_B and a low level is input to the second data voltage terminal D_B, the signals may be active signals for opening the second control sub-circuit 302. In other states, the second control sub-circuit 302 is in a closed state. It should be noted that steps S101 and S102 can be executed in the second stage t2 within one scanning period shown in FIG.

[0072] In addition, if the driving circuit 01 further includes a compensation sub-circuit 40, in the second stage t2, when a first scanning signal is provided to the first scanning signal terminal G_A, the compensation sub-circuit 40 is opened and compensates for the threshold voltage Vth of the driving transistor Td in the driving sub-circuit 10.

[0073] Step S103 provides a light emission control signal to the light emission control signal terminal EM, and transmits the first operating voltage VDD provided by the first operating voltage terminal VL1 to the driving sub-circuit 10 by the first control sub-circuit 301, so as to make the light emitting element L emit light according to the first operating voltage VDD and the first data voltage Vdata_A under the control of the light emission control signal, the first scanning signal, the second scanning signal, and the second data voltage Vdata_B. Wherein, the light emission control signal terminal EM has two states, a high level and a low level, as shown in FIG. 9. In the embodiment of the present application, when the light emission control signal terminal EM provides a low level, it can be used as an active signal for opening the first control sub-circuit 301. When the light emission control signal terminal EM provides a high level, the first control sub-circuit 301 is closed.

[0074] Specifically, the driving sub-circuit 10 generates a driving current I based on the first data voltage Vdata_A and the first operating voltage VDD. The driving current I is transmitted to the second control sub-circuit 302 via the first control sub-circuit 301. Because both the first control sub-circuit 301 and the second control sub-circuit 302 are open, a current path between the first operating voltage terminal VL1 and the second operating voltage terminal VL2 is turned on, and the driving current I is transmitted to the light-emitting element L via the current path. The light-emitting element L receives the driving current I in the current path and emits light. Note that step S103 may be executed in the third stage t3 within one scanning period shown in FIG.

[0075] In addition, when the driving circuit 10 further includes a reset sub-circuit 50, before S101, the driving method of the driving circuit may include the following steps as shown in FIG. Step S100 further includes providing a reset control signal to a reset control signal terminal RS and providing a reset voltage to a reset voltage terminal VINT, where the reset voltage is transmitted to the driving sub-circuit 10 via the reset sub-circuit 50.

[0076] As shown in FIG. 9, the reset control signal terminal RS has two states, a high level and a low level. In the embodiment of the present application, when a low level is input to the reset control signal terminal RS, it can be used as an active signal for opening the reset sub-circuit 50, and when a high level is input to the reset control signal terminal RS, the reset sub-circuit 50 is closed.

[0077] Step S100 allows the gate of the driving transistor Td of the driving sub-circuit 10 to be reset.

[0078] Step S100 may be performed at a first stage t1 within one scanning period shown in FIG. 7 or 8, the driving method of the driving circuit 10 is described in detail in the operation process of the driving circuit 10 in the above embodiment, and therefore the details will not be described again. In addition, the driving method of the driving circuit has the same technical effects as the driving circuit provided in the above embodiment, and therefore a detailed description will be omitted here.

[0079] 12, the time when the second scanning signal terminal G_A outputs an active signal is later than the time when the first scanning signal terminal G_B outputs an active signal in the second stage t2 of one scanning period S, so that the second control subcircuit 302 opens again after the first data voltage Vdata_A is stably written to the driving subcircuit 10 by the write subcircuit 20. Thus, after the driving current I generated by the driving subcircuit 10 becomes stable, the second control subcircuit 302 opens again and the current path is turned on. The description of the active signal has been given above and will not be repeated here.

[0080] In addition, when the driving sub-circuit 10 includes a driving transistor Td and a second capacitor C2, and the gate of the driving transistor Td is connected to one end of the second capacitor C2 and the other end of the second capacitor C2 is connected to a second voltage terminal V2, the second voltage terminal V2 is close to the position of the first operating voltage terminal VL1, so that the voltages input from the second voltage terminal V2 and the first operating voltage terminal VL1 are the same, in order to make it easier to design the circuit layout. In this way, the first operating voltage terminal VL1 is electrically connected to the second voltage terminal V2. When the driving sub-circuit 10 operates, the first operating voltage VDD provided by the first operating voltage terminal VL1 is transmitted to the second voltage terminal V2.

[0081] According to another embodiment of the present application, as shown in Fig. 13, the driving element 100 may only include a second grayscale control sub-circuit 302, a driving transistor Td, and a second transistor T2. The driving sub-circuit Td can generate a driving current for driving the light-emitting element L according to a source signal provided by a third voltage terminal V3 and a gate signal provided by a fourth voltage terminal V4. The driving time of the light-emitting element L is controlled by the second transistor T2 and the second control sub-circuit 302.

[0082] 14, according to an embodiment of the present application, the driving sub-circuit 10 may only include a driving transistor Td, whose gate is connected to a fourth voltage terminal V4, whose first pole is connected to the writing sub-circuit, and whose second pole is connected to the grayscale control sub-circuit. The fourth voltage terminal V4 is used to provide a suitable voltage signal to the gate of the driving transistor Td to turn on the driving transistor Td.

[0083] The above description is merely a specific embodiment of the present application, and the scope of the claims of the present application is not limited thereby. Any modifications or replacements that can be easily thought of by a person skilled in the art within the technical scope disclosed in this application are all included in the scope of the claims of the present disclosure. Therefore, the scope of the claims of the present disclosure is based on the scope of the claims. [Explanation of symbols]

[0084] 10 Drive Subcircuit 20 Subcircuits 30 Gradation control subcircuit 100 Drive element

Claims

1. A driving circuit including a driving device and a light emitting element, the driving device and the light-emitting element are connected in series between a first operating voltage terminal and a second operating voltage terminal, and the driving device provides a driving signal to the light-emitting element to control an on-time of a current path between the first operating voltage terminal and the second operating voltage terminal; the driving device includes a driving sub-circuit, a writing sub-circuit, and a grayscale control sub-circuit; the write sub-circuit is connected to a first scan signal terminal, a first data signal terminal and the drive sub-circuit, and the write sub-circuit writes a first data voltage provided from the first data signal terminal to the drive sub-circuit under the control of the first scan signal terminal; the grayscale control subcircuit is connected to a drive control signal terminal, a second scanning signal terminal, a second data signal terminal and the drive subcircuit; The grayscale control sub-circuit provides a first operating voltage provided by the first operating voltage terminal to the driving sub-circuit under control of the driving control signal terminal; the drive subcircuit generates the drive signal based on the first data voltage and the first actuation voltage; the grayscale control subcircuit further controls an on-time of the current path under control of the drive control signal terminal, the second scanning signal terminal, and the second data signal terminal; the grayscale control subcircuit includes a first control subcircuit and a second control subcircuit; The first control subcircuit is connected to the drive control signal terminal, the drive subcircuit, and the second control subcircuit, and the first control subcircuit, under the control of the drive control signal terminal: transmitting a first operating voltage provided by the first operating voltage terminal to the drive sub-circuit; the first control subcircuit further transmits a drive current generated by the drive subcircuit to the second control subcircuit under control of the drive control signal terminal to control an on-time of the current path; the second control subcircuit is further connected to the second scan signal terminal and the second data signal terminal, and the second control subcircuit controls an on-time of the current path under control of the second scan signal terminal and the second data signal terminal; the second control sub-circuit is further connected to the first voltage terminal, the second control sub-circuit having a third transistor, a fourth transistor, and a first capacitor; a gate of the third transistor is connected to the second scan signal terminal, a first pole of the third transistor is connected to the second data signal terminal, and a second pole of the third transistor is connected to a gate of the fourth transistor; one end of the first capacitor is connected to the second pole of the third transistor, and the other end of the first capacitor is connected to the first voltage terminal; A cathode of the light-emitting element is connected to the second operating voltage terminal, a first pole of the fourth transistor is connected to the first control sub-circuit, and a second pole of the fourth transistor is connected to the anode of the light-emitting element. Drive circuit.

2. A driving circuit including a driving device and a light emitting element, the driving device and the light-emitting element are connected in series between a first operating voltage terminal and a second operating voltage terminal, and the driving device provides a driving signal to the light-emitting element to control an on-time of a current path between the first operating voltage terminal and the second operating voltage terminal; the driving device includes a driving sub-circuit, a writing sub-circuit, and a grayscale control sub-circuit; the write sub-circuit is connected to a first scan signal terminal, a first data signal terminal and the drive sub-circuit, and the write sub-circuit writes a first data voltage provided from the first data signal terminal to the drive sub-circuit under the control of the first scan signal terminal; the grayscale control subcircuit is connected to a drive control signal terminal, a second scanning signal terminal, a second data signal terminal and the drive subcircuit; The grayscale control sub-circuit transmits a first operating voltage provided by the first operating voltage terminal to the driving sub-circuit under the control of the driving control signal terminal; the drive subcircuit generates the drive signal based on the first data voltage and the first actuation voltage; the grayscale control subcircuit further controls an on-time of the current path under control of the drive control signal terminal, the second scanning signal terminal, and the second data signal terminal; the grayscale control subcircuit includes a first control subcircuit and a second control subcircuit; The first control subcircuit is connected to the drive control signal terminal, the drive subcircuit, and the second control subcircuit, and the first control subcircuit, under the control of the drive control signal terminal: transmitting a first operating voltage provided by the first operating voltage terminal to the drive sub-circuit; the first control subcircuit further transmits a drive current generated by the drive subcircuit to the second control subcircuit under control of the drive control signal terminal to control an on-time of the current path; the second control subcircuit is further connected to the second scan signal terminal and the second data signal terminal, and the second control subcircuit controls an on-time of the current path under control of the second scan signal terminal and the second data signal terminal; the second control sub-circuit is further connected to the first voltage terminal, the second control sub-circuit having a third transistor, a fourth transistor, and a first capacitor; a gate of the third transistor is connected to the second scan signal terminal, a first pole of the third transistor is connected to the second data signal terminal, and a second pole of the third transistor is connected to a gate of the fourth transistor; one end of the first capacitor is connected to the second pole of the third transistor, and the other end of the first capacitor is connected to the first voltage terminal; an anode of the light-emitting element is connected to the first operating voltage terminal, a cathode of the light-emitting element is connected to the first control sub-circuit, a first pole of the fourth transistor is connected to the first control sub-circuit, and a second pole of the fourth transistor is connected to the second operating voltage terminal. Drive circuit.

3. the drive circuit further includes a compensation subcircuit; The compensation subcircuit is connected to the first scanning signal terminal and the driving subcircuit, and the compensation subcircuit compensates a threshold voltage of the driving subcircuit under control of the first scanning signal terminal.

2. The drive circuit according to claim 1.

4. the drive circuit further comprises a reset subcircuit; The reset subcircuit is connected to a reset voltage terminal, a reset control signal terminal and the driving subcircuit, and the reset subcircuit transmits a reset voltage provided by the reset voltage terminal to the driving circuit under the control of the reset control signal terminal.

2. The drive circuit according to claim 1.

5. the first control subcircuit includes a first transistor and a second transistor; an anode of the light-emitting element is connected to the second control sub-circuit, a cathode of the light-emitting element is connected to the second operating voltage terminal, a gate of the first transistor is connected to the drive control signal terminal, a first pole is connected to the first operating voltage terminal, and a second pole is connected to the drive sub-circuit; The second transistor has a gate connected to the drive control signal terminal, a first pole connected to the drive subcircuit, and a second pole connected to the second control subcircuit.

2. The drive circuit according to claim 1.

6. the first control subcircuit includes a first transistor and a second transistor; an anode of the light-emitting element is connected to the first operating voltage terminal, a gate of the first transistor is connected to the drive control signal terminal, a first pole is connected to the cathode of the light-emitting element, and a second pole is connected to the drive sub-circuit; The second transistor has a gate connected to the drive control signal terminal, a first pole connected to the drive subcircuit, and a second pole connected to the second control subcircuit.

3. The drive circuit according to claim 2.

7. the drive subcircuit is further connected to a second voltage terminal, the drive subcircuit further comprising a drive transistor; The gate of the driving transistor is connected to the second voltage terminal, the first pole is connected to the writing subcircuit, and the second pole is connected to the grayscale control subcircuit.

2. The drive circuit according to claim 1.

8. the drive subcircuit is further connected to a second voltage terminal, the drive subcircuit comprising a drive transistor and a second capacitor; A gate of the driving transistor is connected to one end of the second capacitor, a first pole of the second capacitor is connected to the writing subcircuit, and a second pole of the second capacitor is connected to the grayscale control subcircuit; The other end of the second capacitor is connected to the second voltage terminal.

5. A drive circuit according to claim 3 or 4.

9. the write subcircuit includes a fifth transistor; The gate of the fifth transistor is connected to the first scan signal terminal, a first pole is connected to the first data signal terminal, and a second pole is connected to the driving sub-circuit.

2. The drive circuit according to claim 1.

10. the compensation subcircuit includes a sixth transistor; The gate of the sixth transistor is connected to the first scanning signal terminal, and the first pole and the second pole are both connected to the driving sub-circuit.

4. The drive circuit according to claim 3.

11. the reset subcircuit comprises a seventh transistor; The seventh transistor has a gate connected to the reset control signal terminal, a first pole connected to the reset voltage terminal, and a second pole connected to the drive subcircuit.

5. The drive circuit according to claim 4.

12. The light emitting device is a micro light emitting diode.

2. The drive circuit according to claim 1.

13. A drive circuit for driving and operating a light-emitting element, the drive circuit comprising first to seventh transistors, a first capacitor, a second capacitor, a drive transistor, a reset control signal terminal, a drive control signal terminal, a first data signal terminal, a second data signal terminal, a first scanning signal terminal, a second scanning signal terminal, a first operating voltage terminal, a first voltage terminal, a second voltage terminal, and a reset voltage terminal, the drive control signal terminal is connected to the gate of the first transistor and the gate of the second transistor; the first data signal terminal is connected to a first pole of the fifth transistor; the second data signal terminal is connected to a first pole of the third transistor; the first scanning signal terminal is connected to a gate of a fifth transistor and a gate of a sixth transistor; the second scanning signal terminal is connected to the gate of the third transistor; the first operating voltage terminal is connected to a first pole of the first transistor; the first voltage terminal is connected to one end of the first capacitor; the second voltage terminal is connected to one end of the second capacitor; the reset control signal terminal is connected to the gate of the seventh transistor; the reset voltage terminal is connected to a first pole of the seventh transistor; a second pole of the first transistor and a second pole of the fifth transistor are connected to a first pole of the drive transistor; the other end of the second capacitor, a second pole of the sixth transistor, and a second pole of the seventh transistor are connected to a gate of the drive transistor; a first pole of the second transistor and a first pole of the sixth transistor are connected to a second pole of the drive transistor; a second pole of the second transistor is connected to a first pole of the fourth transistor; the other end of the first capacitor and the second electrode of the third transistor are connected to the gate of the fourth transistor; a second electrode of the fourth transistor is connected to a light emitting element; the fifth transistor is included in a write subcircuit, the write subcircuit writing a first data voltage provided by the first data signal terminal to a drive subcircuit under control of the first scan signal terminal; the first transistor and the second transistor are included in a first control subcircuit, the first control subcircuit transmitting a first operating voltage provided by a first operating voltage terminal to a drive subcircuit under control of the drive control signal terminal; the drive transistor and the second capacitor are included in the drive sub-circuit, the drive sub-circuit generating a drive signal based on the first data voltage and the first actuation voltage; The third transistor, the fourth transistor, and the first capacitor are included in a second control sub-circuit, and the second control sub-circuit is a drive circuit that controls an on-time of a current path between the first operating voltage terminal and the second operating voltage terminal under control of the second scanning signal terminal and the second data signal terminal.

14. A drive circuit for driving and operating a light-emitting element, the drive circuit comprising first to seventh transistors, a first capacitor, a second capacitor, a drive transistor, a reset control signal terminal, a drive control signal terminal, a first data signal terminal, a second data signal terminal, a first scanning signal terminal, a second scanning signal terminal, a power supply voltage terminal, a first voltage terminal, a second voltage terminal, and a reset voltage terminal, the drive control signal terminal is connected to the gate of the first transistor and the gate of the second transistor; the first data signal terminal is connected to a first pole of the fifth transistor; the second data signal terminal is connected to a first pole of the third transistor; the first scanning signal terminal is connected to a gate of a fifth transistor and a gate of a sixth transistor; the second scanning signal terminal is connected to the gate of the third transistor; the power supply voltage terminal is connected to the second pole of the fourth transistor; the first voltage terminal is connected to one end of the first capacitor; the second voltage terminal is connected to one end of the second capacitor; the reset control signal terminal is connected to the gate of the seventh transistor; the reset voltage terminal is connected to a first pole of the seventh transistor; a second pole of the first transistor and a second pole of the fifth transistor are connected to a first pole of the drive transistor; the other end of the second capacitor, a second pole of the sixth transistor, and a second pole of the seventh transistor are connected to a gate of the drive transistor; a first pole of the second transistor and a first pole of the sixth transistor are connected to a second pole of the drive transistor; a second pole of the second transistor is connected to a first pole of the fourth transistor; the other end of the first capacitor and the second electrode of the third transistor are connected to the gate of the fourth transistor; a first electrode of the first transistor is connected to the light emitting element; the fifth transistor is included in a write subcircuit, the write subcircuit writing a first data voltage provided by the first data signal terminal to a drive subcircuit under control of the first scan signal terminal; the first transistor and the second transistor are included in a first control subcircuit, the first control subcircuit transmitting a first operating voltage provided by a first operating voltage terminal to a drive subcircuit under control of the drive control signal terminal; the drive transistor and the second capacitor are included in the drive sub-circuit, the drive sub-circuit generating a drive signal based on the first data voltage and the first actuation voltage; The third transistor, the fourth transistor, and the first capacitor are included in a second control sub-circuit, and the second control sub-circuit controls an on-time of a current path between the first operating voltage terminal and the second operating voltage terminal under control of the second scan signal terminal and the second data signal terminal. Drive circuit.

15. A display device comprising: a display substrate; a display region of the display substrate having a plurality of sub-pixels; and a drive circuit according to any one of claims 1 to 12 and a light-emitting element in at least one of the sub-pixels, the drive circuit supplying a drive signal to the light-emitting element. Display device.

16. In one image frame, the driving circuit has a plurality of scanning periods, the gradation control subcircuit has a first control subcircuit and a second control subcircuit, and in one of the scanning periods, a driving method of the driving circuit includes: providing a first scan signal to the first scan signal terminal and a first data voltage to the first data signal terminal, the first data voltage being written to a drive sub-circuit via a write sub-circuit; providing a second scan signal to a second scan signal terminal and a second data voltage to the second data signal terminal, such that a second control sub-circuit opens or closes under control of the second scan signal and the second data voltage; providing a drive control signal to a drive control signal terminal, providing a first operating voltage to the first operating voltage terminal, and transmitting the first operating voltage to a drive sub-circuit via a first control sub-circuit such that the light-emitting element operates based on the first data voltage and the first operating voltage under control of the drive control signal, the first scanning signal, the second scanning signal, and the second data voltage. A method for driving the drive circuit according to claim 1.

17. The driving method further comprises: The time when the second scanning signal terminal outputs an active signal is later than the time when the first scanning signal terminal outputs an active signal within one scanning period. The driving method according to claim 16.

18. the drive circuit further comprises a reset subcircuit, providing a first scan signal to the first scan signal terminal and a first data voltage to a first data signal terminal, before the first data voltage is written to the drive subcircuit via the write subcircuit, the drive method of the drive circuit further comprising: providing a reset control signal to a reset control signal terminal and providing a reset voltage to a reset voltage terminal, the reset voltage being transmitted through the reset sub-circuit to the drive sub-circuit. The driving method according to claim 16.

19. The driving subcircuit includes a driving transistor and a second capacitor, a gate of the driving transistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to a second voltage terminal, and a voltage input to the second voltage terminal and the first operating voltage terminal is the same. The driving method according to claim 16.

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