In situ quantum error correction

Abstract

To provide a method, a system and an apparatus for continuous and parallel optimization of quantum bit performance in-situ while an error correction operation on a quantum system is running.SOLUTION: A method for parallel optimization of continuously running quantum error correction by closed-loop feedback includes the steps of: continuously and effectively optimizing quantum bit performance in-situ while an error correction operation on a quantum system is running; directly monitoring output from error detection; providing the information as feedback to calibrate quantum gates associated with the quantum system; and spatially partitioning the physical quantum bit into one or more independent hardware patterns, the errors attributable to each hardware pattern being non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved such that all physical quantum bits and operations are optimized.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Optimization of physical gate parameters is required to build fault-tolerant quantum computers. Characterization methods such as randomized benchmarking or tomography require the interruption of necessary error detection operations and do not guarantee optimal performance in error correction circuits. Optimization of physical gate parameters using error model optimization methods requires that error models be trained such that measured physical errors can be linked to physical gates, and that determined errors can be linked back to changes in control parameters, increasing the complexity of the optimization process. Summary of the Invention [Means for solving the problem]

[0002] This specification relates to qubit performance in quantum computing.

[0003] This specification describes techniques for continuous, parallel, on-the-fly optimization of qubit performance while error correction operations on the quantum system are running.

[0004] In general, one inventive aspect of the subject matter described herein includes accessing a quantum information storage system including a plurality of data qubits, a plurality of measurement qubits interleaved with the data qubits such that each data qubit has a nearby measurement qubit, a plurality of readout quantum gates, each readout quantum gate configured to operate on the measurement qubit, a plurality of single-qubit quantum gates, each single-qubit quantum gate configured to operate on either the data qubit or the measurement qubit, and a plurality of CNOT quantum gates, each CNOT quantum gate configured to operate on a data qubit and a nearby measurement qubit, each CNOT gate defining one of a plurality of directions; and partitioning the data qubits and the measurement qubits into a plurality of patterns, , at least one pattern is subject to a non-overlapping error for that pattern, the non-overlapping error for a pattern being an error attributable to that pattern; for each pattern including a measurement qubit, optimizing in parallel parameters of a readout quantum gate operating on that measurement qubit, optimizing in parallel parameters of a single-qubit quantum gate operating on that measurement qubit, for each pattern including a data qubit and a measurement qubit operated by a CNOT gate, optimizing in parallel parameters of a single-qubit quantum gate operating on that data qubit, and selecting a set of CNOT gates that define the same direction and optimizing parameters for the selected CNOT gates in parallel.

[0005] Other implementations of the aspects include corresponding computer systems, devices, and computer programs stored on one or more computer storage devices, each configured to perform the actions of the method. A system of one or more computers can be configured to perform specific operations or actions with software, firmware, hardware, or combinations thereof installed on the system that cause the system to perform the actions. One or more computer programs can be configured to perform specific operations or actions by including instructions that, when executed by a data processing device, cause the device to perform the actions.

[0006] Each of these and other implementations can optionally include one or more of the following features, alone or in combination.

[0007] In some implementations, the plurality of data qubits and measurement qubits are interleaved such that the plurality of data qubits and measurement qubits define a one-dimensional chain of qubits, and the plurality of directions includes a first direction and a second direction opposite the first direction.

[0008] In other implementations, the multiple single-qubit gates are phase-shift gates or rotation gates.

[0009] In some cases, the data qubit is a control qubit and the nearby measurement qubit is a target qubit for a CNOT gate.

[0010] In other cases, the data qubit is a target qubit and the nearby measurement qubit is a control qubit for a CNOT gate.

[0011] In some implementations, optimizing in parallel parameters of a readout quantum gate operating on the measurement qubit is an iterative process with closed-loop feedback, each iteration including, in parallel, defining, for each measurement qubit, a corresponding metric for minimization as the determined error rate, measuring the measurement qubit to determine a current error rate, storing the determined current error rate, calculating the change in error rate between the current error rate and the stored error rate from the previous iteration, and adjusting the readout gate parameters based on the calculated change in error rate.

[0012] In some cases, adjusting the read gate parameters based on the defined metric to minimize includes applying a numerical optimization algorithm.

[0013] In some implementations, optimizing in parallel parameters of a single-qubit quantum gate operating on the measurement qubit is an iterative process with closed-loop feedback, where each iteration includes, in parallel, defining, for each measurement qubit, a corresponding metric for minimization as a determined error rate; measuring the measurement qubit to determine an error rate; storing the determined current error rate; calculating the change in error rate between the current error rate and the stored error rate from the previous iteration; and adjusting the parameters of the single-qubit gate based on the calculated change in error rate.

[0014] In some cases, adjusting a parameter of the single-qubit gate based on the defined metric for minimization includes applying a numerical optimization algorithm.

[0015] In some implementations, optimizing in parallel parameters of a single-qubit quantum gate operating on the data qubit is an iterative process with closed-loop feedback, where each iteration includes, in parallel, defining, for each data qubit, a corresponding metric for minimization as a determined error rate, measuring the corresponding measurement qubit to determine an error rate, storing the determined current error rate, calculating the change in error rate between the current error rate and the stored error rate from the previous iteration, and adjusting the parameters of the single-qubit gate based on the calculated change in error rate.

[0016] In some cases, adjusting a parameter of the single-qubit gate based on a defined metric for minimization includes applying a numerical optimization algorithm.

[0017] In another implementation, selecting a set of CNOT gates defining the same direction and optimizing parameters for the selected CNOT gates in parallel includes, for each selected set of CNOT gates, defining a corresponding metric for minimization as a determined error rate for each data qubit in the selected set, measuring the corresponding measurement qubit to determine an error rate, storing the determined current error rate, calculating the change in error rate between the current error rate and the stored error rate from the previous iteration, and adjusting the CNOT gate parameters based on the calculated change in error rate.

[0018] In some cases, adjusting a parameter of the single-qubit gate based on a defined metric for minimization includes applying a numerical optimization algorithm.

[0019] The subject matter described herein can be implemented to achieve one or more of the following advantages: By continuously and effectively optimizing physical gate parameters, and therefore qubit performance, on the fly while error correction is running, the performance of quantum computers implementing the parallel optimization of continuous error correction runs can achieve improved performance and reliability compared to quantum computers using other characterization methods that may require necessary error detection operations and interruption of other computations. For example, quantum computers implementing the parallel optimization of continuous error correction runs can combat system drift, i.e., drift in optimal parameters as a result of temperature-induced system hardware changes, for each gate parameter per qubit while the system is running without interrupting computation.

[0020] In many situations, the detection events are the only information available that reflects system performance while error detection is occurring. Quantum computers that implement parallel optimization of successive error correction runs require detection events, which is a key technique that is applicable to many different forms of error correction.

[0021] Furthermore, because a primary challenge of error correction operations is knowing how gates characterized in other ways will perform in error detection circuits in multi-qubit systems, quantum computers that implement parallel optimization of successive error correction runs will achieve improved performance in error correction circuits compared to other characterization methods. Although the qubits that store data are generally not measured between computations, they still require optimization, which can be achieved by parallel optimization of successive error correction runs.

[0022] A quantum computer that implements the parallel optimization of successive error correction runs may be model-free, e.g., the initial description may be model-free, avoiding the need to construct an error model. A quantum computer that implements the parallel optimization of successive error correction runs may thus avoid the need to collect statistics on various error types for use in training such an error model, which requires that the physical system be significantly below a threshold such that individual first-order errors are sparse in order to collect sufficient statistics, thus saving time and required computational resources compared to other characterization methods.

[0023] Furthermore, a quantum computer of any size that implements parallel optimization of successive error correction implementations may achieve a high level of scalability, e.g., O(1), due to the optimization of each gate within the quantum computer.

[0024] The details of one or more implementations of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the detailed description, the accompanying drawings, and the appended claims. [Brief description of the drawings]

[0025] [Figure 1A] 1 is a simplified one-dimensional perspective view of an exemplary error correction system. [Figure 1B] FIG. 2 is a simplified two-dimensional perspective view of a quantum bit in an exemplary error correction system. [Figure 2A] FIG. 1 is a one-dimensional schematic perspective view of an exemplary hardware pattern for an error correction system including a one-dimensional array of qubits. [Figure 2B] FIG. 1 is a one-dimensional schematic perspective view of an exemplary hardware pattern for an error correction system including a one-dimensional array of qubits. [Diagram 3] 1 is a one-dimensional schematic perspective circuit representation of a qubit in an exemplary error correction system. [Figure 4]FIG. 2 is a schematic two-dimensional perspective view of an exemplary hardware pattern in an error correction system. [Diagram 5] 4 is a flow diagram of an exemplary process for error correction. [Figure 6] 1 is a flow diagram of an exemplary process for optimizing single-qubit quantum gate parameters on a measured qubit. [Figure 7] 1 is a flow diagram of an exemplary process for optimizing single-qubit quantum gate parameters on a data qubit. [Figure 8] FIG. 1 is a flow diagram of an exemplary process for optimizing CNOT gating parameters. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Like reference numbers and designations in the various drawings indicate like elements.

[0027] This specification describes a quantum system and method for continuously and efficiently optimizing qubit performance in situ while error correction operations are being performed on the quantum system. The method directly monitors the output from error detection and provides this information as feedback to calibrate quantum gates associated with the quantum system. In some implementations, the physical qubits are spatially partitioned into one or more independent hardware patterns, i.e., configurations in which errors attributable to each hardware pattern are non-overlapping. The one or more distinct sets of hardware patterns are then temporally interleaved such that all physical qubits and operations are optimized. The method allows optimization of each section of a hardware pattern to be performed individually and in parallel, which may result in O(1) scaling.

[0028] Example Operating Environment FIG. 1A is a one-dimensional schematic perspective view of an exemplary error correction system 100 for a repetition code. System 100 is a one-dimensional partition of a two-dimensional surface code. The system includes a one-dimensional array of qubits 102. For clarity, nine qubits are shown in FIG. 1A, but the system may include a much larger number of qubits, e.g., millions of qubits. The array of qubits includes data qubits, e.g., data qubits labeled 104, 108, 112, 116, and 120, interleaved with measurement qubits, e.g., measurement qubits labeled 106, 110, 114, and 118. In the case of bit-flip error detection, the qubits may be measurement Z-type qubits.

[0029] The system may include a set of readout quantum gates, such as readout quantum gate 122. The readout gates may be configured to operate on measurement qubits, such as measurement qubits 106, 110, 114, and 118. Each readout gate may provide the state of a corresponding measurement qubit and may be associated with a corresponding set of physical readout gate parameters.

[0030] The system may include a set of single-qubit quantum gates, e.g., single-qubit gates 132 and 134. The single-qubit quantum gates may be configured to operate on either a single data qubit or a single measurement qubit. The single-qubit gates shown in FIG. 1A include a PauliX gate, e.g., PauliX gate 134, and a Hadamard gate, e.g., Hadamard gate 132, although in some implementations the system may include other single-qubit gates. For example, the single-qubit gates may include any phase-shift or rotation gate. Each single-qubit quantum gate may be associated with a corresponding set of physical single-qubit quantum gate parameters.

[0031] The system may include a set of controlled NOT (CNOT) gates, e.g., CNOT gate 124. A controlled gate may operate on two or more qubits, one or more of which may act as a control for some operation. A CNOT gate may operate on two qubits, a control qubit and a target qubit, performing a NOT operation on the target qubit only if the control qubit is 1>. The CNOT gate in FIG. 1A is configured to operate on a pair of nearby measurement and data qubits, one qubit acting as the control qubit and the other as the target qubit, e.g., CNOT gate 124 operates on a pair of nearby qubits 104 and 106. If error detection is designed to detect bit-flip errors, each data qubit operated on by the CNOT gate may be a control qubit and each nearby measurement qubit may be a corresponding target qubit. Each CNOT gate may be associated with a corresponding set of physical CNOT gate parameters.

[0032] A CNOT gate, e.g., 124 operating on a target qubit, e.g., 106, may define one or more directions relative to the target qubit, e.g., left and right of the target qubit, as shown in FIG. 1A. In the example repetition code, a CNOT quantum gate may copy a bit-flip error from the associated data qubit to the associated measurement qubit for detection, as shown in FIG. 1A. In another example, if the error detection is designed to detect phase-flip errors, the measurement qubit may be the control qubit and a nearby data qubit may be the target qubit. The CNOT quantum gate may then copy a phase-flip error from the associated measurement qubit to the associated data qubit.

[0033] The system may include an error correction subsystem 130 in data communication with the qubits 102. The error correction subsystem may be configured to monitor output from error detection and feed this information back to the system to calibrate the quantum gate. The error correction subsystem 130 may spatially divide the qubits 102 into one or more hardware patterns and perform quantum measurements on the measurement qubits in each hardware pattern. The one or more hardware patterns may be independent such that optimization of each hardware pattern relative to each other may be essentially independent. The step of dividing the qubits into one or more hardware patterns is described in more detail below with reference to FIG. 2. The measurement output, or detection event, may indicate a change in the measured pattern of states for a measurement qubit, which indicates the presence of a nearby error, i.e., whether the error has occurred in the associated data qubit or measurement qubit. Thus, the measurement outputs therein and those measurement outputs may not be directly correlated to errors on the data qubit or measurement qubit. The step of correlating errors and gate parameters is described in more detail below with reference to FIGS. 2A and 2B.

[0034] Error correction subsystem 130 may use the results of the performed quantum measurements to calculate a relevant quantity or metric of interest, such as a current error rate per measured qubit. Error correction subsystem 130 may also perform additional calculations using the results of the performed quantum measurements, such as calculating an average of the determined error rates for one or more measured measurement qubits, or determining the change in error rate over time. Error correction subsystem 130 may include a data store and may store the results of the performed quantum measurements or the additional calculations.

[0035] The error correction subsystem may use the results of the measurements performed to optimize parameters of the quantum gate acting on qubit 102. For example, error correction subsystem 130 may implement a numerical optimization algorithm, such as the Nelder-Mead algorithm, to determine an appropriate adjustment to the quantum gate parameters, e.g., minimization of a set of quantum gate parameters. Once an appropriate adjustment is determined, the error correction subsystem may provide the adjustment as feedback to qubit 102, which may adjust the parameters of the quantum gate accordingly.

[0036] FIG. 1B is a two-dimensional schematic perspective view of a qubit 150 in an exemplary error correction system. The system may include a two-dimensional array of qubits 150. Again, for clarity, 81 qubits are shown in FIG. 1B, but the system may include a much larger number of qubits, e.g., millions of qubits. The array of qubits may include a data qubit, e.g., a data qubit labeled 152, interleaved with measurement qubits, e.g., labeled 154, 156, 158, and 160, such that the data qubit has four neighboring measurement qubits to the top, bottom, right, and left of the data qubit. FIG. 1B illustrates the scalability of system 100A of FIG. 1 to higher dimensions.

[0037] Figures 2A and 2B below show an exemplary hardware pattern used to implement the quantum gate optimization.

[0038] 2A is a simplified one-dimensional perspective view of an exemplary hardware pattern 200 for an error correction system including a one-dimensional array of qubits, such as the error correction system including a one-dimensional array of qubits 102 as described above with reference to FIG 1A, where the gate cross-hatching corresponds to which measurement qubit detects an error from that gate.

[0039] Hardware pattern 200 may include four hardware groupings 206, each of which includes a measurement qubit and a corresponding single-qubit operation on that qubit, e.g., hardware grouping 202 includes measurement qubit 204 and corresponding single-qubit operation 208. The groupings in the hardware pattern may be operated independently. Errors from single-qubit operations 208 may not propagate to nearby data qubits, and the relative detection fraction from that measurement qubit may be used to infer changes in gate parameters, as described below with reference to FIG. 6.

[0040] Furthermore, if error detection is designed to detect bit-flip errors, and each data qubit manipulated by a CNOT gate is a control qubit, and each nearby measurement qubit is a corresponding target qubit, then the bit-flip error may not propagate to the data qubit due to the orientation of the CNOT gate applied to the data qubit and measurement qubit pair. Rather, the bit-flip error may be localized to a particular measurement qubit, and thus a particular hardware grouping.

[0041] For gate error localization, the measurement qubits may have single-qubit quantum gate parameters optimized individually and fully in parallel as one hardware pattern 200. Depending on the configuration, the hardware pattern into which the data qubits and measurement qubits are partitioned may include one pattern that includes a hardware grouping that includes only the measurement qubits.

[0042] 2B is a one-dimensional schematic perspective view of exemplary hardware patterns 210 and 220 for an error correction system including a one-dimensional array of qubits, which may be, for example, an error correction system including a one-dimensional array of qubits 102 as described above with reference to FIG 1A, with the gates cross-hatched corresponding to which measurement qubits detect errors from that gate.

[0043] Hardware pattern 210 may include multiple hardware groupings, such as hardware grouping 212, each of which includes one data qubit and at most two measurement qubits along with corresponding single qubit operations for the measurement and data qubits and CNOT gates, e.g., as shown in FIG. 2B, hardware grouping 212 includes measurement qubit 214, single qubit operation 216, and CNOT gates 218 and 219. The groupings within the hardware pattern may be operated independently. Errors from single qubit operation 216 and CNOT gates 218 and 219 may not propagate outside hardware grouping 212, and the detected event fraction of the measurement qubits in each hardware grouping may be used to infer gate parameter changes for the gates in each grouping, as described below with reference to FIGS. 7 and 8.

[0044] Furthermore, if error detection is designed to detect bit-flip errors, and each data qubit manipulated by a CNOT gate is a control qubit, and each nearby measurement qubit is a corresponding target qubit, then, unlike hardware pattern 200, a bit-flip error may be copied from the data qubit through a CNOT gate to the nearby measurement qubit. Thus, a single error on a data qubit may generate two detection events on nearby measurement qubits, and it may not be possible to optimize CNOT gate parameters on the same measurement qubit or data qubit in parallel. There may be natural limitations to such hardware patterns, e.g., 210 and 220. In general, CNOT gates that are entirely contained in a hardware pattern may be optimized in the pattern.

[0045] If the next nearest data qubits simultaneously optimize their single qubit parameters, they may both copy errors to the same measurement qubit. Thus, the errors may become confused. To avoid this problem, all other data qubits may be optimized to avoid double mapping errors to the measurement qubit. Two hardware patterns 210 and 220 may be generated that can simultaneously optimize their single qubit parameters without such confusion, e.g., the optimization of both patterns 210 and 220 relative to each other is essentially independent. By configuration, the hardware patterns into which the data qubits and measurement qubits are partitioned may include at least one pattern, and the corresponding hardware grouping includes both data qubits and measurement qubits.

[0046] The hardware patterns 200, 210 and 220 shown in Figures 2A and 2B constitute a minimum number of hardware patterns that can be used to implement error correction in a one-dimensional error correction system such as that shown in Figure 1A. The table below counts the number of patterns that can be interleaved to optimize all gates in parallel. There are three interleaved patterns, and one gate in each pattern may be optimized in parallel. This number may be a constant for any size of iterative code, assuming that the system is implemented in an ideal sense, i.e., with qubits not having any parasitic interactions with qubits that should not interact with them. The patterns shown are a minimum set of patterns, and in some implementations more may be added as needed. By selecting such hardware patterns for the system, the gate parameters in each hardware grouping in each hardware pattern may be optimized by changing the gate parameters and optimizing the measured error rate per hardware grouping. Furthermore, by selecting a finite number of hardware patterns, each operation required to optimize the quantum computer performing error detection may be accessed. Once a hardware pattern is chosen, every hardware grouping can be optimized independently in parallel, which is an O(1) scaling strategy for optimizing every single gate in a quantum computer of any size.

[0047] [Table 1]

[0048] Although there are three separate patterns requiring optimization, within one pattern there are multiple operations that can be optimized independently. The steps for optimizing the gate parameters are described in more detail below with reference to Figures 5-8.

[0049] The hardware patterns shown in the table above and described above with reference to Figures 2A and 2B are representative patterns and are not comprehensive. The exact patterns and groupings can be customized and determined for the system by tracing error propagation within a particular circuit. For example, the hardware patterns need not be pre-computed by the system software. In some implementations, the hardware patterns may be determined by modifying parameters on particular gates and observing where changes in detection events are found. By modifying each of the parameters on each of the particular gates in such a manner, the information generated may be processed and used to determine the hardware patterns. Such methods of determining hardware patterns are sensitive to hardware non-idealities and may enhance system performance and efficiency.

[0050] 3 is a schematic one-dimensional perspective circuit representation of a qubit in an exemplary error correction system. In this simplified circuit representation, the output of measurement qubit 304 may operate as a multiplexer 308 with three inputs, one for the associated measurement qubit 304 and one for each neighboring data qubit 302 and 306. Only one of the inputs to the multiplexer may be selected at a time to directly probe the output of one of the data or measurement boxes, e.g., data boxes 302, 306 and measurement box 304. This gives rise to the three hardware patterns 200, 210 and 220 described above with reference to FIGS. 2A and 2B.

[0051] 4 is a two-dimensional perspective schematic diagram 400 of an exemplary hardware pattern in an error correction system. The same analysis described above with reference to FIGS. 2A and 2B may be applied to a surface code to generate the illustrated hardware pattern. The hardware pattern may include one hardware pattern 404 that includes measurement qubits. The remaining hardware patterns 406-412 may include both data qubits and measurement qubits.

[0052] The hardware patterns 404-412 shown in FIG. 4 constitute a minimum number of hardware patterns that can be used to implement error correction for a system that includes a two-dimensional array of qubits. The table below counts the number of patterns that can be interleaved to optimize all gates in parallel. There are five interleaved patterns, and one gate in each pattern may be optimized. The patterns shown are representative and not a minimum set. Other patterns may exist and be more complex. The number and complexity of the patterns depends on the exact details of which order the quantum gates are executed across the array. As described above, by selecting such a hardware pattern for the system, the gate parameters within each hardware grouping in each hardware pattern may be optimized by varying the gate parameters to optimize the measured error rate for each hardware grouping. Furthermore, by selecting a finite number of hardware patterns, each operation required to optimize the quantum computer to perform error detection may be accessed. Once a hardware pattern is chosen, every hardware grouping can be optimized independently in parallel, which is an O(1) scaling strategy for optimizing every single gate in a quantum computer of any size.

[0053] [Table 2]

[0054] Although there are five separate patterns requiring optimization, within one pattern there are multiple operations that can be optimized independently. The steps for optimizing the gate parameters are described in more detail below with reference to Figures 5-8.

[0055] The hardware patterns shown in the table above and described above with reference to FIG. 4 are representative patterns and are not comprehensive. The exact patterns and groupings can be customized and determined for the system by tracking error propagation within a particular circuit. For example, the hardware patterns need not be pre-computed in the system's software. In some implementations, the hardware patterns may be determined by modifying parameters on particular gates and observing where changes in detection events are found. By modifying each of the parameters on each of the particular gates in such a manner, the information generated may be processed and used to determine the hardware patterns. Such methods of determining hardware patterns are sensitive to hardware non-idealities and may enhance system performance and efficiency.

[0056] Although the hardware patterns described herein are specific to one-dimensional chains of qubits running an iterative code, the techniques may be generalized to most error correction frameworks. Any framework that detects errors using groups of qubits of a fixed maximum size, where the number of groups to which any qubit belongs does not scale with the system size, may utilize the hardware and methods described herein. For example, the techniques may be compatible with all topology codes, including subsystem codes, and all concatenated codes by focusing on the lowest level of concatenation. This includes surface and color codes, and Steane and Shor codes. The hardware and methods described herein may not be compatible with finite-rate block codes if one wishes to preserve O(1) scaling with system size. Hardware patterns and groupings may be discovered algorithmically by simulating the error detection circuitry, or by physically varying control parameters and determining where the detection fraction changes.

[0057] In particular, although Figures 2A and 2B, 3 and 4 have been described with respect to iterative and surface codes, the methods for tracking error signatures from gates to physical measurements may be applied outside of the iterative and surface codes and may be applied to any quantum circuit and may be used as a method to provide feedback for optimization.

[0058] Implementing in situ quantum error correction 5 is a flow diagram of an exemplary process 500 for performing continuous optimization of quantum gate parameters while performing error correction. For example, process 500 may be performed during an error correction procedure by system 100 or 300 described above with reference to FIGS. 1A-1B and 3. Process 500 uses error detection to self-diagnose and allows for continuous optimization of control parameters while the system is running, thus combating system drift without interrupting computation.

[0059] The system spatially partitions the sets of data qubits and measurement qubits into separate hardware patterns (step 502). The system partitions the sets of data qubits and measurement qubits such that errors attributable to each separate hardware pattern do not overlap with errors attributable to other separate hardware patterns. Depending on the configuration, the hardware patterns may include one pattern having a grouping that includes measurement qubits, and two or more patterns having groupings that include both data qubits and measurement qubits. Configurations for partitioning the sets of data qubits and measurement qubits into separate hardware patterns are described in more detail above with reference to Figures 2A and 2B and Figure 4.

[0060] The system then proceeds to optimize parameters of quantum gates operating on qubits in each hardware pattern having a grouping that includes a measurement qubit (step 504). By configuration, each of the measurement qubits in the set of data qubits and measurement qubits may form one of the hardware patterns constructed in step 502. For example, in one dimension, the system may optimize parameters of quantum gates operating on measurement qubits in hardware pattern 200 described above with reference to FIG. 2A. In another example, in two dimensions, the system may optimize parameters of quantum gates operating on measurement qubits in hardware pattern 404 described above with reference to FIG. 4.

[0061] The step of performing optimization of parameters of quantum gates operating on the measurement qubits may be considered as the simplest optimization stage. For example, when considering the step of performing error correction on an iteration code, the measurement qubits may detect a bit-flip error. Due to the orientation of the CNOT gates applied to the measurement and data qubit pair, the bit-flip error does not propagate from the measurement qubit to the data qubit, so the error is localized to the particular measurement qubit. The measurement qubits may therefore have the parameters of the single-qubit quantum gates operating on them individually optimized fully in parallel as one hardware pattern, as described below with reference to steps 506 and 508.

[0062] The system performs an optimization of parameters of the readout gate operating on the measurement qubit (step 506). Optimization of the parameters of the readout gate operating on the measurement qubit may be performed in parallel for each measurement qubit in the hardware pattern. An exemplary process for optimizing parameters of the readout gate operating on the measurement qubit is described in detail below with reference to FIG.

[0063] The system performs an optimization of parameters of a single-qubit quantum gate operating on the measurement qubit (step 508). Optimization of parameters of the single-qubit quantum gate operating on the measurement qubit may be performed in parallel for each measurement qubit in the hardware pattern. An exemplary process for optimizing parameters of a single-qubit quantum gate operating on the measurement qubit is described in detail below with reference to FIG.

[0064] The system then proceeds to optimize parameters of quantum gates operating on qubits in each hardware pattern having a grouping that includes both data qubits and measurement qubits (step 510). By configuration, in each hardware pattern having a grouping that includes both data and measurement qubits, the data qubits may be accompanied by measurement qubits in their respective hardware groupings established in step 502. For example, in one dimension, the system may optimize parameters of single-qubit quantum gates operating on data qubits in hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system may optimize parameters of single-qubit quantum gates operating on data qubits in hardware patterns 406, 408, 410, and 412 described above with reference to FIG. 4.

[0065] The step of performing optimization of parameters of single-qubit quantum gates operating on the data qubit may be more complex than the step of performing optimization of parameters of single-qubit quantum gates operating on the measurement qubit. For example, when considering performing error correction on an iterative code, a bit-flip error may be copied from the data qubit to a nearby measurement qubit through a CNOT gate operating on both the data qubit and the measurement qubit. Thus, a single error on a data qubit may generate an output, or detection event, at each of its nearby measurement qubits, as described above with reference to Figures 2A and 2B. Data qubits may therefore not have the parameters of the single-qubit quantum gates operating on them optimized individually and completely in parallel as one hardware pattern, because if the next-nearest data qubit simultaneously optimizes the parameters of their single-qubit gates, they may both copy errors to the same measurement qubit and generate error confusion. Instead, all other data qubits may be optimized in parallel as a single hardware pattern, as described below with reference to step 512 and FIG. 6, to avoid double mapping of errors on the measurement qubits.

[0066] The system performs parameter optimization of single-qubit quantum gates operating on data qubits in each hardware pattern having a grouping that includes both data qubits and measurement qubits (step 512). Optimization of parameters of single-qubit quantum gates operating on data qubits in each hardware pattern may be performed separately for each hardware pattern. However, optimization of parameters of single-qubit quantum gates operating on data qubits in each grouping within each hardware pattern may be performed in parallel for each data qubit in the hardware pattern. An exemplary process for optimizing parameters of single-qubit quantum gates operating on data qubits is described in detail below with reference to FIG. 7.

[0067] The step of performing the optimization of parameters of CNOT gates operating on pairs of data qubits and measurement qubits may also be complicated due to error confusion. An error on a data qubit may propagate to the measurement qubits on each side of the involved data qubit. Thus, an error on a data qubit may generate an output, or detection event, in each of its neighboring measurement qubits, as described above with reference to FIG. 2B. The parameters of CNOT gates operating on pairs of data qubits and measurement qubits may therefore not be optimized in parallel on the same data qubit or measurement qubit. This naturally restricts the hardware patterns to the same ones as, for example, described above with reference to step 510. To avoid error confusion, there may be a simple rule: only CNOT gates that are completely contained in a hardware pattern may be optimized with that pattern.

[0068] The system performs optimization of parameters of CNOT gates operating on pairs of data qubits and measurement qubits in each hardware grouping that includes both data qubits and measurement qubits in a hardware pattern (step 514). Optimization of parameters of CNOT gates operating on pairs of data qubits and measurement qubits in the hardware pattern may be performed separately for each hardware pattern. Furthermore, the system selects CNOT gates that define the same direction in the hardware pattern and optimizes parameters of the CNOT gates that define the same direction in parallel for each data qubit in the hardware pattern. For example, in one dimension, for each hardware pattern that includes data qubits and measurement qubits, the system may first select a set of CNOT gates to the left of the data qubit that optimize the selected CNOT gate parameters in parallel, and a set of CNOT gates to the right of the data qubit that optimize the selected CNOT gate parameters in parallel. An exemplary process for optimizing parameters of CNOT gates operating on data qubits and measurement qubits is described in detail below with reference to FIG. 8.

[0069] For clarity, a flow diagram of an exemplary process 500 for performing continuous optimization of quantum gate parameters while performing error correction is described with reference to steps 504-514. However, it is not necessary that the operations of steps 504-514 be performed sequentially in the order presented. The steps may be performed in different sequences, and may be performed multiple times, before the next step in the sequence is performed, if desired. For example, in some implementations, the system may first enter a stage for optimizing parameters of quantum gates operating on qubits in each hardware pattern that includes both data qubits and measurement qubits before entering a stage for optimizing parameters of quantum gates operating on qubits in each hardware pattern that includes measurement qubits. Similarly, for example, once entering a stage for optimizing parameters of quantum gates operating on qubits in each hardware pattern that includes measurement qubits, the system may first perform optimization step 508 before performing optimization step 506. By cycling between steps 506, 508, 512, and 514, i.e., cycling between hardware patterns, one may counter system drift in all parameters of all gates for all qubits while the system is running.

[0070] FIG 6 is a flow diagram of an exemplary process 600 for optimizing parameters of a readout or single qubit quantum gate operating on a measurement qubit. Process 600 may be performed by systems 100 or 300 described above with reference to FIGS. 1A-1B and 3 for optimizing parameters of a readout quantum gate as described above in step 506 of FIG 5, or for optimizing parameters of a single qubit quantum gate as described above in step 508 of FIG 5. By configuration, each of the measurement qubits in the collection of data qubits and measurement qubits described in FIGS. 1A-1B and 3 forms one of the hardware patterns constructed above in step 502 with reference to FIG 5. For example, in one dimension, the system may optimize parameters of a readout or single qubit quantum gate operating on a measurement qubit in hardware pattern 202 described above with reference to FIG 2A. In another example, in two dimensions, the system may optimize parameters of a quantum gate operating on a measurement qubit in hardware pattern 404 described above with reference to FIG 4.

[0071] Process 600 may be performed in parallel for each measurement qubit in a corresponding hardware pattern, and process 600 may be continuously repeated to optimize parameters of a readout gate or single-qubit quantum gate operating on the measurement qubit using closed-loop feedback.

[0072] In parallel, for each measurement qubit, the system defines a corresponding metric for error minimization as the determined error rate (step 602). The quantum gate error may be minimized by minimizing the error rate for each qubit, also referred to as the fraction of detection events. In the case of a hardware pattern including a single measurement qubit, the metric for error minimization may be the fraction of detection events for that qubit. In the case of a hardware pattern including multiple measurement qubits, such as those shown in Figures 2A and 4, the metric for error minimization is the average fraction of detection events taken over all measurement qubits.

[0073] In parallel, for each measurement qubit, the system measures the measurement qubit to determine the current error rate (step 604).

[0074] The system stores the determined error rate, step 606. The system stores the determined error rate for each iteration of process 600 so that changes in the error rate can be monitored over time and correlated with changes made to the quantum gate parameters.

[0075] The system calculates the change in error rate between the determined current error rate and the stored error rate from the previous iteration (step 608). A change in the measured pattern of measurement outputs, or detection events, and states for a measurement qubit may indicate the presence of a nearby error, whether on a data qubit or a measurement qubit. However, the detection events themselves may not directly correlate to an error on the measurement qubit or data qubit. Thus, to correlate the change in error with a change in a gate parameter, the change in the localized detection event fraction, i.e., the error rate, may be compared to the change in the gate parameter.

[0076] In parallel, for each measurement qubit, the system adjusts readout gate parameters, or single qubit quantum gate parameters, based on the calculated change in error rate, step 610. The system may apply a numerical optimization algorithm, such as the Nelder-Mead method, based on the change in error rate calculated in step 608 to determine adjustments to make to the readout gate parameters or single qubit quantum gate parameters.

[0077] The system may continually repeat steps 602 to 610 above. In principle, it may be possible to distinguish between the qubits of measurement X and measurement Y to obtain more information about the physical processes associated with the gate error, and this information may be fed back to the system to optimize the quantum gate more efficiently.

[0078] FIG 7 is a flow diagram of an exemplary process 700 for optimizing parameters of single-qubit quantum gates operating on data qubits. Process 700 may be performed by systems 100 or 300 described above with reference to FIGS. 1A-1B and 3 for optimizing parameters of the single-qubit quantum gates as described above in step 512 of FIG 5. The process may be performed for each hardware pattern having a grouping including both data qubits and measurement qubits constructed in step 502 with reference to FIG 5 above. For example, in one dimension, the system may optimize parameters of single-qubit quantum gates operating on data qubits in hardware patterns 210 and 220 described above with reference to FIG 2B. In another example, in two dimensions, the system may optimize parameters of quantum gates operating on measurement qubits in hardware patterns 406, 408, 410 and 412 described above with reference to FIG 4.

[0079] Process 700 may be performed in parallel for each data qubit in a corresponding hardware pattern, or it may be a continuously iterated process that uses closed-loop feedback to optimize parameters of a single-qubit quantum gate operating on that data qubit.

[0080] In parallel, for each data qubit, the system defines a corresponding metric for error minimization as the determined error rate (step 702). Quantum gate errors may be minimized by minimizing the error rate of each qubit, also called the fraction of detection events. In the present case of hardware patterns having groupings including multiple measurement qubits, such as those shown in Figures 2B and 4, the metric for error minimization may be the average fraction of detection events taken for all measurement qubits.

[0081] In parallel, for each data qubit, the system measures its corresponding nearby measurement qubits to determine the current error rate (step 704). For example, in a one-dimensional system, the system may measure at least two corresponding measurement qubits. For example, in a two-dimensional system, the system may measure at least four corresponding measurement qubits.

[0082] The system stores the determined error rate, step 706. The system stores the determined error rate for each iteration of process 700 so that changes in the error rate can be monitored over time and correlated with changes made to the quantum gate parameters.

[0083] The system calculates the change in error rate between the determined current error rate and the stored error rate from the previous iteration (step 708). A change in the measured pattern of measurement outputs, or detection events, and states for the measurement qubits may indicate the presence of nearby errors, whether on the data qubits or the measurement qubits. However, the detection events themselves may not directly correlate to errors on the measurement qubits or data qubits. Thus, to correlate the change in error with the change in the gate parameters, the change in the localized detection event fraction, i.e., the error rate, may be compared to the change in the gate parameters.

[0084] In parallel, for each data qubit, the system adjusts parameters of a single-qubit gate based on the calculated change in error rate, step 710. The system may apply a numerical optimization algorithm, such as the Nelder-Mead method, to determine adjustments to be made to the single-qubit quantum gate parameters based on the change in error rate calculated in step 708.

[0085] The system may continually repeat steps 702 to 710 above. In principle, it may be possible to distinguish between the qubits of measurement X and measurement Y to obtain more information about the physical processes associated with the gate error, and this information may be fed back to the system to more efficiently optimize the quantum gate.

[0086] FIG. 8 is a flow diagram of an exemplary process 800 for optimizing parameters of CNOT gates operating on pairs of data qubits and measurement qubits. Process 800 may be performed by systems 100 or 300 described above with reference to FIGS. 1A-1B and 3 for optimizing parameters of CNOT gates as described above in step 514 of FIG. 5. The process may be performed for each hardware pattern having a grouping including both data qubits and measurement qubits constructed in step 502 with reference to FIG. 5 above. For example, in one dimension, the system may optimize parameters of CNOT gates operating on pairs of data qubits and measurement qubits in hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system may optimize parameters of quantum gates operating on measurement qubits in hardware patterns 406-412 described above with reference to FIG. 4.

[0087] Process 800 may be performed in parallel for each CNOT gate that is entirely contained in a corresponding hardware pattern that defines the same direction with respect to the data qubits on which the CNOT gate operates. Process 800 may be a continuously iterative process that optimizes parameters of the CNOT gate using closed-loop feedback.

[0088] In parallel, for each data qubit, the system defines a corresponding metric for error minimization as the determined error rate (step 802). Quantum gate errors may be minimized by minimizing the error rate of each qubit, also called the fraction of detection events. In the present case of hardware patterns having groupings including multiple measurement qubits, such as those shown in Figures 2B and 4, the metric for error minimization may be the average fraction of detection events taken for all measurement qubits.

[0089] In parallel, for each data qubit, the system measures corresponding nearby measurement qubits to determine the current error rate (step 804). For example, in a one-dimensional system, the system may measure at least two corresponding measurement qubits. For example, in a two-dimensional system, the system may measure at least four corresponding measurement qubits.

[0090] The system stores the determined error rate, step 806. The system stores the determined error rate for each iteration of process 800 so that changes in the error rate can be monitored over time and correlated with changes made to the quantum gate parameters.

[0091] The system calculates the change in error rate between the determined current error rate and the stored error rate from the previous iteration (step 808). A change in the measured pattern of measurement outputs, or detection events, and states for the measurement qubits may indicate the presence of nearby errors, whether on the data qubits or the measurement qubits. However, the detection events themselves may not directly correlate to errors on the measurement qubits or data qubits. Thus, to correlate the change in error with the change in the gate parameters, the change in the localized detection event fraction, i.e., the error rate, may be compared to the change in the gate parameters.

[0092] In parallel, for each data qubit, the system adjusts CNOT gate parameters based on the calculated change in error rate, step 810. The system may apply a numerical optimization algorithm, such as the Nelder-Mead method, to determine the adjustments to make to the CNOT quantum gate parameters based on the change in error rate calculated in step 808.

[0093] The system may continually repeat the above steps 802 to 810. In principle, it may be possible to distinguish between qubits for measurement X and measurement Y to obtain more information about the physical processes associated with the gate errors, and this information may be fed back to the system to optimize the quantum gate more efficiently.

[0094] The digital and / or quantum subject matter and implementations of digital functional operations and quantum operations described herein may be implemented in digital electronic circuitry, suitable quantum circuitry or, more generally, in a quantum computing system, in tangibly embodied digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware including structures disclosed herein, and structural equivalents thereof, or in one or more combinations thereof. The term "quantum computing system" may include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0095] Implementations of the digital and / or quantum subject matter described herein may be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by or controlling the operation of a data processing apparatus. The digital and / or quantum computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or one or more combinations thereof. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal that may encode digital and / or quantum information, e.g., a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver apparatus for execution by a digital and / or quantum data processing apparatus.

[0096] The terms quantum information and quantum data refer to information or data carried by and held or stored in a quantum system, the smallest non-trivial system being a qubit, i.e., a system that defines a unit of quantum information. It is understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include, for example, multi-level systems having more than two levels. By way of example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are identified with a ground state and a first excited state, although it is understood that other configurations are possible in which the computational states are identified with higher excited states. The term "data processing apparatus" refers to digital and / or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and / or quantum data for processing, including, by way of example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers, and combinations thereof. The device may further be or include special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a quantum simulator, i.e., a quantum data processing device, designed to simulate or generate information about a particular quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The device may optionally include, in addition to hardware, code that generates an execution environment for digital and / or quantum computer programs, e.g., code that constitutes processor firmware, protocol stacks, database management systems, operating systems, or one or more combinations thereof.

[0097] A digital computer program may also be referred to or described as a program, software, software application, module, software module, script, or code, and may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and may be deployed in any form, including stand-alone programs or modules, components, subroutines, or other units suitable for use in a digital computing environment. A quantum computer program may also be referred to or described as a program, software, software application, module, software module, script, or code, and may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and may be converted into a suitable quantum programming language, or may be written in a quantum programming language, for example, QCL or Quipper.

[0098] A digital and / or quantum computer program may, but need not, correspond to a file in a file system. A program may be stored in one or more scripts, e.g., a file storing one or more modules, subprograms, or portions of code, stored as part of a file holding other programs or data, e.g., a markup language document, in a single file dedicated to the program in question, or in multiple cooperating files. A digital and / or quantum computer program may be deployed to run on one digital or one quantum computer or on multiple digital and / or quantum computers, located at one site or distributed across multiple sites interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that may transmit quantum data using quantum systems, e.g., qubits. Generally, a digital data communication network cannot transmit quantum data, but a quantum data communication network may transmit both quantum data and digital data.

[0099] The processes and logic flows described herein may be implemented by one or more programmable digital and / or quantum computers operating on one or more digital and / or quantum processors, as appropriate, executing one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data to generate output. The processes and logic flows may also be implemented by, and apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or a combination of special purpose logic circuitry or a quantum simulator and one or more programmed digital and / or quantum computers.

[0100] To say that one or more digital and / or quantum computer systems are "configured to" perform a particular operation or action means that the system has installed thereon software, firmware, hardware, or a combination thereof that, in operation, causes the system to perform the operation or action. To configure one or more digital and / or quantum computer programs to perform a particular operation or action means that the one or more programs contain instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform the operation or action. A quantum computer may receive instructions from a digital computer that, when executed by the quantum computing device, cause the device to perform the operation or action.

[0101] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program can be based on a general-purpose or special-purpose digital and / or quantum processor or both, or any other kind of central digital and / or quantum processing unit. Typically, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from a read-only memory, a random access memory, or a quantum system suitable for transmitting quantum data, e.g. photons, or a combination thereof.

[0102] The essential elements of a digital and / or quantum computer are a central processing unit for carrying out or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory may be supplemented by special purpose logic circuitry or incorporated into the circuitry or quantum simulator. In general, a digital and / or quantum computer may also include or be operatively connected to one or more mass storage devices, e.g., magnetic, magneto-optical, optical disks suitable for storing quantum information, for transmitting and receiving quantum system digital and / or quantum data. However, a digital and / or quantum computer need not have such devices.

[0103] Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include, by way of example, all forms of non-volatile digital and / or quantum memories, media and memory devices, including semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices, magnetic disks, e.g., internal hard disks or removable disks, magneto-optical disks, CD-ROM and DVD-ROM disks, and quantum systems, e.g., trapped atoms or electrons. It is understood that quantum memories are devices capable of storing quantum data with high fidelity and efficiency for long periods of time, e.g., light-matter interfaces where light is used to transmit and matter stores and preserves quantum characteristics of the quantum data, such as superposition or quantum coherence.

[0104] Control of the various systems described herein, or portions thereof, may be implemented in a digital and / or quantum computer program product stored on one or more non-transitory machine-readable storage media and including instructions executable on one or more digital and / or quantum processing devices. The systems described herein, or portions thereof, may each be implemented as an apparatus, method, or system that may include one or more digital and / or quantum processing devices and memories that store executable instructions for implementing the operations described herein.

[0105] Although the specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in the specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations separately or in any suitable subcombination. Furthermore, although features may be described above as operating in a particular combination and initially claimed as such, one or more features from a claimed combination may in some cases be implemented from that combination, and the claimed combination may relate to a subcombination or a variation of a subcombination.

[0106] Similarly, although operations have been described in a particular order in the figures, this should not be understood as requiring that such operations be performed in the particular order shown, or in a sequential order, or that all of the shown operations be performed, to achieve desired results. In certain environments, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the program components and systems described may generally be integrated into a single software product or packaged into multiple software products.

[0107] Particular implementations of the subject matter have been described. Other implementations are within the scope of the appended claims. For example, the actions recited in the claims may be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order depicted, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. [Explanation of symbols]

[0108] 130 Error Correction Subsystem

Claims

1. 1. A quantum computing system, comprising: an error correction subsystem in data communication with a quantum computer that performs an error correction procedure on data qubits and measurement qubits, the data qubits and the measurement qubits being divided into a plurality of patterns, with errors attributable to each pattern being non-overlapping, the error correction subsystem optimizing in parallel, for each pattern that includes a measurement qubit, parameters of a single-qubit quantum gate operating on the measurement qubit; measuring measurement qubits in the pattern in parallel to determine a current error rate; calculating a change in error rate between the current error rate and a previously calculated error rate; adjusting the parameter of the single-qubit quantum gate based on the change in error rate. an error correction subsystem configured to optimize the error correction; A quantum computing system comprising:

2. The quantum computing system of claim 1, wherein optimizing parameters of a single-qubit quantum gate operating on the measurement qubit in parallel includes performing an iterative process using closed-loop feedback.

3. The quantum computing system of claim 1, wherein the error rate comprises a fraction of detected events or an average fraction of detected events.

4. The error correction subsystem comprises: storing the calculated change in error rate to monitor said change in error rate over time; Correlating the change in error rate over time with adjustment of the parameter of the single qubit quantum gate. The quantum computing system of claim 1 further configured to:

5. The quantum computing system of claim 4, wherein the error correction subsystem is further configured to determine one or more errors in the measurement qubit or the data qubit based on the correlated change in error rate over time and adjustment of the parameters of the single-qubit quantum gate.

6. The quantum computing system of claim 1, wherein adjusting the parameters of the single-qubit quantum gate based on the change in error rate includes applying a numerical optimization algorithm.

7. The quantum computing system of claim 1, wherein optimizing in parallel parameters of single-qubit quantum gates operating on the measurement qubit includes optimizing in parallel parameters of single-qubit quantum gates operating on a qubit of the measurement value X.

8. The quantum computing system of claim 1, wherein optimizing in parallel parameters of single-qubit quantum gates operating on the measurement qubit includes optimizing in parallel parameters of single-qubit quantum gates operating on a qubit of the measurement value Y.

9. The data qubit; interleaving the data qubits such that each data qubit has one or more nearby measurement qubits; a plurality of single-qubit quantum gates, each single-qubit quantum gate configured to operate on a data qubit or a measurement qubit; The quantum computing system of claim 1 further comprising:

10. The quantum computing system of claim 1, wherein the single-qubit quantum gate comprises a phase-shift gate or a rotation gate.

11. A computer-implemented method comprising: Optimizing in parallel parameters of single-qubit quantum gates operating on measurement qubits in a quantum computer that performs an error correction procedure on data qubits and measurement qubits, the data qubits and the measurement qubits being divided into a plurality of patterns, and errors attributable to each pattern being non-overlapping, the optimizing step comprising: measuring measurement qubits in the pattern in parallel to determine a current error rate; calculating a change in error rate between the current error rate and a previously calculated error rate; adjusting the parameter of the single qubit quantum gate based on the change in error rate; Including steps A method comprising:

12. The method described in claim 11, wherein the step of optimizing in parallel parameters of a single-qubit quantum gate operating on the measurement qubit includes a step of performing an iterative process using closed-loop feedback.

13. The method of claim 11, wherein the error rate comprises a fraction of detection events or an average fraction of detection events.

14. The method according to claim 1, storing the calculated change in error rate to monitor said change in error rate over time; correlating the change in error rate over time with adjustments of the parameters of the single qubit quantum gate; The method of claim 11 further comprising:

15. The method of claim 14, further comprising determining one or more errors in the measurement qubit or the data qubit based on the correlated change in error rate over time and adjusting the parameters of the single-qubit quantum gate.

16. The method of claim 11, wherein adjusting the parameters of the single-qubit quantum gate based on the change in error rate comprises applying a numerical optimization algorithm.

17. The method of claim 11, wherein the step of optimizing in parallel parameters of single-qubit quantum gates operating on the measurement qubit comprises the step of optimizing in parallel parameters of single-qubit quantum gates operating on a qubit of the measurement X.

18. The method described in claim 11, wherein the step of optimizing in parallel parameters of single-qubit quantum gates operating on the measurement qubit includes a step of optimizing in parallel parameters of single-qubit quantum gates operating on a qubit of the measurement Y.

19. The quantum computer, the data qubit; and interleaving the data qubits such that each data qubit has one or more nearby measurement qubits; a plurality of single-qubit quantum gates, each single-qubit quantum gate configured to operate on a data qubit or a measurement qubit; The method of claim 11 further comprising:

20. The method of claim 11, wherein the single-qubit quantum gate comprises a phase-shift gate or a rotation gate.

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