Musical tone signal generating device, electronic device, musical tone signal generating method, and program

Abstract

To reduce the occurrence of noise when the number of connection of delay devices is changed with a small amount of calculation while eliminating frequency dependence of an amplitude using all-pass filters (APF).SOLUTION: In a musical sound signal generation device, a wave guide model computing unit 202 outputs, as a musical sound signal and a feedback signal, via a switch, an output of an APR to which a first delay device 302 that generates a delay of an integer part of a delay length corresponding to a designated tone pitch is connected, wherein both ends of each of the first delay device, and zeroth and second delay devices previous and subsequent thereto are connected to APFs #1 to #2, a filter coefficient corresponding to a delay of a fractional part and respective filter coefficients that generate delays of a value 1 and a value 0, respectively, are set. When the designated tone pitch is changed so that the integer part of the delay length is changed, the APF having been connected so far is caused to take over the operation using a new delay device corresponding to the integer part as the first delay device, and other APFs are newly connected to new zeroth and second delay devices previous and subsequent to the new first delay device.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a musical sound signal generating device, an electronic device, a musical sound signal generating method, and a program. [Background technology]

[0002] The number of delay units that make up the waveguide modeling sound source is an integer and is discrete. Therefore, in order to determine the exact frequency, a technology is required to realize a delay length that is a fractional number smaller than the integer equivalent to the number of delay units.

[0003] As a conventional technique for continuously realizing decimal delay lengths in a wide frequency band, a technique for inserting an all-pass filter after the final stage of a delay device is known (for example, the technique described in Patent Document 1). This technique realizes a musical tone signal synthesis device including a first all-pass filter APF1, a second all-pass filter APF2, variable connection means for connecting the first and second all-pass filters to different selected stages of a delay element, control means for controlling the all-pass filters and the variable connection means so that the delay times at the outputs of the first and second all-pass filters are equal, and weighting addition means for weighting and adding the outputs of the first and second all-pass filters. In this conventional technique, the use of an all-pass filter makes it possible to prevent a decrease in amplitude in a high frequency band. In addition, this conventional technology generates a decimal delay length by weighted addition of two all-pass filters, thereby suppressing the generation of noise caused by the all-pass filter coefficients making discontinuous transitions between 0.0 and 1.0 when the high frequency of the sound changes over time, such as during pitch bending, and the integer delay length in the wave guide modeling sound source switches over time. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 6-348277 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned conventional technology, it was necessary to operate the two all-pass filters so that the delay times are always equal, and to perform weighted addition of the outputs of the two all-pass filters. For this reason, in the two all-pass filter calculations, the filter coefficients are always multiplied twice, and a multiplication calculation is also required in the weighted addition, so at least six multiplication calculations are required in total per sample. When using the technology of a wave guide modeling sound source with a high number of multiplication calculations, for example, when 256 polyphonic musical tones are to be generated simultaneously (for example, in the case of a piano modeling sound source), at least 6 times x 256 polyphony = 1,536 multiplication calculations are required in total per sample, which results in a problem that the amount of calculation required for generating musical tones as a whole becomes large.

[0006] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to generate musical tones with a small amount of calculation. [Means for solving the problem]

[0007] A musical tone signal generating device according to one embodiment of the present invention includes a delay line having a plurality of delay elements connected in cascade, each of which delays an input signal by a first delay width, and a plurality of fractional part delay blocks, each of which is connected to a corresponding one of the plurality of delay elements, thereby delaying the input signal by a second delay width that is equal to or shorter than the first delay width; Switch,and at least one processor that sets any one of the plurality of delay units to a first delay unit that generates a delay corresponding to a specified pitch, sets a delay unit preceding the first delay unit among the plurality of delay units to a 0th delay unit, and sets a delay unit following the first delay unit among the plurality of delay units to a second delay unit, wherein the plurality of fractional part delay blocks include a first fractional part delay block and a second fractional part delay block, and the at least one processor The above A second fractional part delay block is connected to the first delay unit and the second delay unit, and the second delay unit is newly delayed in response to a change in the designated pitch. The first When the delay unit before the new first delay unit is set to a new 0th delay unit and the delay unit after the new first delay unit is set to a new 2nd delay unit, the second delay unit that is connected is kept connected to the second fractional part delay block, and the new second delay unit is reconnected to the first fractional part delay block, and the 0th delay unit that is connected is changed to the new The first When the first delay unit is set as the first delay unit, the delay unit preceding the new first delay unit is set as the new 0th delay unit, and the delay unit following the new first delay unit is set as the new second delay unit, the first delay unit that is currently connected is kept connected to the first fractional part delay block, and the new first delay unit is reconnected to the second fractional part delay block. The switch exclusively outputs an output signal from either the first fractional part delay block or the second fractional part delay block. . Effect of the Invention

[0008] According to the present invention, it is possible to generate musical tones with a small amount of calculation. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of hardware of an embodiment of a musical sound signal generating device according to the present disclosure; [Diagram 2] FIG. 2 is a block diagram showing an example of functions realized by a DSP or a waveguide model circuit. [Diagram 3] FIG. 2 is a diagram illustrating an example of a block configuration of a waveguide model calculation unit. [Figure 4] FIG. 1 is a diagram showing an example of connection of three sets of APFs to a delay line. [Diagram 5] 11A and 11B are diagrams illustrating the effect of reducing the calculation load in the embodiment. [Figure 6] FIG. 13 is a diagram showing changes in the connections of three sets of APFs to delay lines when the number k of delay elements, which is the integer part of the delay length, increases. [Figure 7] FIG. 11 is an explanatory diagram of a method for continuous control of filter coefficients. [Figure 8] FIG. 13 is a diagram showing changes in the connections of three sets of APFs to the delay lines when the number k of delay elements, which is the integer part of the delay length, is reduced. [Figure 9] 13 is a flowchart (part 1) illustrating an example of a pitch bend control process. [Figure 10] 13 is a flowchart (part 2) illustrating an example of a pitch bend control process. [Figure 11] FIG. 13 is a diagram showing another embodiment of the waveguide model calculation unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiment for carrying out the present disclosure will be described in detail with reference to the drawings. The electronic device includes a musical tone signal generating device 100, a performance operator (not shown), and a speaker. If the electronic device is a keyboard such as an electronic piano, the performance operator corresponds to a keyboard, and if the electronic device is an electronic wind instrument, the performance operator corresponds to a mouthpiece. FIG. 1 is a block diagram showing an example of hardware of an embodiment of the musical tone signal generating device 100 according to the present disclosure. The musical tone signal generating device 100 includes at least one processor, a CPU (Central Processing Unit: Central Processing Unit) 101, a ROM (Read Only Memory) 102, a RAM (Random Access Memory) 103, a DSP (Digital Signal Processor) or a wave guide model circuit 104 described later, a pitch bend sensor 110 and an ADC (Analog-to-Digital Converter) 106 to which the output of the pitch bend sensor 110 is connected, a volume sensor 109 and an ADC or digital input port 105 that detects the volume sensor 109, a pitch designation switch 111 and a digital input port 107 to which the output of the pitch bend sensor 110 is connected, a DAC (Digital-to-Analog Converter) / amplifier 108, and a system bus 112. The CPU 101, ROM 102, RAM 103, DSP or waveguide model circuit 104, ADC 106, ADC or digital input port 105, digital input port 107, and DAC / amplifier 108 are all interconnected by a system bus 112. Here, the volume sensor 109 and the pitch designation switch 111 may be the same thing. For example, if the musical sound signal generating device 100 is an electronic piano, the switch that senses when a key is played is both the pitch sensor and the volume sensor.

[0011] In this embodiment, an example using a CPU 101 and a DSP 104 will be described as an embodiment for realizing the present disclosure by software. However, the CPU 101 may take on the role of the DSP 104. Also, the function of the DSP 104 may be realized by a hardware waveguide model circuit 104. FIG. 2 is a block diagram showing an example of the function realized by the DSP or the waveguide model circuit 104.

[0012] The waveguide model control unit 201, which is a control circuit, receives as input signals pitch information 203 (for example, the note number of the keyboard in the case of an electronic piano) input from the pitch designation switch 111 in FIG. 1, and bend information (amount of pitch change) 204 sent from the pitch bend sensor 110 in FIG. 1, calculates the delay length of the waveguide model corresponding to the frequency f to be sounded, calculates the number of delay units k, which is the integer part of the delay length, and the filter coefficient g of the all-pass filter (fractional part delay block) which determines the decimal part l of the delay length, and outputs the calculated number of delay units k and filter coefficient g to the waveguide model calculation unit 202.

[0013] Here, the relationship between the fractional part l of the delay length and the filter coefficient g of the all-pass filter is as follows: g = (1 - l) / (1 + l) (1) It is known that there is a relationship between

[0014] Furthermore, the waveguide model control unit 201 calculates a volume 207 of an excitation original sound 206 based on volume information 205 input from the volume sensor 109 in Fig. 1. Then, this volume 207 is multiplied by the excitation original sound 206 in a multiplier 208. Here, the excitation original sound 206 is a signal that is a source of resonance in the waveguide modeling, and is a signal that is recorded in advance and stored in, for example, the ROM 102 in Fig. 1, copied from the ROM 102 to the RAM 103 when the system is started, and read out from the RAM 103 when sound generation control starts, or a signal that is synthesized by calculation.

[0015] The waveguide model calculation unit 202 receives the original excitation sound 206 multiplied by the delay length (the number of delayers k and the filter coefficient g) and the volume 207 as an input signal x(n), performs a calculation described later in Fig. 3, and outputs a musical sound signal 209. The musical sound signal 209 is input to the DAC / amplifier 108 in Fig. 1, and is output via a speaker or the like of an electronic device (electronic musical instrument).

[0016] 3 is a diagram showing an example of a block configuration of the waveguide model calculation unit 202 in FIG. 2. In FIG. 3, a delay line 301 includes N (multiple) delay elements 302, #0 to #N-1, connected in cascade. The delay elements 302 delay an input signal by one sampling time and output the delayed signal. The symbol z -1 indicates that a delay calculation for one sample is executed in the z-transform. A signal obtained by adding, by an adder 311, a signal obtained by multiplying a feedback signal 303 by a predetermined gain by a multiplier 304 to an input signal x(n) (see FIG. 2) generated based on an excitation original sound 206 is input to the head delayer 302 (#0) of this delay line 301. The output of each delayer 302 in the delay line 301 can be taken out from delay line switch terminals d1 to dN.

[0017] In this embodiment, the waveguide model calculation unit 202 includes three all-pass filter circuits (hereinafter, referred to as "APF") 305, #0, #1, and #2. The APF 305 operates as an all-pass filter by being connected (set) to both ends of any one of the delay devices 302 in the delay line 301. APF305 includes a multiplier 306 that multiplies the signal on the input side of the connected delay device 302 by a feedforward gain g (g0, g1, or g2), an adder 309 that adds the signal on the output side of the connected delay device 302, the output signal of multiplier 306, and the output signal of multiplier 308 described below, and selectively outputs the added output signal to switch 310, a feedback delay device 307 that delays the above-mentioned added output signal by one sampling time, and a multiplier 308 that multiplies the output signal of feedback delay device 307 by a feedback gain -g (-g0, -g1, or -g2) and outputs the multiplied output signal to the above-mentioned adder 309.

[0018] Each pair of connection terminals i00 and i01 of APF 305 (#0), connection terminals i10 and i11 of APF 305 (#1), and connection terminals i20 and i21 of APF 305 (#2) are connected (set) to the delay line switch terminals at both ends of the same delay unit 302 in the delay line 301.

[0019] In addition, APF 305(#0), APF 305(#1), and APF 305(#2) have feedforward gains and feedback gains g0 and -g0, g1 and -g1, and g2 and -g2, respectively. Hereinafter, the feedforward gains and feedback gains will be collectively referred to as the filter coefficients of the all-pass filter.

[0020] APF 305(#0), APF 305(#1), and APF 305(#2) are always connected (set) to adjacent delay elements 302 in delay line 301, but their order is controlled by the pitch bend control process described below so that they are switched in the circular order.

[0021] Each output destination of APF 305(#0), APF 305(#1), or APF 305(#2) is connected (set) to each output selection terminal o0, o1, or o2 of switch 310, and one of them is selected as output signal y(n) to output musical tone signal 209. In addition, output signal y(n) is multiplied by output feedback gain in multiplier 304, and the multiplication result is added to input signal x(n) in adder 311.

[0022] Fig. 4 is a diagram showing an example of connection of three sets of APFs 305 #0, #1, and #2 to the delay line 301 in the waveguide model calculation unit 202 of Fig. 2 having the configuration of Fig. 3. As described above, the waveguide model control unit 201 of Fig. 2 calculates the delay length of the waveguide model corresponding to the frequency f to be sounded based on the pitch information 203 input from the pitch designation switch 111 of Fig. 1, which is a performance operator of an electronic musical instrument, and then specifies the number of delay elements k, which is the integer part of the delay length, to the waveguide model calculation unit 202. In addition, the waveguide model control unit 201 of Fig. 2 calculates the filter coefficient g of the APF 305 that determines the decimal part l of the delay length by the calculation shown in the above-mentioned formula (1), and specifies it to the waveguide model calculation unit 202.

[0023] As a result, in the waveguide model calculation unit 202 of FIG. 4, the delay line switch terminals dk and dk+1 at both ends of the delay unit 302(#k) in the delay line 301, which is the first delay unit that generates a delay of the integer part of the delay length corresponding to the designated pitch specified by the waveguide model control unit 201, are respectively connected (set) to the connection terminals i10 and i11 of the APF 305(#1).

[0024] In addition, the connection terminals i00 and i01 of the APF 305(#0) are connected (set) to the delay line switch terminals dk-1 and dk at both ends of the delay element 302(#k-1), which is the zeroth delay element in the delay line 301 and is one stage before the first delay element 302(#k), respectively.

[0025] Furthermore, delay line switch terminals dk+1 and dk+2 at both ends of delay element 302(#k+1), which is the second delay element one stage downstream of delay element 302(#k), which is the first delay element in delay line 301, are connected (set) to connection terminals i20 and i21 of APF 305(#2), respectively.

[0026] On the other hand, the feedforward gain g and feedback gain −g of the filter coefficient g calculated by the calculation shown in equation (1) corresponding to the decimal part l of the delay length corresponding to the specified pitch are set in the multipliers 306 (#1) and 308 (#1) of the APF 305 (#1) from the waveguide model control unit 201 in FIG. 2, respectively.

[0027] Moreover, a value of 0 that generates a delay of a decimal part value of 1 is set in both the multipliers 306 (#0) and 308 (#0) of the APF 305 (#0) as the feedforward gain and feedback gain of the filter coefficient.

[0028] Furthermore, values ​​of 1 and -1 that generate a delay with a decimal part value of 0 are set in the multipliers 306 (#2) and 308 (#2) of the APF 305 (#2) as the feedforward gain and feedback gain of the filter coefficients, respectively.

[0029] Then, the switch 310 makes the output selection terminal o1 conductive. As a result, the output signal of the APF 305 (#1) is selected as the output signal y(n) via the switch 310, and the musical tone signal 209 is output. In addition, the output signal y(n) is multiplied by the output feedback gain in the multiplier 304, and is added to the input signal x(n) in the adder 311.

[0030] As a result of the above control operations, the integer part k of the delay length corresponding to the specified pitch is generated as the musical tone signal 209 by the delay devices 302 #0 to #k-1 in the delay line 301, and the decimal part l of the delay length is generated by the APF 305 (#1) which operates based on the filter coefficient g calculated by the operation shown in equation (1).

[0031] In this case, since the circuit made up of the delay line 301 and the APF 305 (#1) has flat frequency characteristics, it is possible to prevent a decrease in amplitude in the high frequency band.

[0032] 5 is an explanatory diagram of the effect of reducing the calculation load in this embodiment. As described above, the multipliers 306(#0) and 308(#0) of the APF 305(#0) are both set to a value of 0 as the feedforward gain and feedback gain of the filter coefficient, which generates a delay of a decimal part value of 1. Therefore, the multipliers 306(#0) and 308(#0) do not need to execute a multiplication operation that substantially imposes a large load, and the APF 305(#0) of FIG. 4 becomes an equivalent circuit shown in FIG. 5. That is, the APF 305(#0) may execute an operation to output the output from the delay unit 302(#k-1) in the delay line 301 via the delay line switch terminal dk as it is to the output selection terminal o0 of the switch 310.

[0033] On the other hand, as described above, the multipliers 306(#2) and 308(#2) of the APF 305(#2) are set with values ​​1 and -1, respectively, as the feedforward gain and feedback gain of the filter coefficients. Therefore, the multipliers 306(#2) and 308(#2) do not need to execute a multiplication operation with a substantial load, and the APF 305(#2) of Fig. 4 becomes the equivalent circuit shown in Fig. 5. That is, the APF 305(#2) executes an operation in which the output from the delay unit 302(#k) in the delay line 301 via the delay line switch terminal dk+1 is input to the adder 309(#2) as is, instead of being multiplied by the value 1 by the multiplier 306(#2), and the output of the feedback delay unit 307(#2) is input to the adder 309(#2) after changing the sign, instead of being multiplied by the value -1 by the multiplier 308(#2).

[0034] As described above, in this embodiment, multiplication calculation is substantially necessary only in APF 305(#1), and multiplication calculation is not necessary in APF 305(#0) and APF 305(#2). Therefore, compared to the conventional technology of Patent Document 1 that uses two all-pass filters, it is possible to significantly reduce the calculation load in tone generation by waveguide modeling, which has a large number of polyphonic sounds.

[0035] Next, the principle of pitch bend control processing when a performer operates pitch bend sensor 110 (FIG. 1) of a musical instrument to change the pitch of a sound being played will be described.

[0036] In FIG. 2, a waveguide model control section 201 sequentially calculates the delay length of a new designated pitch based on bend information 204 inputted sequentially, and sequentially outputs to a waveguide model calculation section 202 the number of delay devices k, which is the integer part of the delay length, and a filter coefficient g, which is calculated by the calculation shown in equation (1) corresponding to the decimal part l.

[0037] Here, if the value of the number of delays k does not change, only the filter coefficient g changes. This means that the change in the wavelength of the musical tone signal 209 is contained within one sampling time. For example, when the performer performs a pitch bend operation to lower the pitch, and the decimal part l of the delay length corresponding to the newly designated pitch increases, the value of the filter coefficient g calculated by the calculation shown in the above formula (1) is designated to decrease.

[0038] Fig. 6 is a diagram showing changes in the connections (settings) of three sets of APFs 305 to the delay line 301 when the number of delay elements k, which is the integer part of the delay length, increases. When the performer performs a pitch bend operation to lower the pitch, causing the decimal part l of the delay length corresponding to a new specified pitch to increase sequentially and reach a value of 1, the waveguide model control unit 201 in Fig. 2 increments by +1 the value of the number of delay elements k, which is the integer part of the delay length of the specified pitch, which is output to the waveguide model calculation unit 202. At this time, the decimal part l of the delay length becomes 0 as the number of delay elements k is incremented, so the value of the filter coefficient g calculated by the calculation shown in equation (1) becomes 1.

[0039] In this way, when the value of the number of delay elements k specified by the waveguide model control unit 201 is incremented by +1 and changed, in the waveguide model calculation unit 202 shown in FIG. 6, a new delay element 302 (#k+1) in the delay line 301 corresponding to the changed number of delay elements k+1 becomes a new first delay element, and the operation of the all-pass filter is taken over by APF 305 (#2) that was previously connected to delay line switch terminals dk+1 and dk+2 on both ends of the new first delay element.

[0040] Also, in FIG. 6, as a result of the above-mentioned handover, the switch 310 turns off the conduction of the output selection terminal o1 and newly turns on the output selection terminal o2.

[0041] At this time, as described above, the multipliers 306(#2) and 308(#2) of the APF 305(#2) are set with the values ​​1 and -1, respectively, as the feedforward gain and feedback gain of the filter coefficient, which generate a delay with a decimal part value of 0. Therefore, the above-mentioned operation of switching the operation of the all-pass filter from APF 305(#1) to APF 305(#2) matches well with the operation of controlling the decimal part l to 0 specified by the waveguide model control unit 201 in Fig. 2.

[0042] Furthermore, since the APF 305(#2) is continuously operated by the actual signals from the delay line switch terminals dk+1 and dk+2, it is possible to control the APF 305 so that noise is not generated when the APF 305 is switched.

[0043] Here, as the value of the decimal part l increases in APF 305(#1), the value of the filter coefficient g calculated by the operation shown in equation (1) decreases toward 0 as described above. However, when control is switched from APF 305(#1) to APF 305(#2), the value of the decimal part l is reset to 0 to start, and at this moment it becomes necessary to make the value of the filter coefficient g jump from near 0 to near 1. Such discontinuous jumps in value are not very desirable when envelope control of the filter coefficient g is performed.

[0044] Therefore, in this embodiment, when the delay element 302 operating as the first delay element is, for example, an even-numbered delay element, the filter coefficient g is calculated by the arithmetic processing shown in the above-mentioned equation (1).

[0045] On the other hand, when delay element 302 operating as the first delay element is, for example, an odd-numbered delay element, filter coefficient g is calculated by the calculation process shown in equation (2) below. g = 1-(1-l) / (1+l) ={(1+l)-(1-l)} / (1+l) = 2 × l / (1 + l) (2) In this case, the coefficients (1-g) and -(1-g) calculated using the coefficient g calculated by the operation shown in the above equation (2) are set as the feedforward gain and feedback gain in multipliers 306 and 308, respectively.

[0046] In the example of Figure 6, for example, if all-pass filter calculations have been performed by APF 305 (#1) until now and g and -g have been set as the feedforward gain and feedback gain in multipliers 306 (#1) and 308 (#1) at that time, when the operation of the all-pass filter is switched from APF 305 (#1) to APF 305 (#2) as described above, control may be performed so that (1-g) and -(1-g) are set as the feedforward gain and feedback gain in multipliers 306 (#2) and 308 (#2).

[0047] FIG. 7 is an explanatory diagram of a method for continuously controlling the filter coefficient g. For example, consider a case where, in a section l1 in which the value of the number of delay units, which is the integer part of the delay length, is k as shown in FIG. 7(a), the filter coefficient g decreases as the decimal point of the delay length increases by the calculation shown in formula (1) as shown in FIG. 7(b). When the value of the filter coefficient g reaches 0 in the section l1, the value of the number of delay units, which is the integer part of the delay length, is switched from k to k+1 as shown in FIG. 7(a). In this new section l2, the above-mentioned control method controls the value of the filter coefficient g to increase from the minimum value 0 as the decimal point of the delay length increases by the calculation shown in formula (2) as shown in FIG. 7(b).

[0048] As described above, in this embodiment, depending on whether the delay element 302 operating as the first delay element is an even-numbered delay element or an odd-numbered delay element, the filter coefficient g is calculated by switching between the calculation shown in equation (1) and the calculation shown in equation (2), and by switching between setting a set of g and -g or a set of (1-g) and -(1-g) in the multipliers 306 and 308 in the APF 305, it is possible to continuously change the filter coefficient g specified by the waveguide model control unit 201 in FIG. 2 to the waveguide model calculation unit 202, as shown in FIG. 7(b).

[0049] As a result, by using an envelope generator circuit commonly used in electronic musical instrument technology, it is possible to input the decimal part l of the delay length, perform the calculation shown in equation (1) or (2), and output the filter coefficient g, which changes as shown in Figure 7(b), as the envelope value.

[0050] As described above, in FIG. 6, when the number of delay elements k, which is the integer part of the delay length, increases and the target performing the all-pass filter operation as the first delay element is switched from the previous APF 305(#1) to the new APF 305(#2), the delay element 302(#k) that had been operating as the first delay element until now is recognized as the 0th delay element immediately preceding the delay element 302(#k+1), which is the new first delay element, as shown in FIG. 6, and the multipliers 306(#1) and 308(#1) of the APF 305(#1) connected to the delay line switch terminals dk and dk+1 on both sides of the delay element are both set to a value 0 as the feedforward gain and feedback gain of the filter coefficient, which generates a delay of the decimal part value 1 as the all-pass filter circuit connected to the 0th delay element.

[0051] Also, in FIG. 6, delay device 302(#k+2) is recognized as a second delay device that is one stage behind delay device 302(#k+1), which is the new first delay device, and connection terminals i00 and i01 of APF 305(#0) are newly connected (set) to delay line switch terminals dk+2 and dk+3 on both sides of it, respectively, and values ​​1 and -1 that generate a delay with a decimal part value of 0 as the feedforward gain and feedback gain of the filter coefficient are set to multipliers 306(#0) and 308(#0) of APF 305(#0), respectively.

[0052] Incidentally, the output of the feedback delay unit 307 may be cleared to 0 before the connection (setting) of each APF 305 is switched as described above.

[0053] Fig. 8 is a diagram showing changes in the connections (settings) of three sets of APFs 305 to the delay line 301 when the number of delay elements k, which is the integer part of the delay length, is reduced. When the decimal part l of the delay length corresponding to a new designated pitch is sequentially reduced and reaches a value of 0 by a pitch bend operation by the performer to raise the pitch, the waveguide model control unit 201 in Fig. 2 decrements by -1 the value of the number of delay elements k, which is the integer part of the delay length of the designated pitch to be output to the waveguide model calculation unit 202. At this time, the decimal part l of the delay length becomes a maximum value of 1 as the number of delay elements k is decremented, so the value of the filter coefficient g calculated by the calculation shown in equation (1) becomes 0.

[0054] In this way, when the value of the number of delay elements k specified by the waveguide model control unit 201 is changed by decrementing it by -1, in the waveguide model calculation unit 202 shown in FIG. 8, a new delay element 302 (#k-1) in the delay line 301 corresponding to the changed number of delay elements k-1 becomes a new first delay element, and the operation of the all-pass filter is taken over by APF 305 (#0) that was previously connected to delay line switch terminals dk-1 and dk on both ends of the new delay element.

[0055] Also, in FIG. 8, as a result of the above-mentioned handover, the switch 310 turns off the conductivity of the output selection terminal o1 and newly turns on the output selection terminal o0.

[0056] At this time, as described above, the multipliers 306(#0) and 308(#0) of APF 305(#0) are both set to the value 0 as the feedforward gain and feedback gain of the filter coefficient, which generates a delay with a decimal part value of 1. Therefore, the above-mentioned operation of switching the operation of the all-pass filter from APF 305(#1) to APF 305(#0) matches well with the operation of controlling to the decimal part l=1 specified by the waveguide model control unit 201 in FIG.

[0057] Furthermore, since the APF 305(#0) is continuously operated by the actual signals from the delay line switch terminals dk-1 and dk, it is possible to control the APF 305 so that noise is not generated when the APF 305 is switched.

[0058] Here, as the value of the decimal part l decreases in the APF 305(#1), the value of the filter coefficient g calculated by the operation shown in equation (1) increases toward 1 as described above. However, when control is switched from the APF 305(#1) to the APF 305(#0), the value of the decimal part l is set to 1 and started, and at this moment it becomes necessary to make the value of the filter coefficient g jump from near 1 to near 0. This kind of nonlinear jump in value is not very preferable when the filter coefficient g is envelope-controlled, both when the value of the number of delay units k, which is the integer part of the delay length, decreases, as well as when the value of the number of delay units k, which is the integer part of the delay length, increases.

[0059] Therefore, in this embodiment, similarly to the case where the value of the number of delay elements k, which is the integer part of the delay length, increases, the filter coefficient g is calculated by switching between the calculation shown in the above-mentioned equation (1) and the calculation shown in the equation (2) depending on whether the delay element 302 operating as the first delay element is an even-numbered delay element or an odd-numbered delay element, and control is performed to switch between setting a set of g and -g or a set of (1-g) and -(1-g) to the multipliers 306 and 308 in the APF 305.

[0060] In the example of Figure 8, for example, if all-pass filter calculations have been performed by APF 305 (#1) until now and g and -g have been set as the feedforward gain and feedback gain in multipliers 306 (#1) and 308 (#1) at that time, when the operation of the all-pass filter is switched from APF 305 (#1) to APF 305 (#0) as described above, control may be performed so that (1-g) and -(1-g) are set as the feedforward gain and feedback gain in multipliers 306 (#0) and 308 (#0).

[0061] For example, in Fig. 7, consider the case where the filter coefficient g increases as the decimal point of the delay length decreases by the calculation shown in formula (1) in section l1 where the value of the number of delay units, which is the integer part of the delay length, is k as shown in Fig. 7(a) in Fig. 7(b). When the value of the filter coefficient g reaches 1 in section l1, the value of the number of delay units, which is the integer part of the delay length, is switched from k to section l0 where k-1 is k as shown in Fig. 7(a). In this new section l0, the above-mentioned control method is used to control the value of the filter coefficient g to decrease from the maximum value 1 as the decimal point of the delay length decreases by the calculation shown in formula (2) as shown in Fig. 7(b).

[0062] As described above, in this embodiment, just as in the case where the value of the number of delay elements k, which is the integer part of the delay length, increases, even when the value of the number of delay elements k, which is the integer part of the delay length, decreases, the filter coefficient g is calculated by switching between the calculation shown in equation (1) and the calculation shown in equation (2) depending on whether the delay element 302 operating as the first delay element is an even-numbered delay element or an odd-numbered delay element, and by switching between setting a set of g and -g or setting a set of (1-g) and -(1-g) to the multipliers 306 and 308 in the APF 305, it is possible to continuously change the filter coefficient g specified by the waveguide model control unit 201 in FIG. 2 to the waveguide model calculation unit 202, as shown in FIG. 7(b).

[0063] As a result, by using an envelope generator circuit commonly used in electronic musical instrument technology, it is possible to input the decimal part l of the delay length, perform the calculation shown in equation (1) or (2), and output the filter coefficient g, which changes as shown in Figure 7(b), as the envelope value.

[0064] As described above, in FIG. 8, when the number of delay elements k, which is the integer part of the delay length, is decreased and the target performing the all-pass filter operation as the first delay element is switched from the previous APF 305(#1) to the new APF 305(#0), the delay element 302(#k) that had been operating as the first delay element is recognized as the second delay element one stage behind the delay element 302(#k-1), which is the new first delay element, as shown in FIG. 8, and the multipliers 306(#1) and 308(#1) of the APF 305(#1) connected to the delay line switch terminals dk and dk+1 on both sides are set to the values ​​1 and −1, respectively, as the feedforward gain and feedback gain of the filter coefficient, which generate a delay of the decimal part value 0 as an all-pass filter circuit connected to the second delay element.

[0065] Also, in FIG. 8, the delay unit 302(#k - 2) is recognized as the 0th delay unit one stage before the delay unit 302(#k - 1) which is a new 1st delay unit. To the delay line switch terminals dk - 2 and dk - 1 on both sides thereof, the connection terminals i20 and i21 of the APF305(#2) are newly connected (set). To both the multipliers 306(#2) and 308(#2) of the APF305(#2), a value 0 that generates a delay of the fractional part value 1 as an all - pass filter circuit connected to the 0th delay unit is set as the feed - forward gain and feedback gain of the filter coefficient.

[0066] Similar to the case of FIG. 6, before the connection (setting) of each APF305 is switched as described above, the output of the feedback delay unit 307 may be cleared to 0.

[0067] FIGS. 9 and 10 are flowcharts showing examples of pitch - bend control processing executed based on the principle described above. This processing is a process in which the CPU101 in FIG. 1 loads the pitch - bend control processing program stored in the ROM102 into the RAM103 and executes it. The flowcharts of FIGS. 9 and 10 show the control time series of the waveguide model control unit 201 and the waveguide model arithmetic unit 202 in FIG. 2 when the value of the integer part k and the fractional part l of the delay length of the designated pitch changes from L1 to L2 after sound generation, when the APF305(#0) is connected to both ends of the delay unit 302(#k - 1), the APF305(#1) is connected to both ends of the delay unit 302(#k), and the APF305(#2) is connected to both ends of the delay unit 302(#k + 1).

[0068] When pitch - bend is started, in step S1, the CPU101 determines whether L2 is greater than or less than L1, that is, whether it is bend - down or bend - up.

[0069] If L1 < L2, that is, if it is bend - down, the CPU101 adds the rate r to the fractional part l of the delay length in step S2. Note that “+=” represents an operation of accumulating the variable value on the right side to the variable value on the left side.

[0070] If L is greater than the target value in step S3, the CPU 101 makes the decimal part l equal to l2 so as to match the target value in step S4.

[0071] Next, in step S5, the CPU 101 determines whether the number of delay units k is an even number or an odd number. Note that "%" is an operation that calculates the remainder when the value of the number of delay units k is divided by 2. If the result of this operation is 0, the number of delay units k is an even number, and if not 0, the number of delay units k is an odd number.

[0072] If k is an even number, in step S6, the CPU 101 sets the coefficient calculated from the decimal part l by the operation shown in equation (1) as the filter coefficient g.

[0073] If k is an odd number, the CPU 101 sets, in step S8, a coefficient calculated from the decimal part 1 by the operation shown in equation (2) to 1-g.

[0074] Thereafter, if g<0 or 1-g<0 is not satisfied in step S7 or step S9, this means that there is no carry in the number of delay elements k, which is the integer part of the delay length, so CPU 101 goes directly to step S10 to execute all-pass filter calculations of APF 305(#0), APF 305(#1), and APF 305(#2), and then updates the samples in step S11. Updating the samples means shifting the data in each delay element 302 of delay line 301 by one to advance the waveform.

[0075] If CPU 101 determines in step S12 that L has reached the target value, it ends the process. If it determines that L has not reached the target value, it repeats the process while adding rate r to L until it reaches the target value.

[0076] In step S7 or step S9, if g<0 or 1-g<0, a carry has occurred in the number of delay elements k, which is the integer part of the delay length. In this case, the CPU 101 sets g=0 in step S13.

[0077] In this state, the CPU 101 executes all-pass filter calculations of the APF 305(#0), APF 305(#1), and APF 305(#2) in step S14. In this case, the APF 305(#1) executes calculations with the number of delay elements k and the filter coefficient 0, and the APF 305(#2) executes calculations with the number of delay elements k+1 and the filter coefficient 1. Since the APF 305(#2) starts calculations with the feedback delay element value 0, the signal i20 is output as is due to the nature of the all-pass filter. On the other hand, since the APF 305(#1) executes calculations with g=0, the signal i11 is output as is. The signals i20 and i11 are the same. Therefore, at this timing, the signals output to the output selection terminals o1 and o2 are equal. Therefore, even if the switch 310 switches the output selection terminal from o1 to o2 in step S16, no noise is generated.

[0078] After that, in step S15, the CPU 101 executes the same sample update as in step S11.

[0079] Next, the CPU 101 switches the switch 310 to the output selection terminal o2.

[0080] Thereafter, in step S17, the CPU 101 clears the data stored in the feedback delay unit 307(#0) of the APF 305(#0) to 0.

[0081] Thereafter, in step S18, the CPU 101 reconnects the input switches i00 and i01 of the APF 305(#0) to the delay line switch terminals dk+2 and dk+3, respectively, and changes the filter coefficient g0 of the APF 305(#0) from 0 to 1.

[0082] The state of the waveguide model calculation unit 202 after the connection of the APF 305 (#0) is switched is as described above in Fig. 6. The process of step S18 is equivalent to the task of incrementing the number of delay units k, which is the integer part of the delay length, by +1. In the figure, "++" indicates an increment calculation of +1.

[0083] After the process of step S18, the CPU 101 returns to the process of step S2 and repeats the operation of increasing the delay length. At this time, the APF 305(#2) becomes the object for changing the filter coefficient. Thereafter, each time the delay element number k is incremented, the APF 305(#0), the APF 305(#1), and the APF 305(#2) successively become the objects for calculating the filter coefficient in ascending order of the loop.

[0084] In step S1 of FIG. 9, when L1 > L2, that is, when it is a bend-up, the processes after step S19 in the flowchart of FIG. 10 are executed. When L1 > L2, there are the following differences compared with the case where L1 < L2.

[0085] First, in step S19, the CPU 101 subtracts the rate r from the fractional part l. In the figure, "-=" represents an operation of subtracting the variable value on the right side from the variable value on the left side.

[0086] Also, in step S24 or step S26, it is determined whether or not the delay element number k, which is the integer part of the delay length, undergoes a carry-over depending on whether g > 1 or 1 - g > 1.

[0087] When it is determined that g > 1 or 1 - g > 1, it is the case where the delay element number k undergoes a carry-over. In this case, in step S30, the CPU 101 sets g = 1.

[0088] The CPU 101 further executes each operation and sample update of the APF 305(#0), the APF 305(#1), and the APF 305(#2) in steps S31 and S32. In the subsequent state, the APF 305(#1) is operated with the filter coefficient g = 1, and although there is some influence of feedback, the signal of i10 is output almost as it is. Since the APF 305(#0) continues to operate with the filter coefficient 0, the value of i01 is output as it is. The signals of i10 and i01 are almost the same. Therefore, even if the output selection terminal is switched from o1 to o0 at the switch 310 in step S33, no noise is generated.

[0089] In step S33, the CPU 101 switches the switch 310 to the output selection terminal o0.

[0090] Thereafter, in step S34, the CPU 101 clears the data stored in the feedback delay unit 307(#2) of the APF 305(#2) to 0.

[0091] Thereafter, in step S35, the CPU 101 connects (sets) the connection terminals i20 and i21 of the APF 305 (#2) to the delay line switch terminals dk-2 and dk-1, respectively.

[0092] The state of the waveguide model calculation unit 202 after the connection of the APF 305 (#2) is switched is as described above in Fig. 8. The process of step S35 is equivalent to decrementing the number of delay units k, which is the integer part of the delay length, by -1. In the figure, "--" indicates a decrement operation of -1.

[0093] After the process of step S35, the CPU 101 returns to the process of step S19 and repeats the task of decreasing the delay length. At this time, the APF 305(#0) becomes the target for changing the filter coefficient. Thereafter, the APF 305(#0), APF 305(#1), and APF 305(#2) become the targets for calculating the filter coefficient in descending order of the loop each time the number of delay elements k is decremented.

[0094] In the pitch change process in which the delay length is reduced, as explained in step S35 of Fig. 10, the filter coefficient of APF 305 is set to 0 and the connection is changed, and if the rate r is sufficiently small, the calculation is started with the filter coefficient small, so that even if the feedback side value is indefinite (discontinuous), the noise that appears in the next sample is small. Therefore, as a modification of this embodiment, as shown in Fig. 11, APF 305(#1) and APF 305(#2) are calculated in a state in which APF 305(#0) is removed, and in step S18 of Fig. 9, APF 305(#1) is changed instead of APF 305(#0), and in step S35 of Fig. 10, APF 305(#2) is changed to delay line switch terminals dk-1 and dk, and the influence of noise is small and the number of delay units can be changed. In this case, the number of multiplications can be reduced by two.

[0095] 5, it has been explained that the number of multiplications can be reduced in APF 305(#0) and APF 305(#2), but multiplication calculations may be left in place if priority is given to uniformity of algorithms and hardware. The final output signal y(n) is connected to o1 when no pitch bend occurs during sound production. In this case, the output signals of APF 305(#0) and APF 305(#2) are not output from output selection terminals o0 and o2, but are calculated and prepared in case the aforementioned pitch bend occurs during sound production.

[0096] As described above, in this embodiment, by previously connecting a plurality of APFs 305 to adjacent delay elements 302 in the delay line 301, it is possible to prevent indefinite data from entering the delay elements 302 and suppress noise that occurs when the number of delay elements 302 changes while the waveguide model is generating sound. Also, in this embodiment, it is possible to reduce the number of multiplications in the two APFs 305 other than the APF 305 connected to the first delay element.

[0097] In this way, according to this embodiment, by using a fractional delay block such as an all-pass filter in a waveguide modeling sound source, it is possible to eliminate the frequency dependency of the amplitude and suppress the generation of noise when the number of delayer connections changes with a small amount of calculation. Specifically, it has an advantage in that the number of multiplications is reduced by up to four per waveguide model. For example, a piano has about 230 strings, so if all the strings are modeled and operated, the number of multiplications is reduced by 920.

[0098] Furthermore, according to this embodiment, since the filter coefficients can be changed continuously, it becomes possible to easily apply envelope control to the filter coefficients.

[0099] The block diagrams shown in the drawings described above can be replaced by software. For example, when the entire configuration of FIG. 3 is replaced by software, the processor calculates and outputs filter coefficients from a formula that derives the delay widths of the 0th to 2nd delay units and the respective APFs 305 (#0 to #2), and calculates a waveform using the filter coefficient of the first delay unit and APF 305 (#1) pair among them, and applies the waveform to the output, thereby realizing software processing. 6, the processor periodically outputs filter coefficients from a formula deriving the delay width of the 0th to 2nd delay units and the respective APFs 305 (#0 to #2) before switching, and when the filter coefficient corresponding to APF 305 (#1) among them exceeds a predetermined range, it regards it as switching, and after switching, it outputs filter coefficients from a formula deriving the delay width of the new 0th to 2nd delay units and the respective APFs 305 (#0 to #2), and calculates a waveform using the filter coefficient of the new first delay unit and APF 305 (#1) pair among them, and applies it to the output, thereby realizing software processing. Furthermore, it is also possible to combine an embodiment using a circuit with software and replace part of the circuit with software.

[0100] In the above embodiment, the control program is stored in the ROM 102, but the present invention is not limited to this and may be stored in a removable storage medium such as a USB memory, a CD, a DVD, or a server. The musical sound signal generating device 100 may obtain the control program from such a storage medium, or may obtain the control program from a server via a network.

[0101] Furthermore, the number of all-pass filters shown in the above embodiment is not limited to three, and four or more may be provided.

[0102] In addition, the present invention is not limited to the above-mentioned embodiment, and various modifications can be made in the implementation stage without departing from the gist of the invention. In addition, the functions executed in the above-mentioned embodiment may be implemented in appropriate combinations as much as possible. The above-mentioned embodiment includes various steps, and various inventions can be extracted by appropriate combinations of the multiple components disclosed. For example, if an effect can be obtained even if some components are deleted from all the components shown in the embodiment, the configuration from which the components are deleted can be extracted as an invention.

[0103] The following supplementary notes are further disclosed regarding the above-described embodiment. (Appendix 1) a delay line including a plurality of delay devices connected in cascade, each delaying an input signal by a first delay width; At least three fractional delay blocks, each of which is connected to one of the plurality of delay units, delaying an input signal by a second delay width that is equal to or shorter than the first delay width; at least one processor that sets any one of the plurality of delay units as a first delay unit that generates a delay corresponding to a designated pitch, sets a delay unit preceding the first delay unit among the plurality of delay units as a 0th delay unit, and sets a delay unit following the first delay unit among the plurality of delay units as a second delay unit; Equipped with The at least one processor: The at least three fractional delay blocks are respectively connected to the first delay unit, the zero delay unit, and the second delay unit; a delay unit connected to the first delay unit as a new zeroth delay unit, and a delay unit connected to the second delay unit as a new second delay unit in response to a change in the designated pitch; wherein the delay unit connected before the new first delay unit is set to a new zeroth delay unit, and a delay unit connected after the new first delay unit is set to a new second delay unit, the musical tone signal generating device keeps the zeroth delay unit connected to the fractional part delay block, and reconnects at least one of the new zeroth delay unit and the new second delay unit to at least one of the fractional part delay blocks other than the fractional part delay block connected to the new first delay unit. (Appendix 2) The at least three fractional delay blocks each operate as an all-pass filter block together with the corresponding delay. 2. A musical sound signal generating device according to claim 1. (Appendix 3) The at least one processor: A filter coefficient corresponding to the second delay width, which is a fractional part of the delay width corresponding to the designated pitch, is set in the all-pass filter block, which is the fractional part delay block corresponding to the first delay device; setting filter coefficients of values ​​0 and 1 corresponding to the second delay width of values ​​1 and 0, respectively, in the all-pass filter block which is the fractional part delay block corresponding to the 0th delay unit and the all-pass filter block which is the fractional part delay block corresponding to the second delay unit; An output of the all-pass filter block, which is the fractional part delay block corresponding to the first delay device, is output as a musical tone signal and a feedback signal to the input of the delay line. 3. A musical sound signal generating device according to claim 2. (Appendix 4) The at least one processor: When the decimal part of the delay length is l, if the first delay unit is an even-numbered or odd-numbered delay unit, g = (1 - l) / (1 + l) (1) The coefficient g calculated by the above-mentioned arithmetic expression is set as a filter coefficient corresponding to the second delay width, which is a decimal part of the delay width corresponding to the designated pitch, and when the first delay element is an odd-numbered or even-numbered delay element, g = 2 × l / (1 + l) (2) A coefficient (1-g) calculated using a coefficient g calculated by the following formula is set as the filter coefficient, The delay length is input to an envelope generator block that outputs a coefficient g that changes as shown in the formula (1) or (2) as an envelope value. 2. A musical sound signal generating device according to claim 1. (Appendix 5) The fractional part delay block to which both ends of the zeroth delay element are connected performs an operation of outputting the output of the zeroth delay element as is, The fractional part delay block to which both ends of the second delay unit are connected executes an operation of outputting an input value in each multiplication operation as it is or with its sign changed as an output value in each multiplication operation, instead of multiplying a value 1 or a value −1 corresponding to a filter coefficient of a value 1 corresponding to the second delay width of a value 0. 2. A musical sound signal generating device according to claim 1. (Appendix 6) A musical sound signal generating device according to claim 1; An operator; Electronic equipment equipped with (Appendix 7) At least three fractional delay blocks, each of which is connected in cascade to a delay line having a plurality of delay units that delay an input signal by a first delay width, are connected to a first delay unit among the plurality of delay units, the first delay unit being a delay unit that generates a delay corresponding to a designated pitch, a zeroth delay unit among the plurality of delay units corresponding to a stage preceding the first delay unit, and a second delay unit among the plurality of delay units corresponding to a stage succeeding the first delay unit; a delay unit preceding the new first delay unit as a new zeroth delay unit, and a delay unit following the new first delay unit as a new second delay unit in response to a change in the designated pitch; wherein the delay unit continuing to be connected to the zeroth delay unit or the second delay unit is connected to the fractional part delay block, and at least one of the new zeroth delay unit or the new second delay unit is reconnected to at least one of the fractional part delay blocks other than the fractional part delay block connected to the new first delay unit. (Appendix 8) On the computer, a process of connecting at least three fractional delay blocks, each of which is connected in cascade to one of the delay units of a delay line having a plurality of delay units that delay an input signal by a first delay width, to a first delay unit among the plurality of delay units that generates a delay corresponding to a designated pitch, a zeroth delay unit among the plurality of delay units that corresponds to the previous stage of the first delay unit, and a second delay unit among the plurality of delay units that corresponds to the subsequent stage of the first delay unit; a process of setting one of the connected zeroth delay unit and the connected second delay unit as a new first delay unit in response to a change in the designated pitch, setting the delay unit preceding the new first delay unit as a new zeroth delay unit, and setting the delay unit following the new first delay unit as a new second delay unit, keeping one of the connected zeroth delay unit and the connected second delay unit connected to the fractional part delay block, and reconnecting at least one of the new zeroth delay unit and the new second delay unit to at least one of the fractional part delay blocks other than the fractional part delay block connected to the new first delay unit. [Explanation of symbols]

[0104] 100 Musical tone signal generator 101 CPU 102 ROM 103 RAM 104 DSP or Waveguide Model Circuit 105 ADC or digital input ports 106 ADC 107 Digital Input Port 108 DAC / Amplifier 109 Volume Sensor 110 Pitch Bend Sensor 111 Pitch switch 201 Waveguide model control section 202 Waveguide model calculation section 203 Pitch information 204 Bend Information 205 Volume information 206 Excitation Source 207 Volume 208, 304, 306, 308 multipliers 209 Musical Signal 301 Delay Line 302 Delay Unit 303 Feedback Signal 307 Feedback Delay 309, 311 Adder 310 Switch

Claims

1. a delay line including a plurality of delay devices connected in cascade, each delaying an input signal by a first delay width; a plurality of fractional part delay blocks each corresponding to and connected to one of the plurality of delay units, thereby delaying an input signal by a second delay width that is equal to or shorter than the first delay width; Switch, at least one processor that sets any one of the plurality of delay units as a first delay unit that generates a delay corresponding to a designated pitch, sets a delay unit preceding the first delay unit among the plurality of delay units as a 0th delay unit, and sets a delay unit following the first delay unit among the plurality of delay units as a second delay unit; Equipped with the plurality of fractional delay blocks comprises a first fractional delay block and a second fractional delay block; The at least one processor the first fractional delay block and the second fractional delay block are connected to the first delay unit and the second delay unit, respectively; In response to the change in the designated pitch, when the second delay unit connected is set as a new first delay unit, the delay unit preceding the new first delay unit is set as a new 0th delay unit, and the delay unit following the new first delay unit is set as a new second delay unit, the second delay unit connected is kept connected to the second fractional part delay block, and the new second delay unit is reconnected to the first fractional part delay block; In response to a change in the designated pitch, when the zeroth delay unit connected is set as a new first delay unit, the preceding delay unit of the new first delay unit is set as a new zeroth delay unit, and the succeeding delay unit of the new first delay unit is set as a new second delay unit, the first delay unit connected is kept connected to the first fractional part delay block, and the new first delay unit is reconnected to the second fractional part delay block; the switch exclusively outputs an output signal from either the first fractional part delay block or the second fractional part delay block. A musical tone signal generator.

2. The plurality of fractional delay blocks each operate as an all-pass filter block together with the corresponding delay unit.

2. The musical tone signal generating apparatus according to claim 1.

3. When the at least one processor sets the second delay unit connected as the new first delay unit, sets the previous delay unit of the new first delay unit as the new 0th delay unit, and sets the next delay unit of the new first delay unit as the new second delay unit in response to a change in the designated pitch, the switch outputs an output from the second fractional part delay block as a musical tone signal and a feedback signal to an input of the delay line; When the at least one processor sets the connected 0th delay unit as the new 1st delay unit, sets the preceding delay unit of the new 1st delay unit as the new 0th delay unit, and sets the subsequent delay unit of the new 1st delay unit as the new 2nd delay unit in response to a change in the designated pitch, the switch outputs an output from the first fractional part delay block as a musical tone signal and a feedback signal to the input of the delay line.

2. The musical tone signal generating apparatus according to claim 1.

4. A musical tone signal generating device according to claim 1, An operator; Electronic equipment equipped with

5. a first fractional part delay block and a second fractional part delay block of a plurality of fractional part delay blocks, each of which is connected in cascade to a delay line having a plurality of delay units that delay an input signal by a first delay width, and which delay an input signal by a second delay width that is equal to or shorter than the first delay width, are connected to a first delay unit among the plurality of delay units, which is a delay unit that generates a delay corresponding to a specified pitch, and to a second delay unit among the plurality of delay units, which corresponds to a stage subsequent to the first delay unit; In response to the change in the designated pitch, when the second delay unit connected is set as a new first delay unit, the delay unit preceding the new first delay unit is set as a new 0th delay unit, and the delay unit following the new first delay unit is set as a new second delay unit, the second delay unit connected is kept connected to the second fractional part delay block, and the new second delay unit is reconnected to the first fractional part delay block; a 0th delay unit which is a delay unit preceding the first delay unit which is connected, set as a new first delay unit, a delay unit preceding the new first delay unit as a new 0th delay unit, and a delay unit following the new first delay unit as a new second delay unit in response to a change in the designated pitch, the first delay unit which is connected is kept connected to the first fractional part delay block, and the new first delay unit is reconnected to the second fractional part delay block, and an output signal from either the first fractional part delay block or the second fractional part delay block is exclusively output by a switch.

6. On the computer, a process of connecting a first fractional part delay block and a second fractional part delay block of a plurality of fractional part delay blocks, each of which is connected in a cascade to one of the delay units of a delay line having a plurality of delay units that delay an input signal by a first delay width, to a first delay unit among the plurality of delay units that generates a delay corresponding to a specified pitch, and to a second delay unit among the plurality of delay units that corresponds to a stage subsequent to the first delay unit; a process of setting the connected second delay unit as a new first delay unit, setting the previous stage of the new first delay unit as a new 0th delay unit, and setting the next stage of the new first delay unit as a new second delay unit in response to a change in the designated pitch, the process of keeping the connected second delay unit connected to the second fractional part delay block and reconnecting the new second delay unit to the first fractional part delay block; a process of setting a zeroth delay unit, which is a delay unit preceding the first delay unit connected, as a new first delay unit, setting a delay unit preceding the new first delay unit as a new zeroth delay unit, and setting a delay unit following the new first delay unit as a new second delay unit, in response to a change in the designated pitch, keeping the first delay unit connected to the first fractional part delay block and reconnecting the new first delay unit to the second fractional part delay block; a process of exclusively outputting an output signal from either the first fractional part delay block or the second fractional part delay block by a switch.

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