PIXEL DRIVE CIRCUIT AND DISPLAY PANEL

Abstract

In the present application, a pixel driving circuit and a display panel are provided. 100 in a reset stage, the bootstrap capacitor C2 is charged through the pre-charge loop L1 so that the voltage at the first end of the bootstrap capacitor C2 reaches the value of the driving voltage; in a data write stage, the data voltage is received through the bootstrap capacitor C2, and the energy storage capacitor C1 is charged through the bootstrap capacitor C2, thereby adjusting the voltage at the control end of the driving transistor M to a second voltage; in an emission stage, the driving transistor M drives the light emitting element OLED to emit light according to the second voltage and the driving voltage, thereby eliminating uneven display brightness.

Description

[Technical field]

[0001] REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 202210898918.7, filed on July 28, 2022, for the invention titled "Pixel Driving Circuit and Display Panel," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of display technology, and in particular to pixel driving circuits and display panels. [Background technology]

[0003] The statements herein provide only background information pertaining to the present application and do not necessarily constitute a prior art. Organic Light-Emitting Diode (OLED) displays have advantages such as low power consumption, fast response speed, and wide viewing angle, and are therefore becoming more widely used. In an OLED array of an OLED display, each OLED is provided with a corresponding pixel driving circuit. The pixel driving circuit is usually composed of a plurality of thin film transistors (TFTs). However, the parameters of the TFTs in different pixel driving circuits are different. For example, the threshold voltage Vth (i.e., the bias voltage between the gate and source that causes the TFT to be in a critical off state or a critical on state), the mobility, etc. are different. Therefore, the brightness of the light emitted by different OLEDs differs, and the difference is perceived by the human eye. This phenomenon is called the mura phenomenon. The mura phenomenon reduces the display performance of a display device.

[0004] In the prior art, in order to improve the display brightness unevenness caused by the difference in the threshold voltage of the TFT of different pixel driving circuits, pixel driving circuits with compensation functions such as 6T (transistor) 1C (capacitor), 7T1C, 8T1C, etc. are usually designed so that the pixel driving circuits are operated in the reset stage, the data writing stage, and the light emitting stage in sequence. In the conventional pixel driving circuit, after the TFT threshold voltage Vth is compensated in the data writing stage, the display brightness of the OLED correlates with the data voltage Vdata and the driving voltage VDD but does not correlate with the TFT threshold voltage Vth. However, since the power line for transmitting the driving voltage VDD itself has impedance, the driving voltage VDD received by the pixel driving circuits with different distances from the power chip is different. As a result, the display brightness of the OLEDs with different distances from the power chip is different, and the unevenness phenomenon cannot be thoroughly solved and becomes more prominent as the OLED display becomes larger, greatly affecting the visual experience of the user. Summary of the Invention

[0005] In the present application, a pixel driving circuit is provided. The pixel driving circuit is configured to drive the light emission of a light emitting element, and a first end of the light emitting element is configured to receive a reference voltage, and the pixel driving circuit operates in a reset stage, a data writing stage and a light emitting stage in a display period of one frame in sequence, and the pixel driving circuit includes a driving transistor, an energy storage capacitor, an energy storage capacitor reset loop, a bootstrap capacitor, a pre-charge loop, a data writing loop and a light emitting loop. The driving transistor has a control end, a first connection end and a second connection end, the first connection end is configured to receive a driving voltage, and the second connection end is electrically connected to a second end of the light emitting element. The first end of the energy storage capacitor is electrically connected to the control end of the driving transistor, and the second end of the energy storage capacitor is configured to receive a first voltage having a constant voltage value. The energy storage capacitor reset loop is configured to be turned on in the reset stage, receive a first reset voltage, and reset the voltage of the first end of the energy storage capacitor so that the voltage of the first end of the energy storage capacitor reaches a value of the first reset voltage. The first end of the bootstrap capacitor is electrically connected to the first connection end of the driving transistor, and the second end of the bootstrap capacitor is configured to receive a voltage of zero potential in a reset phase and a data voltage in a data write phase. The pre-charge loop is configured to turn on in the reset phase and receive a driving voltage to charge the bootstrap capacitor, thereby adjusting the voltage of the first end of the bootstrap capacitor so that the voltage of the first end of the bootstrap capacitor reaches a value of the driving voltage, and reset the voltage of the second end of the bootstrap capacitor so that the voltage of the second end of the bootstrap capacitor reaches a value of zero potential, thereby making the difference between the voltage of the first end and the voltage of the second end of the bootstrap capacitor reach a value of the driving voltage.The data write loop includes a bootstrap capacitor, a driving transistor and an energy storage capacitor connected in series, the data write loop is configured to be turned on in a data write phase, receive a data voltage at a second end of the bootstrap capacitor, and charge the energy storage capacitor according to the bootstrap effect of the bootstrap capacitor, thereby adjusting the voltage of the control end of the driving transistor so that the voltage of the control end of the driving transistor reaches a second voltage value from a first reset voltage value, and the driving transistor is in a critical on state when the voltage of its control end is equal to the second voltage, and the second voltage is equal to the sum of the driving voltage, the data voltage and the threshold voltage of the driving transistor. The light emitting loop includes a driving transistor and a light emitting element connected in series, the light emitting loop is configured to be turned on in a light emitting phase, receive a driving voltage at a first connection end of the driving transistor, and drive the light emitting element to emit light.

[0006] The pixel driving circuit provided in the present application charges the bootstrap capacitor through a pre-charge loop in a reset stage, so that the voltage of the first end of the bootstrap capacitor reaches the value of the driving voltage; receives a data voltage through a second end of the bootstrap capacitor, and charges an energy storage capacitor according to the bootstrap effect of the bootstrap capacitor, thereby adjusting the voltage of the control end of the driving transistor to a second voltage, the voltage value of which is equal to the sum of the driving voltage, the data voltage and the threshold voltage of the driving transistor; and drives the light emitting element to emit light according to the second voltage received at its control end and the driving voltage received at its first connection end in the light emitting stage, so that the current flowing through the light emitting element is not correlated with the driving voltage and the threshold voltage of the driving transistor, thereby not only eliminating the display brightness unevenness of the display panel caused by the difference in the threshold voltage of the driving transistor in different pixel driving circuits, but also eliminating the display brightness unevenness of the display panel caused by the difference in the driving voltage received by different pixel driving circuits.

[0007] The present application further provides a display panel. The display panel includes a substrate and several pixel driving circuits, the substrate having a display area, and the several pixel driving circuits are arranged in an array in the display area of ​​the substrate. The pixel driving circuit is configured to drive the light emitting element to emit light, and a first end of the light emitting element is configured to receive a reference voltage, and the pixel driving circuit operates in a reset stage, a data writing stage and an emission stage in turn in one frame display period, and the pixel driving circuit includes a driving transistor, an energy storage capacitor, an energy storage capacitor reset loop, a bootstrap capacitor, a pre-charge loop, a data writing loop and an emission loop. The driving transistor has a control end, a first connection end and a second connection end, the first connection end is configured to receive a driving voltage, and the second connection end is electrically connected to the second end of the light emitting element. The first end of the energy storage capacitor is electrically connected to the control end of the driving transistor, and the second end of the energy storage capacitor is configured to receive a first voltage having a constant voltage value. The energy storage capacitor reset loop is configured to be turned on in a reset phase and receive a first reset voltage to reset the voltage of the first end of the energy storage capacitor so that the voltage of the first end of the energy storage capacitor reaches a value of the first reset voltage. The first end of the bootstrap capacitor is electrically connected to the first connection end of the drive transistor, and the second end of the bootstrap capacitor is configured to receive a voltage of zero potential in the reset phase and receive a data voltage in the data write phase. The precharge loop is configured to be turned on in a reset phase and receive a drive voltage to charge the bootstrap capacitor, thereby adjusting the voltage of the first end of the bootstrap capacitor so that the voltage of the first end of the bootstrap capacitor reaches a value of the drive voltage, and reset the voltage of the second end of the bootstrap capacitor so that the voltage of the second end of the bootstrap capacitor reaches a value of zero potential, thereby making the difference between the voltage of the first end and the voltage of the second end of the bootstrap capacitor reach a value of the drive voltage.The data write loop includes a bootstrap capacitor, a driving transistor and an energy storage capacitor connected in series, the data write loop is configured to be turned on in a data write phase, receive a data voltage at a second end of the bootstrap capacitor, and charge the energy storage capacitor according to the bootstrap effect of the bootstrap capacitor, thereby adjusting the voltage of the control end of the driving transistor so that the voltage of the control end of the driving transistor reaches a second voltage value from a first reset voltage value, and the driving transistor is in a critical on state when the voltage of its control end is equal to the second voltage, and the second voltage is equal to the sum of the driving voltage, the data voltage and the threshold voltage of the driving transistor. The light emitting loop includes a driving transistor and a light emitting element connected in series, the light emitting loop is configured to be turned on in a light emitting phase, receive a driving voltage at a first connection end of the driving transistor, and drive the light emitting element to emit light.

[0008] Additional aspects and advantages of the present application will be set forth in part in the description that follows, and in part will be apparent from the description, or may be learned by practice of the present application. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram showing the configuration of a panel according to an embodiment of the present application. [Diagram 2] FIG. 2 is a schematic diagram showing a configuration of a conventional pixel driving circuit. [Diagram 3] FIG. 3 is a schematic diagram showing a configuration of a pixel driving circuit according to an embodiment of the present application. [Figure 4] FIG. 4 is a timing chart showing the operation of the pixel driving circuit shown in FIG. [Figure 5a] FIG. 5a is a circuit schematic diagram of the pixel driving circuit shown in FIG. 3 at stage A. [Figure 5b] FIG. 5b is a circuit schematic diagram of the pixel driving circuit shown in FIG. 3 at stage B. [Figure 5c]FIG. 5c is a circuit schematic diagram of the pixel driving circuit shown in FIG. 3 at stage C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the technical solutions of the embodiments of the present application will be described clearly and comprehensively with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments that a person skilled in the art can obtain without creative efforts all belong to the protection scope of the present application.

[0011] In the description of this application, the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", etc. are directions or positional relationships indicated based on the drawings, and are merely for the purpose of explaining and simplifying the description of this application, and are not intended to indicate or imply that the indicated devices or elements necessarily have a specific orientation, are constructed or operate in a specific direction, and therefore cannot be understood as limitations on this application. In addition, the terms "first", "second", etc. are used for explanation purposes only, and cannot be understood as indicating or implying relative importance.

[0012] Referring to FIG. 1, the present application provides a display panel 1, which includes a substrate 1000 and a main driving circuit 2000 electrically connected to each other, and the substrate 1000 has a display area 1001 and a non-display area 1002. In the display area 1001, several pixel driving circuits 100 are arranged in an array. The main driving circuit 2000 includes a scan signal generating module 110, a data voltage generating module 120, and a driving voltage generating module 130. The scan signal generating module 110 is separately electrically connected to a plurality of rows of pixel driving circuits 100 via a plurality of scan lines 111, and is configured to generate a scan signal corresponding to the pixel driving circuits 100 of each row. The data voltage generating module 120 is separately electrically connected to a plurality of columns of pixel driving circuits 100 via a plurality of data lines 121, and is configured to generate a data voltage Vdata corresponding to the pixel driving circuits 100 of each column. The driving voltage generation module 130 is electrically connected to the multiple rows of pixel driving circuits 100 separately via multiple power supply voltage lines 131, and is configured to generate a driving voltage VDD for the pixel driving circuits 100 of each row.

[0013] 2, which shows a conventional pixel driving circuit 100' having a 2T (transistor) 1C (capacitor) configuration. The pixel driving circuit 100' includes a scan transistor T0, a driving transistor M, an energy storage capacitor C and a light emitting element.

[0014] The pixel driving circuit 100' is configured to drive the light emission of the light-emitting element. In an embodiment of the present application, the light-emitting element is an organic light-emitting diode (OLED), a first end of the light-emitting element corresponds to the cathode of the OLED, and a second end of the light-emitting element corresponds to the anode of the OLED. In another embodiment, the light-emitting element may be a light-emitting diode (LED), a micro LED (MicroLED), or a mini LED (MiniLED). The cathode of the light-emitting element OLED is electrically connected to a reference voltage terminal and configured to receive a reference voltage Vss. The source of the driving transistor M is electrically connected to the power supply voltage line 131 and configured to receive a driving voltage VDD, the drain of the driving transistor M is electrically connected to the anode of the light-emitting element OLED, and the gate of the driving transistor M is electrically connected to the drain of the scanning transistor T0. The source of the scanning transistor T0 is electrically connected to the data line 121 and configured to receive a data voltage Vdata. The gate of the scanning transistor T0 is electrically connected to the scanning line 111 and configured to receive a scanning signal. The first end of the energy storage capacitor C is electrically connected to the gate of the driving transistor M, and the second end of the energy storage capacitor C is electrically connected to the cathode of the light-emitting element OLED. For example, when the scanning signal is an on signal, the scanning transistor T0 is turned on, and the data voltage Vdata on the data line 121 charges the energy storage capacitor C through the scanning transistor T0, thereby adjusting the voltage of the first end of the energy storage capacitor C so that the voltage of the first end of the energy storage capacitor C reaches the value of the data voltage Vdata, and the driving transistor M drives the light emission of the light-emitting element OLED based on the data voltage Vdata received at its gate and the driving voltage VDD received at its source. At this time, the gate-source voltage Vgs of the driving transistor M=Vg-Vs=Vdata-VDD. The following relationship exists between the current Ids flowing through the light-emitting element OLED and the gate-source voltage Vgs of the driving transistor M. [Formula 1] Ids = (K / 2) (Vgs - Vth) 2 =(K / 2)(Vdata-VDD-Vth) 2

[0015] K=Cox×μ×W / L, where Cox is the gate capacitance per unit area, μ is the electron mobility in the channel, W / L is the width-to-length ratio of the channel of the drive transistor M, and Vth is the threshold voltage of the drive transistor M.

[0016] The luminance of the light-emitting element OLED is directly proportional to the current Ids flowing through the light-emitting element OLED, that is, correlated with the data voltage Vdata, the driving voltage VDD, and the threshold voltage Vth of the driving transistor M. In order to avoid uneven display luminance of the display panel caused by the difference in the threshold voltage Vth of the different driving transistors M, in the conventional display panel, the pixel driving circuit 100' is designed as a driving circuit (not shown) having a threshold compensation function. Therefore, the driving circuit operates in the reset stage, the data writing stage, and the light-emitting stage in sequence, and charges the energy storage capacitor C in the data writing stage to adjust the voltage of its first end so that the voltage of its first end reaches a value of (Vdata+Vth). At this time, the gate-source voltage Vgs of the driving transistor M=Vg-Vs=(Vdata+Vth)-VDD. The relationship between the current Ids flowing through the light-emitting element OLED and the gate-source voltage Vgs of the driving transistor M satisfies the following mathematical formula. [Formula 2] Ids = (K / 2) (Vgs - Vth) 2 =(K / 2)(Vdata-VDD) 2

[0017] As is clear from the above formula, the luminance of the light emitting element OLED is correlated with the data voltage Vdata and the driving voltage VDD, but is not correlated with the threshold voltage Vth of the driving transistor M. This can eliminate the unevenness in the display luminance of the display panel 1 caused by the difference in the threshold voltage Vth of the different driving transistors M. However, since the power supply voltage line 131 for transmitting the driving voltage VDD itself has a line impedance, the driving voltage VDD received by the pixel driving circuit 100 having a different distance from the driving voltage generating module 130 is different. Therefore, the unevenness phenomenon cannot be thoroughly solved due to the difference in the display luminance between the light emitting element OLED having a different distance from the driving voltage generating module 130, and becomes more prominent as the display panel 1 becomes larger, which greatly affects the visual experience of the user.

[0018] Referring to FIG. 3, in order to eliminate uneven display luminance of the display panel 1 caused by the line impedance of the power supply voltage line 131 in the conventional pixel driving circuit, the present application provides a pixel driving circuit 100 for driving the emission of the light emitting element OLED.

[0019] The pixel driving circuit 100 includes an energy storage capacitor C1, a bootstrap capacitor C2, a driving transistor M, a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, a fifth switching transistor T5 and a sixth switching transistor T6. The control ends of the switching transistors T1 to T6 (i.e., the switching transistors T1, T2, T3, T4, T5, and T6) are electrically connected to the scanning signal generating module 110, and the switching transistors T1 to T6 can be at least one of a triode or a metal oxide semiconductor (MOS) transistor. In this embodiment, the switching transistors T1 to T6 and the driving transistor M are both low-level on transistors such as P-channel metal oxide semiconductor (PMOS) transistors. In another embodiment, the switching transistors T1 to T6 and the driving transistor M are all high-level-on transistors such as N-channel metal-oxide semiconductor (NMOS) transistors. It is understood that designing the switching transistors T1 to T6 as the same type of transistor is advantageous for simplifying the manufacturing process of the substrate 1000, reducing the difficulty of processing, and reducing the production cost. Of course, in another embodiment, the switching transistors T1 to T6 and the driving transistor M can also adopt different types of transistors, and are not limited here.In addition, the switching transistors T1 to T6 and the driving transistor M in the present application can be amorphous silicon thin film transistors (a-Si TFTs), low-temperature polysilicon thin film transistors (LTPS TFTs), or oxide semiconductor thin film transistors (Oxide TFTs). Among these, an oxide semiconductor (Oxide) such as indium gallium zinc oxide (IGZO) can be used as the active layer of the oxide TFT. Exemplarily, the switching transistors T1 to T6 are oxide TFTs, and the driving transistor M is a low-temperature polysilicon transistor. The high mobility of the low-temperature polysilicon transistor can improve the speed at which the driving transistor M is turned on, which in turn improves the response speed of the pixel driving circuit 100, and the display effect of the display panel 1 can be improved.

[0020] To more clearly explain the circuit configuration and operation principle of the pixel driving circuit 100, please also refer to FIG. 4 and FIG. 5a to FIG. 5c.

[0021] As shown in FIG. 4, the pixel driving circuit 100 operates in a reset stage (stage A), a data writing stage (stage B), and a light emitting stage (stage C) in that order during a display period of one frame.

[0022] As shown in FIG. 5a, the pixel driving circuit 100 includes a pre-charge loop L1 and an energy storage capacitor reset loop L2. Precharge Loop L1The switching element includes a first switching transistor T1, a bootstrap capacitor C2, and a second switching transistor T2, which are connected in series in this order. A first connection terminal of the first switching transistor T1 is configured to receive a driving voltage VDD, and a second connection terminal of the first switching transistor T1 is electrically connected to a first terminal of the bootstrap capacitor C2. A first connection terminal of the second switching transistor T2 is electrically connected to the ground terminal and configured to receive a voltage of zero potential, and a second connection terminal of the second switching transistor T2 is electrically connected to a second terminal of the bootstrap capacitor C2. The precharge loop L1 is turned on in the reset stage (i.e., the first switching transistor T1 and the second switching transistor T2 are both turned on) to receive the driving voltage VDD and charge the bootstrap capacitor C2, thereby adjusting the voltage at the first end of the bootstrap capacitor C2 so that the voltage at the first end of the bootstrap capacitor C2 reaches the value of the driving voltage VDD, and resetting the voltage at the second end of the bootstrap capacitor C2 so that the voltage at the second end of the bootstrap capacitor C2 reaches zero potential, thereby making the difference between the voltage at the first end and the voltage at the second end of the bootstrap capacitor C2 reach the value of the driving voltage VDD. Thus, the bootstrap capacitor C2 can discharge the residual charge of the display period of the previous frame to the ground end through the second switching transistor T2, and reset the voltage at the second end of the bootstrap capacitor C2 so that the voltage at the second end of the bootstrap capacitor C2 reaches zero potential, thereby ensuring the uniformity of the display effect of the display panel 1.

[0023] The energy storage capacitor reset loop L2 includes an energy storage capacitor C1 and a sixth switching transistor T6 connected in series. A first connection end of the sixth switching transistor T6 is configured to receive a first reset voltage, and a second connection end of the sixth switching transistor T6 is electrically connected to a first end of the energy storage capacitor C1. The first end of the energy storage capacitor C1 is further electrically connected to a control end (i.e., gate g) of the driving transistor M. A second end of the energy storage capacitor C1 is configured to receive a first voltage V1 having a constant voltage value. The energy storage capacitor reset loop L2 is configured to turn on in a reset stage (i.e., the sixth switching transistor T6 is turned on) and receive the first reset voltage to reset the voltage of the first end of the energy storage capacitor C1. That is, the energy storage capacitor C1 is charged and the voltage of the first end is reset so that the voltage of the first end reaches the value of the first reset voltage. This can eliminate the influence of the residual charge from the light emitting stage in the display period of the previous frame on the voltage of the energy storage capacitor C1, so that in the data writing stage of each display period of one frame, the voltage at the first end of the energy storage capacitor C1 has the same initial value, i.e., the value of the first reset voltage, to ensure the uniformity of the display effect of the display panel 1. In this embodiment, the first voltage V1 received by the second end of the energy storage capacitor C1 is a zero potential voltage, and in other embodiments, the first voltage V1 may be the driving voltage VDD.

[0024] Furthermore, a first terminal of the light emitting element OLED is configured to receive a reference voltage VSS, and a second terminal of the light emitting element OLED is electrically connected to a second connection terminal (ie, the drain d) of the driving transistor M.

[0025] Optionally, the pixel driving circuit 100 further includes a light-emitting element reset loop L3. The light-emitting element reset loop L3 includes a seventh switching transistor T7 and a light-emitting element OLED connected in series. The first connection end of the seventh switching transistor T7 is configured to receive a second reset voltage, and the 2 connection end is electrically connected to the second end of the light-emitting element OLED. The light-emitting element reset loop L3 is turned on in the reset stage (i.e., the seventh switching transistor T7 is turned on), and is configured to reset the voltage at the second end of the light-emitting element OLED so that the voltage at the second end of the light-emitting element OLED reaches the value of the second reset voltage. Thereby, the influence of the residual charge in the light-emitting stage in the previous frame display period on the voltage at the second end of the light-emitting element OLED can be eliminated. In the light-emitting stage of each frame display period, the voltage at the second end of the light-emitting element OLED has the same initial value, that is, the value of the second reset voltage, and the uniformity of the display effect of the display panel 1 can be further improved. Exemplarily, the voltage value of the first reset voltage and the voltage value of the second reset voltage are both equal to the reset voltage Vint, and Vint < VSS. Thereby, in the reset stage, the second reset voltage does not cause accidental light emission of the light-emitting element OLED. Of course, in other embodiments, the voltage value of the first reset voltage and the voltage value of the second reset voltage may not be equal.

[0026] As shown in Fig. 5b, the pixel driving circuit 100 further includes a data write loop L4. The data write loop L4 includes a third switching transistor T3, a bootstrap capacitor C2, a driving transistor M, a fourth switching transistor T4 and an energy storage capacitor C1, which are connected in series in order. Specifically, a first connection terminal of the third switching transistor T3 is configured to receive a data voltage Vdata, a second connection terminal of the third switching transistor T3 is electrically connected to a second terminal of the bootstrap capacitor C2, and a first terminal of the bootstrap capacitor C2 is further electrically connected to a first connection terminal (i.e., a source s) of the driving transistor M. The fourth switching transistor T4 is electrically connected between the second connection terminal of the driving transistor M and the first terminal of the energy storage capacitor C1. The data write loop L4 is configured to be turned on in the data write phase, receive the data voltage Vdata through the first connection terminal of the third switching transistor T3, and adjust the voltage of the control terminal of the driving transistor M to reach the second voltage value from the first reset voltage value by charging the energy storage capacitor C1 according to the bootstrap effect of the bootstrap capacitor C2. The driving transistor M is in a critical on state when the voltage of its control terminal is equal to the second voltage. The voltage value of the second voltage is equal to the sum of the driving voltage VDD, the data voltage, and the threshold voltage of the driving transistor M. In addition, in the reset phase, the third switching transistor T3 can discharge the residual charge in the display period of the previous frame to the ground terminal through the second switching transistor T2, thereby avoiding the influence of the residual charge in the display period of the previous frame.

[0027] Specifically, as described above, the difference value between the voltage at the first end and the voltage at the second end of the bootstrap capacitor C2 is the value of the driving voltage VDD. When the bootstrap capacitor C2 receives the data voltage Vdata, the voltage at its second end changes from the zero potential to the value of Vdata, that is, the potential at the second end of the bootstrap capacitor C2 changes by the value of Vdata. Due to the bootstrap effect of the bootstrap capacitor C2, the potential at the first end of the bootstrap capacitor C2 (i.e., the source voltage Vs of the driving transistor M) also changes and reaches the value of (Vdata + VDD). In the data writing stage, when the driving transistor M starts to charge the energy storage capacitor C1, the gate voltage Vg = Vint, the source voltage Vs = Vdata + VDD. At this time, the gate-source voltage Vgs = Vg - Vs = Vint - Vdata < Vth. Therefore, the driving transistor M is turned on. Vth is the threshold voltage of the driving transistor M. When Vgs < Vth, the driving transistor M is turned on. When Vgs > Vth, the driving transistor M is turned off. The source voltage Vs charges the energy storage capacitor C1 through the turned-on data writing loop L4, and continuously raises the voltage at the first end of the energy storage capacitor C1. When the voltage at the first end of the energy storage capacitor C1 rises to Vg = Vdata + VDD + Vth, Vgs = (Vdata + VDD + Vth) - (Vdata + VDD) = Vth, and the driving transistor M enters the critical on state, and the voltage at the first end of the energy storage capacitor C1 stops rising. The voltage value of the second voltage becomes (Vdata + VDD + Vth). In addition, due to the bootstrap effect of the bootstrap capacitor C2, the speed at which the data voltage Vdata is transmitted to the energy storage capacitor C1 is fast. As a result, the time length of the data writing stage can be shortened, the time length of the display period of one frame can be reduced, and it is advantageous to increase the refresh rate of the display panel 1.

[0028] As shown in Fig. 5c, the pixel driving circuit 100 further includes a light-emitting loop L5. The light-emitting loop L5 includes a first switching transistor T1, a driving transistor M, a fifth switching transistor T5 and a light-emitting element OLED, which are connected in series in order. The fifth switching transistor T5 is electrically connected between the second connection terminal of the driving transistor M and the second end of the light-emitting element OLED. The light-emitting loop L5 is configured to be turned on in a light-emitting stage and receive a driving voltage VDD at the first connection terminal of the driving transistor M to drive the light-emitting element OLED to emit light.

[0029] Specifically, in the light emitting stage, the driving transistor M continues to be on. The first switching transistor T1 and the fifth switching transistor T5 both operate in a linear region, while the driving transistor M operates in a saturation region, so that the magnitude of the current flowing through the light emitting element OLED mainly depends on the current Ids between the source and drain of the driving transistor M. Based on the operating characteristics of the switching transistors, it can be seen that the following mathematical relationship is satisfied between the current Ids and the gate-source voltage Vgs. [Formula 3] Ids = (K / 2) (Vgs - Vth) 2 =(K / 2)(Vdata) 2

[0030] K=Cox×μ×W / L, where Cox is the gate capacitance per unit area, μ is the electron mobility in the channel, and W / L is the width-to-length ratio of the channel of the drive transistor M.

[0031] As is clear from the above formula, the data write loop L 4Since the driving transistor M can provide the compensation voltage to the driving transistor M, the current Ids flowing through the light emitting element OLED is not correlated with the threshold voltage Vth and driving voltage VDD of the driving transistor M. In other words, if the writing accuracy of the data voltage Vdata is guaranteed, the light emission brightness of the light emitting element OLED can be controlled with high accuracy. Therefore, the pixel driving circuit 100 provided in the present application can eliminate not only the unevenness in the display brightness of the display panel 1 caused by the difference in the threshold voltage of the driving transistor M in different pixel driving circuits 100, but also the unevenness in the display brightness of the display panel 1 caused by the difference in the driving voltage VDD received by different pixel driving circuits 100. In addition, the current Ids flowing through the light emitting element OLED is not correlated with the driving voltage VDD. 2 Due to the characteristic that the light emission luminance does not change unless the voltage difference between the ends changes, the voltage value of the driving voltage VDD can be appropriately reduced, thereby reducing the power consumption of the pixel driving circuit 100.

[0032] As described above, in this embodiment, the switching transistors T1 to T7 and the driving transistor M are all transistors that are turned on at a low level. Next, the operation flow of the pixel driving circuit 100 provided in the present application in one frame scanning period will be described in detail with reference to Figures 3 to 5c.

[0033] In the embodiment of the present application, the scanning signal received by the control end of the first switching transistor T1 is the first scanning signal SCAN1. The scanning signals received by the control ends of the second switching transistor T2, the sixth switching transistor T6, and the seventh switching transistor T7 are all the second scanning signal SCAN2. The scanning signals received by the control ends of the third switching transistor T3 and the fourth switching transistor T4 are all the third scanning signal SCAN3. The scanning signal received by the control end of the fifth switching transistor T5 is the fourth scanning signal SCAN4. Since the switching transistors having the same conduction timing can be controlled by the same scanning signal, the wiring structure of the substrate 1000 can be simplified. Of course, in other embodiments, one scanning signal can be provided separately for each switching transistor to control the switching transistor, and is not limited here.

[0034] In the reset stage (stage A), the first scan signal SCAN1 and the second scan signal SCAN2 are all at a low level, and the third scan signal SCAN3 and the fourth scan signal SCAN4 are all at a high level. Therefore, the switching transistors T1, T2, T6, and T7 are all turned on, and the switching transistors T3 to T5 are all turned off. As a result, the pre-charge loop L1 is turned on to adjust the voltage at the first end of the bootstrap capacitor C2 so that the voltage at the first end of the bootstrap capacitor C2 reaches the value of the driving voltage VDD, and resets the voltage at the second end of the bootstrap capacitor C2 so that the voltage at the second end of the bootstrap capacitor C2 reaches zero potential. The energy storage capacitor reset loop L2 is turned on to reset the voltage at the first end of the energy storage capacitor C1 so that the voltage at the first end of the energy storage capacitor C1 reaches the value of the first reset voltage. The light emitting element reset loop L3 is turned on to reset the voltage at the second end of the light emitting element OLED so that the voltage at the second end of the light emitting element OLED reaches the value of the second reset voltage. Additionally, the data write loop L4 and the light emission loop L5 are turned off.

[0035] In the data writing stage (stage B), the third scanning signal SCAN3 is at a low level, and the first scanning signal SCAN1, the second scanning signal SCAN2 and the fourth scanning signal SCAN4 are all at a high level. Therefore, the switching transistors T3 and T4 and the driving transistor M are all turned on, and the switching transistors T1, T2, T5, T6 and T7 are all turned off. Thus, the data writing loop L4 is turned on to adjust the voltage of the control end of the driving transistor M so that the voltage of the control end of the driving transistor M reaches the second voltage value from the first reset voltage value. The pre-charge loop L1, the energy storage capacitor reset loop L2, the light emitting element reset loop L3 and the light emitting loop L5 are all turned off.

[0036] In the light-emitting stage (stage C), the first scanning signal SCAN1 and the fourth scanning signal SCAN4 are all at low level, and the second scanning signal SCAN2 and the third scanning signal SCAN3 are all at high level, so that the switching transistors T1, T5 and the driving transistor M are all turned on, and the switching transistors T2, T3, T4, T6, and T7 are all turned off, so that the light-emitting loop L5 is turned on and receives the driving voltage VDD to drive the light-emitting element OLED to emit light, and the pre-charge loop L1, the energy storage capacitor reset loop L2, the light-emitting element reset loop L3, and the data write loop L4 are all turned off.

[0037] The pixel driving circuit 100 provided in the present application charges the bootstrap capacitor C2 through the pre-charge loop L1 in a reset stage, so that the voltage of the first end of the bootstrap capacitor C2 reaches the value of the driving voltage VDD; in a data writing stage, receives the data voltage Vdata through the second end of the bootstrap capacitor C2, and charges the energy storage capacitor C1 based on the bootstrap effect of the bootstrap capacitor C2 to adjust the voltage of the control end of the driving transistor M to a second voltage, and the voltage value of the second voltage is the driving voltage VDD, the data voltage Vdata, and the driving transistor M. The light emitting element OLED is driven to emit light based on the second voltage received at the control end of the drive transistor M and the driving voltage VDD received at the first connection end of the drive transistor M in the light emitting stage, so that the current flowing through the light emitting element OLED is no longer correlated with the driving voltage VDD and the threshold voltage Vth of the drive transistor M. This not only eliminates unevenness in the display brightness of the display panel 1 caused by differences in the threshold voltages of the drive transistors M in different pixel driving circuits 100, but also eliminates unevenness in the display brightness of the display panel 1 caused by differences in the driving voltages VDD received by different pixel driving circuits 100.

[0038] Although the embodiments of the present application have been shown and described above, it will be understood by those skilled in the art that various modifications, alterations, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is limited by the claims and their equivalents.

Claims

1. 1. A pixel driving circuit, comprising: The pixel driving circuit is configured to drive a light emitting element to emit light, and a first end of the light emitting element is configured to receive a reference voltage. The pixel driving circuit operates in a reset stage, a data writing stage and an emission stage in sequence in a display period of one frame, and the pixel driving circuit includes a driving transistor, an energy storage capacitor, an energy storage capacitor reset loop, a bootstrap capacitor, a pre-charge loop, a data writing loop and an emission loop; The driving transistor has a control end, a first connection end and a second connection end, the first connection end is configured to receive a driving voltage, and the second connection end is electrically connected to a second end of the light emitting element; A first end of the energy storage capacitor is electrically connected to a control end of the drive transistor, and a second end of the energy storage capacitor is configured to receive a first voltage having a constant voltage value; the energy storage capacitor reset loop is configured to be turned on during the reset phase to receive a first reset voltage and reset a voltage at a first end of the energy storage capacitor such that the voltage at a first end of the energy storage capacitor reaches a value of the first reset voltage; a first end of the bootstrap capacitor is electrically connected to a first connection end of the driving transistor, and a second end of the bootstrap capacitor is configured to receive a zero potential voltage in the reset phase and a data voltage in the data write phase; the pre-charge loop is configured to turn on in the reset stage and charge the bootstrap capacitor with the driving voltage, thereby adjusting the voltage of the first end of the bootstrap capacitor so that the voltage of the first end of the bootstrap capacitor reaches a value of the driving voltage, and resetting the voltage of the second end of the bootstrap capacitor so that the voltage of the second end of the bootstrap capacitor reaches a value of zero potential, thereby making a difference between the voltage of the first end and the voltage of the second end of the bootstrap capacitor reach a value of the driving voltage; the data write loop includes the bootstrap capacitor, the driving transistor and the energy storage capacitor connected in series, the data write loop is configured to be turned on in the data write phase, receive the data voltage at a second end of the bootstrap capacitor, and charge the energy storage capacitor according to a bootstrap effect of the bootstrap capacitor, thereby adjusting a voltage of the control end of the driving transistor so that the voltage of the control end of the driving transistor reaches a second voltage value from a value of the first reset voltage, the driving transistor is in a critical on state when the voltage of its control end is equal to the second voltage, the second voltage being equal to the sum of the driving voltage, the data voltage and a threshold voltage of the driving transistor; The light emitting loop includes the driving transistor and the light emitting element connected in series, and the light emitting loop is configured to be turned on in the light emitting stage, receive the driving voltage at the first connection end of the driving transistor, and drive the light emitting element to emit light.

2. A pixel drive circuit comprising:

2. the precharge loop includes a first switching transistor, the bootstrap capacitor, and a second switching transistor connected in series; a first connection end of the first switching transistor configured to receive the driving voltage, and a second connection end of the first switching transistor electrically connected to a first end of the bootstrap capacitor; a first connection terminal of the second switching transistor is electrically connected to a ground terminal and configured to receive the zero potential voltage, and a second connection terminal of the second switching transistor is electrically connected to a second terminal of the bootstrap capacitor; In the reset step, the first switching transistor is turned on according to a scan signal received at a control end thereof, and the second switching transistor is turned on according to a scan signal received at a control end thereof, thereby turning on the precharge loop.

2. The pixel driving circuit according to claim 1 .

3. the data write loop includes a third switching transistor, the bootstrap capacitor, the driving transistor, a fourth switching transistor and the energy storage capacitor connected in series; a first connection end of the third switching transistor configured to receive the data voltage, and a second connection end of the third switching transistor electrically connected to a second end of the bootstrap capacitor; the fourth switching transistor is electrically connected between the second connection terminal of the driving transistor and the first terminal of the energy storage capacitor; In the data writing step, the third switching transistor and the fourth switching transistor are both turned on in response to a scanning signal received at each control end, thereby turning on the data writing loop.

3. The pixel driving circuit according to claim 2.

4. the light emitting loop includes the first switching transistor, the driving transistor, the fifth switching transistor and the light emitting element, which are connected in series; a second connection terminal of the first switching transistor electrically connected to a first connection terminal of the driving transistor; the fifth switching transistor is electrically connected between the second connection terminal of the driving transistor and the second terminal of the light emitting element; In the light emitting step, the first switching transistor is turned on according to a scanning signal received at its control end, and the fifth switching transistor is turned on according to a scanning signal received at its control end, so that the light emitting loop is turned on.

4. The pixel driving circuit according to claim 3.

5. the energy storage capacitor reset loop includes the energy storage capacitor and a sixth switching transistor connected in series, a first connection end of the sixth switching transistor configured to receive the first reset voltage, and a second connection end of the sixth switching transistor electrically connected to a first end of the energy storage capacitor; In the reset step, the sixth switching transistor is turned on according to a scanning signal received at its control end, so that the energy storage capacitor reset loop is turned on.

5. A pixel driving circuit as claimed in claim 4.

6. The pixel driving circuit further includes a light emitting element reset loop, the light emitting element reset loop including a seventh switching transistor and the light emitting element connected in series, a first connection end of the seventh switching transistor configured to receive a second reset voltage, and a second connection end of the seventh switching transistor electrically connected to a second end of the light emitting element; In the reset step, the seventh switching transistor is turned on according to a scanning signal received at its control end, so that the light emitting device reset loop is turned on and resets the voltage of the second end of the light emitting device to reach the value of the second reset voltage.

6. A pixel driving circuit as claimed in claim 5.

7. the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, the sixth switching transistor, the seventh switching transistor, and the driving transistor are all transistors that are turned on at a low level.

7. A pixel driving circuit according to claim 6.

8. the first voltage received at the second end of the energy storage capacitor comprises the drive voltage or the zero potential voltage; 2. The pixel driving circuit according to claim 1 .

9. In the light emission stage, a current Ids between the source and drain of the driving transistor satisfies the following formula: Ids=(K / 2)(Vdata) 2 K=Cox×μ×W / L, where Cox is the gate capacitance per unit area, μ is the electron mobility in the channel, and W / L is the width-to-length ratio of the drive transistor channel.

2. The pixel driving circuit according to claim 1 .

10. A display panel, The display panel includes a substrate and a number of pixel driving circuits, the substrate having a display area, and the number of pixel driving circuits are arranged in an array in the display area of ​​the substrate; The pixel driving circuit is configured to drive a light emitting element to emit light, and a first end of the light emitting element is configured to receive a reference voltage. The pixel driving circuit operates in a reset stage, a data writing stage and an emission stage in sequence in a display period of one frame, and the pixel driving circuit includes a driving transistor, an energy storage capacitor, an energy storage capacitor reset loop, a bootstrap capacitor, a pre-charge loop, a data writing loop and an emission loop; The driving transistor has a control end, a first connection end and a second connection end, the first connection end is configured to receive a driving voltage, and the second connection end is electrically connected to a second end of the light emitting element; A first end of the energy storage capacitor is electrically connected to a control end of the drive transistor, and a second end of the energy storage capacitor is configured to receive a first voltage having a constant voltage value; the energy storage capacitor reset loop is configured to be turned on during the reset phase to receive a first reset voltage and reset a voltage at a first end of the energy storage capacitor such that the voltage at a first end of the energy storage capacitor reaches a value of the first reset voltage; a first end of the bootstrap capacitor is electrically connected to a first connection end of the driving transistor, and a second end of the bootstrap capacitor is configured to receive a zero potential voltage in the reset phase and a data voltage in the data write phase; the pre-charge loop is configured to turn on in the reset stage and charge the bootstrap capacitor with the driving voltage, thereby adjusting the voltage of the first end of the bootstrap capacitor so that the voltage of the first end of the bootstrap capacitor reaches a value of the driving voltage, and resetting the voltage of the second end of the bootstrap capacitor so that the voltage of the second end of the bootstrap capacitor reaches a value of zero potential, thereby making a difference between the voltage of the first end and the voltage of the second end of the bootstrap capacitor reach a value of the driving voltage; the data write loop includes the bootstrap capacitor, the driving transistor and the energy storage capacitor connected in series, the data write loop is configured to be turned on in the data write phase, receive the data voltage at a second end of the bootstrap capacitor, and charge the energy storage capacitor according to a bootstrap effect of the bootstrap capacitor, thereby adjusting a voltage of the control end of the driving transistor so that the voltage of the control end of the driving transistor reaches a second voltage value from a value of the first reset voltage, the driving transistor is in a critical on state when the voltage of its control end is equal to the second voltage, the second voltage being equal to the sum of the driving voltage, the data voltage and a threshold voltage of the driving transistor; The light emitting loop includes the driving transistor and the light emitting element connected in series, and the light emitting loop is configured to be turned on in the light emitting stage, receive the driving voltage at the first connection end of the driving transistor, and drive the light emitting element to emit light. A display panel characterized by:

11. the precharge loop includes a first switching transistor, the bootstrap capacitor, and a second switching transistor connected in series; a first connection end of the first switching transistor configured to receive the driving voltage, and a second connection end of the first switching transistor electrically connected to a first end of the bootstrap capacitor; a first connection terminal of the second switching transistor is electrically connected to a ground terminal and configured to receive the zero potential voltage, and a second connection terminal of the second switching transistor is electrically connected to a second terminal of the bootstrap capacitor; In the reset step, the first switching transistor is turned on according to a scan signal received at a control end thereof, and the second switching transistor is turned on according to a scan signal received at a control end thereof, thereby turning on the precharge loop.

11. The display panel according to claim 10.

12. the data write loop includes a third switching transistor, the bootstrap capacitor, the driving transistor, a fourth switching transistor and the energy storage capacitor connected in series; a first connection end of the third switching transistor configured to receive the data voltage, and a second connection end of the third switching transistor electrically connected to a second end of the bootstrap capacitor; the fourth switching transistor is electrically connected between the second connection terminal of the driving transistor and the first terminal of the energy storage capacitor; In the data writing step, the third switching transistor and the fourth switching transistor are both turned on in response to a scanning signal received at each control end, thereby turning on the data writing loop.

12. The display panel according to claim 11.

13. the light emitting loop includes the first switching transistor, the driving transistor, the fifth switching transistor and the light emitting element, which are connected in series; a second connection terminal of the first switching transistor electrically connected to a first connection terminal of the driving transistor; the fifth switching transistor is electrically connected between the second connection terminal of the driving transistor and the second terminal of the light emitting element; In the light emitting step, the first switching transistor is turned on according to a scanning signal received at its control end, and the fifth switching transistor is turned on according to a scanning signal received at its control end, so that the light emitting loop is turned on.

13. The display panel according to claim 12.

14. the energy storage capacitor reset loop includes the energy storage capacitor and a sixth switching transistor connected in series, a first connection end of the sixth switching transistor configured to receive the first reset voltage, and a second connection end of the sixth switching transistor electrically connected to a first end of the energy storage capacitor; In the reset step, the sixth switching transistor is turned on according to a scanning signal received at its control end, so that the energy storage capacitor reset loop is turned on.

14. The display panel according to claim 13.

15. The pixel driving circuit further includes a light emitting element reset loop, the light emitting element reset loop including a seventh switching transistor and the light emitting element connected in series, a first connection end of the seventh switching transistor configured to receive a second reset voltage, and a second connection end of the seventh switching transistor electrically connected to a second end of the light emitting element; In the reset step, the seventh switching transistor is turned on according to a scanning signal received at its control end, so that the light emitting device reset loop is turned on and resets the voltage of the second end of the light emitting device to reach the value of the second reset voltage.

15. The display panel according to claim 14.

16. In the light emission stage, a current Ids between the source and drain of the driving transistor satisfies the following formula: Ids=(K / 2)(Vdata) 2 K=Cox×μ×W / L, where Cox is the gate capacitance per unit area, μ is the electron mobility in the channel, and W / L is the width-to-length ratio of the drive transistor channel.

11. The display panel according to claim 10.

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