Silicon-based Josephson Junctions for Qubit Devices

Abstract

Techniques are provided for qubit devices comprising silicon-based Josephson junctions, and / or for fabricating qubit devices comprising silicon-based Josephson junctions. For example, one or more embodiments described herein may comprise a device that may include a Josephson junction that includes a tunnel barrier disposed between two vertically stacked superconducting silicon electrodes.

Description

[Technical field]

[0001] The present disclosure relates to one or more silicon-based Josephson junctions that may be incorporated into qubit devices, and more particularly to Josephson junctions including superconducting silicon material that may be implemented in a vertical structure orientation. Summary of the Invention

[0002] SUMMARY OF THE DISCLOSURE The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements or to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a general form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, apparatus and / or methods relating to silicon-based Josephson junctions for one or more qubit devices are described.

[0003] According to one embodiment, there is provided an apparatus, which may comprise a Josephson junction including a tunnel barrier disposed between two vertically stacked superconducting silicon electrodes.

[0004] According to another embodiment, there is provided an apparatus, which may comprise a Josephson junction including a dielectric tunnel barrier disposed between two superconducting silicon electrodes.

[0005] According to one embodiment, a method is provided. The method may include doping a portion of a silicon substrate to form a first superconducting electrode. The method may also include depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier. Furthermore, the method may include doping a portion of the tunnel barrier to form a second superconducting electrode to form a Josephson junction. [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 is an exemplary, non-limiting cross-sectional view of a device including silicon-based Josephson junctions that may be oriented in a vertical stack according to one or more embodiments described herein. [Figure 1B] FIG. 2 is an exemplary, non-limiting top view of a device including silicon-based Josephson junctions that may be oriented in a vertical stack, according to one or more embodiments described herein. [Diagram 2] FIG. 1 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a first stage of fabrication according to one or more embodiments described herein. [Diagram 3] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a second stage of fabrication according to one or more embodiments described herein. [Figure 4] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a third stage of fabrication according to one or more embodiments described herein. [Figure 5A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a fourth stage of fabrication according to one or more embodiments described herein. [Figure 5B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a fourth stage of fabrication according to one or more embodiments described herein. [Figure 6A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a fifth stage of fabrication according to one or more embodiments described herein. [Figure 6B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a fifth stage of fabrication according to one or more embodiments described herein. [Figure 7A]FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a sixth stage of fabrication according to one or more embodiments described herein. [Figure 7B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a sixth stage of fabrication according to one or more embodiments described herein. [Figure 8A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a seventh stage of fabrication according to one or more embodiments described herein. [Figure 8B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a seventh stage of fabrication according to one or more embodiments described herein. [Figure 9A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during an eighth stage of fabrication according to one or more embodiments described herein. [Figure 9B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during an eighth stage of fabrication according to one or more embodiments described herein. [Figure 10A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a ninth stage of fabrication according to one or more embodiments described herein. [Figure 10B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a ninth stage of fabrication according to one or more embodiments described herein. [Figure 11A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a tenth stage of fabrication according to one or more embodiments described herein. [Figure 11B]FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a tenth stage of fabrication according to one or more embodiments described herein. [Figure 12A] FIG. 2 is an exemplary, non-limiting cross-sectional view of a device including a silicon-based Josephson junction having one or more isolation implants according to one or more embodiments described herein. [Figure 12B] FIG. 2 is an exemplary, non-limiting top view of a device including a silicon-based Josephson junction having one or more isolation implants according to one or more embodiments described herein. [Figure 13] FIG. 1 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a first stage of fabrication according to one or more embodiments described herein. [Figure 14A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a second stage of fabrication according to one or more embodiments described herein. [Figure 14B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a second stage of fabrication according to one or more embodiments described herein. [Figure 15A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a third stage of fabrication according to one or more embodiments described herein. [Figure 15B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a third stage of fabrication according to one or more embodiments described herein. [Figure 16A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a fourth stage of fabrication according to one or more embodiments described herein. [Figure 16B]FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a fourth stage of fabrication according to one or more embodiments described herein. [Figure 17A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a fifth stage of fabrication according to one or more embodiments described herein. [Figure 17B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a fifth stage of fabrication according to one or more embodiments described herein. [Figure 18A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a sixth stage of fabrication according to one or more embodiments described herein. [Figure 18B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a sixth stage of fabrication according to one or more embodiments described herein. [Figure 19A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a seventh stage of fabrication according to one or more embodiments described herein. [Figure 19B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a seventh stage of fabrication according to one or more embodiments described herein. [Figure 20A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during an eighth stage of fabrication according to one or more embodiments described herein. [Figure 20B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during an eighth stage of fabrication according to one or more embodiments described herein. [Figure 21A]FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a ninth stage of fabrication according to one or more embodiments described herein. [Figure 21B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a ninth stage of fabrication according to one or more embodiments described herein. [Figure 22A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a tenth stage of fabrication according to one or more embodiments described herein. [Figure 22B] FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a tenth stage of fabrication according to one or more embodiments described herein. [Figure 23A] FIG. 11 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during an eleventh stage of fabrication according to one or more embodiments described herein. [Figure 23B] FIG. 11 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during an eleventh stage of fabrication according to one or more embodiments described herein. [Figure 24A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a twelfth stage of fabrication according to one or more embodiments described herein. [Figure 24B] FIG. 15 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a twelfth stage of fabrication according to one or more embodiments described herein. [Figure 25A] FIG. 13 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a thirteenth stage of fabrication according to one or more embodiments described herein. [Figure 25B]FIG. 13 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a thirteenth stage of fabrication according to one or more embodiments described herein. [Figure 26A] FIG. 14 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a fourteenth stage of fabrication according to one or more embodiments described herein. [Figure 26B] FIG. 15 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a fourteenth stage of fabrication according to one or more embodiments described herein. [Figure 27A] FIG. 15 is an illustrative, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a fifteenth stage of fabrication according to one or more embodiments described herein. [Figure 27B] FIG. 15 is an illustrative, non-limiting top view of a device comprising a silicon-based Josephson junction during a fifteenth stage of fabrication according to one or more embodiments described herein. [Figure 28] 1 is a flow diagram of an example, non-limiting method that may facilitate fabrication of one or more silicon-based Josephson junctions in accordance with one or more embodiments described herein. [Figure 29] 1 is a flow diagram of an example, non-limiting method that may facilitate fabrication of one or more silicon-based Josephson junctions in accordance with one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The following detailed description is merely illustrative and is not intended to limit the embodiments or the application and / or uses of the embodiments, nor is it intended to be bound by any expressed or implied information presented in the preceding Background or Summary sections or in the Detailed Description section.

[0008] One or more embodiments will now be described with reference to the drawings, in which like reference numerals are used throughout to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various cases one or more embodiments may be practiced without such specific details. Additionally, features shown in the drawings with similar shading, cross-hatching, or color coding, or combinations thereof, may include shared compositions and / or materials.

[0009] Josephson junctions have been used to fabricate quantum bits (e.g., superconducting qubits) with the goal of increasing the coherence time exhibited by quantum computing devices. However, the theoretical coherence times associated with Josephson junctions are often shorter than those actually exhibited by the qubits. The material composition of the Josephson junction can affect the coherence time. For example, the type of superconducting material utilized, impurities within the superconducting material, or defects introduced by the manufacturing process for the superconducting material, or a combination thereof, can adversely affect the coherence time exhibited by a Josephson junction qubit. For example, aluminum-based Josephson junctions can exhibit longer coherence times than niobium-based Josephson junctions, but can still suffer from decoherence caused by defects (e.g., aluminum oxide defects) that are commonly introduced during the manufacturing and / or deposition of aluminum and / or aluminum derivatives.

[0010] Various embodiments described herein may relate to an apparatus and / or method for fabricating a silicon-based Josephson junction for incorporation into one or more qubit devices. For example, one or more embodiments may relate to a Josephson junction that includes a silicon material, which may be crystalline, such as a doped superconducting silicon electrode, with single crystal undoped silicon acting as the junction. By using silicon material, chemical purification, crystal growth, or defect control, or a combination thereof, may be achieved in various embodiments described herein while implementing complementary metal oxide semiconductor ("CMOS") technology. In one or more embodiments, the silicon-based Josephson junction may include a silicon dielectric material as a tunnel barrier to the two superconducting silicon electrodes. Additionally, one or more embodiments may include orienting the silicon-based Josephson junction structure in a vertical orientation. Additionally, in various embodiments, electrical isolation of the Josephson junction may be achieved through intrinsic silicon, or the incorporation of one or more isolation implants into the silicon, or both.

[0011] As described herein, the term "superconducting" may characterize a material that exhibits superconducting properties at or below a superconducting critical temperature. Additionally, as described herein, the term "deposition process" may refer to any process in which one or more first materials are grown, coated, deposited, or transferred onto one or more second materials, or combinations thereof. Exemplary deposition processes include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), atomic layer deposition ("ALD"), low pressure chemical vapor deposition ("LPCVD"), plasma enhanced chemical vapor deposition ("PECVD"), high density plasma chemical vapor deposition ("HDPCVD"), subatmospheric pressure chemical vapor deposition ("SACVD"), rapid thermal chemical vapor deposition ("RTCVD"), in-situ radical assisted deposition ("RTCVD"), and the like. The deposition may include techniques such as deposition, high temperature oxide deposition ("HTO"), low temperature oxide deposition ("LTO"), limited reaction processing CVD ("LRPCVD"), ultra-high vacuum chemical vapor deposition ("UHVCVD"), metal organic chemical vapor deposition ("MOCVD"), physical vapor deposition ("PVD"), chemical oxidation, sputtering, plating, evaporation, spin-on-coating, ion beam deposition, electron beam deposition, laser assisted deposition, and / or chemical solution deposition.

[0012] As described herein, the terms "epitaxial growth process" and / or "epitaxial growth process" may refer to any process of growing an epitaxial material (e.g., a crystalline semiconductor material) on a deposition surface of another semiconductor material, where the epitaxial material grown has substantially identical crystalline properties to the semiconductor material of the deposition surface. In an epitaxial deposition process, chemical reactants provided by a source gas (e.g., a gas containing silicon and / or germanium) and / or a source liquid may be controlled and system parameters may be set such that the deposition atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves relative to the crystalline configuration of the atoms of the deposition surface. Thus, the grown epitaxial material has substantially identical crystalline properties to the deposition surface on which the epitaxial material is formed. For example, <100> Epitaxially grown semiconductor material deposited on a crystal surface with an orientation of <100> Exemplary epitaxial growth processes may include, but are not limited to, vapor phase epitaxy ("VPE"), molecular beam epitaxy ("MBE"), or liquid phase epitaxy ("LPE"), or combinations thereof.

[0013] As described herein, the terms "etching process" and / or "removal process" may refer to any process that removes one or more first materials from one or more second materials. Exemplary etching and / or removal processes may include, but are not limited to, wet etching, dry etching (e.g., reactive ion etching ("RIE")), or chemical mechanical planarization ("CMP"), or combinations thereof, etc.

[0014] As described herein, the term "laser doping process" may refer to one or more gas immersion laser doping techniques that may achieve a homogeneous doped layer of silicon with varying active concentration or thickness or both. The laser doping process may be performed in an ultra-high vacuum ("UHV") chamber, and a precursor gas (e.g., boron trichloride) may be injected into the chamber and onto the surface of the silicon material (e.g., thereby saturating one or more chemisorption sites of the silicon material). The silicon material may then be melted using a pulsed laser (e.g., a pulsed excimer XeCl laser) to heat the silicon material for a well-defined duration. One or more dopants (e.g., boron, gallium, or germanium, or a combination thereof) from the precursor gas may diffuse into the silicon material and be substitutionally incorporated. Thereby, silicon dopant (e.g., silicon-boron (Si:B), silicon-germanium (Si:Ge), or silicon-gallium (Si:Ga)) crystals may be grown on the underlying silicon via one or more epitaxial growth processes.

[0015] 1A and / or 1B show diagrams of an exemplary, non-limiting qubit device 100 that may include a silicon-based Josephson junction that may include a first superconducting silicon electrode 102, a second superconducting silicon electrode 104, and / or a tunnel barrier 106, in accordance with one or more embodiments described herein. FIG 1A shows a cross-sectional view of qubit device 100, and FIG 1B shows a top view of qubit device 100. For the sake of brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted.

[0016] As shown in FIG. 1A, the silicon-based Josephson junction may be disposed on a semiconductor substrate 108. Further, the first superconducting silicon electrode 102, the second superconducting silicon electrode 104, and / or the dielectric tunnel barrier 106 may be stacked on the semiconductor substrate 108 in a vertical orientation (e.g., along the “Y” axis). Furthermore, at least a portion of the semiconductor substrate 108 and one or more isolation layers 110 may form an isolation region 112 (e.g., shown by a bold dashed line) adjacent to the silicon-based Josephson junction. Furthermore, the silicon-based Josephson junction may include a first metal contact 114 operably coupled to the first superconducting silicon electrode 102, or a second metal contact 116 operably coupled to the second superconducting silicon electrode 104, or both.

[0017] The semiconductor substrate 108 may be crystalline, paracrystalline, microcrystalline, or amorphous. The semiconductor substrate 108 may essentially comprise (e.g., excluding foreign matter) a single element (e.g., silicon or germanium) or compound (e.g., aluminum oxide, silicon dioxide, gallium arsenide, silicon carbide, or silicon germanium, or combinations thereof). The semiconductor substrate 110 may also have multiple layers of materials, such as, but not limited to, a semiconductor-on-insulator substrate ("SeOI"), a silicon-on-insulator substrate ("SOI"), a germanium-on-insulator substrate ("GeOI"), or a silicon-germanium-on-insulator substrate ("SGOI"), or combinations thereof. Additionally, the semiconductor substrate 110 may also have other layers, such as high-dielectric constant oxides ("high-K oxides") and / or nitrides. In one or more embodiments, the semiconductor substrate 110 may be a silicon wafer. In various embodiments, the semiconductor substrate 110 may include single crystal silicon (Si), silicon germanium (eg, characterized by the chemical formula SiGe), or a III-V semiconductor wafer or surface / active layer, or a combination thereof.

[0018] In one or more embodiments, at least a top portion of the semiconductor substrate 108 may provide structural support for the silicon-based Josephson junction and / or qubit device 100 (e.g., as shown in FIG. 1A and / or FIG. 1B). In various embodiments, at least a top portion of the semiconductor substrate 108 may comprise intrinsic silicon. In some embodiments, at least a top portion of the semiconductor substrate 108 may comprise silicon germanium (SiGe).

[0019] The first superconducting silicon electrode 102 may include a laser doped crystalline silicon material. For example, one or more dopants may be incorporated into a portion of the silicon material via one or more laser doping processes to promote superconductivity. Exemplary dopants that may be included in the first superconducting silicon electrode 102 may include, but are not limited to, boron, gallium, or germanium, or combinations thereof. In one or more embodiments, the first superconducting silicon electrode 102 may have an active concentration of dopant ranging, for example, from 4 atomic percent (At%) or more to 40 At% or less (e.g., at least 4 At% to 11 At% if the first superconducting electrode 102 includes a boron dopant, or at least 10 At% to 40 At% if the first superconducting electrode 102 includes a gallium dopant, or both). In various embodiments, the critical temperature of the first superconducting electrode 102 can range, for example, from 500 milliKelvin (mK) or more to 6 K or less (e.g., 500 mK to 600 mK if the first superconducting electrode 102 includes a boron dopant, or 5 K to 6 K if the first superconducting electrode 102 includes a gallium dopant, or both).

[0020] One skilled in the art will appreciate that the length (e.g., along the "X" axis) of the first superconducting silicon electrode 102 may vary depending on the function of the silicon-based Josephson junction and / or the structure of the qubit device 100. For example, the length (e.g., along the "X" axis) of the first superconducting silicon electrode 102 may be 100 nanometers (nm) or more and hundreds of microns or less (e.g., 500 nm to 1,000 nm). Similarly, the thickness (e.g., along the "Y" axis) of the first superconducting silicon electrode 102 may vary depending on the function of the silicon-based Josephson junction and / or the structure of the qubit device 100. For example, the thickness (e.g., along the "Y" axis) of the first superconducting silicon electrode 102 may be 5 nm or more and 500 nm or less (e.g., 10 nm to 50 nm). Furthermore, in one or more embodiments, the first superconducting silicon electrode 102 may be embedded in a semiconductor substrate 108 (e.g., as shown in FIG. 1A).

[0021] In one or more embodiments, the tunnel barrier 106, one or more isolation layers 110, and / or the first metal contact may be disposed on (e.g., directly on) the first superconducting silicon electrode 102. The tunnel barrier 106 is shown in FIG. 1A with a dashed line. In various embodiments, the tunnel barrier 106 may include a dielectric material to make the silicon-based Josephson junction a superconductor-insulator-superconductor ("SIS") Josephson junction. For example, the tunnel barrier 106 may include an intrinsic silicon material. In one or more embodiments, the tunnel barrier 106 may include doped silicon to make the silicon-based Josephson junction a superconductor-normal-superconductor ("SNS") Josephson junction. For example, one or more dopants that may be included in the tunnel barrier 106 may include, but are not limited to, phosphorus (P) or arsenic (As) or both. One skilled in the art will appreciate that the length (e.g., along the "X" axis) of the tunnel barrier 106 may vary depending on the function of the silicon-based Josephson junction and / or qubit device 100. For example, the length (e.g., along the "X" axis) of the tunnel barrier 106 may be greater than or equal to 30 nm and less than or equal to 1,000 nm (e.g., 100 nm to 300 nm). Similarly, the thickness (e.g., along the "Y" axis) of the tunnel barrier 106 may vary depending on the function of the silicon-based Josephson junction and / or qubit device 100. For example, the thickness (e.g., along the "Y" axis) of the tunnel barrier 106 may be greater than or equal to 0.5 nm and less than or equal to 300 nm.

[0022] The second superconducting silicon electrode 104 may be disposed on the tunnel barrier 106 such that the tunnel barrier 106 is located between the first superconducting silicon electrode 102 and the second superconducting silicon electrode 104. In one or more embodiments, the second superconducting silicon electrode 104 may have the same or nearly the same composition as the first superconducting silicon electrode 102. Alternatively, in one or more embodiments, the second superconducting silicon electrode 104 may have a different composition than the first superconducting silicon electrode 102.

[0023] For example, the second superconducting silicon electrode 104 may include a laser doped crystalline silicon material. For example, one or more dopants may be incorporated into a portion of the silicon material via one or more laser doping processes to promote superconductivity. Exemplary dopants that may be included in the second superconducting silicon electrode 104 may include, but are not limited to, boron or gallium, or a combination thereof. In one or more embodiments, the second superconducting silicon electrode 104 may have an active concentration of dopant ranging, for example, from 4 At% or more to 40 At% or less (e.g., at least 4 At% to 11 At% if the first superconducting electrode 102 includes a boron dopant, or at least 10 At% to 40 At% if the first superconducting electrode 102 includes a gallium dopant, or both). In various embodiments, the critical temperature of the second superconducting silicon electrode 104 can range, for example, from 500 mK or more to 6 K or less (e.g., 500 mK to 600 mK if the second superconducting electrode 104 includes a boron dopant, or 5 K to 6 K if the second superconducting electrode 104 includes a gallium dopant, or both).

[0024] One skilled in the art will appreciate that the length (e.g., along the "X" axis) of the second superconducting silicon electrode 104 may vary depending on the function of the silicon-based Josephson junction and / or qubit device 100. For example, the length (e.g., along the "X" axis) of the second superconducting silicon electrode 104 may be 10 nm or more and hundreds of microns or less (e.g., 500 nm to 1,000 nm). Similarly, the thickness (e.g., along the "Y" axis) of the second superconducting silicon electrode 104 may vary depending on the function of the silicon-based Josephson junction and / or qubit device 100. For example, the thickness (e.g., along the "Y" axis) of the second superconducting silicon electrode 104 may be 5 nm or more and 500 nm or less (e.g., 10 nm to 50 nm).

[0025] In one or more embodiments, one or more isolation layers 110 may be adjacent to the first superconducting silicon electrode 102, the tunnel barrier 106, or the second superconducting silicon electrode 104, or a combination thereof. The one or more isolation layers 110 may include one or more insulator materials and / or may electrically isolate the silicon-based Josephson junction from adjacent hardware and / or devices (e.g., adjacent qubit devices 100). In various embodiments, the one or more isolation layers 110 may include intrinsic silicon and / or may be deposited in the same fabrication step as the tunnel barrier 106. The one or more isolation layers 110 or at least a portion of the semiconductor substrate 108 or both may define an isolation region 112 (e.g., shown by a bold dashed line in FIG. 1A). As shown in FIG. 1A, in one or more embodiments, the semiconductor substrate 108, the tunnel barrier 106, or the isolation layer 110, or a combination thereof may include the same or nearly the same material (e.g., intrinsic silicon).

[0026] 1A, the first metal contact 114 and / or the second metal contact 116 may be disposed adjacent to the isolation region 112 (e.g., on top of the isolation region 112 if the first superconducting silicon electrode 102, the tunnel barrier 106, and / or the second superconducting silicon electrode 104 are arranged in a stacked vertical orientation). The second metal contact 116 may be operatively coupled (e.g., directly contacting) the second superconducting silicon electrode 104. Additionally, the first metal contact 114 may extend through what would otherwise be a portion of the isolation region 112 that is operatively coupled to the first superconducting silicon electrode 102. The first metal contact 114 or the second metal contact 116, or both, may include a conductive superconductor such as, but not limited to, aluminum (Al), niobium (Nb), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), vanadium (V), tin (Sb), or lead (Pb), or combinations thereof.

[0027] FIG. 1B illustrates a top view of qubit device 100 shown in FIG. 1A and / or illustrates an example arrangement and / or structural configuration of one or more of the features of qubit device 100 along the “Z” axis. Although FIG. 1A and / or FIG. 1B illustrate a qubit device comprising a single Josephson junction disposed on a semiconductor substrate 108, the architecture of qubit device 100 is not so limited. For example, qubit devices 100 comprising multiple Josephson junctions (e.g., multiple first superconducting silicon electrodes 102, tunnel barriers 106, or second superconducting silicon electrodes 104, or combinations thereof) are also contemplated. For example, one or more qubit devices 100 may comprise multiple Josephson junctions including features described herein (e.g., as shown in FIG. 1A or FIG. 1B) and disposed adjacent to one another on a semiconductor substrate 108.

[0028] FIG. 2 illustrates a diagram of an exemplary, non-limiting qubit device 100 during a first stage of fabrication according to one or more embodiments described herein. For the sake of brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the first stage of fabrication, one or more resist masks 202 may be deposited on the semiconductor substrate 108 via one or more deposition processes. The thickness (e.g., along the “Y” axis) of the resist mask 202 may vary, for example, from 100 or more to 1,000 nm or less (e.g., 100 nm to 300 nm). The exposed (e.g., not covered by the resist mask 202) areas of the semiconductor substrate 108 may define one or more boundaries of silicon-based Josephson junctions.

[0029] 3 illustrates a diagram of an exemplary, non-limiting qubit device 100 during a second stage of fabrication according to one or more embodiments described herein. For brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the second stage of fabrication, the first superconducting silicon electrode 102 may be formed, or the resist mask 202 may be removed, or both.

[0030] In one or more embodiments, exposed (e.g., not covered by resist mask 202) areas of semiconductor substrate 108 may be subjected to one or more laser doping processes to form first superconducting silicon electrode 102. For example, exposed areas may be subjected to one or more laser doping processes to drive in boron dopants to form first superconducting silicon electrode 102. In one or more embodiments, first superconducting silicon electrode 102 may be formed by etching a trench in the exposed area of ​​semiconductor substrate 108 (e.g., via one or more etching processes). Then, epitaxial silicon material, such as epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, and / or combinations thereof), may be selectively deposited in the trench via one or more epitaxial growth processes. If the first superconducting silicon electrode 102 is grown via one or more epitaxial growth processes, the thickness (e.g., along the "Y" axis) of the first superconducting silicon electrode 102 may be defined via one or more CMP processes. The resist mask 202 may be removed via one or more etching processes.

[0031] FIG. 4 illustrates a diagram of an exemplary, non-limiting qubit device 100 during a third stage of fabrication according to one or more embodiments described herein. For brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the third stage of fabrication, one or more silicon layers 402 may be deposited on the first superconducting electrode 102 and / or the semiconductor substrate 108 via one or more deposition and / or epitaxial growth processes. In one or more embodiments, the one or more silicon layers 402 may be deposited at low temperatures (e.g., by molecular beam epitaxy ("MBE"), e.g., at temperatures less than 500 degrees Celsius (° C.)) via one or more epitaxial growth processes.

[0032] In one or more embodiments, the one or more silicon layers 402 may then form the tunnel barrier 106 and / or the one or more isolation layers 110. Thereby, the thickness (e.g., along the "Y" axis) of the one or more silicon layers 402 may vary depending on the desired thickness of the tunnel barrier 106, the one or more isolation layers 110, or the second superconducting silicon electrode 104, or a combination thereof. For example, the thickness (e.g., along the "Y" axis) of the one or more silicon layers 402 may range from 5 nm or more to 500 nm or less (e.g., 20 nm to 50 nm).

[0033] 5A and / or 5B show diagrams of an exemplary, non-limiting qubit device 100 during a fourth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 5A shows a cross-sectional view of the qubit device 100 during a fourth stage of fabrication, and / or FIG. 5B shows a top view of the qubit device 100 during a fourth stage of fabrication. During the fourth stage of fabrication, one or more resist masks 202 may be deposited on the one or more silicon layers 402 via one or more deposition processes. The exposed (e.g., not covered by the resist mask 202) areas of the one or more silicon layers 402 may define one or more boundaries of the second superconducting silicon electrodes 104.

[0034] 6A and / or 6B show diagrams of an exemplary, non-limiting qubit device 100 during a fifth stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 6A shows a cross-sectional view of qubit device 100 during a fifth stage of fabrication, and / or FIG. 6B shows a top view of qubit device 100 during a fifth stage of fabrication. During the fifth stage of fabrication, a second superconducting silicon electrode 104 may be formed.

[0035] In one or more embodiments, exposed (e.g., not covered by resist mask 202) areas of one or more silicon layers 402 may be subjected to one or more laser doping processes to form the second superconducting silicon electrode 104. For example, the exposed areas may be subjected to one or more laser doping processes to implant dopants (e.g., boron) to form the second superconducting silicon electrode 104. In one or more embodiments, the second superconducting silicon electrode 104 may be formed by etching (e.g., via one or more etching processes) a trench in the exposed areas of one or more silicon layers 402. An epitaxial silicon material, such as an epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, and / or Ge), may then be selectively deposited in the trench via one or more epitaxial growth processes. If the second superconducting silicon electrode 104 is grown via one or more epitaxial growth processes, the thickness (e.g., along the "Y" axis) of the second superconducting silicon electrode 104 may be defined via one or more CMP processes.

[0036] The formation of the second superconducting silicon electrode 104 may thereby define a tunnel barrier 106 and / or one or more isolation layers 110 from the remaining portions of the one or more silicon layers 402. For example, the portion of the one or more silicon layers 402 remaining between the first and second superconducting silicon electrodes 102 and 104 may be the tunnel barrier 106. For example, the tunnel barrier 106 may comprise intrinsic silicon (e.g., which may act as a dielectric at a critical temperature of about 20 mK). Additionally, the portion of the one or more silicon layers 402 remaining adjacent to the second superconducting silicon electrode 104 and the tunnel barrier 106 may be the one or more isolation layers 110.

[0037] In one or more embodiments, the remaining portion of the silicon layer 402, which may become the tunnel barrier 106, may be doped (e.g., with P and / or As) to form a conventional metallic tunnel barrier 106. For example, the remaining portion of the silicon layer 402, which may become the tunnel barrier 106, may be doped prior to an epitaxial growth process that may form the second superconducting silicon electrode 104.

[0038] 7A and / or 7B show diagrams of an exemplary, non-limiting qubit device 100 during a sixth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 7A shows a cross-sectional view of qubit device 100 during a sixth stage of fabrication, and / or FIG. 7B shows a top view of qubit device 100 during a sixth stage of fabrication. During the sixth stage of fabrication, one or more resist masks 202 may be removed from one or more isolation layers 110 via one or more etching processes.

[0039] 8A and / or 8B show diagrams of an exemplary, non-limiting qubit device 100 during a seventh stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 8A shows a cross-sectional view of qubit device 100 during a seventh stage of fabrication, and / or FIG. 8B shows a top view of qubit device 100 during a seventh stage of fabrication.

[0040] During a seventh stage of fabrication, one or more resist masks 202 may be deposited on the one or more isolation layers 110 and / or the second superconducting silicon electrode 104 via one or more deposition processes. As shown in FIG. 8A and / or FIG. 8B, the resist mask 202 may be deposited to leave a portion of the one or more isolation layers 110 exposed. Further, the exposed portion of the one or more isolation layers 110 (e.g., the portion not covered by the resist mask 202) may be aligned with a portion of the first superconducting silicon electrode 102 along the "Y" axis (e.g., as shown in FIG. 8A).

[0041] 9A and / or 9B show diagrams of an exemplary, non-limiting qubit device 100 during an eighth stage of fabrication in accordance with one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 9A shows a cross-sectional view of qubit device 100 during an eighth stage of fabrication, and / or FIG. 9B shows a top view of qubit device 100 during an eighth stage of fabrication.

[0042] During an eighth stage of fabrication, exposed portions of the one or more isolation layers 110 may be etched away (e.g., via one or more etching processes, such as RIE) to form contact holes 902 in the isolation layers 110, which may extend to the first superconducting silicon electrode 102. As shown in FIG. 9A and / or FIG. 9B, etching the contact holes 902 may expose a portion of the first superconducting silicon electrode 102 (e.g., by removing at least a portion of the isolation layer 110 that previously covered the first superconducting silicon electrode 102). After etching the contact holes 902, the one or more resist masks 202 may be removed (e.g., via one or more etching processes) and / or the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF).

[0043] 10A and / or 10B show diagrams of an exemplary, non-limiting qubit device 100 during a ninth stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG 10A shows a cross-sectional view of qubit device 100 during a ninth stage of fabrication, and / or FIG 10B shows a top view of qubit device 100 during a ninth stage of fabrication.

[0044] During a ninth stage of fabrication, one or more resist masks 202 may be patterned (e.g., via one or more lift-off processes) over the second superconducting silicon electrode 104 and / or isolation layer 110 to facilitate formation of one or more metal contacts and / or incorporation of one or more capacitors and / or resonators for the qubit device 100. As shown in Figures 10A and / or 10B, at least a portion of the first superconducting silicon electrode 102 and / or second superconducting silicon electrode may remain exposed (e.g., uncovered) by the one or more resist masks 202 deposited during the ninth stage of fabrication.

[0045] 11A and / or 11B show diagrams of an exemplary, non-limiting qubit device 100 during a tenth stage of fabrication in accordance with one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG 11A shows a cross-sectional view of qubit device 100 during a tenth stage of fabrication, and / or FIG 11B shows a top view of qubit device 100 during a tenth stage of fabrication.

[0046] During a tenth stage of fabrication, a conductive metal material 1102 may be deposited (e.g., via one or more deposition processes) on exposed surfaces of the qubit device 100 and / or the one or more resist masks 202. After depositing the conductive metal material 1102, the resist mask 202 and the portions of the conductive metal material 1102 disposed on the resist mask 202 may be removed (e.g., via one or more etching processes) to form the first metal contact 114 and / or the second metal contact 116 (e.g., as shown in FIG. 1A and / or FIG. 1B). Thereby, the conductive metal material 1102 may be the same metal contained in the first metal contact 114 and / or the second metal contact 116. As shown in FIG. 11A, the conductive metal material may be deposited in the contact holes 902 such that the conductive metal material is deposited on the first superconducting silicon electrode 102. One skilled in the art will understand that the thickness (e.g., along the “Y” axis) of the conductive metal material 1102 may vary depending on the function of the quantum bit device 100 and / or the structural characteristics of the first metal contact 114 and / or the second metal contact 116.

[0047] 12A and / or 12B show diagrams of an exemplary, non-limiting qubit device 100 having an isolation layer 110, which may include one or more isolation implants, according to one or more embodiments described herein. For brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG 12A shows a cross-sectional view of qubit device 100 including isolation implants, and / or FIG 12B shows a top view of qubit device 100 including isolation implants.

[0048] In one or more embodiments, one or more isolation implants may be incorporated into one or more portions of the one or more silicon layers 402 and / or the semiconductor substrate 108 to form one or more isolation layers 110. Exemplary isolation implants may include, but are not limited to, carbon, oxygen, or nitrogen, or combinations thereof. For example, one or more isolation implants may be incorporated into one or more portions of the one or more silicon layers 402 and / or the semiconductor substrate 108 using one or more plasma immersion processes. In one or more embodiments, the one or more isolation implants may be carbon implants, and acetylene or benzene, or combinations thereof, may be used as the carbon source in the one or more plasma immersion processes. The one or more isolation implants may suppress the electrical conductivity of the one or more isolation layers 110, thereby defining the isolation regions 112. According to various embodiments described herein, the qubit device 100 with isolation implants may include one or more silicon-based Josephson junctions arranged in a stacked vertical orientation. Furthermore, the tunnel barrier 106 of the qubit device 100 with the isolation implant may comprise a dielectric material or a conventional metallic material according to various embodiments described herein.

[0049] FIG. 13 illustrates a diagram of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a first stage of fabrication according to one or more embodiments described herein. For brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. During the first stage of fabrication, a cap layer 1302 may be deposited (e.g., via one or more deposition processes) on a multi-layer structure comprising a semiconductor substrate 108, one or more superconducting silicon layers 1304, or a silicon barrier layer 1306, or a combination thereof. Exemplary materials that may be included within the cap layer 1302 may include, but are not limited to, silicon oxide, silicon nitride, silicon, or CVD carbon, or a combination thereof, and the like. Those skilled in the art will appreciate that the thickness (e.g., along the "Y" axis) of the cap layer 1302 may vary. For example, the thickness (e.g., along the "Y" axis) of the cap layer 1302 may be 5 nm or more and 500 nm or less (e.g., 30 nm to 100 nm).

[0050] As shown in FIG. 13, a silicon barrier layer 1306 may be disposed between one superconducting silicon layer 1304 (e.g., disposed on the semiconductor substrate 108) and another superconducting silicon layer 1304 (e.g., disposed adjacent to the cap layer 1302). In one or more embodiments, the superconducting silicon layer 1304 may go on to constitute the first superconducting silicon electrode 102 or the second superconducting silicon electrode 104 or both in a subsequent fabrication step. Thus, the superconducting silicon layer 1304 may comprise the same material as the first superconducting silicon electrode 102 or the second superconducting silicon electrode 104 or both according to various embodiments described herein. Furthermore, in one or more embodiments, a multi-layer structure may be formed via one or more laser doping processes, epitaxial growth processes, or etching processes according to one or more embodiments described herein (e.g., according to the features shown in FIGS. 2-7B).

[0051] 14A and / or 14B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a second stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 14A shows a cross-sectional view of qubit device 100 with one or more isolation implants during a second stage of fabrication, and / or FIG. 14B shows a top view of qubit device 100 with one or more isolation implants during a second stage of fabrication. During a second stage of fabrication of qubit device 100 with one or more isolation implants, one or more resist layers 202 may be deposited (e.g., via one or more deposition processes) on cap layer 1302. In one or more embodiments, one or more resist layers 202 may cover a portion of cap layer 1302 that is aligned with a boundary to be defined of a silicon-based Josephson junction.

[0052] 15A and / or 15B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a third stage of fabrication according to one or more embodiments described herein. For brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 15A shows a cross-sectional view of qubit device 100 with one or more isolation implants during a third stage of fabrication, and / or FIG. 15B shows a top view of qubit device 100 with one or more isolation implants during a third stage of fabrication. During a third stage of fabrication of qubit device 100 with one or more isolation implants, one or more of the exposed portions of cap layer 1302 (e.g., portions not covered by one or more resist masks 202) may be removed via one or more etching processes (e.g., using dilute hydrofluoric acid ("DHF") and / or oxygen plasma).

[0053] 16A and / or 16B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a fourth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 16A shows a cross-sectional view of qubit device 100 with one or more isolation implants during a fourth stage of fabrication, and / or FIG. 16B shows a top view of qubit device 100 with one or more isolation implants during a fourth stage of fabrication. During a fourth stage of fabrication of qubit device 100 with one or more isolation implants, one or more resist layers 202 may be removed via one or more etching processes to expose remaining portions of cap layer 1302.

[0054] 17A and / or 17B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a fifth stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 17A shows a cross-sectional view of qubit device 100 with one or more isolation implants during a fifth stage of fabrication, and / or FIG. 17B shows a top view of qubit device 100 with one or more isolation implants during a fifth stage of fabrication.

[0055] During a fifth stage of fabrication of qubit device 100 comprising one or more isolation implants, cap layer 1302 or one or more portions of the multilayer stack (e.g., comprising one or more superconducting silicon layers 1304 or silicon barrier layer 1306 or both) may be subjected to a first plasma dip 1702 with one or more isolation implant sources. For example, if the one or more isolation implants are carbon, cap layer 1302 or one or more portions of the multilayer stack or both may be subjected to a first plasma dip 1702 with one or more carbon sources, such as acetylene or benzene or both. As shown in FIG. 17A and / or FIG. 17B, cap layer 1302 or one or more portions of the multilayer stack or both may be saturated with an isolation implant source (e.g., a carbon source, such as acetylene or benzene or both).

[0056] In various embodiments, the portion or portions of the multi-layer stack to which the first plasma immersion 1702 is applied may be the isolation region 112 of the qubit device 100. The first plasma immersion 1702 may thereby define one or more boundaries of one or more Josephson junctions included within the qubit device 100. For example, the first plasma immersion 1702 may define the structural boundaries of the first superconducting silicon electrode 102 and / or the tunnel barrier 106 (e.g., as shown in FIG. 17A ).

[0057] 18A and / or 18B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a sixth stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 18A shows a cross-sectional view of qubit device 100 with one or more isolation implants during a sixth stage of fabrication, and / or FIG. 18B shows a top view of qubit device 100 with one or more isolation implants during a sixth stage of fabrication.

[0058] During a sixth stage of fabrication of qubit device 100 with one or more isolation implants, the portion of qubit device 100 saturated with the isolation implant source may be annealed (e.g., laser annealed) to drive in the isolation implants (e.g., and / or reduce lattice damage). For example, the laser anneal may melt silicon in the irradiated area, and a pulsing time may be established based on how much silicon is desired to melt. For example, in one or more embodiments, isolation region 112 may be annealed (e.g., laser annealed) to form one or more isolation layers 110 that may suppress electrical conductivity in isolation region 112. For example, in various embodiments, isolation region 112 may be saturated with a carbon source in a fifth stage and laser annealed in a sixth stage to drive in one or more carbon isolation implants in isolation region 112 and form one or more isolation layers 110. As shown in FIG. 18A and / or FIG. 18B, the cap layer 1302 may protect the superconducting silicon layer 1304, the tunnel barrier 106, and / or the first superconducting silicon electrode 102 from being hit with an isolation implant during the sixth stage.

[0059] 19A and / or 19B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a seventh stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 19A shows a cross-sectional view of qubit device 100 with one or more isolation implants during a seventh stage of fabrication, and / or FIG. 19B shows a top view of qubit device 100 with one or more isolation implants during a seventh stage of fabrication.

[0060] During a seventh stage of fabrication of qubit device 100 including one or more isolation implants, one or more resist layers 202 may be deposited (e.g., via one or more deposition processes) on cap layer 1302. In one or more embodiments, one or more resist layers 202 may cover a portion of cap layer 1302 that is aligned with a boundary of second superconducting silicon electrode 104 to be defined.

[0061] 20A and / or 20B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during an eighth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 20A shows a cross-sectional view of qubit device 100 with one or more isolation implants during an eighth stage of fabrication, or FIG. 20B shows a top view of qubit device 100 with one or more isolation implants during an eighth stage of fabrication. During an eighth stage of fabrication of qubit device 100 with one or more isolation implants, one or more of the exposed portions of cap layer 1302 (e.g., portions not covered by one or more resist masks 202) may be removed via one or more etching processes (e.g., using DHF). Thereafter, remaining portions of one or more resist masks 202 may be removed. Thereby, the remaining portion of the cap layer 1302 may be positioned above (eg, along the "Y" axis) the location of the second superconducting silicon electrode 104 to be defined.

[0062] 21A and / or 21B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a ninth stage of fabrication according to one or more embodiments described herein. For brevity, repetitive descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 21A shows a cross-sectional view of qubit device 100 with one or more isolation implants during a ninth stage of fabrication, or FIG. 21B shows a top view of qubit device 100 with one or more isolation implants during a ninth stage of fabrication.

[0063] During a ninth stage of fabrication of qubit device 100 including one or more isolation implants, cap layer 1302 and / or one or more portions of remaining superconducting silicon layer 1304 may be subjected to a second plasma dip 2102 with one or more isolation implant sources. For example, if the one or more isolation implants are carbon, cap layer 1302 and / or one or more portions of superconducting silicon layer 1304 may be subjected to a second plasma dip 2102 with one or more carbon sources, such as acetylene or benzene or both. As shown in FIG. 21A and / or FIG. 21B, cap layer 1302 and / or one or more portions of superconducting silicon layer 1304 may be saturated with an isolation implant source (e.g., a carbon source, such as acetylene or benzene or both). In various embodiments, one or more portions of the superconducting silicon layer 1304 to which the second plasma immersion 2102 is applied may extend the separation region 112 (e.g., shown by the bold dashed line in FIG. 21A ) of the qubit device 100. The second plasma immersion 2102 may thereby define one or more boundaries of the second superconducting silicon electrode 104 (e.g., as shown in FIG. 21A and / or FIG. 21B ).

[0064] 22A and / or 22B show diagrams of an exemplary, non-limiting qubit device 100 with one or more isolation implants during a tenth stage of fabrication in accordance with one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 22A may show a cross-sectional view of qubit device 100 with one or more isolation implants during a tenth stage of fabrication, and / or FIG. 22B may show a top view of qubit device 100 with one or more isolation implants during a tenth stage of fabrication.

[0065] During a tenth stage of fabrication of qubit device 100 comprising one or more isolation implants, the portion of qubit device 100 saturated with the isolation implant source may be annealed (e.g., laser annealed) to drive in the isolation implants. For example, in one or more embodiments, isolation region 112 may be annealed (e.g., laser annealed) to form one or more isolation layers 110 that may suppress electrical conductivity in isolation region 112. For example, in various embodiments, isolation region 112 may be saturated with a carbon source in a ninth stage and laser annealed in a tenth stage to drive in one or more carbon isolation implants into isolation region 112 to extend one or more isolation layers 110. As shown in FIG. 22A and / or FIG. 22B, cap layer 1302 may protect second superconducting silicon electrode 104 from being driven in with the isolation implants during the tenth stage. Further, in one or more embodiments, the tunnel barrier 106 and / or the first superconducting silicon electrode 102 may be left unimplanted with an isolation implant during the tenth stage to control the depth of saturation (e.g., along the "Y" axis) of the isolation implant source during the ninth stage of fabrication, and thereby the depth of isolation implant incorporation (e.g., along the "Y" axis) during the tenth stage of fabrication.

[0066] 23A and / or 23B show diagrams of an exemplary, non-limiting qubit device 100 during an eleventh stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 23A may show a cross-sectional view of qubit device 100 during an eleventh stage of fabrication, and / or FIG. 23B may show a top view of qubit device 100 during an eleventh stage of fabrication.

[0067] During an eleventh stage of fabrication, one or more resist masks 202 may be deposited on one or more isolation layers 110 and / or cap layer 1302 via one or more deposition processes. As shown in FIG. 23A and / or FIG. 23B, the resist mask 202 may be deposited to leave a portion of the one or more isolation layers 110 exposed. Further, the exposed portion of the one or more isolation layers 110 (e.g., the portion not covered by the resist mask 202) may be aligned with a portion of the first superconducting silicon electrode 102 along the "Y" axis (e.g., as shown in FIG. 23A).

[0068] 24A and / or 24B show diagrams of an exemplary, non-limiting qubit device 100 during a twelfth stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 24A shows a cross-sectional view of qubit device 100 during a twelfth stage of fabrication, and / or FIG. 24B shows a top view of qubit device 100 during a twelfth stage of fabrication.

[0069] During a twelfth stage of fabrication, exposed portions of the one or more isolation layers 110 may be etched away (e.g., via one or more etching processes, such as RIE) to form contact holes 902 in the isolation layers 110, which may extend to the first superconducting silicon electrode 102. As shown in FIG. 9A and / or FIG. 9B, etching the contact holes 902 may expose a portion of the first superconducting silicon electrode 102 (e.g., by removing at least a portion of the isolation layer 110 and / or tunnel barrier 106 that previously covered the first superconducting silicon electrode 102). After etching the contact holes 902, the one or more resist masks 202 may be removed (e.g., via one or more etching processes) and / or the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF).

[0070] FIG. 25A and / or FIG. 25B show diagrams of an exemplary, non-limiting qubit device 100 during a thirteenth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 25A shows a cross-sectional view of the qubit device 100 during a thirteenth stage of fabrication, and / or FIG. 25B shows a top view of the qubit device 100 during a thirteenth stage of fabrication. During the thirteenth stage of fabrication, the cap layer 1302 may be etched away (e.g., via one or more etching processes, such as RIE) to expose the second superconducting silicon electrode 104. Additionally, the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF).

[0071] FIGURE 26A and / or FIGURE 26B show diagrams of an exemplary, non-limiting qubit device 100 during a fourteenth stage of fabrication, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIGURE 26A shows a cross-sectional view of qubit device 100 during a fourteenth stage of fabrication, and / or FIGURE 26B shows a top view of qubit device 100 during a fourteenth stage of fabrication.

[0072] During a fourteenth stage of fabrication, one or more resist masks 202 may be patterned (e.g., via one or more lift-off processes) over the second superconducting silicon electrode 104 and / or isolation layer 110 to facilitate formation of one or more metal contacts and / or incorporation of one or more capacitors and / or resonators for the qubit device 100. As shown in Figure 26A and / or 26B, at least a portion of the first superconducting silicon electrode 102 and / or second superconducting silicon electrode may remain exposed (e.g., uncovered) by the one or more resist masks 202.

[0073] 27A and / or 27B show diagrams of an exemplary, non-limiting qubit device 100 during a fifteenth stage of fabrication in accordance with one or more embodiments described herein. For brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted. FIG. 27A shows a cross-sectional view of qubit device 100 during a fifteenth stage of fabrication, and / or FIG. 27B shows a top view of qubit device 100 during a fifteenth stage of fabrication.

[0074] During the fifteenth stage of fabrication, a conductive metal material 1102 may be deposited (e.g., via one or more deposition processes) on exposed surfaces of the qubit device 100 and / or the one or more resist masks 202. After depositing the conductive metal material 1102, the resist mask 202 and the portions of the conductive metal material 1102 disposed on the resist mask 202 may be removed (e.g., via one or more etching processes) to form the first metal contact 114 and / or the second metal contact 116 (e.g., as shown in FIG. 12A and / or FIG. 12B). Thereby, the conductive metal material 1102 may be the same metal contained in the first metal contact 114 and / or the second metal contact 116. As shown in FIG. 27A, the conductive metal material may be deposited in the contact holes 902 such that the conductive metal material is deposited on the first superconducting silicon electrode 102. One skilled in the art will understand that the thickness (e.g., along the “Y” axis) of the conductive metal material 1102 may vary depending on the function of the quantum bit device 100 and / or the structural characteristics of the first metal contact 114 and / or the second metal contact 116.

[0075] 28 illustrates a flow diagram of an example, non-limiting method 2800 that may facilitate fabrication of one or more qubit devices 100 comprising one or more silicon-based Josephson junctions in accordance with one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted.

[0076] At 2802, the method 2800 may include doping a portion of the semiconductor substrate 108 to form a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, the doping at 2802 may be performed according to at least the second stage of fabrication shown in Figure 3. For example, the first superconducting electrode may be the first superconducting silicon electrode 102, or the doping may include one or more laser doping processes according to one or more embodiments described herein, or both.

[0077] At 2804, the method 2800 may include depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form the tunnel barrier 106. For example, the deposition at 2804 may be performed according to at least the third stage of fabrication illustrated in FIG. 4. For example, in one or more embodiments, the deposition at 2804 may grow a layer of intrinsic silicon that may act as a dielectric tunnel barrier 106 of a silicon-based Josephson junction during operation of the qubit device 100 at near-zero temperatures. In another example, the deposition at 2804 may further include doping one or more portions of the deposited silicon layer to form a regular metallic tunnel barrier 106 according to one or more embodiments described herein.

[0078] At 2806, the method 2800 may include doping one or more portions of the tunnel barrier 106 to form a second superconducting electrode (e.g., the second superconducting silicon electrode 104) to form a Josephson junction. For example, the doping at 2806 may be performed according to at least the fifth stage of fabrication shown in FIG. 6A and / or FIG. 6B. For example, the second superconducting electrode may be the second superconducting silicon electrode 104, or the doping may include one or more laser doping processes according to one or more embodiments described herein, or both. In various embodiments, the Josephson junction formed by the method 2800 may be a silicon-based Josephson junction comprising a superconducting silicon electrode. Additionally, the superconducting silicon electrodes may be stacked in a vertical orientation. Additionally, in one or more embodiments, the tunnel barrier 106 may be a dielectric tunnel barrier comprising intrinsic silicon.

[0079] 29 illustrates a flow diagram of an exemplary, non-limiting method 2900 that may facilitate fabrication of one or more qubit devices 100 comprising one or more silicon-based Josephson junctions electrically isolated via one or more isolation layers 110, which may include one or more isolation implants, in accordance with one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted.

[0080] At 2902, the method 2900 may include doping a portion of the semiconductor substrate 108 to form a first superconducting electrode (e.g., the first superconducting silicon electrode 102). For example, the doping at 2902 may be performed according to at least the second stage of fabrication shown in Figure 3. For example, the first superconducting electrode may be the first superconducting silicon electrode 102, or the doping may include one or more laser doping processes according to one or more embodiments described herein, or both.

[0081] At 2904, the method 2900 may include depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form the tunnel barrier 106. For example, the deposition at 2904 may be performed according to at least the third stage of fabrication illustrated in FIG. 4. For example, in one or more embodiments, the deposition at 2904 may grow a layer of intrinsic silicon that may act as a dielectric tunnel barrier 106 of a silicon-based Josephson junction during operation of the qubit device 100 at near-zero temperatures. In another example, the deposition at 2904 may further include doping one or more portions of the deposited silicon layer to form a regular metallic tunnel barrier 106 according to one or more embodiments described herein.

[0082] At 2906, method 2900 may include doping one or more portions of tunnel barrier 106 to form a second superconducting electrode (e.g., second superconducting silicon electrode 104) to form a Josephson junction. For example, doping at 2806 may be performed according to at least the fifth stage of fabrication shown in FIG. 6A and / or FIG. 6B. For example, the second superconducting electrode may be second superconducting silicon electrode 104, or the doping may include one or more laser doping processes according to one or more embodiments described herein, or both. In various embodiments, the Josephson junction formed in method 2906 may be a multi-layer stack structure, such as the multi-layer stack shown in FIG. 13, and one or more subsequent fabrication steps may further define one or more structural features of the Josephson junction, or may electrically isolate the Josephson junction via incorporation of an isolation implant, or both.

[0083] At 2908, the method 2900 may include forming an isolation region 112 from the Josephson junction through plasma immersion of one or more isolation implants into portions of the first superconducting electrode (e.g., the first superconducting silicon electrode 102), the tunnel barrier 106, and the second superconducting electrode (e.g., the second superconducting silicon electrode 104). For example, forming the isolation region at 2908 may be performed according to the fifth through tenth stages of fabrication shown in Figures 17A through 22B. For example, forming the isolation region at 2908 may include one or more plasma immersion and / or annealing processes according to one or more embodiments described herein.

[0084] At 2910, the method 2900 may include forming a contact hole 902 in the isolation region 112, which may extend to a first superconducting electrode (e.g., the first superconducting silicon electrode 102). For example, forming the contact hole 902 may be performed according to the eleventh to twelfth stages of fabrication shown in Figures 23A to 24B.

[0085] At 2912, the method 2900 may include depositing a first metal layer (e.g., conductive metal material 1102) in the contact hole 902 to form a first metal contact 114 operably coupled to the first superconducting electrode (e.g., first superconducting silicon electrode 102). For example, forming the first metal contact 114 at 2912 may be performed according to the fourteenth and / or fifteenth stages of fabrication shown in Figures 26A-27B and / or 12A-12B.

[0086] At 2914, the method 2900 may include depositing a second metal layer (e.g., the conductive metal material 1102) on the second superconducting electrode (e.g., the second superconducting silicon electrode 104) to form a second metal contact 116 operably coupled to the second superconducting electrode (e.g., the second superconducting silicon electrode 104). For example, forming the first metal contact 114 at 2914 may be performed according to the fourteenth and / or fifteenth stages of fabrication shown in Figures 26A-27B and / or 12A-12B.

[0087] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X utilizes A or B" is intended to mean any of the natural inclusive permutations. That is, if X utilizes A, X utilizes B, or X utilizes both A and B, then "X utilizes A or B" is met under any of the above examples. Furthermore, the articles "a" and "an" as used herein and in the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from the context that the singular form is intended. As used herein, the terms "example" and / or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Moreover, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not meant to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0088] Of course, it is not impossible to describe every conceivable combination of components, products, or methods to describe the present disclosure, but one of ordinary skill in the art will appreciate that many other combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "comprising," "having," "owning," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as "comprising" is interpreted when utilized as a transitional term in the claims. Although descriptions of various embodiments have been presented for illustrative purposes, the descriptions are not intended to be exhaustive and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best describe the principles of the embodiments, practical applications or technical improvements over the art found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein. The present disclosure also discloses the following inventions. <Appendix 1> A Josephson junction containing a tunnel barrier disposed between two vertically stacked superconducting silicon electrodes. An apparatus comprising: <Appendix 2> 2. The apparatus of claim 1, wherein the two vertically stacked superconducting silicon electrodes comprise silicon doped with at least one dopant selected from the group consisting of boron, gallium, and germanium. <Appendix 3> 3. The apparatus of claim 2, wherein the at least one dopant is boron and the two vertically stacked superconducting silicon electrodes each contain greater than 4 atomic percent boron and less than or equal to 11 atomic percent boron. <Appendix 4> a first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; a second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; an isolation layer disposed on the tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, the isolation layer including a carbon implant in silicon; 4. The apparatus of any one of claims 1 to 3, further comprising: <Appendix 5> a first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; a second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; an isolation layer disposed on the tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, the isolation layer comprising intrinsic silicon; and 5. The apparatus of any one of claims 1 to 4, further comprising: <Appendix 6> 6. The device of any one of claims 1 to 5, wherein the tunnel barrier is doped with at least one dopant selected from the group consisting of phosphorus and arsenic. <Appendix 7> 7. The device of any one of claims 1 to 6, wherein the tunnel barrier comprises intrinsic crystalline silicon. <Appendix 8> Josephson junctions containing a dielectric tunnel barrier placed between two superconducting silicon electrodes. An apparatus comprising: <Appendix 9> 9. The apparatus of claim 8, wherein the two superconducting silicon electrodes comprise silicon doped with at least one dopant selected from the group consisting of boron, germanium, and gallium. <Appendix 10> 10. The apparatus of claim 9, wherein the at least one dopant is boron and the two superconducting silicon electrodes each contain greater than 4 atomic percent boron and less than or equal to 11 atomic percent boron. <Appendix 11> a first metal contact operably coupled to a first superconducting silicon electrode from the two superconducting silicon electrodes; a second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes; an isolation layer disposed on the dielectric tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, the isolation layer including a carbon implant in silicon; 11. The apparatus of any one of claims 8 to 10, further comprising: <Appendix 12> a first metal contact operably coupled to a first superconducting silicon electrode from the two superconducting silicon electrodes; a second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes; an isolation layer disposed on the dielectric tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, the isolation layer comprising intrinsic silicon; and 12. The apparatus of any one of claims 8 to 11, further comprising: <Appendix 13> 13. The device of any one of claims 8 to 12, wherein the dielectric tunnel barrier comprises intrinsic crystalline silicon. <Appendix 14> 14. The apparatus of any one of claims 8 to 13, wherein the two superconducting silicon electrodes and the dielectric tunnel barrier are vertically stacked on a dielectric substrate. <Appendix 15> doping a portion of a silicon substrate to form a first superconducting electrode; depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier; doping a portion of said tunnel barrier to form a second superconducting electrode to form a Josephson junction; The method includes: <Appendix 16> 16. The method of claim 15, wherein a first dopant applied by doping the portion of the silicon substrate and a second dopant applied by doping the portion of the silicon layer are at least one member selected from the group consisting of boron, gallium, and germanium. <Appendix 17> forming an isolation region from said Josephson junction through plasma immersion of an isolation implant into portions of said first superconducting electrode, said tunnel barrier, and said second superconducting electrode; 17. The method of claim 15 or 16, further comprising: <Appendix 18> forming a contact hole in the isolation region extending to the first superconducting electrode; depositing a first metal layer into the contact hole to form a first metal contact operably coupled to the first superconducting electrode; depositing a second metallic layer over the second superconducting electrode to form a second metallic contact operably coupled to the second superconducting electrode; 18. The method of claim 17, further comprising: <Appendix 19> 19. The method of any one of claims 15 to 18, wherein the undoped portion of the silicon substrate and the undoped portion of the silicon layer define an isolation region adjacent to the Josephson junction. <Appendix 20> forming a contact hole in the isolation region extending to the first superconducting electrode; depositing a first metal layer into the contact hole to form a first metal contact operably coupled to the first superconducting electrode; depositing a second metallic layer over the second superconducting electrode to form a second metallic contact operably coupled to the second superconducting electrode; 20. The method of claim 19, further comprising:

Claims

1. a Josephson junction including a tunnel barrier disposed between two vertically stacked superconducting silicon electrodes, the two vertically stacked superconducting silicon electrodes including a first superconducting electrode and a second superconducting electrode underlying the first superconducting electrode; an isolation layer, the isolation layer having a boundary with the first superconducting electrode defined by an isolation implant incorporated into the material of the first superconducting electrode, the isolation layer being disposed on the tunnel barrier so as to electrically isolate a first side of the first superconducting electrode at the boundary and a second side of the first superconducting electrode from adjacent devices, the isolation layer being connected to the first side of the first superconducting electrode and the second side of the first superconducting electrode, the first side being opposite the second side; An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the two vertically stacked superconducting silicon electrodes comprise silicon doped with at least one dopant selected from the group consisting of boron, gallium, and germanium.

3. 3. The apparatus of claim 2, wherein said at least one dopant is boron and said two vertically stacked superconducting silicon electrodes each contain greater than 4 atomic percent boron and less than or equal to 11 atomic percent boron.

4. a first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; a second metal contact operatively coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes; the isolation layer disposed on the tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, the isolation implant including a carbon implant in silicon; The apparatus of claim 1 , further comprising:

5. 5. The device of claim 1, wherein the tunnel barrier is doped with at least one dopant selected from the group consisting of phosphorus and arsenic.

6. 6. The device of claim 1, wherein the tunnel barrier comprises intrinsic crystalline silicon.

7. a Josephson junction including a dielectric tunnel barrier disposed between two superconducting silicon electrodes, the two superconducting silicon electrodes including a first superconducting electrode and a second superconducting electrode underlying the first superconducting electrode; an isolation layer, the isolation layer having a boundary with the first superconducting electrode defined by an isolation implant incorporated into the material of the first superconducting electrode, the isolation layer being disposed on the dielectric tunnel barrier so as to electrically isolate a first side of the first superconducting electrode at the boundary and a second side of the first superconducting electrode from adjacent devices, the isolation layer being connected to the first side of the first superconducting electrode and the second side of the first superconducting electrode, the first side being opposite the second side; An apparatus comprising:

8. 8. The apparatus of claim 7, wherein the two superconducting silicon electrodes comprise silicon doped with at least one dopant selected from the group consisting of boron, germanium, and gallium.

9. 9. The apparatus of claim 8, wherein the at least one dopant is boron and the two superconducting silicon electrodes each contain greater than 4 atomic percent boron and less than or equal to 11 atomic percent boron.

10. a first metal contact operably coupled to a first superconducting silicon electrode from the two superconducting silicon electrodes; a second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes; the isolation layer disposed on the dielectric tunnel barrier such that the isolation layer electrically isolates the first metal contact from the second metal contact, the isolation implant including a carbon implant in silicon; 10. The apparatus of claim 7, further comprising:

11. 11. The device of claim 7, wherein the dielectric tunnel barrier comprises intrinsic crystalline silicon.

12. 12. The device of claim 7, wherein the two superconducting silicon electrodes and the dielectric tunnel barrier are vertically stacked on a dielectric substrate.

Images