Cryogenic refrigeration for cryogenic devices

Abstract

An active cooling structure is provided that includes a non-superconducting layer, a superconducting layer, and an array of superconductor-insulator-normal metal (NIS) tunnel junctions. The non-superconducting layer can include a plurality of non-superconducting traces. The superconducting layer can include a plurality of superconducting traces. The array of superconductor-insulator-normal metal (NIS) tunnel junctions can be disposed between the plurality of non-superconducting traces and the plurality of superconducting traces.

Description

[Technical Field]

[0001] Disclosed herein are cooling apparatus and methods of manufacture for low temperature electronic devices, and more particularly active cooling for low temperature and cryogenic superconducting devices. [Background technology]

[0002] Molecules and subatomic particles are subject to the laws of quantum mechanics, a branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave strangely, existing in more than one state simultaneously, and interacting with other particles at great distances. Quantum computing harnesses these quantum phenomena to process information.

[0003] Many quantum devices suitable for use in quantum computing require low or cryogenic temperatures to function. If temperatures increase beyond these levels, errors will be introduced into the quantum computing process. However, conventional vapor compression refrigerators are bulky, expensive, and not entirely reliable for maintaining arrays of devices at these temperatures. Summary of the Invention

[0004] According to one or more embodiments, an active cooling structure includes a non-superconducting layer, a superconducting layer, and an array of superconductor-insulator-normal metal (NIS) tunnel junctions. The non-superconducting layer can include a plurality of non-superconducting traces. The superconducting layer can include a plurality of superconducting traces. The array of superconductor-insulator-normal metal (NIS) tunnel junctions can be disposed between the plurality of non-superconducting traces and the plurality of superconducting traces.

[0005] According to one or more embodiments, a quantum processor includes a first substrate, a plurality of qubits formed on the first substrate, and an active cooling structure in thermal communication with the qubits. The active cooling structure can include a non-superconducting layer, a superconductor layer, and an insulator layer between the non-superconducting layer and the superconductor layer.

[0006] The quantum processor may further include, for example, at least one or more of the following features.

[0007] The active cooling structure can include a grid of superconductor-insulator-normal metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer can include a plurality of non-superconducting traces extending in a first direction, and the superconductor layer can include a plurality of superconducting traces extending in a second direction. The plurality of superconducting traces and the plurality of non-superconducting traces can intersect at a plurality of locations in the XY plane.

[0008] The non-superconducting layer may comprise silver, the insulator layer may be selected from the group consisting of silicon dioxide and hafnium dioxide, and the superconductor layer may be selected from the group consisting of aluminum and niobium.

[0009] According to one or more embodiments, a method of cryogenically cooling a quantum processor includes applying a voltage to an active cooling structure in thermal communication with the quantum processor, the active cooling structure may include a non-superconducting layer, a superconductor layer, and an insulator layer between the non-superconducting layer and the superconductor layer.

[0010] According to one or more embodiments, a method for fabricating an active cooling structure is provided that includes forming an array of superconductor-insulator-normal-metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer can include a plurality of non-superconducting traces extending in a first direction. The superconductor layer can include a plurality of superconducting traces extending in a second direction.

[0011] The method for manufacturing an active cooling structure may further include, for example, at least one or more of the following features.

[0012] The manufacturing method can include forming a first plurality of pads that electrically connect a plurality of superconducting traces in parallel, and forming a second plurality of pads that electrically connect non-superconducting traces in parallel.

[0013] The manufacturing method can include applying a photoresist layer to a substrate, exposing the photoresist layer to a pattern to produce exposed and unexposed photoresist, removing the exposed photoresist layer, applying a metal layer over the unexposed photoresist and the substrate, and removing the unexposed photoresist.

[0014] The method can include forming an insulator layer on the non-superconducting layer.

[0015] The manufacturing method can include applying a lift-off resist layer to an insulator layer, exposing the lift-off resist layer to a pattern to generate exposed lift-off resist and unexposed lift-off resist, removing the exposed lift-off resist layer, applying a superconducting layer onto the unexposed lift-off resist layer and the insulator layer, and removing the unexposed lift-off resist.

[0016] According to one or more embodiments, a method of manufacturing a quantum processor is provided that includes forming a plurality of qubits formed on a first substrate and forming an active cooling structure in thermal communication with the qubits. The active cooling structure can include a non-superconducting metal layer, an insulator layer formed on the non-superconducting layer, and a superconductor layer formed on the insulator layer.

[0017] The manufacturing method for a quantum processor may further include, for example, at least one or more of the following features.

[0018] The manufacturing method can include applying a photoresist layer to a substrate, exposing the photoresist layer to a pattern to produce exposed and unexposed photoresist, removing the exposed photoresist layer, applying a metal layer over the unexposed photoresist and the substrate, and removing the unexposed photoresist.

[0019] The method can include forming an insulator layer on the non-superconducting layer.

[0020] The manufacturing method can include applying a lift-off resist layer to an insulator layer, exposing the lift-off resist layer to a pattern to generate exposed lift-off resist and unexposed lift-off resist, removing the exposed lift-off resist layer, applying a superconducting layer onto the unexposed lift-off resist layer and the insulator layer, and removing the unexposed lift-off resist.

[0021] According to one or more embodiments, a semiconductor manufacturing system for fabricating a thermalized structure is provided. The semiconductor manufacturing system can include a computer-readable storage medium encoded with a set of instructions for a manufacturing facility that, when operated by a processor, causes the manufacturing facility to perform a manufacturing method. The manufacturing method can include forming an array of superconductor-insulator-normal-metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer can include a plurality of non-superconducting traces extending in a first direction, and the superconductor layer can include a plurality of superconducting traces extending in a second direction.

[0022] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0023] The drawings included in this application are incorporated into and form a part of this specification. These drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings are merely illustrative of particular embodiments and are not intended to limit the disclosure. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a block diagram of a network of data processing systems consistent with some embodiments; [Figure 2] 2A and 2B are top and side views of an exemplary active planar cooling structure consistent with some embodiments, respectively, and a cross-sectional view of the exemplary cooling structure of FIG. [Figure 2C] FIG. 1 illustrates another exemplary active planar cooling structure consistent with some embodiments. [Figure 3A] FIG. 1 illustrates an exemplary actively cooled quantum processor consistent with some embodiments. [Figure 3B] FIG. 1 illustrates another exemplary actively cooled quantum processor consistent with some embodiments. [Figure 4] FIG. 1 illustrates another exemplary actively cooled quantum processor consistent with some embodiments. [Figure 5] FIG. 1 illustrates another exemplary actively cooled quantum processor consistent with some embodiments. [Figure 6] 1A and 1B illustrate another exemplary actively cooled quantum processor consistent with some embodiments; [Figure 7] 1A-1D are cross-sectional views of a device illustrating the device at various stages of an exemplary process for fabricating an active planar quantum cooling structure consistent with some embodiments. [Figure 8] FIG. 1 illustrates an exemplary computer-implemented process for fabricating an active planar quantum cooling structure consistent with some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0025] While the invention is susceptible to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

[0026] The "low temperature" range, as used herein, refers to the cryogenic temperature range beginning at or about 77 Kelvin (K). "Cryogenic" begins at or about 10 Kelvin and extends down to at least 1 milliKelvin (0.001 K), and in some cases as low as possible using available technology, currently reaching approximately 0.000001 K.

[0027] A "low temperature device" (LTD) is a device that operates in the low temperature or cryogenic range. Most LTDs that operate at low or extreme temperatures rely on materials that exhibit superconducting properties at those temperatures.

[0028] overview Aspects of the present disclosure relate to cooling apparatus and manufacturing methods for low-temperature electronic devices, and more particular aspects relate to active cooling for low-temperature and cryogenic superconducting devices. While the present disclosure is not necessarily limited to such applications, various aspects of the present disclosure may be understood through a discussion of various examples using this context.

[0029] LTD devices, including superconducting devices, generate heat during operation, but heat removal in such cryogenic temperature ranges presents unique challenges.

[0030] Some embodiments package an active solid-state cooling device near or in contact with the LTD device within the cooling chamber of the dilution refrigerator to help maintain the LTD device at low or cryogenic temperatures. Some embodiments may also eliminate some of the other cooling structures, improving overall reliability.

[0031] Quantum Computing Most computers in use today are known as classical computers. Classical computers use conventional processors fabricated with semiconductor materials and technologies, semiconductor memory, and magnetic or solid-state storage devices in what is known as the von Neumann architecture. Notably, the processor in a classical computer is a binary processor, i.e., it operates on binary data represented by 1s and 0s. Quantum processors (q-processors), in contrast, use the exotic properties of entangled quantum bit devices (referred to herein simply as "qubits") to perform computational tasks. In the specific domain where quantum mechanics operates, particles of matter can exist in multiple states, such as "on" states, "off" states, and both "on" and "off" states simultaneously. While binary computing using semiconductor processors is limited to using only on and off states (equivalent to 1s and 0s in binary code), quantum processors utilize these quantum states of matter to output signals usable for data computing.

[0032] Classical computers encode information with bits. Each bit can have a value of 1 or 0. These 1s and 0s ultimately act as on / off switches that drive computer functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both a 1 and a 0 simultaneously. Entanglement means that qubits in superposition can correlate with each other in a nonclassical way—that is, the state of one (whether 1, 0, or both) can depend on the state of the other—and that more information can be ascertained about two qubits when they are entangled than when they are treated individually.

[0033] Using these two principles, qubits act as more sophisticated processors of information, allowing quantum computers to function in such a way that they can solve difficult problems that are intractable using classical computers.

[0034] Superconducting qubits generally use one or more layers of different materials to implement device properties and functionality. The layers of material may be superconducting, conductive, semiconductive, insulating, resistive, inductive, capacitive, or have any number of other properties. Different layers of material may have to be formed using different methods, taking into account the properties of the material, the shape, size, or placement of the material, other materials adjacent to the material, and many other considerations.

[0035] Most quantum devices suitable for use as qubits in quantum computing require low or cryogenic temperatures to function.

[0036] Data Processing Environment 1 illustrates a block diagram of a network of data processing environments in which exemplary embodiments may be implemented. Data processing environment 100 is a network of computers in which exemplary embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is the medium used to provide communications links between the various devices and computers connected to each other within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0037] Data processing environment 100 includes multiple clients 110, 112, 114, and 132 and multiple servers 104 and 106 communicatively coupled to storage unit 108 via network 102. Clients 110, 112, and 114, servers 104 and 106, and storage unit 108 shown in FIG. 1 are devices described only in their exemplary roles as particular data processing systems connected to network 102 and are not intended to exclude other configurations or roles of these data processing systems. Any of the components within data processing environment 100, such as servers 104 or 106 or clients 110, 112, 114, or 132, can contain data and can have software applications and / or tools 105 executing thereon.

[0038] Device 132 and client 114 are examples of client devices. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a wearable computing device, an appliance, or any other suitable device. Software applications and / or tools 105 described as executing in another data processing system in FIG. 1 may, in some embodiments, be configured to execute in a similar manner in device 132. Data or information stored or generated in another data processing system in FIG. 1 may, in some embodiments, be configured to be stored or generated in a similar manner in device 132.

[0039] Photolithography application 105a can be used to implement or partially implement some embodiments described herein. In these embodiments, photolithography application 105a is a software component of a system for fabricating active planar cooling structures, Josephson junctions, qubits, or other superconducting structures, or combinations thereof, used in quantum computing devices. Photolithography application 105a provides instructions to such a fabrication system for effecting the assembly of several novel cryogenic methods and systems contemplated in some embodiments described herein.

[0040] cooling structure FIG. 2(A) illustrates a top view of an exemplary active planar cooling structure 200 consistent with some embodiments. FIG. 2(B) illustrates the exemplary cooling structure 200 of FIG. 2(A) cut along line B. The embodiment of the cooling structure 200 of FIGS. 2(A) and 2(B) includes a superconductor layer 210 and a normal metal (i.e., non-superconducting) layer 220 separated by an insulator layer 230. The superconductor layer 210 in some embodiments is formed into a plurality of generally parallel superconductor traces 212 (only some of which are labeled for clarity) extending in a first direction (the Y-direction as shown). The superconductor traces 212 may be electrically connected to common pads 214a and 214b. The normal metal layer 220 is similarly formed into a plurality of generally parallel normal metal traces 222 (only some of which are labeled for clarity) extending in a second direction (the X-direction as shown) orthogonal to the first direction. Normal metal trace 222 is electrically connected to common pads 224a and 224b. In some embodiments, superconductor layer 210 is first formed on (i.e., adjacent to) substrate 260, after which normal metal layer 220 is formed on (i.e., adjacent to) insulator layer 230. In other embodiments, normal metal layer 220 is first formed on (i.e., adjacent to) substrate 260, after which superconductor layer 210 is formed on (i.e., adjacent to) insulator layer 230.

[0041] An array of superconductor-insulator-normal metal (NIS) tunnel structures 240 (only some of which are labeled for clarity) are formed in a grid pattern at the intersections (in the XY plane) of the superconductor traces 212 and the normal metal traces 222. The exemplary cooling structure 200 also includes a plurality of electrical contacts 250 (only some of which are labeled for clarity), which may be fabricated on the surface of the substrate 260.

[0042] In some embodiments, when a small electric potential (bias voltage V) is applied between the superconductor layer 210 and the normal metal layer 220, relatively high-energy ("hot") electrons can cross the dielectric between the two layers. In contrast, relatively low-energy ("cold") electrons cannot cross the dielectric. Combined, this has the effect of transferring thermal energy away from heat sources such as quantum devices or interface electronics.

[0043] In some embodiments, the normal metal layer may be any material that is compatible with substrate 260 and with any subsequent fabrication processes required to form the remainder of structure 200 (see FIGS. 7-8) and / or the cooled device (see FIGS. 3-6). In some embodiments and applications, it may be desirable for the normal metal layer to not function as a superconductor at the selected low and / or cryogenic operating temperature, but still be a good normal conductor to reduce heat added to the system through resistance, and for the normal metal layer to be nonmagnetic to avoid interference with the qubits. Suitable normal metals include, but are not limited to, silver, gold, copper, platinum, and palladium.

[0044] In some embodiments, superconductor layer 210 may be any material that exhibits superconducting properties at selected low and / or cryogenic operating temperatures, is compatible with other selected materials, and is compatible with any fabrication processes used. Suitable superconducting materials for some embodiments and applications include, but are not limited to, aluminum, niobium, tantalum, titanium, tantalum nitride, titanium nitride, vanadium, lead, tin, and gallium. Insulator layer 230 may be any material that functions as a dielectric between superconducting metal layer 210 and normal conducting layer 220 at low and / or cryogenic operating temperatures, as well as being compatible with other selected materials and fabrication processes. In some embodiments and applications, suitable such materials include silicon dioxide (SiO), hafnium dioxide (HfO), and aluminum oxide (AlO). Various nitrides, such as silicon nitride, hafnium nitride, aluminum nitride, and zirconium nitride, may also be suitable for some embodiments and applications.

[0045] FIG. 2C illustrates another exemplary active planar cooling structure 200c consistent with some embodiments. The active planar cooling structure 200c of FIG. 2C also includes a superconductor layer 210 and a normal metal (i.e., non-superconducting) layer 220 separated by an insulator layer 230. However, the superconductor layer 210 and the normal metal layer 220 of FIG. 2C each include a single planar surface 272, 282 of superconductor material or normal metal. As with the embodiment of FIGS. 2(A)-2(B), an NIS tunnel structure 240 is formed where the two planes 272, 282 overlap. This active planar cooling structure embodiment 200c may be desirable for active cooling in space-constrained locations, such as the active planar cooling structure 303 of FIG. 3B.

[0046] 3A and 3B illustrate an exemplary actively cooled quantum processor 300 consistent with some embodiments. Quantum processor 300a of FIG. 3A includes four active planar cooling structures 302 arranged in a strip around the periphery of a cooled device, such as quantum processor 310. Quantum circuit 310 includes multiple quantum devices, such as qubits 315 (only some of which are labeled for clarity). Quantum processor 300B of FIG. 3B includes five active planar cooling structures 302, 303. As in FIG. 3A, four of the active planar cooling structures 302 are arranged in a strip around the periphery of a cooled device, such as quantum processor 310. A fifth active planar cooling structure 303 is positioned within the periphery of the cooled device, such as between two groups of qubits 315.

[0047] 3A and 3B, the active planar cooling structure 302 is formed directly on the same surface (e.g., the top surface) of the substrate 360, beside and / or between the qubits 315 that make up the quantum circuit 310. These arrangements may be desirable because the active planar cooling structure 302 can be formed simultaneously using the same fabrication process as the quantum circuit 310. This arrangement may also be desirable because it places the active planar cooling structure 302 in close physical proximity to the quantum device.

[0048] 4 illustrates another exemplary actively cooled quantum processor 400 consistent with some embodiments of the present invention. Quantum processor 400 includes a substantially square active planar cooling structure 402 formed on one surface (e.g., the bottom) of a substrate 460. Formed on the opposite surface (e.g., the top) are multiple quantum devices 415 (only some of which are labeled for clarity) that can be combined to form a quantum circuit 410.

[0049] 5 shows another exemplary actively cooled quantum processor 500. In this example, an active planar cooling structure 502 is formed on one substrate 560a, and quantum devices 515 (only one is labeled for clarity) that make up a quantum circuit 510 are formed on a second substrate 560b. The two substrates 560a and 560b are then bonded, mechanically clamped, or otherwise adhered together back-to-back. These quantum processor embodiments 400 and 500 may be desirable because they may offer greater options in materials and manufacturing processes.

[0050] FIG. 6(A) illustrates another exemplary actively cooled quantum processor 600a consistent with some embodiments of the present invention. The quantum processor 600 of FIG. 6(A) includes two active planar cooling structures: an active planar cooling structure 602a formed on one surface (e.g., the bottom) of a first substrate 660a; and an active planar cooling structure 602b formed on one surface (e.g., the top) of a second substrate 660b. The two substrates 660a and 660b in this embodiment may be bonded, clamped, or otherwise adhered together such that the two substrates 660a and 660b sandwich a quantum device 615 (only one is labeled for clarity) that constitutes a quantum circuit 610. FIG. 6(B) illustrates another exemplary actively cooled quantum processor 600b consistent with some embodiments of the present invention. In this embodiment of quantum processor 600b, top active planar cooling structure 602b is on the surface of substrate 660b closest to (i.e., facing) quantum devices 615 (only one labeled for clarity) that make up quantum circuit 610.

[0051] Figure 6(B) also includes a plurality of spacers 680 that prevent physical contact with quantum device 615 when the two substrates 660a and 660b are bonded, clamped, or otherwise adhered together. Spacers 680 can optionally include channels (not shown) that allow the passage of a coolant (e.g., liquid hydrogen or helium) into and through passages 690 between quantum circuit 610 and top active planar cooling structure 602b. The embodiments of Figures 6(A) and 6(B) may be desirable because they can also protect quantum device 615 and quantum circuit 610.

[0052] Manufacturing method 7(A)-7(D) are cross-sectional views of a device illustrating various stages of an exemplary process for fabricating an active planar quantum cooling structure consistent with some embodiments. As shown in FIG. 7(A), a photoresist layer 770 is first deposited on a substrate 760. Then, using a mask and a light source (not shown), a photoresist pattern for a first layer 710 (e.g., a normal metal layer) is exposed onto the photoresist layer 770. After rinsing away the exposed / developed photoresist, the material for the first layer of the structure (e.g., a selected normal metal) can be applied. The remaining unexposed / undeveloped photoresist layer 770 can then be dissolved using a solvent appropriate for the selected material and substrate. FIG. 7(B) shows the resulting structure.

[0053] Next, an insulating layer 730 (e.g., SiO2 or HfO2) is deposited over the remaining (i.e., patterned) layer 710 (e.g., normal metal layer) of the structure. Suitable methods include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). The resulting structure is shown in Figure 7(C). A patterned lift-off resist layer 780 may be applied for use in forming the next layer 720 (e.g., superconductor layer) of the structure. A mask and light source (not shown) can then be used to expose a reverse pattern onto the resist layer 780, allowing a second layer of material (e.g., a selected superconductor) to be deposited. The resulting structure is shown in Figure 7(D). The exposed / developed resist layer 780, along with any material on its surface, is then washed away to form the second layer (e.g., superconductor) of the desired shape. Finally, appropriate electrical contacts (not shown) are made to the normal metal and / or superconductor array and packaged in an orientation suitable for installation in a cryogenic cooling structure.

[0054] FIG. 8 illustrates an exemplary computer-implemented process 800 for fabricating an active planar quantum cooling structure consistent with some embodiments. Process 800 may, in some embodiments, be implemented in photolithography application 105a of FIG. 1. In block 802, photolithography application 105a creates a pattern for a first layer 710 (e.g., a normal metal layer) of the planar active cooling structure to be deposited on substrate 760. Next, in block 804, photolithography application 105a deposits a photoresist layer on substrate 760 and exposes the first pattern in the photoresist layer. In block 806, photolithography application 105a washes away the exposed / developed photoresist and applies an appropriate material (e.g., a selected normal metal) to the resulting structure. Photolithography application 105 a then causes the unexposed / undeveloped photoresist to be removed along with any adjacent normal metal in block 807 , thus forming patterned layer 710 .

[0055] In block 808, the photolithography application 105a deposits an insulating layer 730 over the patterned layer 710. In block 810, the photolithography application 105a creates a pattern for a second (e.g., superconducting) layer 720. The photolithography application 105a then directs the application of a patterned lift-off resist layer 780 to the current structure (block 812), which is then exposed using a mask and light (block 814). The photolithography application 105a then deposits a second layer 720 (e.g., a superconductor layer) over the current structure in block 816. In block 818, the photolithography application 105a directs the washing away of the exposed / developed resist layer 780, along with any superconductor on its surface, to form the patterned layer 720. Finally, in block 820, the photolithography application 105a causes electrical contacts to be attached to the current structure, and the photolithography application 105a ends.

[0056] general Although the present invention has been described in detail with reference to specific examples thereof, it may be embodied in other specific forms without departing from its essential spirit or attributes. For example, some embodiments may be distributed as a set of instructions for a manufacturing facility ("fab") encoded on a computer-readable storage medium (e.g., release interface tape or "RIT," "tape-out," "GDS2," etc.). The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or raised structures in grooves on which instructions are recorded, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, should not be construed as being ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through wires.

[0057] The computer-readable instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper transmission cables, fiber optic transmission cables, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to a computer-readable storage medium within the respective computing / processing device for storage.

[0058] Embodiments of the invention may also be delivered as part of a service engagement with a client company, non-profit organization, government agency, internal organizational structure, etc. Aspects of these embodiments may also include analyzing specifications from the client entity, making recommendations in response to the analysis, generating a design for a circuit that implements some or all of the recommendations, delivering manufacturing instructions for the design, and testing the resulting circuit.

[0059] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternate embodiments may be devised without departing from the scope of the present invention. While various connections and relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and in the drawings, those skilled in the art will recognize that many of the relationships described herein are orientation-independent, provided that the described functionality is maintained even when the orientation is changed. These connections and / or relationships may be direct or indirect, unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, coupling of entities can refer to either direct or indirect coupling, and relationships between entities may be direct or indirect. As an example of an indirect relationship, reference herein to forming layer "A" on layer "B" includes situations in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," so long as the relevant properties and functionality of layers "A" and "B" are not substantially altered by the intermediate layers.

[0060] The following definitions and abbreviations are used for interpreting the claims and this specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and can include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0061] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include indirect and direct "connections."

[0062] References herein to "one embodiment," "embodiment," "exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but that all embodiments may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0063] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on equipment available at the time of filing this application. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0064] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements to technology found in the market, or to enable others skilled in the art to understand the embodiments described herein. Therefore, the embodiments described herein are to be considered in all respects to be illustrative and not restrictive, and reference should be made to the appended claims to determine the scope of the invention.

Claims

1. 1. An active cooling structure comprising: a non-superconducting layer including a plurality of non-superconducting traces; a superconductor layer including a plurality of superconducting traces, the plurality of non-superconducting traces extending orthogonally to the plurality of superconducting traces; a grid of superconductor-insulator-normal-metal (NIS) tunnel junctions between the plurality of non-superconducting traces and the plurality of superconducting traces; An active cooling structure comprising:

2. The active cooling structure of claim 1 , further comprising a first plurality of common pads electrically connecting said plurality of superconducting traces in parallel.

3. The active cooling structure of claim 1 or 2, further comprising a second plurality of common pads electrically connecting the plurality of non-superconducting traces in parallel.

4. The active cooling structure of claim 1 , further comprising an insulator layer between the non-superconducting layer and the superconductor layer.

5. a non-superconducting layer including a plurality of non-superconducting traces; a superconductor layer including a plurality of superconducting traces; an insulator layer between the non-superconducting layer and the superconductor layer; an array of superconductor-insulator-normal-metal (NIS) tunnel junctions between the plurality of non-superconducting traces and the plurality of superconducting traces; wherein the non-superconducting layer comprises silver; the insulator layer comprises silicon dioxide; The active cooling structure wherein the superconductor layer comprises aluminum.

6. a non-superconducting layer including a plurality of non-superconducting traces; a superconductor layer including a plurality of superconducting traces; an insulator layer between the non-superconducting layer and the superconductor layer; an array of superconductor-insulator-normal-metal (NIS) tunnel junctions between the plurality of non-superconducting traces and the plurality of superconducting traces; wherein the non-superconducting layer comprises silver; the insulator layer comprises silicon dioxide; The active cooling structure wherein the superconductor layer comprises niobium.

7. a non-superconducting layer including a plurality of non-superconducting traces; a superconductor layer including a plurality of superconducting traces; an insulator layer between the non-superconducting layer and the superconductor layer; an array of superconductor-insulator-normal-metal (NIS) tunnel junctions between the plurality of non-superconducting traces and the plurality of superconducting traces; wherein the non-superconducting layer comprises silver; the insulator layer comprises hafnium dioxide; The active cooling structure wherein the superconductor layer comprises aluminum.

8. a non-superconducting layer including a plurality of non-superconducting traces; a superconductor layer including a plurality of superconducting traces; an insulator layer between the non-superconducting layer and the superconductor layer; an array of superconductor-insulator-normal-metal (NIS) tunnel junctions between the plurality of non-superconducting traces and the plurality of superconducting traces; wherein the non-superconducting layer comprises silver; the insulator layer comprises hafnium dioxide; The active cooling structure wherein the superconductor layer comprises niobium.

9. 1. A quantum processor, comprising: a first substrate; a plurality of quantum bits formed on the first substrate; an active cooling structure in thermal communication with the qubit; Non-superconducting layer, a superconductor layer, and the active cooling structure including an insulator layer between the non-superconducting layer and the superconductor layer; the non-superconducting layer comprising a plurality of non-superconducting traces; the superconductor layer includes a plurality of superconducting traces that intersect the plurality of non-superconducting traces; A quantum processor, wherein a grid of superconductor-insulator-normal metal (NIS) tunnel junctions is formed between the plurality of non-superconducting traces and the plurality of superconducting traces.

10. The quantum processor of claim 9 , wherein the plurality of non-superconducting traces and the plurality of superconducting traces are orthogonal.

11. 11. The quantum processor of claim 9 or 10, wherein the active cooling structure is adjacent to the plurality of qubits.

12. 12. The quantum processor of claim 9, wherein the active cooling structure is between the plurality of qubits.

13. the non-superconducting layer comprises a flat surface of a non-superconducting material; 13. The quantum processor of claim 9, wherein the superconductor layer comprises a flat surface of superconductor.

14. 1. A quantum processor, comprising: a first substrate including a first surface and a second surface; a plurality of quantum bits formed on the first substrate; an active cooling structure in thermal communication with the qubit; Non-superconducting layer, a superconductor layer, and the active cooling structure including an insulator layer between the non-superconducting layer and the superconductor layer, wherein the plurality of qubits are formed on the first surface and the active cooling structure is formed on the second surface.

15. 1. A quantum processor, comprising: a first substrate; a second substrate; a plurality of quantum bits formed on the first substrate; an active cooling structure in thermal communication with the qubit; Non-superconducting layer, a superconductor layer, and the active cooling structure including an insulator layer between the non-superconducting layer and the superconductor layer, wherein the plurality of qubits are formed on the first substrate and the active cooling structure is formed on the second substrate.

16. the first substrate includes a first surface and a second surface; the second substrate includes a third surface and a fourth surface; the plurality of qubits are formed on the first surface of the first substrate, and the active cooling structure is formed on the third surface of the second substrate.

16. The quantum processor of claim 15.

17. 17. The quantum processor of claim 16, wherein the second surface is in contact with the fourth surface.

18. 18. The quantum processor of claim 15, further comprising a fluidic channel between the first substrate and the second substrate.

19. 1. A method of cryogenically cooling a quantum processor, comprising: applying a voltage to an active cooling structure in thermal communication with the quantum processor, wherein the active cooling structure a non-superconducting layer including a plurality of non-superconducting traces; a superconductor layer including a plurality of superconducting traces; an insulating layer between the non-superconducting layer and the superconducting layer; wherein the plurality of non-superconducting traces extend across the plurality of superconducting traces to form a grid of superconductor-insulator-normal-metal (NIS) tunnel junctions between the plurality of non-superconducting traces and the plurality of superconducting traces. applying the voltage; A method comprising:

20. 1. A method for manufacturing an active cooling structure, comprising: forming a grid of superconductor-insulator-normal metal (NIS) tunnel structures between a non-superconducting layer and a superconductor layer; the non-superconducting layer includes a plurality of non-superconducting traces extending generally parallel to a first direction; forming a grid, the superconductor layer including a plurality of superconducting traces extending generally parallel to a second direction, the plurality of superconducting traces intersecting the plurality of non-superconducting traces to form the grid; A method comprising:

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