Three-dimensional integrated packaging structure and packaging process thereof

Abstract

The invention discloses a three-dimensional integrated packaging structure and a packaging process thereof. The three-dimensional integrated packaging structure comprises a flip or normal chip with a functional surface and an opposite back surface; the rewiring layer and the chip are vertically stacked and electrically connected with each other; electrically leading the rewiring layer out of the packaging structure; the stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, the inductor and the chip, the rewiring layer and the lead-out structure are physically isolated through an insulating medium layer, the inductor is of a spiral, multi-ring layer overlapping or sectional winding structure, the inductor comprises a magnetic core, a spiral coil surrounding the surface of the magnetic core is formed through etching and electroplating processes, and the lead-out structure is arranged on the surface of the spiral coil. The spiral coil comprises a circuit A, a circuit B and a circuit C, and the magnetic core and the spiral coil are encapsulated by the insulating medium layer. The inductor and the chip are stacked in an inverted or normal mode, the three-dimensional structure saves space, reduces parasitic inductance, resistance and the like, signal transmission is stable, electromagnetic interference is small, and the three-dimensional structure is suitable for the chip packaging field of miniaturization, high integration and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a three-dimensional integrated packaging structure and a packaging process thereof. Background Art

[0002] With the continuous advancement of integrated circuit packaging technology, the integration level is increasing, the functions are becoming more and more abundant, and the overall package size is also developing in the direction of miniaturization or even micro-miniaturization. In some structures, it is necessary to electrically connect the chip with other devices. For example, in the field of semiconductor or other chip device packaging, certain specific types of chips need to be integrated or stacked with inductors to achieve efficient energy conversion, signal processing or radio frequency (RF) functions.

[0003] Currently, the packaging field generally adopts a planar spatial layout scheme, that is, inductors or other components and chips (such as power devices, RF chips, etc.) are usually arranged side by side or embedded in the substrate. This design scheme has some technical defects: low space utilization, the layout leads to redundant packaging area, and it is difficult to meet the high-density integration requirements of miniaturized scenarios such as mobile terminals; high-frequency performance is limited, the electrical interconnection path is long, and the parasitic resistance is large, resulting in serious signal loss and electromagnetic interference. Summary of the Invention

[0004] In order to solve the above problems in the prior art, the present invention provides a three-dimensional integrated packaging structure and a packaging process thereof.

[0005] To achieve the above objectives, the present invention proposes a three-dimensional integrated packaging structure, comprising: A flip-chip or face-up chip has a functional side and a back side opposite to the functional side; The inductor is vertically stacked and electrically interconnected with the chip through a redistribution layer; Lead-out structure, electrically leading the redistribution layer to the outside of the package structure; The stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, and the two, the redistribution layer and the lead-out structure are physically isolated by an insulating dielectric layer.

[0006] Furthermore, the inductor has a spiral, multi-layer overlapping or segmented winding structure.

[0007] Furthermore, the inductor is formed by a layer-by-layer encapsulation electroplating process, and the inductance value of the inductor ranges from 1 nH to 100 μH.

[0008] Furthermore, the inductor includes a magnetic core, and a spiral coil is formed around the surface of the magnetic core through etching and electroplating processes. The spiral coil includes line A, line B and line C. The magnetic core and the spiral coil are encapsulated by an insulating medium layer.

[0009] Furthermore, when the chip is mounted face-up, the inductor is stacked below the back side of the chip; when the chip is mounted flip-chip, the inductor is stacked below the functional surface of the chip.

[0010] Furthermore, when the chip is flip-chip mounted, the back side of the chip is exposed outside the insulating dielectric layer.

[0011] Furthermore, the lead-out structure is a metal pillar formed by etching the insulating dielectric layer to form a groove and then electroplating metal to fill the inside of the groove.

[0012] Furthermore, the insulating medium layer is a plastic packaging material.

[0013] Furthermore, the structure is further integrated into a fan-out wafer-level packaging or system-level packaging module.

[0014] A packaging process for a three-dimensional integrated structure comprises the following steps: Encapsulated inductor: The inductor is formed by layer-by-layer encapsulation and electroplating process; Electroplating redistribution layer: After the redistribution layer is electroplated, the inductor electrical properties are rearranged; Chip mounting: The chip is mounted face-up or flip-chip, stacked vertically with the inductor through a redistribution layer and electrically interconnected; Electroplating lead-out structure: electrically lead the redistribution layer to the outside of the package structure; The stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, and the two, the redistribution layer and the lead-out structure are physically isolated by an insulating dielectric layer.

[0015] Furthermore, in the step of encapsulating the inductor, the inductor has a spiral, multi-layer overlapping or segmented winding structure.

[0016] Furthermore, in the step of encapsulating the inductor, the inductance value of the inductor ranges from 1 nH to 100 μH.

[0017] Furthermore, in the step of encapsulating the inductor, circuit A is electroplated on the insulating dielectric layer, which is then encapsulated and polished to expose the top surface of circuit A, and a magnetic core is mounted on the top surface of circuit A. The magnetic core is further encapsulated to expose the top surface of the magnetic core, and the insulating dielectric layer is etched to expose the end of circuit A. Circuit B is electroplated in the etching groove to connect with circuit A, and circuit C is electroplated on the exposed top surface of the magnetic core to connect with circuit B. Circuit A, circuit B, and circuit C constitute a spiral coil surrounding the magnetic core, which is then encapsulated again so that the magnetic core and the spiral coil are encapsulated by the insulating dielectric layer.

[0018] Furthermore, in the chip mounting step, when the chip is mounted face up, the inductor is stacked below the back side of the chip, and when the chip is mounted flip-chip, the inductor is stacked below the functional surface of the chip.

[0019] Furthermore, in the chip mounting step, when the chip is flip-chip mounted, the back side of the chip is exposed outside the insulating dielectric layer.

[0020] Furthermore, in the step of electroplating the lead-out structure, the lead-out structure is a metal column formed by etching the insulating dielectric layer to form a groove and then electroplating metal to fill the groove.

[0021] Furthermore, the insulating dielectric layer in this process step is a plastic packaging material.

[0022] Furthermore, the process also includes further integrating the packaging structure into a fan-out wafer-level packaging or system-level packaging module.

[0023] The three-dimensional integrated packaging structure and packaging process provided by the present invention have the following advantages: 1. In a stacked structure, the inductor is formed by layer-by-layer encapsulation and electroplating. The number of coil turns is adjusted by rationally utilizing the packaging space, thereby increasing the inductance, reducing the inductor volume, and lowering the interlayer capacitance. This makes it suitable for miniaturized and highly integrated chip packaging. The product structure is compact due to the rational layout of electrical ports through rewiring and the rational allocation of packaging space. 2. The inductor and chip are flip-chip or face-mounted and stacked. The three-dimensional structure saves space, has a wide range of product applications, high design flexibility, reduces parasitic inductance and resistance, etc., and has stable signal transmission and low electromagnetic interference. The close layout of the inductor and chip can reduce loop impedance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1-Figure 7 A cross-sectional view of an inductor electroplating step in a packaging process for a three-dimensional integrated structure of the present invention; Figures 8-11 A cross-sectional view of a step of electroplating a redistribution layer in Example 1 of a packaging process for a three-dimensional integrated structure of the present invention; Figure 12-14 A cross-sectional view of a chip mounting step in a first embodiment of a packaging process for a three-dimensional integrated structure of the present invention; Figure 15-17 A cross-sectional view of the electroplating lead-out structure step in Example 1 of a packaging process for a three-dimensional integrated structure of the present invention; Figure 18 This is a cross-sectional view of a product of Example 1 of a three-dimensional integrated packaging structure of the present invention; Figures 19-21 A cross-sectional view of a redistribution layer electroplating step in a second embodiment of a packaging process for a three-dimensional integrated structure of the present invention; Figure 22-24 A cross-sectional view of a chip mounting step in a second embodiment of a packaging process for a three-dimensional integrated structure of the present invention; Figure 25-29A cross-sectional view of the electroplating lead-out structure step of Example 2 of a packaging process for a three-dimensional integrated structure of the present invention; Figure 30 This is a cross-sectional view of a product of Example 2 of a three-dimensional integrated packaging structure of the present invention.

[0025] In the figure: 1. Chip; 2. Inductor; 3. Redistribution layer; 4. Metal pillar; 5. Insulation dielectric layer; 6. Line A; 7. Line C; 8. Magnetic core. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The content of the present invention will be explained below in conjunction with specific implementation methods. Examples of the implementation methods are shown in the drawings, where the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.

[0027] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein; the directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference to the directions of the drawings. The implementation methods and directional terms used in the following description with reference to the drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the examples of various specific processes and materials provided by the present invention are all examples of other processes and / or the use of other materials that a person of ordinary skill in the art can recognize.

[0028] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a three-dimensional integrated packaging structure and its packaging process proposed by the present invention in conjunction with the accompanying drawings. The process includes the following steps: Encapsulated inductor 2: Inductor 2 is formed by layer-by-layer encapsulation and electroplating processes; Electroplating redistribution layer 3: After electroplating, the redistribution layer 3 re-arranges the electrical layout of inductor 2; Chip 1 mounting: Chip 1 is mounted face-up or flip-chip, vertically stacked and electrically interconnected with inductor 2 via redistribution layer 3; Electroplating lead-out structure: electrically lead the redistribution layer 3 to the outside of the package structure; The stacking direction of the inductor 2 and the chip 1 is parallel to the thickness direction of the chip 1 , and the two, the redistribution layer 3 and the lead-out structure are physically isolated by the insulating dielectric layer 5 .

[0029] There is no specific order for the above steps. The inductor 2 can be electroplated and encapsulated first, and then the chip 1 can be mounted and subsequent processing can be continued. Alternatively, the chip 1 can be mounted and encapsulated first, and then the inductor 2 can be electroplated and encapsulated and subsequent processing can be continued. The present invention takes the first order of steps as an example.

[0030] The more specific process steps of the encapsulated inductor process are as follows: S1: Provide a substrate, which can be a resin plate commonly used in the art, and a certain thickness of insulating dielectric layer 5 (such as Figure 1 As shown), the surface of the insulating dielectric layer 5 is horizontal and flat after solidification. The insulating dielectric layer 5 is covered first and then the circuit is electroplated to prevent the risk of the bottom circuit falling off and failing when the substrate is peeled off and removed in the subsequent process.

[0031] S2: Electroplating the circuit A6 on the upper surface of the insulating dielectric layer 5 (such as Figure 2 As shown), the circuit A6 includes multiple parallel and evenly spaced electroplated metals, and the height, width and spacing of the electroplated circuit A6 are not limited.

[0032] S3: Using the insulating dielectric layer 5, the circuit A6 is completely encapsulated on the basis of the insulating dielectric layer 5 of S1 to form a new encapsulation top surface (such as Figure 3 As shown), the two parts of the insulating dielectric layer 5 are combined into a complete part.

[0033] S4: The top surface of the package formed in step S3 is horizontally ground by mechanical grinding until the top surface of the line A6 is exposed. The top surface of the package after grinding is horizontal and flat (such as Figure 4 shown).

[0034] S5: Mount the magnetic core 8 on the corresponding position of the circuit A6 on the polished top surface of the package. The magnetic core 8 is in direct contact with the circuit A6. The insulating dielectric layer 5 is then used to completely encapsulate the magnetic core 8 to form the top surface of the package again. The top surface of the magnetic core 8 is exposed by mechanical polishing of the top surface of the package (e.g. Figure 5 As shown), the insulating dielectric layer 5 is encapsulated layer by layer to form a whole.

[0035] S6: Etch the corresponding positions of the insulating dielectric layer 5 to form multiple grooves. The two ends of the line A6 are exposed in the corresponding grooves. The inside of the grooves are filled with the metal-plated line B (not shown in the figure) through the electroplating process. Line B is connected to line A6.

[0036] S7: Electroplating circuit C7 on the top surface of the exposed magnetic core 8, circuit C7 connects circuit A6 and circuit B together, circuit A6, circuit B and circuit C7 form a spiral coil around the magnetic core 8, and then encapsulate again so that the magnetic core 8 and the spiral coil are encapsulated by the insulating medium layer 5, and the encapsulated top surface is horizontal and flat (such as Figure 7 As shown in FIG, the inductor 2 packaging structure is constituted as a whole. The inductor 2 is formed by layer-by-layer encapsulation and electroplating processes. According to the size of the substrate area and the actual size of the product space occupied, multiple inductor 2 structures can be formed on the substrate at one time. The present invention takes the formation of two inductors 2 at one time as an example.

[0037] The inductor 2 can be a spiral type, a multi-layer overlapping type or a segmented winding structure. In the present invention, taking the spiral type inductor 2 as an example, through layer-by-layer encapsulation, electroplating and other processes, spiral coils of line A6, line B and line C7 are formed around the magnetic core 8, and then the inductor 2 structure encapsulated in the insulating dielectric layer 5 is formed. The number of coil turns can be increased in a limited space, the inductance can be significantly improved, the volume of the inductor 2 can be reduced, the device can be miniaturized, and it is suitable for high-integration chip 1 packaging; the layer-by-layer encapsulated dielectric material can effectively reduce the interlayer capacitance, increase the self-resonant frequency of the inductor 2, and expand the high-frequency working range; the coil pattern can be finely controlled, and the winding limitations of the special-shaped magnetic core 8 can be broken through, and the electroplating production has high flexibility.

[0038] In actual applications, the selection of inductor 2 needs to be determined according to specific circuit requirements. For example, in the power supply filter circuit, the selection of inductance value will affect the filtering effect and circuit stability; in the LC oscillation circuit, the selection of inductance value will affect the oscillation frequency. The inductance value range of inductor 2 in the present invention is 1nH to 100μH. This inductance value range is suitable for different circuits and application scenarios. Power management chips 1, RF chips 1, analog or mixed signal chips 1, etc. match inductance values ​​in different ranges. Example 1

[0039] The more specific process of step 3 of electroplating the redistribution layer is as follows: S1: Etch the corresponding position on the insulating dielectric layer 5 encapsulating the top surface of the circuit C7 through an etching process, so that the end of the circuit C7 is exposed at the bottom of the etched groove (such as Figure 8 As shown), the exposed end of line C7 is a separate end without any other connection relationship, and serves as an external port for connecting inductor 2 to other components.

[0040] S2: Electroplating metal in the etched grooves to fill the grooves, and the electroplated metal extends on the surface of the insulating dielectric layer 5 to form a redistribution layer 3 (such as Figure 9As shown in the figure), the redistribution layer 3 rearranges the position of the external port of the inductor 2 and is flexibly adjusted according to the connection relationship between the inductor 2 and other connecting components. The extension direction of the redistribution layer 3 is designed according to the actual product situation. For example, when the inductor 2 is large in size and other components electrically connected to the inductor 2, such as the chip 1, are small in size, the electrical ports between the two are difficult to match and connect. At this time, the electrical port position is adjusted by electroplating the redistribution layer 3 to achieve connection between the two. At the same time, a conductive block (not marked in the figure) is electroplated on the redistribution layer 3 as the electrical port for the external connection of the redistribution layer 3.

[0041] S3: Continue to use the insulating dielectric layer 5 to completely encapsulate the redistribution layer 3 and the conductive block, and mechanically grind the top surface of the encapsulation horizontally until the top surface of the conductive block is exposed (such as Figure 10 As shown in FIG, the exposed top surface of the conductive block is used as a port for external electrical connection; further, in order to lead the electrical properties of the chip 1 to the outside of the package structure, other lead layers (such as Figure 11 As shown, the lead layer is not marked in the figure), and at the same time, the top surface of the conductive block is electroplated to the same height as the lead layer.

[0042] The more specific process of chip 1 placement step is as follows: S1: Flip-chip mounting of chip 1, which may be a power management chip 1, a radio frequency chip 1, an analog or mixed signal chip 1, etc. Chip 1 has a functional surface and a back surface opposite to the functional surface. The functional surface of chip 1 has an electrical port of chip 1, such as a bump (conductive block). Mount the chip 1 with the functional surface facing the conductive block. The conductive block of the electrical port of chip 1 is welded to the conductive block of the redistribution layer 3 through solder paste, and the other conductive blocks of the electrical port of chip 1 are welded to the lead layer through solder paste to achieve flip-chip mounting of chip 1 (such as Figure 12 As shown), the chip 1 is electrically connected to the inductor 2 through the redistribution layer 3; the inductor 2 in the package structure of the power management chip 1 is used as an energy storage element to smooth the current, filter out high-frequency noise, and participate in energy conversion (such as inductor-capacitor (LC) filtering in a switching power supply); the inductor 2 in the package structure of the radio frequency chip 1 is used for impedance matching, resonant circuits (such as LC oscillators), filtering (such as bandpass filters) or radio frequency signal coupling; the inductor 2 in the package structure of the analog or mixed-signal chip 1 is used to eliminate power supply noise, suppress electromagnetic interference (EMI) or build a low-pass / high-pass filter.

[0043] S2: The chip 1 is completely encapsulated using the insulating dielectric layer 5 (eg Figure 13 As shown), further, in order to improve the heat dissipation performance of the packaging structure, the top surface of the insulating dielectric layer 5 after encapsulation and curing can be horizontally mechanically polished to expose the back side of the chip 1 (as shown). Figure 14As shown in the figure, the back side of the chip 1 is exposed outside the insulating dielectric layer 5, which can directly dissipate heat outside the insulating dielectric layer 5, thereby avoiding the situation where the thermal resistance of the insulating dielectric layer 5 causes heat accumulation inside the packaging structure and causes the internal structure to be damaged due to heat. At the same time, the exposed back side of the chip 1 can be covered with a protective layer commonly used in the art to extend the service life of the device.

[0044] After the chip 1 is mounted, the stacking direction of the inductor 2 and the chip 1 is parallel to the thickness direction of the chip 1 , and the two, the redistribution layer 3 and the lead-out structure are physically isolated by the insulating dielectric layer 5 .

[0045] The more specific process of the electroplating lead structure step is: S1: Etching the insulating dielectric layer 5 at a corresponding position on the top surface of the ground insulating dielectric layer 5 by an etching process so that one end of the lead layer is exposed in the etching groove (eg Figure 15 shown).

[0046] S2: Electroplating metal fills the grooves etched on the insulating dielectric layer 5 to form metal pillars 4. The bottom of the metal pillars 4 is connected to the lead layer as a whole, and the top of the metal pillars 4 is flush with the upper surface of the insulating dielectric layer 5 and exposed (such as Figure 16 As shown), the chip 1 is electrically connected to the outside of the package structure through the lead layer and the metal pillar 4.

[0047] S3: For the case where multiple inductors 2 are formed on the substrate at one time, after the inductors 2 are completed, all subsequent process steps form the same structure on each inductor 2. Finally, a cutting step is required to cut the insulating dielectric layer 5 to separate each product unit (such as Figure 17 As shown), and the substrate is peeled off to obtain multiple product units at one time. Since the present invention forms two inductors 2 at one time, two product units are finally formed at one time.

[0048] In this embodiment of the present invention, the inductor 2 is stacked below the functional surface of the chip 1, and the stacking direction of the inductor 2 and the chip 1 is parallel to the thickness direction of the chip 1. The inductor 2 and the chip 1 are stacked and packaged up and down. The electrical connection port of the inductor 2 packaging structure is readjusted by the electroplated redistribution layer 3 to be electrically connected to the conductive block of the functional surface of the flip-chip mounted chip 1, so as to rationally utilize the packaging space, have a compact structure, and have a high integration density, meeting the requirements of miniaturized devices; the chip 1 is flip-chip mounted, and the functional surface of the chip 1 and the electrical interface (redistribution layer 3) of the inductor 2 are close to each other, and the interconnection path between the chip 1 and the inductor 2 is short, which reduces parasitic inductance 2 and resistance, is suitable for high-frequency circuit requirements, reduces inductor 2 loss, and improves power conversion; it is suitable for high-frequency, high-power density, miniature and other packaging structure designs, such as radio frequency chips 1, power management chips 1, etc. Example 2

[0049] Different from the flip-chip mounting and stacking of the inductor 2 and the chip 1 in the first embodiment, the inductor 2 and the chip 1 in this embodiment are face-down mounting and stacking.

[0050] The more specific process of step 3 of electroplating the redistribution layer is as follows: S1: Etch the corresponding position on the insulating dielectric layer 5 encapsulating the top surface of the circuit C7 through an etching process, so that the end of the circuit C7 is exposed at the bottom of the etched groove (such as Figure 19 As shown), the exposed end of line C7 is a separate end without any other connection relationship, and serves as an external port for connecting inductor 2 to other components.

[0051] S2: Electroplating metal in the etched grooves to fill the grooves, and the electroplated metal extends on the surface of the insulating dielectric layer 5 to form a redistribution layer 3 (such as Figure 20 As shown in the figure, the redistribution layer 3 rearranges the position of the external port of the inductor 2 and is flexibly adjusted according to the connection relationship between the inductor 2 and other connecting components. The extension direction of the redistribution layer 3 is designed according to the actual product situation. For example, when the inductor 2 is large in size and the other components electrically connected to the inductor 2, such as the chip 1, are small in size, the electrical ports between the two are difficult to match and connect. At this time, the electrical port position is adjusted by electroplating the redistribution layer 3 to achieve connection between the two.

[0052] S3: Continue to use the insulating dielectric layer 5 to completely encapsulate the redistribution layer 3 (such as Figure 21 shown).

[0053] The more specific process of chip 1 placement step is as follows: S1: Mount the chip 1 upright. The chip 1 is the same as that in the first embodiment. The back of the chip 1 is mounted toward the insulating dielectric layer 5. The chip 1 is located above the inductor 2 (e.g. Figure 22 shown).

[0054] S2: Use the insulating dielectric layer 5 to completely encapsulate the chip 1 (such as Figure 23 As shown), and mechanically grind the top surface of the package horizontally until the conductive blocks of the functional surface of the chip 1 are exposed. The top surface of the package after grinding is horizontal and flat (as shown Figure 24 shown).

[0055] After the chip 1 is mounted, the stacking direction of the inductor 2 and the chip 1 is parallel to the thickness direction of the chip 1 , and the two, the redistribution layer 3 and the lead-out structure are physically isolated by the insulating dielectric layer 5 .

[0056] The more specific process of the electroplating lead structure step is: S1: Vertically etch the insulating dielectric layer 5 at the corresponding position on the top surface of the package until the end of the redistribution layer 3 is exposed (eg Figure 25 shown).

[0057] S2: The metal pillars 4 are electroplated to fill the etched grooves. The bottom ends of the metal pillars 4 are electrically connected to the ends of the redistribution layer 3. The electroplated metal extends on the top surface of the insulating dielectric layer 5 to form a lead layer. The lead layer is electrically connected to the conductive blocks exposed on the functional surface of the chip 1. Other exposed conductive blocks on the functional surface of the chip 1 are also electroplated with metal to increase their height (such as Figure 26 shown).

[0058] S3: Use the insulating dielectric layer 5 to encapsulate the electroplated metal and the electroplated raised portion on the conductive block (such as Figure 27 As shown in FIG), the top surface of the package is horizontally ground by mechanical grinding until the electroplated raised portion on the conductive block is exposed (as shown in FIG). Figure 28 As shown in FIG), in the case where multiple inductors 2 are formed on a substrate at one time, after the inductors 2 are completed, all subsequent process steps form the same structure on each inductor 2, and finally a cutting step is required to cut the insulating dielectric layer 5 to separate each product unit (as shown in FIG). Figure 29 shown).

[0059] In this embodiment, the inductor 2 is stacked below the back of the chip 1. The stacking direction of the inductor 2 and the chip 1 is parallel to the thickness direction of the chip 1. The inductor 2 and the chip 1 are stacked and packaged up and down. The electrical connection ports of the inductor 2 packaging structure are readjusted and arranged through the electroplated redistribution layer 3 to electrically connect with the functional surface conductive blocks of the face-up mounted chip 1, thereby rationally utilizing the packaging space. The chip 1 is face-up mounted, and the inductor 2 is stacked on the back of the chip 1, which can reduce the direct conduction of heat generated by the inductor 2 to the chip 1 and is suitable for low-power scenarios. The face-up process of the chip 1 is highly mature and low-cost, and is suitable for low-cost, high-power inductor 2 chip 1 stacking and other packaging structure designs, such as analog or mixed-signal chip 1.

[0060] In other embodiments such as the above-mentioned embodiment 1 and embodiment 2, finally, according to the specific conditions of the actual product, external solder pins can be electroplated on the top of the metal pillar 4 exposed on the surface of the insulating dielectric layer 5 or on the raised portion of the conductive block on the functional surface of the chip 1. The external solder pins can serve as a medium for electrically connecting external devices to the internal structure of the insulating dielectric layer 5. The entire product unit can be further integrated into a fan-out wafer-level package or a system-level package module, or integrated into other suitable packaging modules through the external solder pins. Of course, the embodiments of the present invention and the accompanying drawings only show the electrical connection relationship and electrical direction of each component part. Other necessary electrical connection relationships and electrical directions of each component, such as electrical grounding, also fall within the scope of protection of the present invention.

[0061] Moreover, all the encapsulation processes using the insulating dielectric layer 5 in the present invention are performed by plastic encapsulation. The materials selected for plastic encapsulation may be epoxy resin, cyanate, polyimide, etc., which have the advantages of low cost and good curing performance. The encapsulation process plays an important role in the field of semiconductor manufacturing, mainly in terms of protection, connection, support, reliability and promotion of technological progress. The chip 1 is protected from damage by environmental humidity, mechanical vibration and impact through encapsulation. The encapsulation method is other suitable methods such as compression molding commonly used in this field.

[0062] All the processes of grinding the top surface of the package after encapsulation in the present invention use a grinding machine commonly used in this technical field to perform surface treatment on the top surface of the package, that is, horizontal mechanical grinding is performed on the top surface of the package, and the final grinding surface is horizontal and flat, and the outer surface of the entire packaging structure is flat and smooth.

[0063] The electroplating process used in the present invention is to first use a photoresist film to form electroplating protection on the surface through the photolithography technology of exposure and development, protect the areas that do not need to be electroplated with a photoresist film, expose the areas that need to be electroplated, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is copper or other metal materials. The metal seed layer is to ensure the bonding strength between the subsequent electroplated metals and between the metals and the encapsulation materials, and at the same time provide a surface for the attachment of conductive ions for electroplating to ensure the electroplating effect. The entire steps in the electroplating process and the materials used are also technical common sense in this field. The metals electroplated in all the electroplating processes of the present invention are all metallic copper or other metal materials.

[0064] By using the packaging process of the three-dimensional integrated structure of the above-mentioned Embodiment 1 and Embodiment 2 and other embodiments, a three-dimensional integrated packaging structure can be obtained, which includes: The flip-chip or face-mounted chip 1 has a functional surface and a back surface opposite to the functional surface; when the chip 1 is face-mounted, the inductor 2 is stacked below the back surface of the chip 1 (e.g. Figure 30 As shown); when the chip 1 is flip-chip mounted, the inductor 2 is stacked below the functional surface of the chip 1. At this time, the back of the chip 1 is exposed outside the insulating dielectric layer 5 (as shown in FIG. Figure 18 shown); Inductor 2 is vertically stacked and electrically interconnected with chip 1 via a redistribution layer 3. Inductor 2 has a spiral, multi-turn overlapping, or segmented winding structure. Inductor 2 is formed by a layer-by-layer encapsulation and electroplating process. The inductor 2 has an inductance range of 1 nH to 100 μH. Inductor 2 includes a magnetic core 8 and a spiral coil formed around the surface of magnetic core 8 by etching and electroplating processes. The spiral coil includes line A6, line B, and line C7. The magnetic core 8 and the spiral coil are encapsulated by an insulating dielectric layer 5. The lead-out structure electrically leads the chip 1 to the outside of the package structure; the lead-out structure includes a metal pillar 4 and a lead layer. The metal pillar 4 is formed by etching the insulating dielectric layer 5 to form a groove and then electroplating the metal to fill the groove. The lead layer electrically connects the chip 1 to the metal pillar 4; The stacking direction of the inductor 2 and the chip 1 is parallel to the thickness direction of the chip 1 , and the two, the redistribution layer 3 and the lead-out structure are physically isolated by the insulating dielectric layer 5 , which is a plastic encapsulation material.

[0065] The structure is further integrated into a fan-out wafer-level package or a system-in-package module, or other suitable packaging modules.

[0066] The present invention forms a spiral or other type of inductor 2 through layer-by-layer encapsulation and electroplating, which can increase the number of coil turns in a limited packaging space, improve the inductance, reduce the volume of the inductor 2, and miniaturize the device. It is suitable for the packaging of a high-integration chip 1. The dielectric material encapsulated layer by layer effectively reduces the interlayer capacitance and improves the self-resonant frequency of the inductor 2; the electrical ports of the inductor 2 are readjusted and arranged through the redistribution layer 3 to match the position and size of the electrical ports of the chip 1, and the packaging space is reasonably configured; the inductor 2 is flip-chip stacked on the chip 1, and the interconnection path between the chip 1 and the inductor 2 is short, which reduces the parasitic inductance and resistance, stabilizes the signal transmission, and reduces electromagnetic interference, which is suitable for high-frequency circuit requirements; the inductor 2 is face-mounted and stacked on the chip 1 to reduce the direct conduction of heat generated by the inductor 2 to the chip 1, has a mature process and low cost, and is suitable for low-power circuit requirements; the inductor 2 and the chip 1 are stacked three-dimensionally up and down, which saves space and has high design flexibility. The close layout of the inductor 2 and the chip 1 can reduce the loop impedance, reduce the parasitic inductance and resistance, etc., and ensure stable signal transmission.

[0067] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are intended to be protected by the present invention.

Claims

1. A three-dimensional integrated packaging structure, characterized in that: include: A flip-chip or face-up chip has a functional side and a back side opposite to the functional side; The inductor is vertically stacked and electrically interconnected with the chip through a redistribution layer; Lead-out structure, electrically leading the chip out to the outside of the package structure; The stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, and the two, the redistribution layer and the lead-out structure are physically isolated by an insulating dielectric layer.

2. The three-dimensional integrated packaging structure according to claim 1, characterized in that: The inductor has a spiral, multi-layer overlapping or segmented winding structure.

3. The three-dimensional integrated packaging structure according to claim 2, characterized in that: The inductor is formed by a layer-by-layer encapsulation electroplating process, and the inductance value of the inductor ranges from 1 nH to 100 μH.

4. The three-dimensional integrated packaging structure according to claim 3, characterized in that: The inductor includes a magnetic core, and a spiral coil formed around the surface of the magnetic core through etching and electroplating processes. The spiral coil includes line A, line B and line C. The magnetic core and the spiral coil are encapsulated by an insulating medium layer.

5. The three-dimensional integrated packaging structure according to claim 1, characterized in that: When the chip is mounted face up, the inductor is stacked below the back of the chip; when the chip is mounted flip-chip, the inductor is stacked below the functional surface of the chip.

6. The three-dimensional integrated packaging structure according to claim 5, characterized in that: When the chip is flip-chip mounted, the back side of the chip is exposed outside the insulating dielectric layer.

7. The three-dimensional integrated packaging structure according to claim 1, characterized in that: The lead-out structure includes a metal column and a lead layer. The metal column is formed by etching an insulating dielectric layer to form a groove and then electroplating metal to fill the groove. The lead layer electrically connects the chip to the metal column.

8. The three-dimensional integrated packaging structure according to claim 1, characterized in that: The insulating medium layer is a plastic packaging material.

9. The three-dimensional integrated packaging structure according to claim 1, characterized in that: The structure is further integrated into fan-out wafer-level packaging or system-level packaging modules.

10. A packaging process for a three-dimensional integrated structure, characterized in that: The following steps are involved: Encapsulated inductor: The inductor is formed by layer-by-layer encapsulation and electroplating process; Electroplating redistribution layer: After the redistribution layer is electroplated, the inductor electrical properties are rearranged; Chip mounting: The chip is mounted face-up or flip-chip, stacked vertically with the inductor through a redistribution layer and electrically interconnected; Electroplating lead-out structure: electrically lead the chip out to the outside of the package structure; The stacking direction of the inductor and the chip is parallel to the thickness direction of the chip, and the two, the redistribution layer and the lead-out structure are physically isolated by an insulating dielectric layer.

11. The packaging process of the three-dimensional integrated structure according to claim 10, characterized in that: In the step of encapsulating the inductor, the inductor has a spiral, multi-layer overlapping or segmented winding structure.

12. The packaging process of the three-dimensional integrated structure according to claim 11, characterized in that: In the step of encapsulating the inductor, the inductance value of the inductor ranges from 1 nH to 100 μH.

13. The packaging process of the three-dimensional integrated structure according to claim 12, characterized in that: In the encapsulated inductor step, circuit A is electroplated on the insulating dielectric layer, which is then encapsulated and polished to expose the top surface of circuit A. A magnetic core is mounted on the top surface of circuit A, the magnetic core is further encapsulated to expose the top surface of the magnetic core, the insulating dielectric layer is etched to expose the end of circuit A, and circuit B is electroplated in the etching groove to connect with circuit A. Circuit C is electroplated on the exposed top surface of the magnetic core to connect with circuit B. Circuit A, circuit B, and circuit C form a spiral coil surrounding the magnetic core, which is then encapsulated again so that the magnetic core and the spiral coil are encapsulated by the insulating dielectric layer.

14. The packaging process of the three-dimensional integrated structure according to claim 10, characterized in that: In the chip mounting step, when the chip is mounted face up, the inductor is stacked below the back side of the chip; when the chip is mounted flip-chip, the inductor is stacked below the functional surface of the chip.

15. The packaging process of the three-dimensional integrated structure according to claim 14, characterized in that: In the chip mounting step, when the chip is flip-chip mounted, the back side of the chip is exposed outside the insulating dielectric layer.

16. The packaging process of the three-dimensional integrated structure according to claim 10, characterized in that: In the electroplating lead-out structure step, the lead-out structure includes a metal column and a lead layer. The metal column is formed by etching the insulating dielectric layer to form a groove and then electroplating metal to fill the groove. The lead layer electrically connects the chip to the metal column.

17. The packaging process of the three-dimensional integrated structure according to claim 10, characterized in that: The insulating dielectric layer in this process step is a plastic encapsulation compound.

18. The packaging process of the three-dimensional integrated structure according to claim 10, characterized in that: The process also includes further integration of the packaging structure into fan-out wafer-level packaging or system-level packaging modules.

Images