Detection circuit and communication system

Abstract

To provide a detection circuit and a communication system, capable of detecting deterioration of an insulating element with high accuracy, as an object of one embodiment.SOLUTION: According to one embodiment, there is provided a detection circuit including a first insulating element, a second insulating element, a first transmission test circuit, a second transmission test circuit, and a reception test circuit. The first transmission test circuit is connected to the first insulating element. The second transmission test circuit is connected to the second insulating element. The reception test circuit is connected to each of the first insulating element and the second insulating element. The reception test circuit is configured to output a detection signal corresponding to a difference between a voltage of the first insulating element and a voltage of the second insulating element.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a detection circuit and a communication system. [Background technology]

[0002] In an insulating element insulated from the primary side and the secondary side from each other, the insulation state may deteriorate due to aging or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 8,782,503 [Patent Document 2] U.S. Patent No. 9,224,670 [Patent Document 3] U.S. Pat. No. 9,274,167 [Patent Document 4] U.S. Patent No. 9,335,370 [Patent Document 5] US Patent Application Publication No. 2012 / 0153964 [Non-patent literature]

[0004] [Non-Patent Document 1] R. Yun, J. Sun, E. Gaalaas, B. Chen, “A Transformer-based Digital Isolator with 20kVPK Surge Capability and > 200kV / us Common Mode Transient Immunity”, 2016 Symposium on VLSI Circuits Digest of Technical Papers, pp15-17. [Non-Patent Document 2] Thomas Kugelstadt, “New Digital Capacitive Isolator Training Guide ISO74xx & ISO75xx”, Texas Instruments, 2010. [Non-Patent Document 3] Tom Bonifield, “High-voltage isolation quality and reliability for AMC130x”, Texas Instruments Technical Document, SSZY024. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a detection circuit and a communication system capable of detecting aging and other deterioration of an insulating element with high accuracy. [Means for solving the problem]

[0006] According to one embodiment, a first isolation element, a second isolation element, a first transmit test circuit, a second transmit test circuit, and a receive test circuit. Control circuit A detection circuit is provided having a first transmit test circuit and a first isolation element. Primary side of is connected to. The first transmit test circuit transmits a first test signal to the first isolation element. The second transmit test circuit includes a second isolation element Primary side of is connected to. The second transmit test circuit transmits a second test signal corresponding to the first test signal to the second isolation element. The receiving test circuit is 1. difference or if the second difference is equal to or less than a threshold, the first level A detection signal is output. The first difference is a difference between a voltage on the primary side of the first isolation element and a voltage on the primary side of the second isolation element. The second difference is a difference between a voltage on the secondary side of the first isolation element and a voltage on the secondary side of the second isolation element. The receiving test circuit outputs a detection signal of a second level when the first difference exceeds a threshold value. The control circuit controls a frequency of the first test signal to a first frequency. The first transmitting test circuit transmits a first test signal having the first frequency to the first isolation element. The second transmitting test circuit transmits a second test signal having the first frequency to the second isolation element. [Brief description of the drawings]

[0007] [Figure 1] 1 is a circuit diagram showing a configuration of a communication system including a detection circuit according to an embodiment. [Diagram 2] FIG. 4 is a circuit diagram showing a mechanism for detecting an abnormality in the embodiment. [Diagram 3] 6A and 6B are diagrams showing a difference in voltage of an insulating element depending on whether degradation occurs or not in the embodiment. [Figure 4] FIG. 13 is a diagram showing a configuration of a communication system including a detection circuit according to a first modified example of an embodiment. [Diagram 5] FIG. 13 is a diagram showing a configuration of a communication system including a detection circuit according to a second modified example of the embodiment. [Figure 6] FIG. 13 is a diagram showing a configuration of a communication system including a detection circuit according to a third modified example of the embodiment. [Figure 7] FIG. 13 is a diagram showing a configuration of a communication system including a detection circuit according to a fourth modified example of the embodiment. [Figure 8] FIG. 13 is a diagram showing a mechanism of anomaly detection in a fourth modified example of the embodiment. [Figure 9] FIG. 13 is a diagram showing a voltage of an insulating element to which a test signal is input in a fourth modified example of the embodiment. [Figure 10] FIG. 13 is a circuit diagram showing a configuration of a communication system including a POR (Power On Reset) circuit according to a fifth modified example of the embodiment. [Figure 11] FIG. 13 is a circuit diagram showing a configuration of a communication system including a UVLO (Under Voltage Lock Out) circuit according to a sixth modified example of an embodiment. [Figure 12] FIG. 13 is a circuit diagram showing a configuration of a communication system including an input circuit according to a seventh modified example of the embodiment. [Figure 13] FIG. 13 is a circuit diagram showing a configuration of a communication system including a trimming circuit according to an eighth modified example of the embodiment. [Figure 14] FIG. 13 is a diagram showing an operation of a reception test circuit according to a ninth modification of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, a communication system according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

[0009] (Embodiment) The detection circuit according to the embodiment is devised to detect insulation deterioration of the insulation element as a sign of insulation failure. Insulation deterioration of the insulation element refers to a state in which the insulation performance of the primary side and the secondary side has deteriorated, and refers to a state before the insulation element reaches an insulation failure (for example, a short circuit failure).

[0010] As shown in Fig. 1, the communication system 1 including the detection circuit 3 includes isolation elements 31 and 32. Each of the isolation elements 31 and 32 includes a galvanic isolation element that transmits signals by isolating the ground potential. Each of the isolation elements 31 and 32 is, for example, an isolation transformer. The communication system 1 detects insulation deterioration of the galvanic isolation elements. When insulation deterioration is detected, the communication system 1 stops signal transmission and issues a detection signal to the user indicating that insulation deterioration has been detected.

[0011] The galvanic isolation element may be either an isolation transformer (magnetic field coupling) or an isolation capacitance (electric field coupling). Also, it may be either a double isolation method in which there are two isolation elements on each chip, or a single isolation method in which there is one isolation element on either board. Alternatively, a dedicated board may have an isolation element and each chip without an isolation element may be connected. Furthermore, the insulating layer may be a silicon oxide film, a silicon nitride film, or a polyimide film.

[0012] When connecting high-voltage and low-voltage devices, galvanic isolation elements are used to prevent noise leakage and electric shock. Galvanic isolation elements are elements that transmit electrical signals while ensuring electrical isolation between input and output. Light, electric fields, and magnetic fields are often selected as the medium used to transmit signals.

[0013] Before going into the description of the embodiment, the insulation deterioration mode of the insulation element that is intended to be detected in this embodiment will be described. First, it is assumed that the insulation deterioration of the insulation element causes a leakage current to flow through the insulation element. In other words, the aged deterioration state is when the insulation element equivalently loses capacitance (C iso ) and resistance (R Leak) parallel model. This system is also based on the assumption that a differential signal is being transmitted to the isolation elements. Therefore, two transformers are used for the isolation transformer, and two capacitances are used for the isolation capacitance. Since the deterioration of an isolation element over time progresses from an area where a defect is inherent, it is unlikely that two isolation elements will deteriorate "simultaneously." Furthermore, the deterioration of an isolation element progresses gradually, and it is thought that it is unlikely that it will deteriorate suddenly at the same time intervals as a transmission signal (for example, less than a few nanoseconds).

[0014] For this reason, in the communication system 1, a plurality of isolation elements 31, 32 are configured as a differential transmission system, and the isolation elements 31 and 32 form a differential pair. As shown in Fig. 1, the detection circuit 3 is configured so as to be able to detect deterioration of the plurality of isolation elements 31, 32 from the difference between the characteristics of the elements. For example, the communication system 1 including the detection circuit 3 may be configured as shown in Fig. 1. Fig. 1 is a circuit diagram showing the configuration of the communication system 1 including the detection circuit 3.

[0015] The communication system 1 includes a transmission circuit 2, a reception circuit 4, and a detection circuit 3. The transmission circuit 2 is disposed between a signal source SS and the detection circuit 3. The communication system 1 may be implemented in the form of a transmission chip 11, an insulating layer 13, and a reception chip 12. In this case, the transmission chip 11 includes the transmission circuit 2, transmission test circuits 33 and 34, a reception test circuit 35, a primary part (inductive element 311) of the insulating element 31, and a primary part (inductive element 321) of the insulating element 32. The reception chip 12 includes a secondary part (inductive element 312) of the insulating element 31, a secondary part (inductive element 322) of the insulating element 32, and a reception circuit 4. The transmission chip 11 and the reception chip 12 are insulated from each other via the insulating layer 13. The primary part of the insulating element 31 and the secondary part of the insulating element 31 are insulated from each other via the insulating layer 13. The primary side portion of the insulating element 32 and the secondary side portion of the insulating element 32 are insulated from each other via the insulating layer 13. The insulating layer 13 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0016] The transmission circuit 2 has a differential driver circuit 21. The differential driver circuit 21 is, for example, of a single-phase input / differential output type, and has an input node 21a electrically connected to an output node of a signal source SS, a positive-phase output node 21b electrically connected to an input node 3ip on the P side of the detection circuit 3, and a negative-phase output node 21c electrically connected to an input node 3in on the N side of the detection circuit 3.

[0017] The differential driver circuit 21 receives a disable signal DS from an external device (e.g., a higher-level controller) at an input node 21d, and receives a signal V IN When the disable signal DS is at a non-active level (for example, at an L level), the differential driver circuit 21 receives a signal V IN Differential signal V according to D+ , V D- and output the signal V IN is a high-frequency signal, and the differential signal V D+ , V D- (not shown) respectively indicate the signal V IN When the disable signal DS is at an active level (for example, an H level), the differential driver 21 is disabled and stops operating.

[0018] The differential driver circuit 21 also receives a detection signal V BR The differential driver circuit 21 receives the detection signal V BR When is at an active level (for example, H level), operation stops regardless of the level of the disable signal DS.

[0019] The signal source SS may be configured differentially. In this case, the differential driver circuit 21 may be a differential input / differential output type differential amplifier. The positive phase input node of the differential driver 21 may be electrically connected to the positive phase output node of the signal source SS, and the negative phase input node may be electrically connected to the negative phase output node of the signal source SS.

[0020] The receiving circuit 4 is disposed between the detection circuit 3 and the load circuit LD. The receiving circuit 4 has a differential receiver circuit 41. The differential receiver 41 is of a differential input / single-phase output type, with a positive phase input node 41a electrically connected to a P-side output node 30p of the detection circuit 3, a negative phase input node 41b electrically connected to an N-side output node 30n of the detection circuit 3, and an output terminal 41c electrically connected to an input node of the load circuit LD. The output node 41c of the differential receiver circuit 41 is connected to the load circuit LD.

[0021] The differential receiver circuit 41 receives a differential signal V D+ , V D- The differential receiver circuit 41 receives a differential signal V D+ , V D- The load circuit LD outputs a signal Vout according to the input signal Vout to the load circuit LD.

[0022] The load circuit LD may be configured differentially. In this case, the differential receiver circuit 41 may be a differential input / differential output type differential amplifier. The positive phase output terminal of the differential receiver 41 may be electrically connected to the P-side input node of the load circuit LD, and the negative phase output terminal may be electrically connected to the N-side input node of the load circuit LD.

[0023] The detection circuit 3 is connected between the transmission circuit 2 and the reception circuit 4. The detection circuit 3 includes an insulating element (first insulating element) 31, an insulating element (second insulating element) 32, a transmission test circuit (first transmission test circuit) 33, a transmission test circuit (second transmission test circuit) 34, a reception test circuit 35, and a capacitance element C C1P , capacitance element C C2P , capacitance element C C1N , capacitance element C C2N , resistor element R LP , resistor element R LN has.

[0024] The primary side and the secondary side of the insulating element 31 are electrically insulated from each other. The insulating element 31 has an input node 31a and a ground node 31c on the primary side, and an output node 31b and a ground node 31d on the secondary side. The input node 31a and the output node 31b are electrically insulated from each other. The ground node 31c and the ground node 31d each have a ground potential, but are electrically insulated from each other.

[0025] The isolation element 31 is, for example, a galvanic isolation element that transmits a high-frequency signal while isolating the ground potential. The isolation element 31 includes an isolation transformer 313. The isolation transformer 313 has an inductive element 311 and an inductive element 312. The inductive element 311 has one end connected to the input node 31a and the other end connected to the ground node 31c. The inductive element 312 has one end connected to the output node 31b and the other end connected to the ground node 31d.

[0026] The inductive element 311 and the inductive element 312 in the isolation transformer 313 are electrically insulated from each other and magnetically coupled to each other. A parasitic capacitance C ISO The winding direction of inductive element 311 and the winding direction of inductive element 312 are in such a relationship that when a current flows from input node 31a to the ● of inductive element 311, a current flows from the ● of inductive element 311 to output node 31b. Note that inductive element 311 and inductive element 321 may be connected so that their winding directions are in opposite directions with respect to the current path, and connected to the same ground node. In that case, it is desirable that inductive element 312 and inductive element 322 have the same winding direction with respect to the current path.

[0027] The primary side and the secondary side of the insulating element 32 are electrically insulated from each other. The insulating element 32 has an input node 32a and a ground node 32c on the primary side, and an output node 32b and a ground node 32d on the secondary side. The input node 32a and the output node 32b are electrically insulated from each other. The ground node 32c and the ground node 32d each have a ground potential, but are electrically insulated from each other.

[0028] The insulating element 32 includes, for example, a galvanic insulating element that transmits a high-frequency signal while isolating the ground potential. The insulating element 32 includes an insulating transformer 323. The insulating transformer 323 has an inductive element 321 and an inductive element 322. The inductive element 321 has one end connected to the input node 32a and the other end connected to the ground node 32c. The inductive element 322 has one end connected to the output node 32b and the other end connected to the ground node 32d.

[0029] The inductive element 321 and the inductive element 322 in the isolation transformer 323 are electrically insulated from each other and magnetically coupled to each other. A parasitic capacitance C ISO The winding directions of inductive element 321 and inductive element 322 are related in such a way that when a current flows from input node 32a to the ● of inductive element 321, a current flows from the ● of inductive element 321 to output node 32b.

[0030] The transmission test circuit 33 receives an inverted disable signal DSB from the outside (for example, a higher-level controller) at an input node 33a. The inverted disable signal DSB is a signal obtained by logically inverting the disable signal DS, and is an L-active signal. The transmission test circuit 33 has an output node 33b connected to a capacitance element C C1P The output node 33b of the transmission test circuit 33 is connected to the primary side of the insulating element 31 via a capacitance element C C1P The transmission test circuit 33 is electrically connected to one end of the inductive element 311 via a test signal i TEST (ω) can be generated. Test signal i TEST (ω) is a high frequency signal.

[0031] When the inverted disable signal DSB is at an active level (for example, an L level), the transmission test circuit 33 outputs the test signal i TEST(ω) and outputs it to the isolation element 31. When the inverted disable signal DS is at a non-active level (for example, H level), the transmission test circuit 33 is disabled and stops operating.

[0032] The transmission test circuit 34 receives an inverted disable signal DSB from the outside (for example, a higher-level controller) at an input node 34a. The inverted disable signal DSB is a signal obtained by logically inverting the disable signal DS, and is an L-active signal. The transmission test circuit 34 has an output node 34b connected to a capacitance element C C1N The output node 34b of the transmission test circuit 34 is connected to the primary side of the insulating element 32 via a capacitance element C C1N The transmission test circuit 34 is electrically connected to one end of the inductive element 321 via a test signal i TEST (ω) can be generated. Test signal i TEST (ω) is a high frequency signal.

[0033] When the inverted disable signal DSB is at an active level (for example, an L level), the transmission test circuit 34 outputs the test signal i TEST (ω) and outputs it to the isolation element 32. When the inverted disable signal DS is at a non-active level (for example, H level), the transmission test circuit 34 is disabled and stops operating.

[0034] The receiving test circuit 35 has an input node 35a connected to a capacitance element C C1P and the input node 35b is connected to the primary side of the insulating element 31 via a capacitance element C C1N The receiving test circuit 35 has an input node 35a connected to the primary side of the insulating element 32 via a capacitance element C, and an output node 35c connected to an external device (for example, a circuit in a subsequent stage) and the differential driver circuit 21 of the transmitting circuit 2. C1P The input node 35b is electrically connected to one end of the inductive element 311 via a capacitance element C C1N is electrically connected to one end of the inductive element 321 via

[0035] The receiving test circuit 35 outputs a detection signal V according to the difference between the voltage of the insulating element 31 and the voltage of the insulating element 32. BR When the difference between the voltage of the insulating element 31 and the voltage of the insulating element 32 is equal to or less than the threshold, the receiving test circuit 35 outputs a detection signal V BR When the difference between the voltage of the insulating element 31 and the voltage of the insulating element 32 exceeds a threshold, the receiving test circuit 35 outputs a detection signal V BR The detection signal V BR A non-active level indicates that no sign of insulation failure has been detected, and an active level indicates that a sign of insulation failure has been detected.

[0036] Non-active level detection signal V BR Upon receiving this, the differential driver 21 of the transmission circuit 2 performs a signal transmission operation if the disable signal DS is at a non-active level, and stops the signal transmission operation if the disable signal DS is at an active level.

[0037] Active level detection signal V BR At the input node 21e, the differential driver 21 of the transmission circuit 2 stops the signal transmission operation regardless of the level of the disable signal DS.

[0038] Capacitive element C C1P are connected between the transmission circuit 2, the transmission test circuit 33, the reception test circuit 35 and the isolation element 31. C1P has one end connected to the output node 21 b of the transmission circuit 2 , the output node 33 b of the transmission test circuit 33 , and the input node 35 a of the reception test circuit 35 , and the other end connected to the input node 31 a of the isolation element 31 .

[0039] Capacitive element C C2P is connected between the insulating element 31 and the resistive element RLP and the receiving circuit 4. C2P has one end connected to the output node 31b of the insulating element 31 and one end of the resistive element RLP, and has the other end connected to the input node 41a of the receiving circuit 4.

[0040] Capacitive element C C1N are connected between the transmission circuit 2, the transmission test circuit 34, the reception test circuit 35 and the isolation element 32. C1N has one end connected to the output node 21 c of the transmission circuit 2 , the output node 34 b of the transmission test circuit 34 , and the input node 35 b of the reception test circuit 35 , and the other end connected to the input node 32 a of the isolation element 32 .

[0041] Capacitive element C C2N is connected between the insulating element 32 and the resistive element RLN and the receiving circuit 4. C2N One end of the resistor R LN and the other end is connected to an input node 41b of the receiving circuit 4.

[0042] Resistance element R LP is an insulating element 31 and a capacitive element C C2P The resistor element R LP One end of the capacitor C is connected to the output node 31b of the insulating element 31 and the other end of the capacitor C is connected to the output node 31b of the insulating element 31. C2P and the other end is connected to the ground potential.

[0043] Resistance element R LN is an insulating element 32 and a capacitive element C C2N The resistor element R LN One end of the capacitor C is connected to the output node 32b of the insulating element 32 and the other end of the capacitor C is connected to the output node 32b of the insulating element 32. C2N and the other end is connected to the ground potential.

[0044] In the communication system 1, the detection circuit 3 can detect the deterioration of the insulating elements 31 and 32 with high accuracy.

[0045] When the disable signal DS is at an L level, the communication system 1 operates in a normal mode. In the normal mode, the transmission test circuits 33 and 34 are disabled, and the transmission circuit 2 is enabled. In the normal mode, communication is performed via the isolation elements 31 and 32 (isolation transformers 313 and 314). The input signal is differentiated by the transmission circuit 2, and the differential signal is transmitted by the isolation elements 31 and 32, so that the signal can be detected by the differential reception circuit 4.

[0046] When the disable signal DS is at H level, the communication system 1 operates in a test mode. In the test mode, the transmission test circuits 33 and 34 are enabled and the transmission circuit 2 is disabled. In the test mode, the same test signal (e.g., a sine wave) i is output from the transmission test circuit 33 and the transmission test circuit 34. TEST (ω) is applied to the isolation element 31 and the isolation element 32. The test signal i TEST (ω) and the test signal i of the transmission test circuit 34 TEST (ω) may be signals of substantially the same frequency and phase.

[0047] If no deterioration occurs in the isolation elements 31 and 32 over time, the terminal voltages of the isolation elements 31 and 32 will be substantially the same, so that the input differential voltage of the receiving test circuit 35 will be approximately 0V.

[0048] On the other hand, when the isolation elements 31 and 32 are degraded with age, the degradation progresses from the weakest point, and the input impedance of the isolation elements 31 and 32 becomes different. Therefore, the transmission test circuit 33 and the transmission test circuit 34 transmit the test signal i of the same frequency and the same amplitude. TEST When (ω) is input, an input difference voltage of the receiving test circuit 35 is generated.

[0049] When a differential voltage exceeding a threshold is input to the receiving test circuit 35, the receiving test circuit 35 determines that the insulating element 31 or the insulating element 32 has deteriorated with age, and outputs a detection signal V BR The detection signal V BRWhen this signal is sent, the transmission circuit 2 is forcibly controlled to stop signal transmission, and the detection signal V BR This allows the user to be informed of the deterioration of the device over time.

[0050] The receiving test circuit 35 may have either two single-phase inputs or one differential input. In the case of two single-phase inputs, the determination can be made by comparing the maximum, average, and effective values ​​of each single-phase signal. In the case of one differential signal, the comparison is simple, but it is desirable that the signals sent from the transmitting test circuit 33 and the transmitting test circuit 34 are in phase with each other.

[0051] Now, let us take a closer look at the mechanism of fault detection in the embodiment. The fault detection mechanism in the isolation transformers 313 and 323 will be described with reference to Fig. 2. Fig. 2 shows the P-side portion of Fig. 1.

[0052] When the disable signal DS is at H level, the transmission circuit 2 is in a disabled operation state, and it is desirable that the output of the transmission circuit 2 be Hi-Z (high impedance). In this state, the transmission test circuit 33 outputs a test signal i TEST When the current (ω) is output, it does not flow to the output terminal of the transmission circuit 2, but most of it flows to the isolation transformer 313. The input impedance (Z IN ) is the inductance value L1 of the inductive element 311, the inductance L2 of the inductive element 312, the coupling coefficient k between the inductive element 311 and the inductive element 312, and the parasitic capacitance C between the inductive element 311 and the inductive element 312. ISO , resistor element R LP Resistance value R LP , the resistance value R of the insulating leak path between the inductive element 311 and the inductive element 312 Leak It depends on.

[0053] Input impedance Z of the isolation transformer 313 IN There exists a maximum ω0. ω0 is, for example, the inductive element 311, the parasitic capacitance C ISOis the resonant frequency of the loop including the inductive element 312. When the insulation deterioration of the insulating transformer 313 progresses, a parasitic capacitance C ISO In parallel with the insulation leakage path resistance R Leak is connected to the test signal i TEST When the frequency of (ω) is set to ω=ω0, the resistance value of the insulation leakage path R Leak The change in the voltage v of the isolation transformer 313 MEAS It can be detected with high sensitivity as a change in (ω).

[0054] In Figure 3, the test signal i TEST The voltage v of the isolation transformer 313 when (ω) is input MEAS The solid line shows the case where there is no deterioration of the insulating elements 31 and 32, and the dashed line shows the case where the insulating elements 31 and 32 have deteriorated with time and the resistance value of the insulating leak path is R Leak 3, when there is no deterioration of the isolation elements 31 and 32, the input impedance of the isolation elements becomes high because of resonance at ω = ω0, and a large v MEAS (ω0)=v1. On the other hand, due to aging, the resistance of the insulation leakage path becomes R Leak = 1kΩ, the Q factor drops and the measured v MEAS (ω0)=v2 is a small value. In the example of Figure 3, the test signal i TEST It is shown that by setting the frequency ω of (ω) to ω0, it is possible to ensure a large voltage difference Δv between the voltage v1 when there is no aging deterioration and the voltage v2 when there is aging deterioration. The voltage difference Δv corresponds to, for example, an impedance change of 100 times (40 dB) compared to 1 kΩ in short-circuit mode. The threshold value used in the receiving test circuit 35 can be determined according to the voltage difference Δv. For example, the threshold value can be determined to be Δv×α (0<α≦1).

[0055] In the case of the differential signal transmission system in Figure 1, the test signal i TESTWhen testing isolation elements 31 and 32 at (ω), if deterioration over time occurs in either isolation element 31, 32, it is found that a large differential voltage is input to receiving test circuit 35. As a result, insulation deterioration due to aging or the like of the isolation elements can be detected with high sensitivity, and signs of insulation failure of the isolation elements can be detected.

[0056] The load impedance of the isolation transformer 313 is the resistive element R LP The load impedance of the isolation transformer 323 is the resistive element R LN In addition, the coupling capacitance (capacitance element C C1P ,C C1N ) and coupling capacitance (capacitance element C C2P ,C C2N ) may be omitted.

[0057] As described above, in the embodiment, in the detection circuit 3 of the communication system 1, the two transmission test circuits 33, 34 transmit the same test signal to the two isolation elements 31, 32, and the reception test circuit 35 outputs a detection signal according to the voltage difference between the two isolation elements 31, 32. When the voltage difference between the two isolation elements 31, 32 is equal to or less than a threshold, the reception test circuit 35 outputs a detection signal (for example, L level) indicating that no degradation has occurred, and when the voltage difference between the two isolation elements 31, 32 exceeds the threshold, the reception test circuit 35 outputs a detection signal (for example, H level) indicating that degradation has occurred. This makes it possible to detect the degradation of the isolation elements with high accuracy as a sign of insulation failure. When the isolation elements 31, 32 are isolation transformers 313, 323, the degradation of the isolation elements 31, 32 can be detected with high sensitivity by using the resonance phenomenon.

[0058] For example, in an isolation element, when the primary and secondary sides are optically coupled with a photocoupler, the photocoupler can ensure electrical insulation with the molded resin between the light-emitting element (e.g., light-emitting diode) and the light-receiving element (e.g., photodiode). In the event of dielectric breakdown in the resin, the resin explodes due to the heat associated with the breakdown, and the primary and secondary sides do not become conductive, resulting in a breakdown mode. This provides high reliability in the insulation function.

[0059] However, when transmitting multiple signals, photocouplers must be used for each signal, which increases costs. Furthermore, mounting multiple light-emitting elements and multiple light-receiving elements in one package can cause crosstalk problems, complicating assembly, which can lead to reduced reliability and increased costs.

[0060] On the other hand, in this embodiment, the insulating elements 31 and 32 use a magnetic field as a signal transmission medium. In the detection circuit, a configuration is used in which the primary side and the secondary side are magnetically coupled by the insulating elements 31 and 32. When the magnetic field is used as the transmission medium, insulating transformers 313 and 323 having coils formed on both ends of an insulating layer are used. The insulating transformer may use the insulating layer of a polyimide layer on the chip or the wiring layer of the chip, but in either case, the thickness of the insulating layer is about 10 to 30 μm, which is an order of magnitude thinner than the insulating interval (400 μm or more) of the molded resin of the photocoupler. For this reason, insulation failures such as short circuit failures are likely to occur.

[0061] In response to this problem, it is possible to configure the isolation elements in a cascade connection to provide a double-insulation system. This configuration can improve the dielectric strength, but the insulation interval is still narrower than that of a photocoupler, and does not fundamentally solve the problem. Therefore, it is effective to detect the deterioration of the isolation elements 31 and 32 as a sign of insulation failure before it occurs, as in this embodiment.

[0062] Although not shown, the detection circuit 3 may have a plurality of insulating elements 31 connected in series in a cascade connection between the primary side and the secondary side, and a plurality of insulating elements 32 connected in series in a cascade connection between the primary side and the secondary side. This can improve the dielectric strength.

[0063] The transmission test circuit 33 and the transmission test circuit 34 each transmit a test signal i TEST (ω) may be received from the outside (for example, a higher-level controller). In this case, the test signals i TESTThe configuration for generating (ω) can be omitted, and the configurations of the transmission test circuits 33 and 34 can be simplified.

[0064] At least one of the disable signal DS received by the transmission circuit 2 and the inverted disable signal DSB received by each of the transmission test circuit 33 and the transmission test circuit 34 may be input from the outside (for example, a higher-level controller).

[0065] As a first modified example of the embodiment, the communication system 1i may be configured as shown in Fig. 4. Fig. 4 is a diagram showing the configuration of a communication system 1i including a detection circuit 3i according to a first modified example of the embodiment.

[0066] The communication system 1i has a detection circuit 3i instead of the detection circuit 3 (see FIG. 1). In the detection circuit 3i, a transmission test circuit 33, a transmission test circuit 34, and a reception test circuit 35 are arranged on the reception circuit 4 side. The communication system 1i may be implemented in the form of a transmission chip 1i1, an insulating layer 1i3, and a reception chip 1i2. In this case, the transmission chip 1i1 is equipped with the transmission circuit 2, the inverter INV1, the inverter INV2, the insulating element DE, the primary side part (inductive element 311) of the insulating element 31, and the primary side part (inductive element 321) of the insulating element 32. The reception chip 1i2 is equipped with the secondary side part (inductive element 312) of the insulating element 31, the secondary side part (inductive element 322) of the insulating element 32, the transmission test circuits 33 and 34, the reception test circuit 35, and the reception circuit 4. The transmission chip 1i1 and the reception chip 1i2 are insulated from each other via the insulating layer 1i3. The primary side portion of the insulating element 31 and the secondary side portion of the insulating element 31 are insulated from each other via an insulating layer 1i3. The primary side portion of the insulating element 32 and the secondary side portion of the insulating element 32 are insulated from each other via an insulating layer 1i3. The insulating layer 1i3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0067] The output node 33b of the transmission test circuit 33 is connected to an input node 41a of the differential receiver circuit 41 of the receiving circuit 4, and a capacitance element C C2P 1. The insulating element 31 is connected to the secondary side thereof via a resistor R1.

[0068] The transmission test circuit 34 has an output node 34b connected to an input node 41b of the differential receiver 41 of the receiving circuit 4, and a capacitance element C C2N 1. The secondary side of the insulating element 32 is connected via

[0069] The receiving test circuit 35 has an input node 35a connected to an input node 41a of the differential receiver circuit 41 of the receiving circuit 4, and a capacitance element C C2P The input node 35b is connected to the input node 41b of the differential receiver circuit 41 of the receiving circuit 4, and the capacitance element C C2N The output node 35c is connected to the outside (for example, a circuit at a subsequent stage) and an input node 41d of the differential receiver 41 of the receiving circuit 4.

[0070] The principle of detecting the deterioration of the insulating elements 31 and 32 is the same as in the embodiment, except that when the input impedance of the receiving circuit 4 is large, the input of the receiving circuit 4 does not need to be controlled.

[0071] In the test mode operation, when the difference between the voltage of the isolation element 31 and the voltage of the isolation element 32 is equal to or less than a threshold value, the receiving test circuit 35 outputs a non-active level detection signal V BR When the difference between the voltage of the insulating element 31 and the voltage of the insulating element 32 exceeds a threshold, the detection signal V BR The point of outputting the signal is the same as in the embodiment.

[0072] Non-active level detection signal V BR Upon receiving this, the differential receiver circuit 41 of the receiving circuit 4 performs a signal output operation, and outputs an active-level detection signal V BR When a warning signal is received, the differential receiver circuit 41 of the receiving circuit 4 stops outputting signals. This makes it possible to prevent the output signal of the receiving circuit from becoming unstable in response to the detection of a sign of insulation failure.

[0073] 4, inverters INV1, INV2 and an isolation element DE may be connected in series between the input node 21d of the differential driver circuit 21 and input nodes 33a, 34a of the transmission test circuits 33, 34. The input side and output side of each of the isolation elements DE are electrically insulated from each other, and a signal can be transmitted from the input side to the output side.

[0074] This makes it possible to synchronize the disable signal DS of the transmission circuit 2 with the inverted disable signal DSB of the transmission test circuits 33 and 34, thereby enabling proper switching between the normal mode and the test mode.

[0075] As a second modified example of the embodiment, a communication system 1j may be configured as shown in Fig. 5. Fig. 5 is a diagram showing the configuration of a communication system 1j including a detection circuit 3j according to the second modified example of the embodiment.

[0076] In the communication system 1j, a plurality of insulating elements 31 and 32 are configured as a plurality of single-phase transmission systems. The communication system 1j has a plurality of transmitting circuits 2j-1 and 2j-2, a detecting circuit 3j, and a plurality of receiving circuits 4j-1 and 4j-2 instead of the transmitting circuit 2, the detecting circuit 3, and the receiving circuit 4 (see FIG. 1). The communication system 1j may be implemented in the form of a transmitting chip 1j1, an insulating layer 1j3, and a receiving chip 1j2. In this case, the transmitting chip 1j1 is equipped with the transmitting circuits 2j-1 and 2j-2, the control circuit 36j, the transmitting test circuits 33 and 34, the receiving test circuit 35, the primary side part of the insulating element 31 (the inductive element 311), and the primary side part of the insulating element 32 (the inductive element 321). The receiving chip 1j2 is equipped with a secondary part (inductive element 312) of the insulating element 31, a secondary part (inductive element 322) of the insulating element 32, and receiving circuits 4j-1 and 4j-2. The transmitting chip 1j1 and the receiving chip 1j2 are insulated from each other via an insulating layer 1j3. The primary part of the insulating element 31 and the secondary part of the insulating element 31 are insulated from each other via an insulating layer 1j3. The primary part of the insulating element 32 and the secondary part of the insulating element 32 are insulated from each other via an insulating layer 1j3. The insulating layer 1j3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0077] Each transmission circuit 2j has a single-phase input / single-phase output type single-phase driver 21j. The single-phase driver 21j of each transmission circuit 2j-1, 2j-2 has an input node 21a electrically connected to the output nodes of the signal sources SS-1, SS-2, and an output node 21b connected to a capacitance element C C1P ,C C1N Each of the receiving circuits 4j-1 and 4j-2 has a single-phase receiver 41j of a single-phase input / single-phase output type. The single-phase receiver 41j of the receiving circuits 4j-1 and 4j-2 has an input node 41a connected to a capacitance element C C2P ,C C2N and an output node 41c is electrically connected to the load circuits LD-1 and LD-2.

[0078] As a result, each of the transmission circuits 2j-1 and 2j-2 transmits a single-phase signal V S1 ,V S2 The isolation elements 31 and 32 of the detection circuit 3j transmit a single-phase signal V S1 ,V S2 Each of the receiving circuits 4j-1 and 4j-2 transmits a single-phase signal V S1 ,V S2 In other words, signal transmission is performed in each of the multiple single-phase transmission systems.

[0079] On the other hand, the difference between the characteristics of two insulating elements is used to detect deterioration of the insulating element. C1P ,C C1N , and are connected to two input nodes 35a, 35b of a receiving test circuit 35. For example, the two transmitting test circuits 33, 34 transmit test signals i TEST (ω) is transmitted to the receiving test circuit 35, and the difference in voltage between the insulating elements 31 and 32 is detected by the receiving test circuit 35. When the difference in voltage between the insulating elements 31 and 32 is equal to or less than a threshold, the receiving test circuit 35 transmits a detection signal V BRWhen the voltage difference between the insulating elements 31 and 32 exceeds a threshold value, a detection signal V BR By adopting this configuration, it becomes possible to detect deterioration of the insulating elements 31 and 32 even in a communication system 1j in which a plurality of single-phase transmission systems are configured.

[0080] In addition, when the communication system 1j is in the normal mode, one single-phase signal V S1 but the other single-phase signal V S2 When the communication system 1j does not transmit the signal, the transmission circuit 2j-2, the isolation element 32, and the reception circuit 4j-2 may be configured as dummy circuits. By leaving the transmission circuit 2j-2 in a disabled state, the communication system 1j can execute both the normal mode and the test mode.

[0081] As a third modified example of the embodiment, the communication system 1k may be configured as shown in Fig. 6. Fig. 6 is a diagram showing the configuration of a communication system 1k including a detection circuit 3k according to the third modified example of the embodiment.

[0082] The communication system 1k has a detection circuit 3k instead of the detection circuit 3 (see FIG. 1). The detection circuit 3k further has a control circuit 36k. The communication system 1k may be implemented in the form of a transmission chip 1k1, an insulating layer 1k3, and a reception chip 1k2. In this case, the transmission chip 1k1 is equipped with a transmission circuit 2, transmission test circuits 33 and 34, a reception test circuit 35, a primary part (inductive element 311) of the insulating element 31, and a primary part (inductive element 321) of the insulating element 32. The reception chip 1k2 is equipped with a secondary part (inductive element 312) of the insulating element 31, a secondary part (inductive element 322) of the insulating element 32, and a reception circuit 4. The transmission chip 1k1 and the reception chip 1k2 are insulated from each other via the insulating layer 1k3. The primary part of the insulating element 31 and the secondary part of the insulating element 31 are insulated from each other via the insulating layer 1k3. The primary side portion of the insulating element 32 and the secondary side portion of the insulating element 32 are insulated from each other via an insulating layer 1k3. The insulating layer 1k3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0083] The control circuit 36k receives the inverted disable signal DSB at an input node 36a, and has an output node 36b connected to a control node 33c of the transmission test circuit 33, a control node 34c of the transmission test circuit 34, and a control node 35c of the reception test circuit 35. This allows the control circuit 36k to supply control signals to each of the transmission test circuit 33, the transmission test circuit 34, and the reception test circuit 35.

[0084] For example, in order to make the voltage difference between the presence and absence of degradation large, it is effective to set the frequency of the test signal to a specific frequency ω0 as shown in FIG. 3. The frequency ω0 is, for example, the frequency of the inductive element 311, the parasitic capacitance C ISO , is the resonant frequency of the loop that includes the inductive element 312.

[0085] However, the resonant frequency may vary due to the influence of manufacturing variations in the elements.

[0086] For example, the inductive element 311, the parasitic capacitance C ISO , the resonant frequency of the loop including the inductive element 312 is ω1, and the inductive element 321 and the parasitic capacitance C ISO Assume that the resonant frequency of the loop including the inductive element 322 is ω1. In this case, the control circuit 36k shown in FIG. 6 controls the transmission test circuit 33 to generate a test signal i TEST The control circuit 36k controls the transmission test circuit 34 to supply a test signal i of frequency ω1 to the isolation element 31. TEST (ω2) is supplied from the transmission test circuit 34 to the isolation element 32.

[0087] Here, ω1 is smaller than ω0, and Z IN (ω1)>Z IN (ω0). Parameter ΔZ IN =Z IN (ω1)-Z IN (ω0) and parameter ΔZ IN The difference voltage Δv of the isolation transformers 313 and 323 according toMEAS When the parameter ΔZ is defined, the parameter ΔZ IN The magnitude of the difference voltage Δv of the isolation transformers 313 and 323 changes. MEAS The receiving test circuit 35 detects the difference voltage Δv MEAS The deterioration of the insulating transformers 313 and 323 over time can be detected depending on whether the amount of change from the standard value exceeds a threshold value.

[0088] As a fourth modified example of the embodiment, the communication system 1n may be configured as shown in Fig. 7. Fig. 7 is a diagram showing the configuration of a communication system 1n including a detection circuit 3n according to the fourth modified example of the embodiment.

[0089] In the embodiment to the third modified example of the embodiment, an insulating transformer is assumed as the insulating element, but aging deterioration of the insulating element can also be detected for the insulating capacitance.

[0090] In the communication system 1n, the insulating element 31n has an insulating capacitance 313n instead of the insulating transformer 313 (see FIG. 1), and a parasitic capacitance C SP The communication system 1n may be implemented in the form of a transmitting chip 1n1, an insulating layer 1n3, and a receiving chip 1n2. In this case, the transmitting chip 1n1 is equipped with a transmitting circuit 2, transmitting test circuits 33 and 34, a primary part (inductive element 311) of the insulating element 31, and a primary part (inductive element 321) of the insulating element 32. The receiving chip 1n2 is equipped with a receiving test circuit 35, a secondary part (inductive element 312) of the insulating element 31, a secondary part (inductive element 322) of the insulating element 32, and a receiving circuit 4. The transmitting chip 1n1 and the receiving chip 1n2 are insulated from each other via the insulating layer 1n3. The primary part of the insulating element 31 and the secondary part of the insulating element 31 are insulated from each other via the insulating layer 1n3. The primary part of the insulating element 32 and the secondary part of the insulating element 32 are insulated from each other via the insulating layer 1n3. The insulating layer 1n3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0091] The insulating capacitance 313n has one end connected to the transmission test circuit 33n and the transmission circuit 2, and the other end connected to the reception test circuit 35n and the reception circuit 4. SP is a resistor R LP and the other end is connected to the ground potential.

[0092] The insulating element 32n has an insulating capacitance 323n instead of the insulating transformer 323 (see FIG. 1), and has a parasitic capacitance C SN The insulating capacitance 323n has one end connected to the transmission test circuit 34n and the transmission circuit 2, and the other end connected to the reception test circuit 35n and the reception circuit 4. A parasitic capacitance C SN is a resistor element R LN and the other end is connected to the ground potential.

[0093] The insulating capacitors 313n and 323n can be constructed by disposing metal plates on both ends of an insulating layer. The thickness of the insulating layer is, for example, 10 to 30 μm, which is an order of magnitude thinner than the insulating interval (400 μm or more) of the mold resin of the photocoupler.

[0094] In the fourth modified example of the embodiment, two insulating capacitances 31n, 32n are configured as a differential transmission system, and by placing the transmitting test circuits 33n, 34n on the transmitting side and the receiving test circuit 35n on the receiving side, it is possible to detect signs of insulation failure, as in the embodiment.

[0095] When the disable signal DS is at an L level, the transmission test circuits 33n, 34n and the reception test circuit 35n are disabled, the transmission circuit 2 is enabled, and communication is performed via the insulating capacitances 313n, 323n.

[0096] When the disable signal DS is at H level, the transmission test circuits 33n, 34n and the reception test circuit 35n are enabled, the transmission circuit 2 is disabled, and the test mode operation is performed. In the test mode operation, the same test signal v is output from the transmission test circuit 33n and the transmission test circuit 34n. TEST (ω) is applied to insulating element 33n and insulating element 34n.

[0097] When the isolation elements 33n, 34n are in good condition, the output voltages of the isolation elements 33n, 34n are approximately the same, so that the difference voltage of the receiving test circuit 35n is approximately 0V.

[0098] When an insulation leak occurs in one of the insulation elements (insulation element 33n or insulation element 34n), a corresponding differential voltage is input to the reception test circuit 35n. When a differential voltage exceeding a threshold is input, the reception test circuit 35n performs control so that unnecessary output Vout is not output from the reception circuit 4 to the load LD.

[0099] Now, let us take a closer look at the fault detection mechanism in the fourth modified example of the embodiment. The fault detection mechanism in the insulating capacitance will be explained with reference to Fig. 8. Fig. 8 shows the P side portion of Fig. 7.

[0100] When the disable signal DS is at H level, the transmission circuit 2 is in a disabled operation state, and it is desirable that the output of the transmission circuit 2 be Hi-Z (high impedance). In this state, the transmission test circuit 33n outputs a test signal v TEST When the test signal v (ω) is output, it does not flow to the output terminal of the transmission circuit 2, but mostly flows to the insulating capacitance 313n. TEST (ω) may be a voltage signal that depends on frequency ω.

[0101] Test signal v TEST (ω) is transmitted from the primary side through the insulating capacitance 313n to the secondary side, and the test voltage v MEAS (ω) is applied. The transfer function H of the insulating capacitance 313n is C1 / C SP / R LP / R LeakThe low-frequency transfer function H is determined by the resistance value R of the insulating leakage path. Leak It varies greatly depending on

[0102] Therefore, the resistance value R of the insulation leakage path Leak The response signal v MEAS The detection sensitivity is the change in the test signal v TEST The lower the frequency ω0, the higher the gain. However, in a typical system, a high-pass filter HPF (C1 and R LP ) is inserted, so the test signal v TEST When the frequency ω0 is low, the response signal v MEAS Therefore, the level of the test signal v TEST The frequency ω0 of the response signal v MEAS The level of may be determined to be an appropriate level.

[0103] Figure 9 shows the test signal v TEST Response signal v when (ω) is input MEAS In FIG. 9, the solid line shows the case where there is no deterioration of the insulating element, and the dashed line shows the case where deterioration of the insulating element occurs and R Leak This shows the case where the resistance is 10kΩ.

[0104] As shown in Figure 9, in the case of an isolation element without aging, the low-frequency band frequency F T The transfer function at R becomes a small value, and the detected voltage v11 becomes a small level. Leak = 10kΩ, the low frequency band frequency F T The transfer function becomes a large value, and the detected voltage v12 becomes a large level. In the example of Figure 9, the short circuit mode of 10 kΩ can be detected as a differential voltage Δv10 corresponding to an impedance change of 5 times (14 dB).

[0105] In the case of the differential signal transmission system in Figure 7, the test signal v TESTWhen the isolation elements 31n and 32n are tested at (ω), it can be seen that if deterioration occurs in one of the isolation elements (isolation element 31n or isolation element 32n), a large differential voltage Δv10 is input to the receiving test circuit 35n. As a result, it is possible to detect the deterioration of the isolation elements with high sensitivity, and to detect signs of insulation failure in the isolation elements. Furthermore, when a differential voltage Δv10 exceeding a threshold is input to the receiving test circuit 35n, the receiving test circuit 35n is controlled so that unnecessary output is not output from the receiving test circuit 35n to the load circuit LD.

[0106] The load impedance of the insulating capacitances 313n and 323n does not have to be a resistance.

[0107] In this way, when the insulating capacitances 313n and 323n are used as the insulating elements 31n and 32n, the frequency ω in the low frequency band is T A test signal v having TEST By using the test signal v (ω), the deterioration of the insulating elements 31n and 32n can be detected with high sensitivity. TEST By changing the frequency ω of (ω), the deterioration over time of the insulating elements 31n and 32n can be detected with high sensitivity.

[0108] As a fifth modification of the embodiment, the communication system 1p may generate a disable signal DS in a POR (Power On Reset) circuit 5p as shown in Fig. 10. Fig. 10 is a circuit diagram showing a configuration of the communication system 1p including the POR circuit 5p in the fifth modification of the embodiment.

[0109] The communication system 1p further includes a POR circuit 5p, an electronic circuit 6p, an electronic circuit 7p, an inverter INV1, and an inverter INV2, in comparison with the communication system 1 (see FIG. 1). The communication system 1p may be implemented in the form of a transmitting chip 1p1, an insulating layer 1p3, and a receiving chip 1p2. In this case, the transmitting chip 1p1 is equipped with a POR circuit 5p, an electronic circuit 6p, a transmitting circuit 2, an inverter INV1, an inverter INV2, transmitting test circuits 33 and 34, a receiving test circuit 35, a primary part (inductive element 311) of the insulating element 31, and a primary part (inductive element 321) of the insulating element 32. The receiving chip 1p2 is equipped with a POR circuit 8p, a secondary part (inductive element 312) of the insulating element 31, a secondary part (inductive element 322) of the insulating element 32, a receiving circuit 4, and an electronic circuit 7p. The transmitting chip 1p1 and the receiving chip 1p2 are insulated from each other via an insulating layer 1p3. The primary side portion of the insulating element 31 and the secondary side portion of the insulating element 31 are insulated from each other via an insulating layer 1p3. The primary side portion of the insulating element 32 and the secondary side portion of the insulating element 32 are insulated from each other via an insulating layer 1p3. The insulating layer 1p3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0110] The POR circuit 5p is a circuit that initializes the communication system 1p after the power supply voltage has been stabilized at a predetermined voltage (e.g., a recommended voltage) for a predetermined period of time when the communication system 1p is powered on. The predetermined period of time may be experimentally determined in advance as the time required for the power supply of the communication system 1p to be stabilized.

[0111] The POR circuit 5p is connected between the power supply terminal PS1 and the transmitting circuit 2, the detection circuit 3, and the electronic circuit 6p. The POR circuit 5p has an input node 5p1 connected to the power supply terminal PS1, an output node 5p2 connected to the electronic circuit 6p, and an output node 5p3 connected to the transmitting circuit 2 and also connected to the transmitting test circuits 33 and 34 via inverters INV1 and INV2. The electronic circuit 6p is connected to the input side of the transmitting circuit 2.

[0112] The POR circuit 8p is connected between the power supply terminal PS2 and the receiving circuit 4 and the electronic circuit 7p. The POR circuit 8p has an input node 8p1 connected to the power supply terminal PS2 and an output node 8p2 connected to the electronic circuit 7p. The electronic circuit 7p is connected to the output side of the receiving circuit 4.

[0113] In the communication system 1p, the issuance period of the disable signal DS is based on the POR circuit 5p. The POR circuit 5p monitors the power supply voltage received from the outside at the input node 5p1 via the power supply terminal PS1. The POR circuit 8p monitors the power supply voltage received from the outside at the input node 8p1 via the power supply terminal PS2.

[0114] At power-on, when the power supply voltage received at the input node 5p1 reaches a predetermined voltage (eg, the lower limit of a recommended voltage range) and a predetermined time has elapsed, the POR circuit 5p issues a reset pulse signal RST1, and the electronic circuit 6p is reset.

[0115] At power-on, when the power supply voltage received at the input node 8p1 reaches a predetermined voltage (for example, the lower limit of a recommended voltage range) and a predetermined time has elapsed, the POR circuit 8p issues a reset pulse signal RST2, and the electronic circuit 7p is reset.

[0116] In response to the release of the reset state, the POR circuit 5p issues a disable signal DS. The POR circuit 5p generates an active-level disable signal DS and supplies it to the transmission circuit 2, the inverter INV1, and the inverter INV2. The transmission circuit 2 is disabled in response to the active-level disable signal DS, and the transmission test circuits 33 and 34 receive an inverted disable signal DSB obtained by logically inverting the disable signal DS at the inverters INV1 and INV2, respectively. The transmission test circuits 33 and 34 are enabled in response to the active-level (e.g., L level) inverted disable signal DSB, and transmit test signals to the isolation elements 31 and 32 (see FIG. 1). As a result, the detection circuit 3 detects a sign of insulation failure in the isolation elements 31 and 32.

[0117] If no sign of insulation failure is detected, the receiving test circuit 35 outputs a detection signal V BR Also, a signal is input from the electronic circuit 6p to the transmission circuit 2, the signal is transmitted from the transmission circuit 2 through the insulating elements 31 and 32 to the reception circuit 4, and the signal is output from the reception circuit 4 to the electronic circuit 7p.

[0118] If a sign of insulation failure is detected, the receiving test circuit 35 outputs a detection signal V BR The active level detection signal V BR In response, signal transmission through the isolation elements 31 and 32 is not performed.

[0119] In this way, in the communication system 1p, a sign of insulation failure can be detected during the period when the reset of the internal circuit is released at power-on, and signal transmission is performed according to the detection result, so that signal transmission can be performed appropriately.

[0120] As a sixth modified example of the embodiment, a communication system 1r may generate a disable signal DS in an Under Voltage Lock Out (UVLO) circuit 5r as shown in Fig. 11. Fig. 11 is a circuit diagram showing a configuration of a communication system 1r including a UVLO circuit 5r in the sixth modified example of the embodiment.

[0121] The communication system 1r further includes a UVLO circuit 5r, an electronic circuit 6p, an electronic circuit 7p, an inverter INV1, and an inverter INV2, in comparison with the communication system 1 (see FIG. 1). The communication system 1r may be implemented in the form of a transmitting chip 1r1, an insulating layer 1r3, and a receiving chip 1r2. In this case, the transmitting chip 1r1 is equipped with a UVLO circuit 5r, an electronic circuit 6p, a transmitting circuit 2, an inverter INV1, an inverter INV2, transmitting test circuits 33 and 34, a receiving test circuit 35, a primary part (inductive element 311) of the insulating element 31, and a primary part (inductive element 321) of the insulating element 32. The receiving chip 1r2 is equipped with a UVLO circuit 8r, a secondary part (inductive element 312) of the insulating element 31, a secondary part (inductive element 322) of the insulating element 32, a receiving circuit 4, and an electronic circuit 7p. The transmitting chip 1r1 and the receiving chip 1r2 are insulated from each other via an insulating layer 1r3. The primary side portion of the insulating element 31 and the secondary side portion of the insulating element 31 are insulated from each other via an insulating layer 1r3. The primary side portion of the insulating element 32 and the secondary side portion of the insulating element 32 are insulated from each other via an insulating layer 1r3. The insulating layer 1r3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0122] The UVLO circuit 5r is a circuit that monitors the power supply voltage of the communication system 1r, and locks out the internal circuitry when the power supply voltage falls below a predetermined voltage (for example, a recommended voltage).

[0123] The UVLO circuit 5r is connected between the power supply terminal PS1 and the transmitting circuit 2, the detection circuit 3, and the electronic circuit 6p. The UVLO circuit 5r has an input node 5r1 connected to the power supply terminal PS1, an output node 5r2 connected to the electronic circuit 6p, and an output node 5r3 connected to the transmitting circuit 2 and also connected to the transmitting test circuits 33 and 34 via inverters INV1 and INV2. The electronic circuit 6p is connected to the input side of the transmitting circuit 2.

[0124] The UVLO circuit 8r is connected between the power supply terminal PS2 and the receiving circuit 4 and the electronic circuit 7p. The UVLO circuit 8r has an input node 8r1 connected to the power supply terminal PS2 and an output node 8r2 connected to the electronic circuit 7p. The electronic circuit 7p is connected to the output side of the receiving circuit 4.

[0125] In the communication system 1r, the output period of the disable signal DS is determined by a UVLO circuit 5r. The UVLO circuit 5r monitors the power supply voltage received at the input node 5r1 via the power supply terminal PS1 from the outside. The UVLO circuit 8r monitors the power supply voltage received at the input node 8r1 via the power supply terminal PS2 from the outside.

[0126] The UVLO circuit 5r issues a lockout signal UVLO1 when the power supply voltage received at the input node 5r1 becomes lower than a predetermined voltage (e.g., a recommended voltage) during operation of the communication system 1r. The UVLO circuit 5r supplies the lockout signal UVLO1 of an active level from the output node 5r2 to the internal circuits such as the electronic circuit 6p. This allows the UVLO circuit 5r to lock out the internal circuits such as the electronic circuit 6p to prevent malfunction.

[0127] The UVLO circuit 8r issues a lockout signal UVLO2 when the power supply voltage received at the input node 8r1 becomes lower than a predetermined voltage (for example, a recommended voltage) during operation of the communication system 1r. The UVLO circuit 8r supplies the lockout signal UVLO2 of an active level from the output node 8r2 to the internal circuits such as the electronic circuit 7p. This allows the UVLO circuit 8r to lock out the internal circuits such as the electronic circuit 7p to prevent malfunction.

[0128] The UVLO circuit 5r releases the lockout signal UVLO1 when the power supply voltage received at the input node 5r1 recovers to a predetermined voltage (e.g., a recommended voltage) or higher. The UVLO circuit 5r supplies the lockout signal UVLO1 at a non-active level from the output node 5r2 to the internal circuits such as the electronic circuit 6p. This allows the UVLO circuit 5r to release the lockout of the internal circuits such as the electronic circuit 6p.

[0129] The UVLO circuit 8r releases the lockout signal UVLO2 when the power supply voltage received at the input node 8r1 recovers to a predetermined voltage (e.g., a recommended voltage) or higher. The UVLO circuit 8r supplies the lockout signal UVLO2 of a non-active level from the output node 8r2 to the internal circuits such as the electronic circuit 7p. This allows the UVLO circuit 8r to release the lockout of the internal circuits such as the electronic circuit 7p.

[0130] In response to the release of the lockout, the UVLO circuit 5r issues a disable signal DS. The UVLO circuit 5r supplies the disable signal DS at an active level to the transmission circuit 2, the inverter INV1, and the inverter INV2. The transmission circuit 2 is disabled in response to the disable signal DS at an active level, and the transmission test circuits 33 and 34 receive an inverted disable signal DSB obtained by logically inverting the disable signal DS at the inverters INV1 and INV2, respectively. The transmission test circuits 33 and 34 are enabled in response to the inverted disable signal DSB at an active level (for example, L level), and transmit test signals to the isolation elements 31 and 32 (see FIG. 1). As a result, the detection circuit 3 detects a sign of insulation failure in the isolation elements 31 and 32.

[0131] As a seventh modification of the embodiment, the communication system 1s may generate a disable signal DS in an input circuit 5s as shown in Fig. 12. Fig. 12 is a circuit diagram showing a configuration of a communication system 1s including an input circuit 5s in the seventh modification of the embodiment.

[0132] The communication system 1s further includes an input circuit 5s, an electronic circuit 6p, an electronic circuit 7p, an inverter INV1, and an inverter INV2, in comparison with the communication system 1 (see FIG. 1). The communication system 1s may be implemented in the form of a transmitting chip 1s1, an insulating layer 1s3, and a receiving chip 1s2. In this case, the transmitting chip 1s1 is equipped with the input circuit 5s, the electronic circuit 6p, the transmitting circuit 2, the inverter INV1, the inverter INV2, the transmitting test circuits 33 and 34, the receiving test circuit 35, the primary part (inductive element 311) of the insulating element 31, and the primary part (inductive element 321) of the insulating element 32. The receiving chip 1s2 is equipped with the secondary part (inductive element 312) of the insulating element 31, the secondary part (inductive element 322) of the insulating element 32, the receiving circuit 4, and the electronic circuit 7p. The transmitting chip 1s1 and the receiving chip 1s2 are insulated from each other via the insulating layer 1s3. The primary side portion of the insulating element 31 and the secondary side portion of the insulating element 31 are insulated from each other via an insulating layer 1s3. The primary side portion of the insulating element 32 and the secondary side portion of the insulating element 32 are insulated from each other via an insulating layer 1s3. The insulating layer 1s3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0133] The input circuit 5s is a circuit to which a control signal EN is input. The input circuit 5s is connected between the control terminal EN and the transmitting circuit 2 and the detection circuit 3. The input circuit 5s has an input node 5s1 connected to the control terminal EN, an input node 5s4 connected to the receiving test circuit 35, and an output node 5s3 connected to the transmitting circuit 2 and to the transmitting test circuits 33 and 34 via inverters INV1 and INV2. The electronic circuit 6p is connected to the input side of the transmitting circuit 2. The electronic circuit 7p is connected to the output side of the receiving circuit 4.

[0134] In the communication system 1s, the output period of the disable signal DS is determined by the input circuit 5s. The input circuit 5s monitors a control signal EN received at an input node 5s1 from the outside via a control terminal EN. The input circuit 5s can output or release the disable signal DS depending on whether the level of the control signal EN is a non-active level or an active level.

[0135] If the level of the control signal EN is a non-active level, the input circuit 5s issues a disable signal DS. The input circuit 5s generates an active-level disable signal DS and supplies it to the transmission circuit 2, the inverter INV1, and the inverter INV2. The transmission circuit 2 is disabled in response to the active-level disable signal DS, and the transmission test circuits 33 and 34 receive an inverted disable signal DSB obtained by logically inverting the disable signal DS at the inverters INV1 and INV2, respectively. The transmission test circuits 33 and 34 are enabled in response to the active-level (e.g., L level) inverted disable signal DSB, and transmit test signals to the isolation elements 31 and 32 (see FIG. 1). As a result, the detection circuit 3 detects a sign of insulation failure in the isolation elements 31 and 32.

[0136] If no sign of insulation failure is detected, the receiving test circuit 35 outputs a detection signal V BR is not issued. The input circuit 5s waits until the level of the control signal EN becomes active. When the level of the control signal EN becomes active, the input circuit 5s disables the transmission test circuits 33, 34 and enables the transmission circuit 2 to transition to a normal operation state. This allows signal transmission through the isolation elements 31, 32. That is, a signal is input from the electronic circuit 6p to the transmission circuit 2, transmitted from the transmission circuit 2 to the reception circuit 4 through the isolation elements 31, 32, and output from the reception circuit 4 to the electronic circuit 7p.

[0137] If a sign of insulation failure is detected, the receiving test circuit 35 outputs a detection signal V BR The input circuit 5s keeps the transmission circuit 2 in a disabled state, so that no signal transmission through the isolation elements 31 and 32 takes place.

[0138] In this way, in the communication system 1s, a sign of insulation failure can be detected during an idle period when the level of the control signal EN is at a non-active level, and signal transmission is performed according to the detection result, thereby enabling appropriate signal transmission.

[0139] As an eighth modification of the embodiment, the communication system 1t may be provided with a trimming circuit 5t as shown in Fig. 13. Fig. 13 is a circuit diagram showing a configuration of the communication system 1t including the trimming circuit 5t in the eighth modification of the embodiment.

[0140] The communication system 1t is implemented as, for example, a semiconductor chip, and is configured to be able to trim the frequency of the test signal of the transmission test circuits 33, 34 in an inspection process before shipment. FIG. 13 illustrates a configuration in the case where a trimming method using a memory is performed. Compared to the communication system 1 (see FIG. 1), the communication system 1t further includes a trimming circuit 5t, an electronic circuit 6p, an electronic circuit 7p, and a plurality of pad electrodes PD1 to PD5. The communication system 1t may be implemented in the form of a transmission chip 1t1, an insulating layer 1t3, and a receiving chip 1t2. In this case, the transmission chip 1t1 is equipped with the electronic circuit 6p, the transmission circuit 2, the transmission test circuits 33, 34, the receiving test circuit 35, the primary side part of the insulating element 31 (the inductive element 311), and the primary side part of the insulating element 32 (the inductive element 321). The receiving chip 1t2 is equipped with a secondary part (inductive element 312) of the insulating element 31, a secondary part (inductive element 322) of the insulating element 32, a trimming circuit 5t, and a plurality of pad electrodes PD1 to PD5. The transmitting chip 1t1 and the receiving chip 1t2 are insulated from each other via an insulating layer 1t3. The primary part of the insulating element 31 and the secondary part of the insulating element 31 are insulated from each other via an insulating layer 1t3. The primary part of the insulating element 32 and the secondary part of the insulating element 32 are insulated from each other via an insulating layer 1t3. The insulating layer 1t3 may be any of a silicon oxide film, a silicon nitride film, and a polyimide film.

[0141] Each of the pad electrodes PD1 to PD5 is connected to a tester 100t. The impedance of the insulating elements 31 and 32 can be measured by the tester 100t. For example, one end of the inductive element 312 in the insulating element 31 is connected to the tester 100t via the pad electrode PD1, and the other end is connected to the tester 100t via the pad electrode PD2. One end of the inductive element 322 in the insulating element 32 is connected to the tester 100t via the pad electrode PD5, and the other end is connected to the tester 100t via the pad electrode PD2.

[0142] The tester 100t is connected to the pad electrodes PD1 and PD2 by, for example, bringing probes into contact with the pad electrodes PD1 and PD2.

[0143] The tester 100t outputs a test signal (typically a sine wave) and detects the response (e.g., voltage) to measure the impedance of the insulating element 31. From the measurement result, the tester 100t calculates the expected resonant frequency ω2.

[0144] Similarly, the tester 100t is connected to the pad electrodes PD5 and PD2 by, for example, bringing probes into contact with the pad electrodes PD5 and PD2.

[0145] The tester 100t outputs a test signal (typically a sine wave) and detects the response (e.g., voltage) to measure the impedance of the insulating element 32. From the measurement result, the tester 100t calculates the expected resonant frequency ω2.

[0146] The trimming circuit 5t has an input node 5a connected to the pad electrode PD3, an input node 5b connected to the pad electrode PD4, an output node 5c connected to the transmission test circuit 33, and an output node 5d connected to the transmission test circuit .

[0147] The tester 100t supplies the calculated resonant frequency ω2 for the isolation element 31 to the trimming circuit 5t via the pad electrode PD3. The trimming circuit 5t stores the resonant frequency ω2 in association with the isolation element 31. Similarly, the tester 100t supplies the calculated resonant frequency ω2 for the isolation element 32 to the trimming circuit 5t via the pad electrode PD4. The trimming circuit 5t stores the resonant frequency ω2 in association with the isolation element 32.

[0148] For example, when the test mode is entered, the transmission test circuit 33 reads out the resonant frequency ω2 from the trimming circuit 5t and outputs the test signal i TEST The frequency of the resonant frequency ω is set to ω2 (ω), and the transmission test circuit 34 reads out the resonant frequency ω2 from the trimming circuit 5t and outputs the test signal i TEST The frequency of (ω) is set to ω=ω2. This makes it possible to make the resonant frequency calculated by the tester 100t and the frequency of the test signal approximately coincident.

[0149] In this manner, the communication system 1t can set an appropriate (e.g., optimal) frequency to be used for the test signal in the trimming circuit 5t by trimming the frequency of the test signal of the transmission test circuits 33 and 34. This enables the communication system 1t to stably detect a sign of insulation failure in the isolation elements 31 and 32.

[0150] In addition, FIG. 13 illustrates a configuration in which a trimming method using a memory is performed, but the communication system 1t is not limited to the trimming method using a memory, and various trimming methods can be applied. For example, the trimming method applied to the communication system 1t may be a Zener zap trimming method, a laser trimming method, a fuse blow trimming method, or the like. The Zener zap trimming method is a trimming method in which a desired electrical characteristic corresponding to a trimming value is obtained by selectively destroying and short-circuiting a plurality of Zener diodes by applying a high voltage. The laser trimming method is a trimming method in which a desired electrical characteristic corresponding to a trimming value is obtained by selectively cutting a plurality of metals with a laser. The fuse blow trimming method is a trimming method in which a desired electrical characteristic corresponding to a trimming value is obtained by selectively activating a plurality of fuse circuits.

[0151] As a ninth modification of the embodiment, the reception test circuit 35 in the communication system 1 may be configured to perform differential comparison having an offset width (dead band), as shown in Fig. 14. Fig. 14 is a diagram showing the operation of the reception test circuit 35 in the ninth modification of the embodiment, and illustrates an example of the input / output characteristics of the reception test circuit 35.

[0152] In the ninth modification, the input of the receiving test circuit 35 is a differential voltage. The differential voltage is, for example, the input voltage v 311 and the input voltage v of the inductive element 321 321 The voltage difference Δv (=v 311 -v 321 The voltage difference Δv may be expressed as the input voltage v 311 is the input voltage v 321 If it is greater than the input voltage v 311 is the input voltage v 321 If it is smaller than the offset voltage +v, it is a negative value. T and -v T (v T >0). The receiving test circuit 35 is provided with a voltage difference Δv of +v T Above or -v TWhen the detection signal V BR The receiving test circuit 35 outputs the signal when the input differential voltage Δv is +v T Less than -v T If it is greater than the non-active level (e.g., low level V L ) detection signal V BR The receiving test circuit 35 generates and outputs the voltage difference Δv. T Above or -v T If it is below the active level (e.g. high level V H ) detection signal V BR Generate and output.

[0153] As shown in Figure 14, the difference voltage Δv TEST (ω) vs. dead zone (-v T ~+v T ) can realize stable operation of the receiving test circuit 35. Note that, although the input is a differential voltage in Fig. 14, it is to be understood that the same applies when comparing two single-phase voltages (for example, the operation of the receiving test circuit 35 shown in Fig. 5).

[0154] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0155] 1, 1i, 1j, 1k, 1n, 1p, 1r, 1s, 1t communication systems, 3, 3i, 3j, 3k, 3n detection circuits, 31, 31n, 32, 32n isolation elements, 33, 33n, 34, 34n transmission test circuits, and 35, 35n reception test circuits.

Claims

1. A first insulating element; A second insulating element; and a first transmitting test circuit connected to a primary side of the first isolation element and configured to transmit a first test signal to the first isolation element; a second transmitting test circuit connected to a primary side of the second isolation element and configured to transmit a second test signal corresponding to the first test signal to the second isolation element; a receiving test circuit that outputs a detection signal of a first level when a first difference between a voltage on a primary side of the first isolation element and a voltage on a primary side of the second isolation element or a second difference between a voltage on a secondary side of the first isolation element and a voltage on a secondary side of the second isolation element is equal to or smaller than a threshold value, and outputs the detection signal of a second level when the first difference or the second difference exceeds the threshold value; a control circuit that controls a frequency of the first test signal to a first frequency; Equipped with the first transmit test circuit transmits the first test signal having the first frequency to the first isolation element; The second transmit test circuit transmits the second test signal having the first frequency to the second isolation element. Detection circuit.

2. A first insulating element; A second insulating element; and a first transmitting test circuit connected to a secondary side of the first isolation element and configured to transmit a first test signal to the first isolation element; a second transmitting test circuit connected to a secondary side of the second isolation element and configured to transmit a second test signal corresponding to the first test signal to the second isolation element; a receiving test circuit that outputs a detection signal of a first level when a first difference between a voltage on a primary side of the first isolation element and a voltage on a primary side of the second isolation element or a second difference between a voltage on a secondary side of the first isolation element and a voltage on a secondary side of the second isolation element is equal to or smaller than a threshold value, and outputs the detection signal of a second level when the first difference or the second difference exceeds the threshold value; a control circuit that controls a frequency of the first test signal to a first frequency; Equipped with the first transmit test circuit transmits the first test signal having the first frequency to the first isolation element; The second transmit test circuit transmits the second test signal having the first frequency to the second isolation element. Detection circuit.

3. A first insulating element; A second insulating element; and a first transmitting test circuit connected to a primary side of the first isolation element and configured to transmit a first test signal to the first isolation element; a second transmitting test circuit connected to a primary side of the second isolation element and configured to transmit a second test signal corresponding to the first test signal to the second isolation element; a receiving test circuit that outputs a detection signal of a first level when a first difference between a voltage on a primary side of the first isolation element and a voltage on a primary side of the second isolation element or a second difference between a voltage on a secondary side of the first isolation element and a voltage on a secondary side of the second isolation element is equal to or smaller than a threshold value, and outputs the detection signal of a second level when the first difference or the second difference exceeds the threshold value; a storage circuit that stores a trimmed second frequency for the first test signal; Equipped with the first transmit test circuit transmits the first test signal having the second frequency to the first isolation element; The second transmit test circuit transmits the second test signal having the second frequency to the second isolation element. Detection circuit.

4. A first insulating element; A second insulating element; and a first transmitting test circuit connected to a secondary side of the first isolation element and configured to transmit a first test signal to the first isolation element; a second transmitting test circuit connected to a secondary side of the second isolation element and configured to transmit a second test signal corresponding to the first test signal to the second isolation element; a receiving test circuit that outputs a detection signal of a first level when a first difference between a voltage on a primary side of the first isolation element and a voltage on a primary side of the second isolation element or a second difference between a voltage on a secondary side of the first isolation element and a voltage on a secondary side of the second isolation element is equal to or smaller than a threshold value, and outputs the detection signal of a second level when the first difference or the second difference exceeds the threshold value; a storage circuit that stores a trimmed second frequency for the first test signal; Equipped with the first transmit test circuit transmits the first test signal having the second frequency to the first isolation element; The second transmit test circuit transmits the second test signal having the second frequency to the second isolation element. Detection circuit.

5. A detection circuit comprising a first isolation element, a second isolation element, a first transmitting test circuit connected to the primary side of the first isolation element, a second transmitting test circuit connected to the primary side of the second isolation element, and a receiving test circuit outputting a detection signal corresponding to a first difference between a voltage on the primary side of the first isolation element and a voltage on the primary side of the second isolation element, or a second difference between a voltage on the secondary side of the first isolation element and a voltage on the secondary side of the second isolation element, the detection circuit having a first input node arranged on the primary side of the first isolation element, a second input node arranged on the primary side of the second isolation element, a first output node arranged on the secondary side of the first isolation element, and a second output node arranged on the secondary side of the second isolation element; a transmission circuit connected to the first input node and the second input node of the detection circuit, a receiving circuit connected to the first output node and the second output node of the detection circuit, respectively; A communication system comprising:

6. A detection circuit comprising a first isolation element, a second isolation element, a first transmitting test circuit connected to the secondary side of the first isolation element, a second transmitting test circuit connected to the secondary side of the second isolation element, and a receiving test circuit outputting a detection signal corresponding to a first difference between the voltage on the primary side of the first isolation element and the voltage on the primary side of the second isolation element or a second difference between the voltage on the secondary side of the first isolation element and the voltage on the secondary side of the second isolation element, the detection circuit having a first input node arranged on the primary side of the first isolation element, a second input node arranged on the primary side of the second isolation element, a first output node arranged on the secondary side of the first isolation element, and a second output node arranged on the secondary side of the second isolation element; a transmission circuit connected to the first input node and the second input node of the detection circuit, a receiving circuit connected to the first output node and the second output node of the detection circuit, respectively; A communication system comprising:

7. The first transmission test circuit transmits a first test signal to the first isolation element; The second transmission test circuit transmits a second test signal corresponding to the first test signal to the second isolation element. A communication system according to claim 5 or 6.

8. The receiving test circuit outputs the detection signal at a first level when the first difference or the second difference is equal to or less than a threshold, and outputs the detection signal at a second level when the first difference or the second difference exceeds the threshold. A communication system according to claim 5 or 6.

9. The detection circuit further includes a control circuit that controls a frequency of the first test signal to a first frequency; the first transmit test circuit transmits the first test signal having the first frequency to the first isolation element; The second transmit test circuit transmits a second test signal having the first frequency to the second isolation element. A communication system according to claim 5 or 6.

10. The detection circuit further includes a memory circuit that stores the trimmed second frequency for the first test signal; the first transmit test circuit transmits the first test signal having the second frequency to the first isolation element; The second transmit test circuit transmits a second test signal having the second frequency to the second isolation element. A communication system according to claim 5 or 6.

11. the transmitting circuit is inactivated during a first time period and is operable during a second time period; The first transmission test circuit and the second transmission test circuit both operate during the first period and are inactivated during the second period. A communication system according to claim 5 or 6.

12. the reception test circuit outputs the detection signal at a first level when the first difference or the second difference is equal to or smaller than a threshold during the first period, and outputs the detection signal at a second level when the first difference or the second difference exceeds the threshold; The transmission circuit performs a signal transmission operation during the second period when the detection signal of the first level is received, and stops the signal transmission operation during the second period when the detection signal of the second level is received.

12. The communication system of claim 11.

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