Backside illuminated sensor and method for manufacturing sensor using silicon-on-insulator wafer - Patents.com

Abstract

The image sensor is fabricated by first heavily p-doping the thin upper monocrystalline silicon substrate of an SOI wafer, then forming a relatively lightly p-doped epitaxial layer on the upper surface of the upper silicon substrate, and controlling the p-doping level during these two processes to create a p-dopant concentration gradient in the upper silicon substrate. The sensing (circuit) elements and associated metal interconnects are fabricated on the epitaxial layer, and then the SOI wafer's handling substrate and oxide layer are at least partially removed to expose the underside of either the upper silicon substrate or the epitaxial layer. A pure boron layer is then formed on the exposed underside. The p-dopant concentration gradient monotonically decreases from a maximum level near the upper silicon / epitaxial layer interface to a minimum concentration level at the upper surface of the epitaxial layer.

Description

[Technical field]

[0001] This application relates to image sensors suitable for sensing radiation in the deep ultraviolet (DUV) and vacuum ultraviolet (VUV) wavelengths, and methods for making such image sensors. [Background technology]

[0002] This application claims priority from U.S. Provisional Patent Application 63 / 006,724 ("BACK-ILLUMINATED SENSOR AND A METHOD OF MANUFACTURING A SENSOR USING A SILICON ON INSULATING WAFER", filed April 8, 2020), which is incorporated herein by reference. This application is also related to U.S. Patent Application 16 / 562,396 ("BACK-ILLUMINATED SENSOR AND A METHOD OF MANUFACTURING A SENSOR", filed September 5, 2019), entitled "Back-illuminated sensor with boron layer", all to Chern et al., and U.S. Patent Nos. 9,496,425, 9,818,887, 10,121,914, and 10,446,696. These patents and applications are incorporated herein by reference.

[0003] The integrated circuit industry requires inspection tools with increasingly higher resolution to resolve smaller and smaller features of integrated circuits, photomasks, reticles, solar cells, charge-coupled devices, and the like, as well as to detect defects whose sizes are on the order of or smaller than the size of those features.

[0004] Inspection systems operating at short wavelengths, e.g., wavelengths shorter than about 250 nm, can often provide such resolution. In particular, for photomask or reticle inspection, it is desirable to inspect using wavelengths that are the same as or close to those used for lithography, i.e., near 193.4 nm for current generation lithography and near 13.5 nm for future EUV lithography. The phase shift of the inspection light induced by the pattern will be the same or very similar to that induced during lithography. For inspecting semiconductor patterned wafers, inspection systems operating over a relatively wide range of wavelengths, such as a wavelength range that includes wavelengths in the near UV, DUV, and / or VUV ranges, can be advantageous because a wide range of wavelengths can reduce sensitivity to small changes in layer thickness or pattern dimensions that can cause large changes in reflectivity at individual wavelengths.

[0005] A high signal-to-noise ratio is required to detect small defects or particles on photomasks, reticles, and semiconductor wafers. A high photon flux density is required to ensure a high signal-to-noise ratio when inspecting at high speeds, because the statistical fluctuations in the number of photons detected (Poisson noise) are the fundamental limit of the signal-to-noise ratio. In many cases, about 100,000 or more photons per pixel are required. Inspection systems are typically used 24 hours a day with only minor outages, so sensors are exposed to large doses of radiation after only a few months of operation.

[0006] The energy of photons at a vacuum wavelength of 250 nm is about 5 eV. The band gap of silicon dioxide is about 10 eV. Although it may seem that photons at such wavelengths cannot be absorbed by silicon dioxide, silicon dioxide growing on a silicon surface must have some dangling bonds at the interface with silicon, since the silicon dioxide structure cannot perfectly match that of a silicon crystal. In addition, since silicon dioxide is amorphous, dangling bonds exist within the material. In reality, the density of defects and impurities within the oxide as well as at the interface with the underlying semiconductor, which can absorb photons with DUV wavelengths, especially wavelengths shorter than about 250 nm, will not be negligible. Furthermore, under high radiation flux density, two high-energy photons may arrive near the same position within a very short time interval (nanoseconds or picoseconds), which may result in electrons being excited into the conduction band of silicon dioxide by two absorption events in rapid succession or by two-photon absorption.

[0007] A further requirement for sensors used in inspection, metrology, and related applications is high sensitivity. As explained above, a high signal-to-noise ratio is required. If the sensor does not convert a large percentage of the incident photons into a signal, a higher intensity light source is required to maintain the same inspection or measurement speed compared to an inspection or metrology system with a more efficient sensor. A higher intensity light source can be used to measure the light intensity of the equipment being inspected or measured. 、 This exposes the optics and sample to higher light intensities, potentially causing damage or degradation over time. Higher intensity light sources are also more expensive or may not be available, especially at DUV and VUV wavelengths. Silicon reflects a high percentage of the DUV and VUV light incident on it. For example, at wavelengths near 193 nm, silicon with a 2 nm oxide layer (such as a native oxide layer) on its surface reflects about 65% of the light incident on it. Growing an oxide layer of about 21 nm on the silicon surface reduces the reflectivity to nearly 40% at wavelengths near 193 nm. A detector with 40% reflectivity is significantly more efficient than a detector with 65% reflectivity, but a lower reflectivity, and therefore a higher efficiency, is desirable.

[0008] DUV and VUV wavelengths are strongly absorbed by silicon. Such wavelengths may be absorbed within about 10 nm or tens of nm of the surface of the silicon in most cases. The efficiency of a sensor operating at DUV or VUV wavelengths depends on how large a proportion of the electrons generated by the absorbed photons can be collected before the electrons recombine. Silicon dioxide can form a high-quality interface with silicon, which has a low density of defects. Most other materials, including many of those typically used for anti-reflective coatings, when deposited directly on silicon, result in a very high density of electrical defects at the surface of the silicon. A high density of electrical defects on the surface of silicon may not be a problem for sensors intended to operate at visible wavelengths, because such wavelengths can typically travel about 100 nm or more into the silicon before being absorbed, and therefore may be largely unaffected by electrical defects on the silicon surface. However, because DUV and VUV wavelengths are absorbed very close to the silicon surface, electrical defects on the surface and / or charges trapped within layers on the surface may result in a significant portion of the generated electrons being lost to recombination at or near the silicon surface, resulting in a low efficiency sensor.

[0009] U.S. Patent Nos. 9,496,425, 9,818,887 and 10,121,914, all to Chern et al., describe image sensor structures and methods of fabricating image sensors that include a boron layer deposited on at least the exposed back surface of the image sensor. Different temperature ranges for the deposition of boron are disclosed, including a range of about 400-450°C and a range of about 700-800°C. The inventors have discovered that one advantage of higher deposition temperatures of boron, such as a deposition temperature of about 600°C to about 900°C, is that at such temperatures boron diffuses into the silicon to provide a very thin, highly p-doped silicon layer on the photosensitive back surface. This p-doped silicon layer is important for ensuring high quantum efficiency for DUV and VUV radiation, as it creates an electrostatic field near the surface that accelerates electrons from the surface into the silicon layer. P-type silicon also increases the conductivity of the back side of the silicon, which is important for high speed operation of image sensors because a return path is required for ground currents induced by the switching of signals on the electrodes on the front side of the sensor.

[0010] However, processing temperatures above 450°C are too high for the aluminum and copper materials typically used in the manufacture of CMOS devices. Melting Point of MetalsBecause copper is close to 1000 nm, it cannot be used on semiconductor wafers containing conventional CMOS circuits. At high temperatures, such as temperatures greater than 450°C, these metals can expand, soften, and delaminate. Furthermore, at high temperatures, copper can easily diffuse through silicon altering the electrical properties of CMOS circuits. By thinning the wafer before metal is deposited on it, a boron layer can be deposited on the backside at temperatures between 600 and 900°C, as described in the aforementioned patents, and boron can be diffused to the front side during or after the deposition of the boron layer. Metal interconnects can then be formed on the front side. After the image sensor area of ​​the wafer is thinned to a thickness of, for example, about 25 μm or less, the thinned area can warp significantly and have peak-valley non-planarity of tens of microns or more. It is therefore necessary to use relatively wide metal interconnect lines and vias, with widths of multiple microns or more, to ensure that the lines and vias will connect despite any misalignment caused by the non-planarity. Such wide metal interconnects and vias increase the capacitance per unit area associated with those lines and vias. Furthermore, wide interconnects and vias can make it difficult or impossible to interconnect all the signals on a large area sensor with about one million or more pixels. In some cases, polysilicon jumpers may be required to connect the metal interconnects, but polysilicon has a much higher resistivity than any metal, and therefore the use of such jumpers can limit the maximum operating speed of the sensor. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] US Patent Application Publication No. 2007 / 0020893 [Patent Document 2] US Patent Application Publication No. 2016 / 0290932 Summary of the Invention [Problem to be solved by the invention]

[0012] Thus, there is a need for an image sensor that can efficiently detect high energy photons without degradation while overcoming some or all of the above drawbacks. In particular, a method for fabricating backside thin image sensors with a boron layer and boron doping on the backside while allowing for the formation of metal interconnects on relatively flat wafers (i.e., having a flatness of about 10 μm or less) would allow for the use of finer design rules (e.g., design rules that are compatible with 0.35 μm processes or greater). Such a method would allow for narrower metal lines connecting to critical features such as floating diffusions, allowing for smaller floating diffusion capacitances and higher charge-to-voltage conversion efficiencies. Finer design rules would also allow for more interconnect lines per unit area of ​​the sensor, allowing for more flexibility in connecting the circuitry on the image sensor. [Means for solving the problem]

[0013] High quantum efficiency (high QE) image sensors and methods for fabricating image sensors for DUV, VUV, EUV, X-ray and / or charged particle (such as electron) imaging on SOI wafers are described. These image sensors are capable of long-life operation under high radiation flux. These methods include process steps for forming light-sensitive active and / or passive circuit elements in a layer of semiconductor material (preferably silicon) and for forming metal interconnects between electrical elements of the sensor. These image sensors can include fine metal interconnects and vias (such as those that meet design rules of about 0.35 pm or finer) while having a backside coated with an amorphous boron layer and a highly doped p-type silicon layer directly adjacent to the boron layer. The metal interconnects can include tungsten, aluminum, copper, or other metals used in fabricating interconnects in known CMOS processes.

[0014] An exemplary method for fabricating an image sensor begins by utilizing a boron layer to highly p-dope a thin top silicon substrate of a silicon-on-insulator (SOI) wafer. An epitaxial layer is then formed on the top silicon substrate in a manner that produces a monotonically decreasing p-type dopant concentration gradient (doping profile) with a maximum concentration level of p-type dopant (e.g., boron) atoms in the top silicon substrate (i.e., near the bottom of the epitaxial layer) and a minimum concentration level of p-type dopant atoms near the top surface of the epitaxial layer. The doping of the thin top silicon substrate is performed, for example, by forming an amorphous boron layer on the top silicon substrate, performing a boron drive-in anneal at high temperature (i.e., 800°C or higher), and then removing the boron layer during or after the drive-in anneal (i.e., before forming the epitaxial layer). Producing an epitaxial layer with a desired doping gradient involves growing intrinsic or lightly p-doped epitaxial silicon on a top silicon substrate at high temperatures (i.e., at least 800°C) such that boron diffusion from the highly p-doped thin top silicon into the epitaxial silicon produces a desired p-type dopant concentration gradient in the epitaxial silicon. Circuit elements are then formed on the top (relatively low p-doped) surface of the epitaxial layer, for example, using standard CMOS fabrication processes, and metal interconnects (lines and vias) are then formed to connect these circuit elements together. The thick handling substrate and intervening insulator layer of the SOI wafer are then thinned (i.e., at least partially removed) to expose the backside (underside) of either the top silicon substrate or the epitaxial layer to increase the sensitivity of the image sensor to light incident on the active sensor backside region. In some embodiments, some or all of the top silicon substrate is removed during the thinning process to maximize the p-type doping level of the exposed backside region. In one embodiment, removal of the handling substrate, insulator / oxide, and top silicon substrate is performed using known dry etching, wet etching, and / or mechanical polishing techniques.A permanent (second) amorphous pure boron layer is then formed directly on the exposed back surface area, and one or more optional anti-reflective layers are formed on the surface of the second amorphous boron layer.

[0015] In an alternative embodiment, a thin metal coating may be deposited on the boron layer to facilitate detection of charged particles (e.g., electrons), EUV, or X-rays. Such a thin metal coating may also reduce the sensor's susceptibility to stray light, protect the sensor's surface, and facilitate in-situ cleaning of contaminants such as carbon and organic molecules from the sensor surface.

[0016] Another method of manufacturing an image sensor includes producing an epitaxial layer having the monotonically decreasing doping concentration gradient described above, and then forming circuit elements and wiring on the epitaxial layer using the process described above. An optional protective layer is then formed on / above the circuit elements, and then a second handling wafer is bonded over the circuit elements and interconnects. Then, at least a portion of the SOI wafer (i.e., the entire handling substrate, the insulator / oxide layer, and some or all of the top silicon substrate) is removed to expose a backside sensor surface formed by either the remaining top silicon substrate or the epitaxial layer material, and the exposed backside sensor surface defines a maximum boron doping concentration level of the monotonically decreasing doping concentration gradient (i.e., the boron doping concentration level monotonically decreases from the exposed backside sensor surface to the top surface of the epitaxial layer on which the circuit elements are formed). The subsequently formed pure boron layer is then deposited by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) at a temperature of 450° C. or less, followed by the formation of an optional protective layer. One or more anti-reflective coating layers are then formed by atomic layer deposition (ALD) or other processes that can be performed below 450° C. to prevent heat-related damage to the circuit elements and interconnects.

[0017] The image sensors described herein may be fabricated using CCD (charge-coupled device) or CMOS (complementary metal-oxide semiconductor) technology. The image sensor may be a two-dimensional (2D) area sensor, or a one-dimensional (ID) line sensor. [Brief description of the drawings]

[0018] [Figure 1] 1 is a cross-sectional view illustrating an exemplary image sensor manufactured in accordance with the present invention. [Diagram 2] 1 is a flow diagram illustrating an exemplary method for manufacturing an image sensor according to one embodiment. [Figure 3A] 3A-3C are cross-sectional side views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. 2. [Figure 3B] 3A-3C are cross-sectional side views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. 2. [Figure 3C] 3A-3C are cross-sectional side views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. 2. [Figure 3D] 3A-3C are cross-sectional side views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. 2. [Figure 3E] 3A-3C are cross-sectional side views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. 2. [Figure 3F] 3A-3C are cross-sectional side views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. 2. [Figure 4] 4 is a flow diagram illustrating an exemplary method for manufacturing an image sensor according to another embodiment. [Figure 5A] 5A-5C are side cross-sectional views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. [Figure 5B] 5A-5C are side cross-sectional views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. [Figure 5C]5A-5C are side cross-sectional views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. [Figure 5D] 5A-5C are side cross-sectional views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. [Figure 5E] 5A-5C are side cross-sectional views illustrating an exemplary process utilized to manufacture an image sensor according to the method of FIG. [Figure 6A] 11A-11C are cross-sectional side views illustrating an exemplary process utilized to fabricate an image sensor in accordance with another embodiment of the present invention. [Figure 6B] 11A-11C are cross-sectional side views illustrating an exemplary process utilized to fabricate an image sensor in accordance with another embodiment of the present invention. [Figure 6C] 11A-11C are cross-sectional side views illustrating an exemplary process utilized to fabricate an image sensor in accordance with another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Although the claimed subject matter is described with respect to certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features described herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is defined solely by reference to the appended claims.

[0020] The following description is presented to enable those skilled in the art to make and use the present disclosure provided in the context of a particular application and its requirements. As used herein, directional terms such as "top", "bottom", "front", "front side", "back side", "upper", "lower", "upper", "upper", "lower" and the like are intended to provide relative positions for purposes of description and are not intended to provide an absolute frame of reference. Various modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Thus, the present disclosure is not intended to be limited to the embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0021] 1 is a cross-sectional side view of a portion of an image sensor 100 configured to sense deep ultraviolet (DUV), vacuum ultraviolet (VUV), extreme ultraviolet (EUV) radiation, or charged particles, in accordance with an exemplary embodiment of the invention. The image sensor 100 generally includes a silicon substrate 103, an epitaxial layer 104 disposed on a top surface 103U of the silicon substrate 103, at least one circuit element 110 and associated wiring 120 disposed on the top surface 104U of the epitaxial layer 104, and a pure boron layer 106 disposed on a bottom surface 103L of the silicon substrate 103. An optional anti-reflective coating 103 is disposed on a bottom (back or outward facing) surface 106L of the pure boron layer 106.

[0022] The silicon substrate 103 is a relatively heavily p-doped amorphous silicon layer having an upper surface 103U that forms a silicon-substrate / epitaxial layer interface with the lower surface 104L of the epitaxial layer 104, and a lower surface 103L of the silicon substrate 103 that forms a silicon / boron interface with the upper surface 106U of the pure boron layer 106. In one embodiment, the thickness T1 of the silicon substrate 103 is in the range of 5 nm to 100 nm.

[0023] Epitaxial layer 104 is a layer of homoepitaxially grown single crystal silicon otherwise formed on upper surface 103U using fabrication techniques described below. In one embodiment, epitaxial layer 104 has a thickness T2 in the range of 10 μm to 40 μm.

[0024] The circuit elements 110 and interconnects 120 are formed on (i.e., in and / or on) the upper surface 104U of the epitaxial layer 104 using known semiconductor fabrication techniques and include sensor devices (e.g., light-sensing devices such as photodiodes) and associated control transistors. As used herein, the phrase "circuit elements" refers to photosensitive devices such as charge-coupled devices and photodiodes, as well as other semiconductor devices such as transistors, diodes, resistors and capacitors, and the term "interconnects" refers to electrical interconnects (often called metal lines and vias) that pass signals between semiconductor devices. The circuit elements referred to herein are formed using standard semiconductor fabrication processes, including, but not limited to, photolithography, deposition, etching, diffusion, ion implantation, and annealing. In the exemplary embodiment shown in FIG. 1, circuit element 110 includes spaced apart n-doped diffusion regions 111-11, 111-12 and 111-13 extending from top surface 104U into corresponding portions of epitaxial layer 104, and polycrystalline silicon (polysilicon) gate structures 113-21 and 113-22, respectively, separated from top surface 104U by an intervening gate oxide layer.

[0025] Interconnect 120 includes a first metal line 121 formed in / on a first dielectric region 122, a second metal line 123 formed in a second dielectric layer 124, a first metal via 125, and a second metal via 127, all formed on circuit element 110 and operatively electrically connected to associated regions of circuit element 110 using known techniques. 121 10 includes one or more dielectric layers deposited on the circuit element 110. 122 A first metal via formed in or on the 125is formed by forming a via in a dielectric layer using known via formation techniques. 122 The second metal line 123 extends through the first metal line 121 1, the first metal line 121 and the second metal line 123 are formed in one or more second dielectric layers 124 disposed over the first metal line 121 and the second metal line 123, and the second metal vias 127 extend through one or both of the dielectric layers 112 and 122. In one embodiment, a protective layer (not shown in FIG. 1) is formed between the first metal line 121 and the second metal line 123, and all the second metal vias 127 include at least one of tungsten, aluminum, and copper and extend through the protective layer. The exemplary diffusion regions and gate structures forming the circuit element 110 shown in FIG. 1, along with the exemplary metal interconnects 120, are arbitrarily configured for illustrative purposes and are not intended to represent a functional sensor device or to limit the scope of the appended claims.

[0026] The pure boron layer 106 and optional anti-reflective coating 103 are formed using techniques described below during backside processing performed after formation of the circuit elements 110 and interconnects 120. The pure boron layer 106 includes a boron concentration of 80% or more, with interdiffused silicon and oxygen atoms primarily making up the remaining 20% ​​or less. In one embodiment, the pure boron layer 106 has a thickness T3 in the range of 2 nm to 20 nm. In one particular embodiment, the thickness T3 of the pure boron layer 106 is in the range of 3 nm to 10 nm, and an optional protective layer (e.g., a thin metal layer (not shown)) and one or more anti-reflective coating (e.g., silicon dioxide) layers 108 are deposited on the lower (outward-facing) surface 106L of the pure boron layer 106. Further structure and details regarding image sensors manufactured in accordance with the present invention are provided in the description of an exemplary manufacturing method below.

[0027] Referring to the right side of FIG. 1, in accordance with one aspect of the present invention, the silicon substrate 103 and epitaxial layer 104 are processed using the methods described below to provide a maximum concentration level np-max A p-type (e.g., boron) dopant concentration gradient d np And the maximum density level n p-max to the minimum doping concentration level n p-min which occurs at the top surface 104U of the epitaxial layer 104. In one embodiment, the maximum concentration level n p-max is about 10 18 cm -3 (i.e. 10 18 Boron atoms / cubic centimeter) ~ 10 21 cm -3 with a minimum doping concentration level n p-min is about 10 13 cm -3 ~10 14 cm -3 In one embodiment, the dopant concentration gradient d created in the silicon substrate 103 is in the range of np The portion is substantially flat (i.e., the intermediate dopant level n occurs at the silicon substrate / epitaxial layer interface defined by the lower surface 104L and the upper surface 103U). p_int is the maximum concentration level n p-max (so that it is substantially equal to FIG. 2 illustrates an exemplary method 200 for fabricating an image sensor using a silicon-on-insulator (SOI) wafer, and FIGS. 3A-3F illustrate an exemplary SOI wafer at various process stages during the execution of method 200. Referring to FIG. 3A, at the start of the fabrication process, SOI wafer 300 includes a relatively thin top (front) silicon substrate 303 having an exposed top (first) surface 303U and an opposing bottom (second) surface 303L attached to a relatively thicker handling substrate 301 by an intervening insulator (oxide) layer 302. SOI wafer 300 is fabricated or procured prior to the start of the fabrication process using a handling wafer 301 and oxide layer 302 having a standard composition and thickness. In a preferred embodiment, SOI wafer 300 is characterized in that top silicon substrate 303 has a thickness in the range of 5-100 nm and is made of either intrinsic or lightly p-type doped monocrystalline silicon.

[0028] Referring to block 201 (FIG. 2), a boron layer is formed by introducing a high boron doping concentration level (i.e., 10 18 cm -3 3A and 3B, the use of boron layer 310 to create a desired high boron doping concentration level in the top silicon substrate of SOI wafer 300 involves forming a first boron layer 310 (as shown and described with reference to FIG. 3A) and then processing SOI wafer 300 (as shown and described with reference to FIG. 3B) to perform both boron drive-in and boron removal, either sequentially or simultaneously.

[0029] 3A, boron layer 310 is formed on top surface 303U and comprises pure amorphous boron (as defined herein) having a thickness T4 in the range of 2 nm to 10 nm. In a preferred embodiment, boron layer 310 is formed using a chemical vapor deposition (CVD) process while SOI wafer 300 is placed in a CVD chamber and heated to an elevated temperature in the range of 600° C. to 800° C. In other embodiments, other processes may be utilized to produce boron layer 310 (e.g., sputtering or molecular beam epitaxy (MBE)), provided that the resulting boron deposit is pure and clean.

[0030] FIG. 3B shows the SOI wafer 300 during or after processing used to generate the desired high boron doping concentration level and to completely remove the boron layer 310 from the top surface 303U. Note that the top silicon substrate is identified in FIG. 3B using reference numeral 303A, with the suffix "A" utilized to distinguish the highly p-doped silicon resulting from the boron diffusion process from the initially lightly doped top silicon substrate 303 of FIG. 3A. In a preferred embodiment, the boron diffusion is performed in situ (e.g., using the same CVD chamber utilized to form the boron layer 310) using a CVD boron drive-in anneal process performed at a temperature in the range of 800°C-900°C. In other embodiments, the boron can be driven in at high temperatures using any clean chamber in H2 or H2 ambient. In a preferred embodiment, boron removal is also performed in situ immediately after boron deposition (i.e., simultaneously with boron drive-in) in a hydrogen environment at a temperature in the range of 800°C-900°C, whereby boron diffuses through the top surface 303U into the upper silicon substrate 303A, while the exposed portions of the boron layer 310 react with hydrogen and leave the surface of the boron layer. Under these conditions, a typical removal rate of the boron layer 310 is 3 nm-5 nm in a period of 30-60 minutes (i.e., thinner boron layers require less than 30 minutes, thicker layers require more than 1 hour). After the boron layer 310 has completely disappeared, the upper silicon substrate 303A is left highly doped (e.g., 10 18 ~10 21 cm -3 ) The dopant profile is relatively uniform with boron concentration levels ranging from 0.01 to 0.01. do. An advantage of performing both the formation and processing (i.e., drive-in and removal) of the boron layer in situ is that epitaxial growth (described below with reference to FIG. 3C) can occur immediately after completion of the boron layer removal (i.e., no additional cleaning process is required). In an alternative embodiment, an SOI wafer 300is removed from the deposition / diffusion chamber, the boron layer 310 is removed using a nitric acid dip (or other oxidizing dip), and then the oxide is removed from the upper surface 303U. Washing After this, epitaxial growth is carried out.

[0031] Referring to block 202 (FIG. 2), the epitaxial silicon layer is then doped with a monotonically decreasing boron concentration gradient (e.g., gradient d np is formed on / above the upper silicon substrate in a manner that provides a doping gradient (e.g., gradient d 1 as shown and described above with reference to FIG. 1). In one embodiment, intrinsic or lightly p-doped epitaxial silicon is grown on the upper surface of the heavily doped upper silicon substrate under conditions that enhance boron diffusion from the upper silicon substrate into the epitaxial layer material at a rate that produces a desired monotonically decreasing boron concentration gradient. FIG. 3C shows that an epitaxial layer 304 is formed on / above the upper surface 303U during which secondary boron diffusion occurs to provide a desired doping gradient (e.g., gradient d 1 as described with reference to FIG. 1). npFIG. 3B shows the SOI wafer after producing a high p-type doping layer (where p is the doped upper silicon substrate). Note that the subscript "B" is used to indicate the difference between the upper silicon substrate 303B after secondary boron diffusion and the heavily p-doped upper silicon substrate 303A (FIG. 3B). In one preferred embodiment, the epitaxial layer 304 is grown in situ immediately after removing the boron layer by decomposing at least one of silane or chlorosilane gases (e.g., SiH4, SiCl4 / , SiHCl3, SiH2Cl2 or SiH3Cl) with hydrogen at a temperature ranging from 800°C to 1250°C in a CVD process. Diborane can be added to the gas mixture for low p-type doping in the epitaxial layer during the CVD process. In some embodiments, silicon epitaxy can be performed using molecular beam epitaxy (MBE). In some embodiments, a drive-in anneal at a temperature greater than 800° C. may be performed after epitaxial silicon growth to migrate (diffuse) p-type dopant (e.g., boron) atoms from the heavily p-doped upper silicon substrate into the epitaxial layer 304, producing a desired monotonically decreasing doping concentration gradient from the upper silicon substrate 303B to the epitaxial layer 304.

[0032] Then, referring to block 203 (FIG. 2) and FIG. 3D, the front side circuit structure (elements) 110 and associated interconnects 120 are fabricated on / above the epitaxial layer 304 using standard semiconductor fabrication processes such as lithography, deposition, etching, ion implantation, and annealing. The purpose and additional details regarding these elements and interconnects are provided above with reference to FIG. 1, and so the details are omitted here for brevity. Charge-coupled device (CCD) and / or CMOS sensor elements and devices may also be created during the fabrication process of block 203. The front side elements and devices are created in the epitaxial layer 304 on the front side of the SOI wafer, and are therefore referred to as front side circuit elements. During front side processing, the formation of poly-Si interconnects and metal interconnects may also be performed along with other high temperature processes. Because the interconnects 120 are formed on the wafer before the back side thinning process (described below), these interconnects may be formed using normal sub-micron CMOS processing techniques and may include multiple layers of high density metal interconnects. The wiring may be made of Al, Cu, or other metals.

[0033] Referring to block 204 (FIG. 2), an optional protective layer is formed over the circuitry to protect the circuitry during subsequent processing (described below). 320 is shown formed over interconnect 120. In some embodiments, protective layer 320 may include a silicon nitride layer deposited using plasma enhanced chemical vapor deposition (PECVD), among many other materials.

[0034] Next, referring to block 205 (FIG. 2) and FIG. 3E, a backside thinning process is performed to remove (thin) at least a portion of the handling silicon substrate and at least a portion of the oxide layer to expose the bottom surface 303L of the top silicon substrate 303B in the photoactive area of ​​the image sensor. In the depicted embodiment, this removal (thinning) process is performed by grinding and / or etching handling and oxide materials to expose a portion of the bottom surface 303L representing the backside sensor surface (i.e., the photosensitive area of ​​the backside illuminated image sensor) while retaining the remaining handling wafer portion 301A and the remaining oxide layer portion 302A around the exposed bottom surface 303L of the top silicon substrate 303B. The etching can be performed by a wet etching method using an alkaline solution such as KOH or TMAH. The silicon substrate-oxide interface between the handling substrate and the oxide layer acts as a natural etch stop for the wet etch. The oxide layer can be removed using hydrofluoric acid and / or a buffered oxide etch. The top silicon-oxide interface between the top silicon substrate and the oxide layer acts as a natural etch stop for the oxide etch. Alternatively, the silicon and oxide layers can be removed using dry etching techniques such as reactive ion etching (RIE) and / or inductively coupled plasma reactive ion etching (ICPRIE) with etching gases such as SF6, O2, and C4F3, among others. As described below with reference to Figures 6A-6C, some or all of the top silicon substrate may be removed during a thinning process, whereby the backside sensor surface is formed by the epitaxial layer 304.

[0035] Then, referring to block 206 (FIG. 2) and FIG. 3F, a pure boron layer 306 and an optional anti-reflective layer (not shown) are deposited on the exposed lower surface 303L of the top silicon substrate 303B (or, alternatively, the exposed lower surface of the epitaxial layer 304 from which the top silicon substrate 303B has been removed). In a preferred embodiment, the lower surface 303L is cleaned and prepared prior to performing the boron deposition. In one embodiment, this cleaning can be performed using a standard RCA1 and 2 cleaning process with a dilute HF or buffered oxide etch to remove surface oxides after the RCA1 and 2 cleaning. In a preferred embodiment, the high purity boron deposition is performed using a combination of diborane and hydrogen at low temperatures (i.e., temperatures below 450°C, e.g., in the range of 300°C to 450°C) to avoid any damage to the front metal interconnects in the CVD process. The thickness of the boron layer 306 is determined based on the target wavelength range of operation of the completed image sensor and the minimum thickness required to avoid pinholes. Typical thicknesses can range from 2 to 20 nm. The time the wafer is kept at high temperature must be kept to a minimum to avoid damage to the front metal interconnects.

[0036] As shown in block 208 (bottom of FIG. 2), the completed image sensor is then packaged in some embodiments. Packaging may include flip-chip bonding or wire bonding of the chip to a substrate. The package may include a window transparent to the wavelengths of interest or may include a flange or seal for interfacing to a vacuum seal. In electron-bombarded image sensor embodiments, the package may include a photocathode as well as other components such as a sealed vacuum tube.

[0037] FIG 4 illustrates an alternative exemplary method 400 for manufacturing an image sensor starting with a silicon-on-insulator (SOI) wafer, and FIGS. 5A-5E illustrate the exemplary SOI wafer at various process stages during the performance of method 400. For brevity, processes and structures produced by method 400 that are substantially the same as those described above with reference to process 200 (FIGS. 2 and 3A-3C) are incorporated in FIGS. 5A-5E. For example, FIG. 5A illustrates the blocks 201 and 202 (figure 2 5A illustrates a processed layer of SOI wafer 300 after completion of processes associated with blocks 401 and 402 (FIG. 4), where top Si layer 303B is connected to Si handling substrate 301 by an intervening oxide (insulator) layer 302. An epitaxial layer 304 is formed on top silicon substrate 303B to generate the monotonically varying doping concentration gradient described above. The descriptions provided above with reference to FIGS. 3A and 3B should be understood as describing similar exemplary processes carried out in association with blocks 401 and 402 and therefore will not be repeated here. Similarly, FIG. 5A illustrates the process associated with blocks 401 and 402, ... 203 (figure 2 3) and block 403 (FIG. 4) depict circuit elements 110 and interconnects 120 formed on upper surface 304U of epitaxial layer 304.

[0038] With reference to block 404 (FIG. 4) and FIG. 5A, a front side protective material (e.g., silicon nitride) is deposited or otherwise formed using a known manufacturing process (e.g., PECVD) on the upper surface 120U above the interconnect 120 previously fabricated on the epitaxial layer 304 in the manner described above with reference to FIG. 3C.

[0039] Then, referring to block 405 (FIG. 4) and FIG. 5B, a handling wafer (second handling substrate) 501 is attached to the front side (e.g., up to the top surface 510U of the protective layer 510) using known techniques, whereby the handling wafer 501 further protects the devices and interconnects formed on the epitaxial layer 304 and serves as a base wafer for the backside processing stage described below. In an exemplary embodiment, the handling wafer 501 comprises a silicon wafer, a quartz wafer, or a wafer made of another suitable material. In some embodiments, the handling wafer 501 may be attached directly to the top surface 120U (i.e., by omitting the intervening protective layer 510). In an alternative embodiment (not shown), the protective layer 510 may be used instead of or in addition to the handling wafer 501 (i.e., the second handling substrate may be omitted). In one embodiment, additional via structures (not shown) are formed through the handling wafer 501 to facilitate front side connections to the circuit elements 110.

[0040] Then, with reference to block 406 (FIG. 4) and FIG. 5C, backside processing is performed to (at least partially) remove the handling substrate and oxide layer of the starting SOI wafer such that the backside sensor surface (e.g., the bottom surface 303L of the top silicon substrate 303B) is exposed. In one embodiment, the removal process is performed using a combination of grinding and / or etching processes as described above with reference to FIG. 3E, including cleaning and treating the bottom surface 303L in preparation for subsequent boron layer formation. In this step, some or all of the top silicon substrate 303B may be removed, for example, by etching or polishing.

[0041] Next, with reference to block 407 (FIG. 4) and FIG. 5D, a pure boron layer 506 is formed on the lower surface 303L of the upper silicon substrate 303B, for example, using the process described above with reference to FIG. 3F.

[0042] With reference to block 408 (FIG. 4) and FIG. 5E, an antireflective material is deposited or otherwise formed on the lower surface 506L of the pure boron layer 506 to produce one or more antireflective layers 508. At least one of the layers may be deposited using an ALD process or other process requiring a temperature less than 450° C. In another embodiment, a thin metal coating may be deposited on the boron layer 506 (i.e., instead of or in addition to the antireflective layer 508). A thin metal coating may be particularly useful when the sensor is used to detect charged particles (such as electrons), EUV or X-rays. Such a thin metal coating may reduce the sensor's susceptibility to stray light, protect the sensor's surface, and facilitate in-situ cleaning of contaminants such as carbon and organic molecules from the sensor surface.

[0043] As indicated in block 409 (FIG. 4), the completed image sensor shown in FIG. 5E can then be packaged using any of the packaging techniques described above.

[0044] 6A-6C illustrate exemplary conditions under which the doping profile produced in the top silicon substrate necessitates the removal of part or all of the top silicon substrate (i.e., along with the handling substrate and oxide layer of the original SOI wafer) during the backside thinning process described above with reference to FIGS. 3E and 5C. That is, with brief reference to FIG. 1, an exemplary ideal top silicon doping profile would have a maximum boron concentration level n p-max and intermediate doping concentration n p_int The gradient d extending between np The maximum boron concentration level n p-maxoccurs at the lower surface 103U, and the doping concentration monotonically decreases (or remains flat) between the lower surface 103U and the upper silicon / epitaxial layer interface. When this ideal upper silicon doping profile is produced, the backside thinning process can be terminated after the handling substate and oxide layer of the SOI wafer are removed (i.e., none of the upper silicon substrate needs to be removed). In practice, however, the maximum boron concentration level occurs somewhere between the upper and lower surfaces of the upper silicon substrate, which requires removal of at least some of the upper silicon substrate, as described below with reference to Figures 6B and 6C.

[0045] 6A shows a partially completed sensor 600A formed on an SOI wafer having a top silicon substrate 603 attached to a handling substrate 601 by an intervening insulator (oxide) layer 602 after a boron layer (not shown) has been applied to a high boron doping concentration level in the top silicon substrate 603. Then, after an epitaxial layer 604 is formed on the top silicon substrate 603, boron diffusion from the top silicon substrate 603 causes the epitaxial layer 604 to diffuse away from the original maximum boron concentration level n p-max10 6. A minimum boron doping concentration level n p-min1 The boron doping concentration gradient d decreases monotonically up to npi However, the maximum boron concentration level n p-max10 occurs at a level located between the upper surface 603U of the upper silicon substrate 603 and the original lower surface 603L0, which corresponds to a boron doping concentration gradient d npi Note that this means that θ does not monotonically decrease between the original lower surface 603L0 of the upper silicon substrate 603 and the upper surface 604U of the epitaxial layer 604, as may be required for optimal sensor performance.

[0046] Specifically, a first intermediate boron concentration level n p-int11 and the second boron concentration n occurring on the original lower surface 603L0p-int12 is the maximum boron concentration level n p-max10 For example, downward boron diffusion from the upper silicon substrate 603 into the silicon oxide film 602 can cause a “dip” (i.e., a maximum boron concentration level n p-max10 and the second boron concentration level n p-int12 A slight decrease in the concentration gradient level between 0 and 1 occurs, and the location on the y-axis where this dip occurs depends on, for example, the peak boron concentration level and the temperature during epitaxial silicon growth.

[0047] Referring to FIG. 6B, the doping concentration gradient d np1 In order to "fix" the boron concentration level n p-max10 and the original lower surface 603L0 (i.e., along the entirety of the handle substrate 601 and the oxide layer 602), thereby removing the maximum boron concentration level n p-max10 A backside process needs to be performed so that the bottom surface 603L1 of the upper silicon layer 603 coincides with the modified bottom surface 603L1. That is, removing the bottom portion of the upper silicon layer 603 is the process to remove the maximum boron concentration level n p-max10 is generated at the back sensor surface (i.e., the modified lower surface 603L1) and decreases monotonically in the Y-axis direction toward the upper surface 604U. np1 As described above, backside processing immediately follows with deposition of boron on the modified lower surface 603L1 and additional processing as described above with reference to blocks 206-208 of FIG. 2 and blocks 407-409 of FIG.

[0048] FIG. 6C shows the doping concentration gradient d npi 6 shows an alternative approach to fixation, where the backside processing is performed such that the thinning process includes the removal of the entire top silicon layer 603 (i.e., along the entire handling substrate 601 and oxide layer 602), thereby defining a new backside sensor surface by exposing the lower surface 604L of the epitaxial layer 604. Thus, the doping concentration gradient d npi is the boron concentration level n p-int11and a new maximum boron concentration level n that decreases monotonically in the Y-axis direction from the new back sensor surface (i.e., bottom surface 604L) to the top surface 604U. p-max11 Once the top silicon layer 603 has been completely removed, boron is deposited on the exposed bottom surface 604L and additional processing is performed as described above with reference to blocks 206-208 of FIG. 2 and blocks 407-409 of FIG. 4.

[0049] The above examples are not meant to limit the scope of the invention disclosed herein. They are meant merely to be illustrative of how the top silicon substrate of an SOI wafer can be processed to contain both the desired p-type dopant concentration gradient and then coated with a boron layer on its photosensitive surface. Because the top silicon substrate contains a p-type dopant concentration gradient with its maximum value adjacent to boron, the image sensor has high efficiency even for short wavelength light or low energy charged particles that penetrate only a few nm or tens of nm into the top silicon and epitaxial layer.

[0050] The various embodiments of the structure and method of the present invention described above are merely illustrative of the principles of the present invention and are not intended to limit the scope of the invention to the specific embodiments described. For example, additional steps may be added to the flow charts shown in Figures 2 and 4, or some of the steps shown may be performed in a different order than shown. Therefore, the present invention is limited only by the following claims and equivalents thereof.

Claims

1. 1. A method for fabricating an image sensor on a silicon-on-insulator (SOI) wafer including a top silicon substrate having an exposed first surface and an opposing second surface attached to a handling substrate by an intervening insulator layer, comprising: utilizing a first boron layer to create a first boron doping concentration level in the upper silicon substrate; forming an epitaxial layer on a first surface of the upper silicon substrate; forming circuit elements on a first surface of the epitaxial layer; removing the handle substrate and the intervening insulator layer so as to expose a second surface of the upper silicon substrate; forming a pure boron layer on the exposed second surface of the upper silicon substrate; having the utilizing of the boron layer and creating the epitaxial layer are performed such that boron diffusion from the upper silicon substrate into the epitaxial layer creates a monotonically decreasing boron doping concentration gradient from a maximum boron concentration level disposed within the upper silicon substrate to a minimum boron doping concentration level adjacent a first surface of the epitaxial layer.

2. Utilizing an amorphous boron layer to generate the first boron doping concentration level includes: forming a first boron layer on a first surface of the upper silicon substrate; processing the SOI wafer such that boron diffusion from the first boron layer produces an initial boron doping concentration level in the upper silicon substrate and the first boron layer is completely removed from the first surface of the upper silicon substrate; 2. The method of claim 1, comprising:

3. 3. The method of claim 2, wherein forming the first boron layer comprises depositing boron at a temperature in the range of 600° C. to 800° C. using a CVD process.

4. 3. The method of claim 2, wherein the process for producing the initial boron doping concentration level includes performing a drive-in anneal at a temperature in the range of 800°C to 900°C.

5. 3. The method of claim 2, wherein the process for removing the first boron layer comprises maintaining the SOI wafer in a hydrogen atmosphere at a temperature in the range of 800°C to 900°C.

6. 6. The method of claim 5, wherein said processing includes simultaneously creating said initial boron doping concentration level and removing said first boron layer.

7. 5. The method of claim 4, wherein each of forming the first boron layer, performing the drive-in anneal, removing the first boron layer, and creating the epitaxial layer occurs while the SOI wafer is maintained in a CVD chamber.

8. 10. The method of claim 1 further comprising depositing an anti-reflective layer on a surface of the pure boron layer.

9. 10. The method of claim 1, further comprising forming a protective layer on an epitaxial layer above the circuit elements before removing the handle substrate and the intervening insulator layer.

10. 10. The method of claim 1, further comprising the step of attaching a second handle substrate to an epitaxial layer above the circuit elements prior to removing the handle substrate and the intervening insulator layer.

11. 10. The method of claim 1, further comprising removing the handle substrate and the intervening insulator layer comprising removing a portion of the top silicon substrate.

12. 1. A method for fabricating an image sensor on a silicon-on-insulator (SOI) wafer including a top silicon substrate having an exposed first surface and an opposing second surface attached to a handling substrate by an intervening insulator layer, comprising: utilizing a first boron layer to create a first boron doping concentration level in the upper silicon substrate; creating an epitaxial layer on the first surface of the upper silicon substrate such that boron diffusion from the upper silicon substrate creates a monotonically decreasing boron doping concentration gradient from a maximum boron concentration level disposed adjacent the first surface of the upper silicon substrate to a minimum boron doping concentration level disposed adjacent the second surface; forming circuit elements on a second surface of the epitaxial layer; removing the handling substrate, the intervening insulator layer, and the top silicon substrate so as to expose a third surface of the epitaxial layer; forming a pure boron layer on the exposed third surface of the epitaxial layer; The method according to claim 1, further comprising:

13. Utilizing an amorphous boron layer to generate the first boron doping concentration level includes: forming a first boron layer on a first surface of the upper silicon substrate; processing the SOI wafer such that boron diffusion from the first boron layer produces an initial boron doping concentration level in the upper silicon substrate and the first boron layer is completely removed from a first surface of the upper silicon substrate; 13. The method of claim 12, comprising:

14. 14. The method of claim 13, wherein forming the first boron layer comprises depositing boron at a temperature in the range of 600° C. to 800° C. using a CVD process.

15. 14. The method of claim 13, wherein the process to generate the initial boron doping concentration level includes performing a drive-in anneal at a temperature in the range of 800°C to 900°C.

16. 14. The method of claim 13, wherein the process for removing the first boron layer comprises maintaining the SOI wafer in a hydrogen atmosphere at a temperature in the range of 800°C to 900°C.

17. 14. The method of claim 13, wherein said processing includes simultaneously creating said initial boron doping concentration level and removing said first boron layer.

18. 16. The method of claim 15, wherein each of forming the first boron layer, performing the drive-in anneal, removing the first boron layer, and creating the epitaxial layer occurs while the SOI wafer is maintained in a CVD chamber.

19. 13. The method of claim 12, further comprising depositing one of an anti-reflective layer on a surface of the pure boron layer.

20. 1. An image sensor for sensing at least one of deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation, and charged particles, comprising: a single crystal silicon substrate having a first surface and an opposing second surface; an epitaxial layer having a third surface forming an interface with the first surface of the single crystal silicon substrate, the epitaxial layer having a fourth surface disposed opposite the third surface; circuit elements and metal wiring formed on a fourth surface of the epitaxial layer; a pure boron layer formed on a second surface of the single crystal silicon substrate, the single crystal silicon substrate and the epitaxial layer including a boron concentration gradient configured such that a concentration of boron atoms monotonically decreases from a highest boron concentration level occurring at the second surface of the single crystal silicon substrate to a lowest boron concentration level at a fourth surface of the epitaxial layer; An image sensor having

21. 21. The image sensor of claim 20, wherein a thickness of the monocrystalline silicon substrate measured between the first surface and the second surface is in the range of 5 nm to 100 nm, a thickness of the epitaxial layer measured between the third surface and the fourth surface is in the range of 10 μm to 40 μm, and the pure boron layer has a thickness in the range of 2 nm to 20 nm.

22. 21. The image sensor of claim 20, further comprising a handle wafer attached to the epitaxial layer over the circuit elements.

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