Imaging device and electronic device

Abstract

An imaging device according to one embodiment of the present invention is provided with: a first semiconductor substrate which has a first surface and a second surface and which also has a sensor pixel that conduct photoelectric conversion; a second semiconductor substrate which has a third surface and a fourth surface, which also has a readout circuit for outputting a pixel signal based on an electric charge outputted from the sensor pixel, and which is stacked on the first semiconductor substrate so as to have the fourth surface face the first surface; and a wiring layer which is provided between the first semiconductor substrate and the second semiconductor substrate, and which has a first wiring and a second wiring that are electrically connected to each other with one of the first wiring and the second wiring being in an electrically floated state while the other being electrically connected to a transistor provided to the first or second semiconductor substrate.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device having a three-dimensional structure and an electronic device equipped with the imaging device. [Background technology]

[0002] The miniaturization of the area per pixel in a two-dimensional imaging device has been realized by introducing a microprocess and improving the mounting density. In recent years, imaging devices with a three-dimensional structure have been developed to further miniaturize imaging devices and increase the density of pixels. In an imaging device with a three-dimensional structure, for example, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by each sensor pixel are stacked on top of each other (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-22561 A Summary of the Invention

[0004] Incidentally, in an imaging device with a three-dimensional structure, it is desired to expand the dynamic range.

[0005] It is desirable to provide imaging devices and electronic devices that are capable of increasing the dynamic range.

[0006] An imaging device according to an embodiment of the present disclosure has a first surface and a second surface, A sensor pixel that performs photoelectric conversion includes a light receiving element and a transfer transistor electrically connected to the light receiving element. a second semiconductor substrate having a third surface and a fourth surface and stacked on the first semiconductor substrate with the first surface and the third surface facing each other; and a first wiring and a second wiring provided between the first semiconductor substrate and the second semiconductor substrate and electrically connected to each other. do A wiring layer is provided. It is what I got , One of the first wiring and the second wiring is in an electrically floating state and is formed so as to surround the transfer transistor, and the other is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate. .

[0007] An electronic device according to an embodiment of the present disclosure includes the imaging device according to the embodiment of the present disclosure.

[0008] In an imaging device and an electronic device according to an embodiment of the present disclosure, in a wiring layer formed on the opposing surfaces of a first semiconductor substrate having a sensor pixel and a second semiconductor substrate having a readout circuit, a first wiring and a second wiring are provided, one of which is electrically floating and the other of which is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate, and which are also electrically connected to each other, thereby increasing the wiring capacitance. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic vertical cross-sectional view illustrating a configuration of an imaging device according to a first embodiment of the present disclosure. [Diagram 2] 2 is a diagram illustrating an example of an equivalent circuit of the imaging device illustrated in FIG. [Diagram 3] 1. FIG. 4 is a diagram illustrating another example of the equivalent circuit of the imaging device illustrated in FIG. [Figure 4] 2 is a schematic diagram showing an example of a layout of gate wiring and a lower wiring layer in the first substrate shown in FIG. 1. [Diagram 5] 2 is a schematic diagram showing an example of a wiring layout of a lower wiring layer and an upper wiring layer in the first substrate shown in FIG. 1. [Figure 6] 2 is a schematic diagram showing an example of a wiring layout of an upper wiring layer and pad electrodes in the first substrate shown in FIG. 1. [Figure 7] 2 is a schematic diagram showing an example of a layout of gate wiring and a lower wiring layer in the second substrate shown in FIG. 1. [Figure 8] 2 is a schematic diagram illustrating an example of a wiring layout of a lower wiring layer and a first intermediate wiring layer in the second substrate illustrated in FIG. 1. [Figure 9]2 is a schematic diagram illustrating an example of a wiring layout of a first intermediate wiring layer and a second intermediate wiring layer in the second substrate illustrated in FIG. 1. [Figure 10] 2 is a schematic diagram illustrating an example of a wiring layout of a second intermediate wiring layer and an upper wiring layer in the second substrate illustrated in FIG. 1. [Figure 11] 2 is a schematic diagram showing an example of a wiring layout of an upper wiring layer and pad electrodes in the second substrate shown in FIG. 1. [Figure 12] FIG. 2 is a diagram illustrating an example of functional blocks of a logic circuit. [Figure 13] 10 is a schematic diagram illustrating an example of a wiring layout of an imaging device according to Modification 1 of the present disclosure. FIG. [Figure 14] 11 is a schematic vertical cross-sectional view illustrating a configuration of an imaging device according to a second embodiment of the present disclosure. FIG. [Figure 15] 15 is a diagram illustrating an example of an exploded perspective configuration of the imaging device illustrated in FIG. 14. [Figure 16] 16 is a diagram illustrating an example of a functional block of the logic circuit illustrated in FIG. 15. [Figure 17] 11 is a schematic vertical cross-sectional view illustrating a configuration of an imaging device according to a second modification of the present disclosure. FIG. [Figure 18] FIG. 2 is a diagram illustrating an example of a schematic configuration of an imaging system including the imaging devices according to the first and second embodiments and the first and second modifications. [Figure 19] 19 is a diagram illustrating an example of an imaging procedure in the imaging system of FIG. 18. [Figure 20] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 21] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. [Figure 22] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Diagram 23] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspect. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing. The order of description is as follows. 1. First embodiment (example of an imaging device in which additional capacitance wiring is provided on a first substrate and a second substrate) 1-1. Overview of the imaging device 1-2. Specific configuration of the imaging device 1-3. Actions and Effects 2. Variation 1 3. Second embodiment (example of imaging device with three stacked substrates) 4. Variation 2 5. Application Examples 6. Application Examples

[0011] <1. First embodiment> (1-1. Schematic configuration of the imaging device) FIG. 1 is a schematic diagram showing an example of a vertical cross-sectional configuration of an imaging device (imaging device 1) according to a first embodiment of the present disclosure. FIG. 2 is a diagram showing an example of an equivalent circuit of the imaging device 1 shown in FIG. 1, and FIG. 3 is a diagram showing another example of an equivalent circuit of the imaging device 1 shown in FIG. 1. FIGS. 4 to 6 are diagrams showing an example of a wiring layout on the first substrate 100 side of the imaging device 1 shown in FIG. 1. FIGS. 7 to 11 are diagrams showing an example of a wiring layout on the second substrate 200 side of the imaging device 1 shown in FIG. 1. Note that FIG. 1 shows a cross section of the imaging device 1 taken along line I-I' shown in FIGS. 4 to 11. The imaging device 1 includes two substrates (the first substrate 100 and the second substrate 200). The imaging device 1 is an imaging device having a three-dimensional structure in which the first substrate 100 and the second substrate 200 are stacked.

[0012] The first substrate 100 has a semiconductor substrate 10 and a wiring layer 30. The semiconductor substrate 10 has a first surface 10A and a second surface 10B facing each other, and the wiring layer 30 is provided on the first surface 10A of the semiconductor substrate 10. The second substrate 200 has a semiconductor substrate 20 and a wiring layer 40. The semiconductor substrate 20 has a first surface 20A and a second surface 20B facing each other, and the wiring layer 40 is provided on the first surface 20A of the semiconductor substrate 10. In the imaging device 1, the first substrate 100 and the second substrate 200 are stacked with the wiring layer 30 provided on the first surface 10A of the semiconductor substrate 10 and the wiring layer 40 provided on the first surface 20A of the semiconductor substrate 20 between them. The semiconductor substrate 10 corresponds to a specific example of a "first semiconductor substrate" of the present disclosure, the first surface 10A corresponds to a specific example of a "first surface" of the present disclosure, and the second surface 10B corresponds to a specific example of a "second surface" of the present disclosure. The semiconductor substrate 20 corresponds to a specific example of a "second semiconductor substrate" of the present disclosure, the first surface 20A corresponds to a specific example of a "third surface" of the present disclosure, and the second surface 20B corresponds to a specific example of a "fourth surface" of the present disclosure. The wiring layer 30 corresponds to a specific example of a "first wiring layer" of the present disclosure, and the wiring layer 40 corresponds to a specific example of a "second wiring layer" of the present disclosure.

[0013] The first substrate 100 has a plurality of sensor pixels 11 that perform photoelectric conversion on a semiconductor substrate 10. Specifically, the first substrate 100 is provided with a transfer transistor TR along with a photodiode PD (light receiving element 12), a floating diffusion FD, and a VSS contact region 13. The second substrate 200 has a readout circuit 21 on a semiconductor substrate 20 that outputs a pixel signal based on the charge output from the sensor pixel 11. The readout circuit 21 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a conversion efficiency switching transistor FDG.

[0014] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD.

[0015] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the power supply line VDD.

[0016] The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 21 .

[0017] The amplification transistor AMP generates a pixel signal whose voltage corresponds to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal whose voltage corresponds to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD, and outputs a voltage corresponding to the potential to a logic circuit 25 (described later) via a vertical signal line VSL.

[0018] The conversion efficiency switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD. In general, the pixel signal is small when shooting in a dark place (low illuminance). Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V when converted to a voltage by the amplification transistor AMP will be small. On the other hand, in a bright place (high illuminance), the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to a voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In consideration of these, when the conversion efficiency switching transistor FDG is turned on, the diffusion layer capacitance or the diffusion layer capacitance and wiring capacitance for the conversion efficiency switching transistor FDG increase, so that the overall FD capacitance C increases. On the other hand, when the conversion efficiency switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the conversion efficiency switching transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0019] In the imaging device 1, for example, a plurality of sensor pixels 11 are repeatedly arranged in an array in a pixel region 110 in the first substrate 100 (see, for example, FIG. 15). Specifically, a pixel sharing unit 111 including a plurality of sensor pixels 11 is a repeating unit, and this is repeatedly arranged in an array in a row direction and a column direction. In the present embodiment, the pixel sharing unit 111 is composed of four sensor pixels 11, and the four sensor pixels 11 share one floating diffusion FD. The four sensor pixels 11 each have one readout circuit 21. The sensor pixels 11 have components in common with each other. In FIG. 1 and FIG. 4 to FIG. 11, in order to distinguish the components of each sensor pixel 11 from each other, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components of each sensor pixel 11. In the following, when it is necessary to distinguish the components of each sensor pixel 11 from one another, an identification number will be added to the end of the symbol of the component of each sensor pixel 11, but when it is not necessary to distinguish the components of each sensor pixel 11 from one another, the identification number at the end of the symbol of the component of each sensor pixel 11 will be omitted.

[0020] In each sensor pixel 11, for example, the cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to, for example, a vertical drive circuit 25a described later.

[0021] The floating diffusion FD shared by the four sensor pixels 11 is electrically connected to the input terminal of a common readout circuit 21. Specifically, the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the conversion efficiency switching transistor FDG. The drain of the conversion efficiency switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the conversion efficiency switching transistor FDG is connected to the drive signal line (FDG of the wiring 43). The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line (RST of the wiring 43). The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line VSL, and the gate of the selection transistor SEL is connected to the drive signal line (SEL of the wiring 43).

[0022] 2 shows an example in which the conversion efficiency switching transistor FDG is connected in series to the reset transistor RST, but the present invention is not limited to this. For example, as shown in FIG. 3, the conversion efficiency switching transistor FDG may be connected in parallel to the reset transistor RST.

[0023] In this embodiment, a capacitance addition wiring X is further connected to, for example, the drain of the conversion efficiency switching transistor FDG. This capacitance addition wiring X, which will be described in detail later, is configured to include a wiring on the first substrate 100 side and a wiring on the second substrate 200 side that are electrically connected to each other. By connecting the capacitance addition wiring X to, for example, the drain of the conversion efficiency switching transistor FDG, a capacitance is added. Specifically, when the conversion efficiency switching transistor FDG is turned on at high illuminance, the FD capacitance increases. This reduces the conversion efficiency, making it possible to handle a high saturation signal amount with the same pixel transistor.

[0024] The second substrate 200 may further include a logic circuit 25 on the semiconductor substrate 20. The logic circuit 25 controls each sensor pixel 11 and each readout circuit 21, and processes pixel signals obtained from each readout circuit 21. The logic circuit 25 includes, for example, a vertical drive circuit 25a, a column signal processing circuit 25b, a horizontal drive circuit 25c, and a system control circuit 25d, as shown in FIG. 12. The logic circuit 25 outputs an output voltage Vout obtained for each sensor pixel 11 to the outside.

[0025] The vertical drive circuit 25a, for example, sequentially selects, row by row, the multiple sensor pixels 11. The vertical drive circuit 25a is, for example, electrically connected to multiple drive wirings 112, and sequentially outputs selection signals to the multiple drive wirings 112, thereby sequentially selecting, row by row, the multiple sensor pixels 11.

[0026] The column signal processing circuit 25b performs, for example, correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 11 in a row selected by the vertical drive circuit 25a. The column signal processing circuit 25b extracts a signal level of the pixel signal by performing, for example, CDS processing, and holds pixel data according to the amount of light received by each sensor pixel 11. The column signal processing circuit 25b is, for example, electrically connected to a plurality of vertical signal lines VSL, and acquires pixel signals from each sensor pixel 11 in a row selected by the vertical drive circuit 25a via the plurality of vertical signal lines VSL. The column signal processing circuit 25b has, for example, an ADC (analog-to-digital) for each vertical signal line VSL, and converts the analog pixel signals acquired via the plurality of vertical signal lines VSL into digital pixel signals.

[0027] The horizontal drive circuit 25c, for example, sequentially outputs pixel data held in the column signal processing circuit 25b to the outside as an output voltage Vout. The system control circuit 25d, for example, controls the driving of each block (the vertical drive circuit 25a, the column signal processing circuit 25b, and the horizontal drive circuit 25c) in the logic circuit 25. The boost circuit 52, for example, generates a power supply potential VDD of a predetermined magnitude.

[0028] (1-2. Specific configuration of the imaging device) The semiconductor substrate 10 is, for example, a silicon substrate. The semiconductor substrate 10 has, for example, a photodiode PD (light receiving element 12), a floating diffusion FD, a VSS contact region 13, and a transfer transistor TR on the first surface 10A side. Furthermore, the semiconductor substrate 10 has a p-well 14 made of a p-type semiconductor region. The light receiving element 12 is made of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well 14. The floating diffusion FD is made of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well 14. The VSS contact region 13 is made of a semiconductor region of the same conductivity type (specifically, p-type) as the p-well 14 and with a higher impurity concentration than the p-well 14, and a part of it is provided in the p-well 14. A reference potential line VSS is connected to the VSS contact region 13, and thus adjacent sensor pixels 11 are electrically isolated from each other by the p-well 14.

[0029] The semiconductor substrate 20 is, for example, a silicon substrate. For example, an n-type semiconductor region 22 constituting the source / drain regions of the amplifying transistor AMP, the selection transistor SEL, the reset transistor RST, and the conversion efficiency switching transistor FDG is provided on the first surface 20A side of the semiconductor substrate 20. Furthermore, a VSS contact region 23 made of a p-type semiconductor region and a VDD contact region 24 made of an n-type semiconductor region are provided on the first surface 20A side.

[0030] In the wiring layer 30, a gate wiring (for example, gate wiring 35, see FIG. 14) that becomes the gate of the transfer transistor TR, a wiring 31 (lower wiring layer), and a wiring 32 (upper wiring layer) are formed in an interlayer insulating layer 33. The gate wiring 35, the wiring 31, and the wiring 32 are provided in this order from the first surface 10A side of the semiconductor substrate 10 in the interlayer insulating layer 33. A plurality of pad electrodes 34 are exposed on the surface of the interlayer insulating layer 33.

[0031] For example, the wiring 31 (lower wiring layer) includes a reference potential line VSS to which a fixed potential is applied, and the reference potential line VSS is electrically connected to the VSS contact region 13 through the via V1. The reference potential line VSS is formed, for example, so as to surround a pixel sharing unit 111 consisting of four sensor pixels 11. The reference potential line VSS has a function as a shield that prevents capacitive coupling between the wirings of the floating diffusion FD between adjacent pixel sharing units 111. The wiring 31 (lower wiring layer) further includes a wiring 31A. The wiring 31A is formed so as to surround the four transfer transistors TR1, TR2, TR3, and TR4 that constitute the pixel sharing unit 111. The wiring 31A is not electrically connected to any of the light receiving element 12, the VSS contact region 13, and the transfer transistor FD provided on the semiconductor substrate 10, and exists in an electrically floating state within the first substrate 100.

[0032] For example, the wiring 32 (upper wiring layer) includes wirings TRG1, TRG2, TRG3, and TRG4 extending in the H direction (row direction). The wirings TRG1, TRG2, TRG3, and TRG4 are for sending drive signals to the transfer gates TG1, TG2, TR3, and TG4 of the transfer transistors TR1, TR2, TR3, and TR4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TR3, and TG4 through the wiring 31 and vias V1 and V2, respectively.

[0033] In the wiring layer 40, a gate wiring 41, a wiring 42 (lower wiring layer), a wiring 43 (first intermediate wiring layer), a wiring 44 (second intermediate wiring layer), and a wiring 45 (upper wiring layer) which become the gates of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the conversion efficiency switching transistor FDG are formed in an interlayer insulating layer 46. The gate wiring 41, the wiring 42, the wiring 43, the wiring 44, and the wiring 45 are provided in this order from the first surface 20A side of the semiconductor substrate 20 in the interlayer insulating layer 46. A plurality of pad electrodes 47 are exposed on the surface of the interlayer insulating layer 46.

[0034] For example, the wiring 42 (lower wiring layer) and the wiring 43 (first intermediate wiring layer) include wirings SEL, RST, and FDG (drive signal lines) extending in the H direction (row direction). The wiring SEL is for sending a drive signal to the gate of the selection transistor SEL, the wiring RST is for sending a drive signal to the gate of the reset transistor RST, and the wiring FDG is for sending a drive signal to the gate of the conversion efficiency switching transistor FDG. The wirings SEL, RST, and FDG are connected to the gates of the selection transistor SEL, the reset transistor RST, and the conversion efficiency switching transistor FDG through vias V4 and V5, respectively. The wiring 42 (lower wiring layer) and the wiring 43 (first intermediate wiring layer) further include a power supply line VDD and a reference potential line VSS. The power supply line VDD is connected to the drain of the amplification transistor AMP through vias V4 and V5. The reference potential line VSS is connected to the VSS contact region 23 of the semiconductor substrate 20 through vias V4 and V5.

[0035] For example, the wiring 44 (second intermediate wiring layer) includes a power supply line VDD, a reference potential line VSS, and a vertical signal line VSL that extend in the V direction (column direction). The power supply line VDD is connected to the power supply line VDD of the wiring 43 through a via V6 and is connected to the drain of the amplification transistor AMP. The reference potential line VSS is connected to the reference potential line VSS of the wiring 43 through a via V6 and is connected to the VSS contact region 23 of the semiconductor substrate 20. The vertical signal line VSL is connected to the source (Vout) of the selection transistor SEL through the wirings 42 and 43 and vias V4, V5, and V6.

[0036] For example, the wiring 45 (upper wiring layer) includes a reference potential line VSS. The reference potential line VSS is formed so as to surround a pixel sharing unit 111 including, for example, four sensor pixels 11, similar to the reference potential line VSS of the wiring 31, and is connected to the reference potential line VSS of the wiring 44 through a via V7.

[0037] The first substrate 100 and the second substrate 200 are bonded together by bonding a plurality of pad electrodes 34 and pad electrodes 47 exposed on the respective surfaces of the wiring layer 30 and the wiring layer 40 provided on the respective first surfaces 10A, 20A, with the first surface 10A of the semiconductor substrate 10 facing the first surface 20A of the semiconductor substrate 20.

[0038] The capacitance-adding wiring X includes the wiring 31A and wiring 32A of the wiring layer 30, which are formed above, for example, the drain of the conversion efficiency switching transistor FGD, and the wiring 42A, wiring 43A, wiring 44A, and wiring 45A of the wiring layer 40. The wiring 31A and wiring 32A are connected, for example, via the via V2, but are not electrically connected to any element provided on the first substrate 100, and are in a so-called floating state. The wiring 42A, wiring 43A, wiring 44A, and wiring 45A are connected to each other via the vias V5, V6, and V7, respectively, and the wiring 42 is electrically connected to the n-type semiconductor region 22, which is, for example, the drain, of the conversion efficiency switching transistor FDG, via the via V4. The wiring 31A and wiring 32A correspond to a specific example of the "first wiring" of the present disclosure, and the wiring 42A, wiring 43A, wiring 44A, and wiring 45A correspond to a specific example of the "second wiring" of the present disclosure.

[0039] The wiring 31A extends within the interlayer insulating layer 33 as shown in FIG. 1, and is formed to surround the four transfer transistors TR1, TR2, TR3, and TR4 constituting the pixel sharing unit 111 as shown in FIG. 4. The wiring 31A and the wiring 32A are connected to the pad electrodes 34A and 47A that are joined to each other via vias V3 and V8, respectively. That is, the wiring 31A and the wiring 32A are electrically connected to the wiring 42A, the wiring 43A, the wiring 44A, and the wiring 45A. As a result, when the conversion efficiency switching transistor FDG is turned on at high illuminance, the capacitance of the n-type semiconductor region 22 (sub-floating diffusion SubFD) that serves as, for example, the drain of the conversion efficiency switching transistor FDG to which the capacitance adding wiring X is connected increases, and the amount of signals that can be handled by the floating diffusion FD increases.

[0040] 1 shows an example in which the adjacent sensor pixels 11 are electrically isolated by the p-well 14, but the adjacent sensor pixels 11 may be isolated by a pixel isolation portion including an insulating film such as silicon oxide (SiO). The pixel isolation portion is provided to separate the adjacent sensor pixels 11 from each other, and has a lattice-like planar shape, for example. The pixel isolation portion may have a full trench isolation (FTI) structure penetrating between the first surface 10A and the second surface 10B of the semiconductor substrate 10, or may have a deep trench isolation (DTI) structure extending from the first surface 10A to the second surface 10B of the semiconductor substrate 10 and having an end portion within the semiconductor substrate 10.

[0041] (1-3. Actions and Effects) In the imaging device 1 of this embodiment, wiring (wires 31A, 32A) that are not electrically connected to any of the elements provided on the semiconductor substrate 10 are provided in the wiring layer 30 laminated on the first surface 10A of the semiconductor substrate 10 having the sensor pixels 11, and these are electrically connected to wiring (wires 42, 43, 44, 45) that are provided in the wiring layer 40 laminated on the first surface 20A of the semiconductor substrate 20 having the readout circuit 21 and are electrically connected to the elements provided on the semiconductor substrate 20. This increases the wiring capacitance. This will be described below.

[0042] As mentioned above, in order to realize further miniaturization of imaging devices and high pixel density, imaging devices with a three-dimensional structure have been developed in which, for example, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by each sensor pixel are stacked on each other. In such imaging devices, the photodiode PD, floating diffusion FD, and transfer transistor are formed on separate silicon substrates, and pixel transistors other than the transfer transistor are formed on separate silicon substrates, thereby expanding the area (volume) of the photodiode, increasing the amount of saturation charge, and improving quantum efficiency. This structure is more effective for finer pixels in which the area ratio of the pixel transistor region to the pixel size is high.

[0043] In addition, an imaging device with a three-dimensional structure has been developed in which the photodiode PD, floating diffusion FD, and transfer transistor are formed on a first substrate, pixel transistors other than the transfer transistor are formed on a second substrate, and the logic circuit is formed on a third substrate, and these three substrates (first substrate, second substrate, and third substrate) are stacked.

[0044] However, even with the above-mentioned structure, the channel width and gate length of the pixel transistor are reduced as the pixels are miniaturized, and this reduces the operating range of each pixel transistor, such as the selection transistor and the reset transistor, resulting in a reduction in the amount of signal charge that can be handled, i.e., there is a problem of a reduced dynamic range.

[0045] Furthermore, the wiring length of the floating diffusion FD becomes shorter as pixels become finer, and the conversion efficiency increases. In other words, the amplitude width of the FD potential when the same amount of charge is received increases, further reducing the amount of signal charge that can be handled.

[0046] As a technology for handling high saturation signal levels, an imaging device has been reported that has a capacitance-adding transistor with a floating diffusion FD connected to one end and a reset transistor connected to the other end. In this imaging device, high conversion efficiency is achieved by turning off the capacitance-adding transistor, and the effects of noise are reduced. On the other hand, in high-illumination areas, the capacitance-adding transistor is turned on, and the wiring capacitance, diffusion layer capacitance, and oxide film capacitance are added to the floating diffusion capacitance, reducing the conversion efficiency. This makes it possible to handle high saturation signal levels with the same pixel transistor.

[0047] However, even if the above technology is applied to an imaging device with a three-dimensional structure, the area for routing the wiring that adds capacitance is limited in miniaturized pixels, so there is a limit to the capacitance that can be added, making it difficult to ensure sufficient capacitance.

[0048] In contrast, in this embodiment, wiring (wires 31A, 32A) that are not electrically connected to any of the elements provided on the semiconductor substrate 10 are provided in the wiring layer 30 laminated on the first surface 10A of the semiconductor substrate 10 having the sensor pixels 11, and this is electrically connected to wiring (wires 42, 43, 44, 45; capacitance adding wiring) that is connected to the conversion efficiency switching transistor FDG and adds capacitance to the conversion efficiency switching transistor FDG, for example, via pad electrodes 34A, 47A. As a result, the conversion efficiency switching transistor FDG is connected to the wiring layer 40 of the second substrate 200 as well as the capacitance adding wiring X routed around the wiring layer 30 of the first substrate 100.

[0049] As a result, in the imaging device 1 of this embodiment, it is possible to increase the capacitance of the floating diffusion FD when the conversion efficiency switching transistor FDG is turned on. Specifically, the capacitance of the n-type semiconductor region 22 (sub-floating diffusion SubFD) that serves as, for example, the drain of the conversion efficiency switching transistor FDG to which the capacitance addition wiring X is connected increases, making it possible to significantly reduce the conversion efficiency. Therefore, the floating diffusion FD can handle a larger amount of signals, and the dynamic range can be expanded.

[0050] In addition, in order to increase the capacity of the floating diffusion FD in a general imaging device, the only way is to increase the total number of wirings, which leads to an increase in the number of processes, i.e., an increase in costs. In contrast, in the imaging device 1 of the present embodiment, the capacitance adding wiring X is routed in a wiring layer (lower wiring layer, wiring 31) in the wiring layer 30 on the first substrate 100 side, so that the capacity of the floating diffusion FD can be increased without increasing the number of processes.

[0051] The following describes the second embodiment and modifications 1 and 2. In the following description, the same components as those in the first embodiment are given the same reference numerals and the description thereof will be omitted as appropriate.

[0052] <2. Variation 1> 13 is a schematic diagram showing another example of the layout of the lower wiring layer (wires 31) in the first substrate 100 of the imaging device 1 as a modified example (modified example 1) of the present disclosure. In the above-described first embodiment, an example (FIG. 4) is shown in which the reference potential line VSS surrounds the pixel sharing unit 111 consisting of four sensor pixels 11, but for example, as shown in FIG. 13, the reference potential VSS extending in the H direction (column direction) may be omitted and the wire 31A constituting the capacitive wiring X may be arranged.

[0053] For example, if pixels are further miniaturized, the reference potential line VSS of the wiring 31 functioning as a shield wiring and the wiring 31A constituting the capacitance adding wiring X may become excessively close to each other, which may make it difficult to route the wiring 31A.

[0054] In contrast, in this modification, the wiring 31A constituting the capacitance adding wiring X also serves as a part of the shield wiring (reference potential line VSS of the wiring 31). When the imaging device 1 is driven in a high conversion efficiency mode at low illuminance, the potential of the capacitance adding wiring X is fixed to VDD when the conversion efficiency switching transistor FDG is turned off and the reset transistor RST is turned on. As a result, the pixel sharing units 111 adjacent to each other in the H direction (row direction) are shielded by the capacitance adding wiring X (wiring 31A) whose potential is fixed to VDD. Therefore, similar to the first embodiment, it is possible to prevent capacitive coupling between the wirings of the floating diffusion FD between the adjacent pixel sharing units 111.

[0055] In addition, the wiring 31A also serves as a part of the shield wiring (reference potential line VSS of the wiring 31), improving the layout efficiency of the wiring. Therefore, even if the pixels are further miniaturized, it becomes possible to route the capacitance adding wiring X. In other words, it becomes possible to maintain the dynamic range.

[0056] <3. Second embodiment> FIG. 14 is a schematic diagram showing an example of a vertical cross-sectional configuration of an imaging device (imaging device 2) according to a second embodiment of the present disclosure. FIG. 15 is a diagram showing an example of a schematic configuration of the imaging device 2 shown in FIG. 14. The imaging device 2 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). The imaging device 2 is an imaging device having a three-dimensional structure in which the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 2 of this embodiment differs from the first embodiment in that a logic circuit (logic circuit 51) is provided on a substrate (the third substrate 300) different from the readout circuit 21.

[0057] The first substrate 100 has a semiconductor substrate 10 and a wiring layer 30 provided on a first surface 10A of the semiconductor substrate 10, similarly to the first embodiment. The semiconductor substrate 10 has a plurality of sensor pixels 11 that perform photoelectric conversion, and the plurality of sensor pixels 11 are provided in a matrix in a pixel region 110 in the first substrate 100. The first substrate 100 has a plurality of drive wirings 112 that extend in the row direction, for example. The plurality of drive wirings 112 are electrically connected to a vertical drive circuit 51a (described later). The plurality of drive wirings 112 correspond to, for example, the wirings TRG1, TRG2, TRG3, and TRG4 of the wiring 32 described above.

[0058] The second substrate 200 has a semiconductor substrate 20 and a wiring layer 40 provided on the first surface 20A of the semiconductor substrate 20, similarly to the first embodiment. The semiconductor substrate 20 has a readout circuit 21 that outputs a pixel signal based on the charge output from the sensor pixel 11, for example, one for every four sensor pixels 11. The multiple readout circuits 21 are provided in a matrix in the readout circuit region 121 in the second substrate 200. The wiring layer 40 includes, for example, multiple drive wirings extending in the row direction and multiple vertical signal lines VSL extending in the column direction. The multiple drive wirings correspond to, for example, the wirings RST, FDG, and SEL of the wiring 43 described above. The multiple drive wirings provided on the second substrate 200 are electrically connected to a vertical drive circuit 51a described later. The multiple vertical signal lines VSL are electrically connected to a column signal processing circuit 51b described later.

[0059] In the wiring layer 30 and the wiring layer 40, as in the above-described first embodiment, a capacitance adding wiring X is provided above, for example, the drain of the conversion efficiency switching transistor FGD, and is formed including the wiring 31A and the wiring 32A of the wiring layer 30 and the wiring 42A, the wiring 43A, the wiring 44A and the wiring 45A of the wiring layer 40, and is connected to, for example, the drain (n-type semiconductor region 22) of the conversion efficiency switching transistor FDG.

[0060] The third substrate 300 has a semiconductor substrate 50 and a wiring layer 60. The semiconductor substrate 50 has a first surface 50A and a second surface 50B facing each other, and the wiring layer 60 is provided on the first surface 50A of the semiconductor substrate 50. The semiconductor substrate 50 has a logic circuit 51 and a boost circuit 52. The logic circuit 51 controls each sensor pixel 11 and each readout circuit 21, as with the logic circuit 25 of the first embodiment, and processes pixel signals obtained from each readout circuit 21. The logic circuit 51 has, for example, a vertical drive circuit 51a, a column signal processing circuit 51b, a horizontal drive circuit 51c, and a system control circuit 51d, as shown in FIG. 16. The logic circuit 51 outputs an output voltage Vout obtained for each sensor pixel 11 to the outside.

[0061] In the imaging device 2, for example, a through-wire 71A is provided around the pixel region 110 to extract the output voltage Vout output from the logic circuit 51 from the imaging device 2 and to supply a reference voltage to the boost circuit 52. Further, around the pixel region 110, through-wires 71B and 71C are provided to reach the first substrate 100 and the second substrate 200. The through-wire 71A is electrically connected to the through-wires 71B and 71C via a wire 72 provided on the second surface 1B of the semiconductor substrate 10, and the output voltage Vout and the boost potential extracted from the logic circuit 51 are supplied to the first substrate 100 and the second substrate 200, respectively, via the through-wires 71B and 71C.

[0062] As described above, in the imaging device 2 of this embodiment, the logic circuit 51 is provided on the third substrate 300, and the first substrate 100, the second substrate 200, and the third substrate 300 are laminated in this order. As in the first embodiment, the wiring layer 30 of the first substrate 100 and the wiring layer 40 of the second substrate 200 are provided with a capacitance-adding wiring X formed by connecting wiring (wiring 31A, 32A) that is not electrically connected to any element provided on the semiconductor substrate 10 and wiring (wiring 42, 43, 44, 45) provided on the wiring layer 40 and connected to the conversion efficiency switching transistor FDG. As a result, as in the first embodiment, it is possible to increase the capacitance of the floating diffusion FD without increasing the number of processes, and to expand the dynamic range.

[0063] <4. Modifications> 17 is a schematic diagram showing an example of a vertical cross-sectional configuration of an imaging device (imaging device 3) according to a modified example (modification 2) of the present disclosure. As in the second embodiment, imaging device 3 is an imaging device having a three-dimensional structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are laminated in this order.

[0064] In this modified example, for example, wirings TRG1, TRG2, TRG3, and TRG4 provided in wiring 32 (upper wiring layer) of the first substrate 100 are electrically connected to wiring (e.g., wiring 44A) that exists in an electrically floating state within the wiring layer 40 of the second substrate 200.

[0065] When pixels are miniaturized, apart from the problem of the dynamic range being reduced as described above, there is a risk that a sufficient coupling capacitance cannot be provided between the FD wiring and the transfer gate wiring.

[0066] Generally, there is a wiring layout technology that intentionally runs the FD wiring and the transfer gate wiring in parallel to add a coupling capacitance between them. This is intended to assist the charge transfer from the photodiode PD to the floating diffusion FD with the potential difference generated between the photodiode PD and the floating diffusion FD by boosting the FD potential through the coupling capacitance with the transfer gate wiring when the transfer transistor is turned on during charge transfer. When pixels are miniaturized, there is a limit to the space for routing the FD wiring and the transfer gate wiring, so sufficient coupling capacitance cannot be secured, and the charge transfer efficiency decreases.

[0067] In contrast, in this modification, as described above, for example, the wirings TRG1, TRG2, TRG3, and TRG4 provided in the wiring 32 (upper wiring layer) of the first substrate 100 are electrically connected to wirings (for example, wirings 43A, 44A, and 45A) that exist in an electrically floating state in the wiring layer 40 of the second substrate 200. As a result, in the wiring layer 30 and wiring layer 40 provided between the semiconductor substrate 10 and the semiconductor substrate 20, wirings (for example, wiring 31A, wiring TRG1, wirings 43A, 44A, and 45A; transfer gate wiring Y) that run parallel to the wiring (FD wiring) that connects between the floating diffusion FD provided on the first surface 10A of the semiconductor substrate 10 and the amplification transistor AMP provided on the first surface 20A of the semiconductor substrate 20 and are electrically connected to the transfer gate TG (for example, transfer gate TG1) are formed, and an inter-wiring capacitance is formed between the FD wiring and the transfer gate wiring Y.

[0068] As a result, even if pixels are further miniaturized, it is possible to ensure a sufficient opposing length between the FD wiring and the transfer gate wiring Y. Therefore, when charges are transferred from the light receiving element 12 to the floating diffusion FD, the FD potential is boosted via the transfer gate wiring Y, making it possible to improve the charge transfer efficiency. In other words, it is possible to improve the afterimage characteristics.

[0069] <5. Application Examples> FIG. 18 shows an example of a schematic configuration of an imaging system 4 including the imaging device (for example, the imaging device 1) according to the first and second embodiments and the first and second modifications thereof.

[0070] The imaging system 4 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 4 includes, for example, the imaging device 1 according to the above embodiment and its modified example, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 4, the imaging device 1 according to the above embodiment and its modified example, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.

[0071] The imaging device 1 according to the above embodiment and its modified examples outputs image data according to incident light. The DSP circuit 243 is a signal processing circuit that processes a signal (image data) output from the imaging device 1 according to the above embodiment and its modified examples. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 on a frame-by-frame basis. The display unit 245 is formed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the imaging device 1 according to the above embodiment and its modified examples. The storage unit 246 records image data of a moving image or a still image captured by the imaging device 1 according to the above embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 4 according to an operation by a user. The power supply unit 248 appropriately supplies various power sources that serve as operating power sources for the imaging device 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247 according to the above embodiment and its modified examples to these supply targets.

[0072] Next, the imaging procedure in the imaging system 4 will be described.

[0073] 19 shows an example of a flowchart of the imaging operation in the imaging system 4. The user issues an instruction to start imaging by operating the operation unit 247 (step S101). Then, the operation unit 247 transmits an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit) executes imaging in a predetermined imaging method (step S103).

[0074] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 243. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 stores the image data that has been subjected to the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the imaging system 4.

[0075] In this application example, the imaging device 1 according to the above-described embodiment and its modified example is applied to an imaging system 4. This allows the imaging device 1 to be made smaller or have higher definition, so that a small or high-definition imaging system 4 can be provided.

[0076] <6. Application Examples> (Application example 1) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0077] FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0078] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0079] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0080] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0081] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0082] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0083] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0084] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0085] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0086] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0087] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 57, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0088] FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

[0089] In FIG. 21, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0090] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0091] 21 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0092] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0093] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0094] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0095] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0096] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the imaging device 1 according to the above embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with little noise can be obtained, and therefore, high-precision control using the captured image can be performed in the mobile object control system.

[0097] (Application example 2) FIG. 22 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0098] 22 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11153 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0099] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0100] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0101] An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0102] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0103] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0104] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like.

[0105] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0106] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0107] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0108] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0109] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in the special light observation, a fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating an excitation light. In the fluorescent observation, it is possible to irradiate an excitation light to a body tissue and observe the fluorescence from the body tissue (autofluorescence observation), or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0110] FIG. 23 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0111] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0112] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0113] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 11402 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is composed of a multi-plate type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0114] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens.

[0115] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0116] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0117] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0118] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0119] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0120] The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0121] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0122] The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0123] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0124] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0125] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0126] Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0127] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, the imaging unit 11402 can be made smaller or have higher resolution, so that a small or high-resolution endoscope 11100 can be provided.

[0128] The present disclosure has been described above by giving the first and second embodiments and their first and second variations, application examples, and applied examples. However, the present disclosure is not limited to the above-mentioned embodiments, and various modifications are possible.

[0129] Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than the effects described in this specification.

[0130] The present disclosure may also be configured as follows: According to the present technology configured as follows, a first wiring and a second wiring are provided in a wiring layer formed on the opposing surfaces of a first semiconductor substrate having a sensor pixel and a second semiconductor substrate having a readout circuit, one of which is electrically floating and the other of which is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate, and which are also electrically connected to each other, thereby increasing the wiring capacitance and enabling the dynamic range to be expanded. (1) a first semiconductor substrate having a first surface and a second surface and having sensor pixels that perform photoelectric conversion; a second semiconductor substrate having a fourth surface and a third surface, the second semiconductor substrate having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second semiconductor substrate being stacked on the first semiconductor substrate with the first surface and the third surface facing each other; a wiring layer provided between the first semiconductor substrate and the second semiconductor substrate, the wiring layer having a first wiring and a second wiring electrically connected to each other, one of the first wiring and the second wiring being in an electrically floating state, and the other of the first wiring and the second wiring being electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate; An imaging device comprising: (2) the wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate; the first wiring is provided in the first wiring layer and is in an electrically floating state in the first wiring layer; The imaging device described in (1), wherein the second wiring is provided within the second wiring layer and is electrically connected to the transistor provided on the second semiconductor substrate. (3) The imaging device according to (2), wherein the first wiring is not electrically connected to the transistor provided on the first semiconductor substrate. (4) the wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate; the first wiring is provided in the second wiring layer and is in an electrically floating state in the second wiring layer; The imaging device described in (1), wherein the second wiring is provided within the first wiring layer and is electrically connected to the transistor provided on the first semiconductor substrate. (5) The imaging device according to (4), wherein the first wiring is not electrically connected to the transistor provided on the second semiconductor substrate. (6) The sensor pixel includes a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds a charge output from the light receiving element via the transfer transistor; The imaging device described in any one of (1) to (5), wherein the readout circuit has a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates a voltage signal corresponding to the level of charge held in the floating diffusion as the pixel signal, a selection transistor that controls the output timing of the pixel signal from the amplification transistor, and a conversion efficiency switching transistor that changes the charge-to-voltage conversion efficiency in the floating diffusion. (7) The imaging device according to (6), wherein the other of the first wiring and the second wiring is electrically connected to the conversion efficiency switching transistor. (8) The imaging device according to (6), wherein the other of the first wiring and the second wiring is electrically connected to the transfer transistor. (9) the first wiring layer and the second wiring layer each have a plurality of pad electrodes exposed on a surface thereof; The imaging device according to any one of (2) to (8), wherein the first wiring layer and the second wiring layer are bonded together by bonding the multiple pad electrodes to each other. (10) The imaging device described in (9), wherein the first wiring and the second wiring are electrically connected to connection wiring provided in the first wiring layer and the second wiring layer via the pad electrodes exposed on the surfaces of the first wiring layer and the second wiring layer, respectively. (11) The imaging device according to any one of (6) to (10), wherein the first semiconductor substrate has the light receiving element, the transfer transistor, and the floating diffusion for each of the sensor pixels. (12) The imaging device according to any one of (6) to (10), wherein the first semiconductor substrate has the light receiving element and the transfer transistor for each sensor pixel, and the floating diffusion is shared by a plurality of the sensor pixels. (13) the first semiconductor substrate has a plurality of pixel sharing units each including a plurality of the sensor pixels sharing one of the floating diffusions; The imaging device according to (12), wherein the first wiring and the second wiring are arranged between adjacent pixel sharing units. (14) The imaging device according to (13), wherein a fixed potential is applied to the first wiring and the second wiring. (15) a third semiconductor substrate further including a signal processing circuit for processing the pixel signals; The imaging device described in any one of (2) to (14), wherein a first substrate consisting of the first semiconductor substrate and the first wiring layer, a second substrate consisting of the second semiconductor substrate and the second wiring layer, and a third substrate are stacked in this order. (16) a first semiconductor substrate having a first surface and a second surface and having sensor pixels that perform photoelectric conversion; a second semiconductor substrate having a fourth surface and a third surface, the second semiconductor substrate having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second semiconductor substrate being stacked on the first semiconductor substrate with the first surface and the third surface facing each other; a wiring layer provided between the first semiconductor substrate and the second semiconductor substrate, the wiring layer having a first wiring and a second wiring electrically connected to each other, one of the first wiring and the second wiring being in an electrically floating state, and the other of the first wiring and the second wiring being electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate; An electronic device having an imaging device comprising:

[0131] This application claims priority based on Japanese Patent Application No. 2019-216511, filed on November 29, 2019 in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0132] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur to those skilled in the art depending on design requirements and other factors, and that such modifications are within the scope of the appended claims and their equivalents.

Claims

1. a first semiconductor substrate having a first surface and a second surface, the first semiconductor substrate having a sensor pixel including a light receiving element and a transfer transistor electrically connected to the light receiving element, the sensor pixel performing photoelectric conversion; a second semiconductor substrate having a third surface and a fourth surface, the second semiconductor substrate having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second semiconductor substrate being stacked on the first semiconductor substrate with the first surface and the third surface facing each other; a wiring layer provided between the first semiconductor substrate and the second semiconductor substrate, the wiring layer having a first wiring and a second wiring electrically connected to each other; Equipped with One of the first wiring and the second wiring is in an electrically floating state and is formed so as to surround the transfer transistor, and the other is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate. Imaging device.

2. the wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate; the first wiring is provided in the first wiring layer and is in an electrically floating state in the first wiring layer; The imaging device according to claim 1 , wherein the second wiring is provided in the second wiring layer and is electrically connected to the transistor provided on the second semiconductor substrate.

3. The image pickup device according to claim 2 , wherein the first wiring is not electrically connected to the transistor provided on the first semiconductor substrate.

4. the wiring layer includes a first wiring layer provided on the first surface of the first semiconductor substrate and a second wiring layer provided on the third surface of the second semiconductor substrate; the first wiring is provided in the second wiring layer and is in an electrically floating state in the second wiring layer; The imaging device according to claim 1 , wherein the second wiring is provided in the first wiring layer and is electrically connected to the transistor provided on the first semiconductor substrate.

5. The image pickup device according to claim 4 , wherein the first wiring is not electrically connected to the transistor provided on the second semiconductor substrate.

6. the sensor pixel further includes a floating diffusion that temporarily holds the charge output from the light receiving element via the transfer transistor, 2. The imaging device of claim 1, wherein the readout circuit comprises: a reset transistor that resets the potential of the floating diffusion to a predetermined position; an amplification transistor that generates, as the pixel signal, a signal having a voltage corresponding to a level of charge held in the floating diffusion; a selection transistor that controls an output timing of the pixel signal from the amplification transistor; and a conversion efficiency switching transistor that changes the charge-to-voltage conversion efficiency in the floating diffusion.

7. The imaging device according to claim 6 , wherein the other of the first wiring and the second wiring is electrically connected to the conversion efficiency switching transistor.

8. The imaging device according to claim 6 , wherein the other of the first wiring and the second wiring is electrically connected to the transfer transistor.

9. the first wiring layer and the second wiring layer each have a plurality of pad electrodes exposed on a surface thereof; The imaging device according to claim 2 , wherein the first wiring layer and the second wiring layer are attached to each other with the pad electrodes being bonded to each other.

10. 10. The imaging device of claim 9, wherein the first wiring and the second wiring are electrically connected to connection wiring provided in the first wiring layer and the second wiring layer via the pad electrodes exposed on the surfaces of the first wiring layer and the second wiring layer, respectively.

11. The imaging device according to claim 6 , wherein the first semiconductor substrate has the light receiving element, the transfer transistor, and the floating diffusion for each of the sensor pixels.

12. The imaging device according to claim 6 , wherein the first semiconductor substrate has the light receiving element and the transfer transistor for each of the sensor pixels, and the floating diffusion is shared by a plurality of the sensor pixels.

13. the first semiconductor substrate has a plurality of pixel sharing units each including a plurality of the sensor pixels sharing one of the floating diffusions; The imaging device according to claim 12 , wherein the first wiring and the second wiring are disposed between adjacent ones of the pixel sharing units.

14. The imaging device according to claim 13 , wherein a fixed potential is applied to the first wiring and the second wiring.

15. a third semiconductor substrate further including a signal processing circuit for processing the pixel signals; 3. The imaging device according to claim 2, wherein a first substrate consisting of the first semiconductor substrate and the first wiring layer, a second substrate consisting of the second semiconductor substrate and the second wiring layer, and a third substrate are stacked in this order.

16. a first semiconductor substrate having a first surface and a second surface, the first semiconductor substrate having a sensor pixel including a light receiving element and a transfer transistor electrically connected to the light receiving element, the sensor pixel performing photoelectric conversion; a second semiconductor substrate having a third surface and a fourth surface, the second semiconductor substrate having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second semiconductor substrate being stacked on the first semiconductor substrate with the first surface and the third surface facing each other; a wiring layer provided between the first semiconductor substrate and the second semiconductor substrate, the wiring layer having a first wiring and a second wiring electrically connected to each other; Equipped with One of the first wiring and the second wiring is in an electrically floating state and is formed so as to surround the transfer transistor, and the other is electrically connected to a transistor provided on the first semiconductor substrate or the second semiconductor substrate. An electronic device having an imaging device.

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