Comparator circuit and driver circuit

Abstract

To provide a comparator circuit and a drive circuit with low power consumption.SOLUTION: A comparator circuit 30 comprises: a comparator element 31 that outputs an accordance signal indicating whether or not a value of a first input signal and a value of a second input signal are agreed with each other; an FF circuit 33 that holds data of a data input terminal D on the basis of a comparator clock signal CMP_CLOCK and outputs an enable signal EN for stopping an operation of the comparator element 31; and an internal signal generation circuit that outputs an internal signal Z1 to the data input terminal D on the basis of the accordance signal Z and an output signal from the FF circuit 33.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a comparator circuit and a drive circuit. [Background technology]

[0002] Patent Document 1 discloses a horizontal drive circuit for a liquid crystal display device. In FIG. 2 of Patent Document 1, a comparator compares the counter output with the pixel value of digital image data. The comparator outputs a match pulse indicating that the two match to a D-type flip-flop circuit. A positive polarity switch and a negative polarity switch are switched in conjunction with the output of the D-type flip-flop. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-105166 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, even after the counter output and the digital image data match, the comparator continues to perform a comparison operation to compare the counter output and the digital image data. In other words, even after the comparator outputs a match pulse, the comparator continues to perform a switching operation. This causes a problem that the power consumption of the comparator becomes large.

[0005] The present disclosure has been made in consideration of the above-mentioned points, and has an object to provide a comparator circuit and a driver circuit with low power consumption. [Means for solving the problem]

[0006] The comparator circuit of this embodiment includes a comparator element that outputs a match signal indicating whether or not a value of a first input signal and a value of a second input signal match, a flip-flop circuit that holds data at a data input terminal based on a comparator clock signal and outputs an enable signal for stopping operation of the comparator element, and an internal signal generation circuit that outputs an internal signal to the data input terminal based on the match signal and an output signal from the flip-flop circuit. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a comparator circuit and a driver circuit with low power consumption. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of a drive circuit using a comparator circuit. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration of a comparator element. [Diagram 3] 1 is a circuit diagram showing the polarities of enable signals EN1 and EN1B. [Figure 4] 2 is a circuit diagram of a NOR circuit 111. [Diagram 5] 2 is a circuit diagram of a NAND circuit 112. FIG. [Figure 6] FIG. 1 is a circuit diagram showing a configuration of a comparator circuit according to a comparative example. [Figure 7] FIG. 1 is a diagram showing a configuration of a liquid crystal display device using a driving circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments. In addition, the following description and drawings are appropriately simplified for clarity of explanation.

[0010] A comparator circuit according to this embodiment and a drive circuit using the same will be described below. Fig. 1 is a circuit diagram showing a drive circuit 100 including a comparator circuit 30. Specifically, the drive circuit shown in Fig. 1 is a horizontal drive circuit for one column of pixels of a liquid crystal display device.

[0011] The driving circuit 100 includes a latch circuit 10, a counter 20, and a comparator circuit 30. Here, 10-bit image data DATA is input to the driving circuit 100. That is, one pixel is expressed in 1024 gradations (=10 bits). Of course, the number of bits of the image data is not particularly limited.

[0012] A latch signal LATCH and image data DATA are input to the latch circuit 10. The latch circuit 10 latches 10-bit image data DATA in response to the latch signal LATCH. The latch circuit 10 outputs the latched image data DATA in parallel to the comparator circuit 30. The image data DATA output from the latch circuit 10 is referred to as latch output A. The latch output A is 10-bit parallel data.

[0013] A counter clock signal CNT_CLOCK and a counter reset signal CNT_RST are input to the counter 20. The counter 20 performs a counting operation in synchronization with the counter clock signal CNT_CLOCK. For example, the counter 20 counts up a count value at the clock frequency of the counter clock signal CNT_CLOCK. The counter 20 outputs the count value resulting from the counting operation to the comparator circuit 30.

[0014] Furthermore, the counter 20 resets the count value to an initial value in response to a counter reset signal CNT_RST. The counter reset signal CNT_RST corresponds to the horizontal scanning frequency. The output of the counter 20 is 10 bits. Therefore, the counter 20 counts up the count value from 0 to 1023. The counter 20 outputs the 10-bit count value to the comparator circuit 30. The count value output from the counter 20 is defined as counter output B. The counter output B is 10-bit parallel data.

[0015] The comparator circuit 30 includes a comparator element 31, a flip-flop (FF) circuit 33, and an internal signal generating circuit 36. The internal signal generating circuit 36 ​​includes an inverter 34 and an OR circuit 35.

[0016] The comparator element 31 compares the latch output A with the counter output B. The comparator element 31 generates a match signal Z indicating that the latch output A and the counter output B match. The comparator element 31 outputs the match signal Z to the OR circuit 35. The latch output A and the counter output B are each 10-bit parallel data. The comparator element 31 compares each bit of the latch output A with the counter output B. The comparator element 31 determines that the latch output A and the counter output B match when all bits of the latch output A and the counter output B match.

[0017] When the latch output A and the counter output B match, the comparator element 31 asserts the match signal Z. When the latch output A and the counter output B differ, the comparator element 31 deasserts the match signal Z. Therefore, the match signal Z is a positive pulse signal that goes to a high level when the latch output A and the counter output B match.

[0018] The internal signal generation circuit 36 ​​generates an internal signal Z1 based on the output signal OUT from the FF circuit 33 and the match signal Z. The internal signal generation circuit 36 ​​outputs the internal signal Z1 to the FF circuit 33.

[0019] The FF circuit 33 is a D-type flip-flop circuit. The FF circuit 33 has a data input terminal D, a clock input terminal CK, a non-inverting output terminal Q, and an inverting output terminal QB. The output of the internal signal generation circuit 36 ​​is connected to the data input terminal D. The internal signal Z1 from the OR circuit 35 is input to the data input terminal D. The comparator clock signal CMP_CLOCK is input to the clock input terminal CK from the outside. The FF circuit 33 samples and holds the data value of the data input terminal D in response to the comparator clock signal CMP_CLOCK. The FF circuit 33 holds a 1-bit value.

[0020] The FF circuit 33 outputs a non-inverted output signal corresponding to the data value held therein from the non-inverted output terminal Q. The FF circuit 33 inverts the non-inverted output signal and outputs an inverted output signal from the inverted output terminal QB. The inverted output signal becomes the output signal OUT from the comparator circuit 30. When the value of the input data held by the FF circuit 33 is 1, the non-inverted output signal becomes high level and the inverted output signal becomes low level. When the value of the input data held by the FF circuit 33 is 0, the non-inverted output signal becomes low level and the inverted output signal becomes high level.

[0021] The output signal OUT of the FF circuit 33 is input to the FF circuit 33 via an inverter 34. The inverter 34 inverts the output signal OUT from the FF circuit 33 and outputs it to the OR circuit 35. The OR circuit 35 outputs the logical sum of the output from the inverter 34 and the match signal Z as the internal signal Z1. The OR circuit 35 outputs the internal signal Z1 to the data input terminal D of the FF circuit 33.

[0022] A comparator reset signal CMP_RST is input to the FF circuit 33. The FF circuit 33 resets the held data in response to the comparator reset signal CMP_RST. As a result, the data value held in the FF circuit 33 becomes 0. When the FF circuit 33 is reset by the comparator reset signal CMP_RST, the inverted output signal becomes high level and the non-inverted output signal becomes low level.

[0023] After being reset by the comparator reset signal CMP_RST, the FF circuit 33 samples the value of the internal signal Z1 in response to the comparator clock signal CMP_CLOCK. Therefore, the output signal OUT output from the inverting output terminal QB becomes a negative step signal when the internal signal Z1 is at a high level.

[0024] Furthermore, the output signal OUT from the inverting output terminal of the FF circuit 33 becomes the enable signal EN that controls the comparator element 31. That is, the output signal OUT is input to the comparator element 31 as the enable signal EN. The comparator element 31 stops operating in response to the enable signal EN. Specifically, when the enable signal is at a high level, the comparator element 31 performs a comparison operation as usual, and when the enable signal is at a low level, the comparator element 31 stops the comparison operation. When the enable signal EN is at a high level, the comparator element 31 compares the latch output A with the counter output B. When the enable signal EN is at a low level, the comparator element 31 does not compare the latch output A with the counter output B, and the match signal Z is fixed at a low level.

[0025] In this way, the comparator element 31 stops operating in response to the output signal OUT from the FF circuit 33. That is, the comparator element 31 stops operating due to the output signal OUT, which is a negative step signal. Specifically, the comparator element 31 stops operating after outputting a positive pulse signal as the match signal Z. This makes it possible to prevent switching operation in the comparator element 31, thereby reducing power consumption.

[0026] 2 is a circuit diagram showing an example of the configuration of the comparator element 31. As described above, the comparator element 31 compares 10-bit data. In the latch output A and the counter output B, the first bit of data is set as the latch output A[1] and the counter output B[1], respectively, and the tenth bit of data is set as the latch output A

[10] and the counter output B

[10] .

[0027] The comparator element 31 includes a plurality of 1-bit comparators 110, a NAND circuit 150, and an inverter 160. The comparator element 31 includes 10 1-bit comparators 110 to compare 10-bit data. The number of 1-bit comparators 110 corresponds to the number of bits of the latch output A, that is, the number of gradation bits. The circuit configuration of the 1-bit comparators 110 is the same. In FIG. 2, the 1-bit comparators 110 are omitted for the data of the second bit to the ninth bit. In the following description, the 1-bit comparator 110 that compares the latch output A[1] and the counter output B[1] will be mainly described.

[0028] The 1-bit comparator 110 includes a NOR circuit 111, a NAND circuit 112, an inverter 113, and a NAND circuit 114. The first bit of the latch output A[1] and the counter output B[1] are input to the NOR circuit 111. The NOR circuit 111 outputs a NOR (negative logical sum) of the latch output A[1] and the counter output B[1] to the inverter 113. The inverter 113 inverts the output of the NOR circuit 111 and outputs it to the NAND circuit 114.

[0029] The first bit of the latch output A[1] and the counter output B[1] are input to the NAND circuit 112. The NAND circuit 112 outputs the NAND (negative logical product) of the latch output A[1] and the counter output B[1] to the NAND circuit 114. The output of the NAND circuit 112 and the output of the inverter 113 are input to the NAND circuit 114. The NAND circuit 114 outputs the NAND (negative logical product) of the output of the NAND circuit 112 and the output of the inverter 113 as the output signal OUT[1] to the NAND circuit 150. When the values ​​of the latch output A[1] and the counter output B[1] match, the output of the NAND circuit 150 becomes high level.

[0030] As described above, the comparator element 31 is provided with ten 1-bit comparators 110. The outputs of the ten 1-bit comparators 110 are input to the NAND circuit 150. For example, the 10th 1-bit comparator 110 outputs the NAND of the NAND circuit 114 to the NAND circuit 150 as the output signal OUT

[10] .

[0031] The NAND circuit 150 outputs the NAND of the 10-bit output signals OUT[1] to OUT

[10] to the inverter 160. The inverter 160 inverts the output of the NAND circuit 150. The signal output from the inverter 160 becomes the match signal Z. When the output signals OUT[1] to OUT

[10] are at high level, the match signal Z becomes high level. When each bit value of the latch outputs A[1] to A

[10] matches each bit value of the counter outputs B[1] to B

[10] , the match signal Z is asserted. When at least one bit value of the latch outputs A[1] to A

[10] differs from the counter outputs B[1] to B

[10] , the match signal Z is deasserted.

[0032] Furthermore, enable signals EN1 and EN1B are input to the NOR circuit 111 and the NAND circuit 112. The enable signals EN1 and EN1B are generated based on the enable signal EN shown in FIG. 1. Specifically, as shown in FIG. 3, an inverter 81 and an inverter 82 output enable signals EN1B and EN1, which have different polarities, respectively. The enable signal EN1B is a signal obtained by inverting the enable signal EN once. The enable signal EN1 is a signal obtained by inverting the enable signal EN twice. Therefore, the enable signal EN1B is a signal obtained by inverting the enable signal EN1.

[0033] When the enable signal EN1 is at a high level, the NOR circuit 111 and the NAND circuit 112 operate. When the enable signal EN1 is at a low level, the NOR circuit 111 and the NAND circuit 112 stop operating. Therefore, when the enable signal EN1 is at a low level, the operation of the comparator element 31 stops.

[0034] 4 is a diagram showing a circuit configuration of the NOR circuit 111. The NOR circuit 111 is a CMOS (Complementary Metal-Oxide-Semiconductor) circuit, and includes seven transistors Tr1 to Tr7. The transistors Tr1 to Tr3 are p-type MOS transistors. The transistors Tr4 to Tr7 are n-type MOS transistors.

[0035] The transistors Tr1 to Tr4 are connected in series. Specifically, from the power supply potential side toward the ground side, the transistors Tr1, Tr2, Tr3, and Tr4 are arranged in this order. Between the transistor Tr4 and the ground, the transistors Tr5 and Tr6 are connected in parallel. An output signal C[1] is output from an output node between the transistors Tr3 and Tr4. In addition, a transistor Tr7 is arranged between the output node between the transistors Tr3 and Tr4 and the ground.

[0036] The latch output A[1] is input to the gate of transistor Tr1 and the gate of transistor Tr5. The counter output B[1] is input to the gate of transistor Tr2 and the gate of transistor Tr6. The enable signal EN1 is input to the gate of transistor Tr3 and the gate of transistor Tr7. The enable signal EN1B is input to the gate of transistor Tr4.

[0037] Therefore, when the enable signal EN1 is at a high level, the NOR circuit 111 operates normally. In other words, the output signal C[1] is the NOR of the latch output A[1] and the counter output B[1]. The output signal C[1] is input to the inverter 113 in FIG.

[0038] When the enable signal EN1 is at a low level, the transistors Tr3 and Tr4 are turned off and the transistor Tr7 is turned on. The NOR circuit 111 does not function and the output signal C[1] is at a low level. This makes it possible to prevent unnecessary switching operations in the NOR circuit 111. This makes it possible to reduce the current flowing from the power supply potential to the ground.

[0039] 5 is a diagram showing a circuit configuration of the NAND circuit 112. The NAND circuit 112 is a CMOS circuit, and includes seven transistors Tr11 to Tr17. The transistors Tr11 to Tr14 are p-type MOS transistors. The transistors Tr15 to Tr17 are n-type MOS transistors.

[0040] Transistors Tr14 to Tr17 are connected in series. Specifically, from the ground toward the power supply potential, transistors Tr17, Tr16, Tr15, and Tr14 are arranged in this order. Transistors Tr11 and Tr12 are connected in parallel between transistor Tr14 and the power supply potential. An output signal D[1] is output from an output node between transistors Tr14 and Tr15. Transistor Tr13 is also arranged between the output node between transistors Tr14 and Tr15 and the power supply potential.

[0041] Latch output A is input to the gates of transistors Tr12 and Tr16. Counter output B is input to the gates of transistors Tr11 and Tr17. Enable signal EN1 is input to the gates of transistors Tr13 and Tr15. Enable signal EN1B is input to the gate of transistor Tr14.

[0042] Therefore, when the enable signal EN1 is at a high level, the NAND circuit 112 operates normally. The output signal D[1] is the NAND of the latch output A[1] and the counter output B[1]. The output signal D[1] is input to the NAND circuit 114 in FIG.

[0043] When the enable signal EN1 is at a low level, the transistors Tr14 and Tr15 are turned off, and the transistor Tr13 is turned on. Therefore, the NAND circuit 112 does not function, and the output signal D[1] becomes a high level. The transistors Tr14 and Tr15 are turned off. This makes it possible to prevent unnecessary switching operations in the NAND circuit 112. This makes it possible to reduce the current flowing from the power supply potential to the ground.

[0044] In this way, the enable signals EN1 and EN1B stop the operation of the 1-bit comparator 110. When the enable signal EN1 is at a low level, the value of the output signal C[1] becomes "0" and the value of the output signal D[1] becomes "1." In other words, regardless of the values ​​of the latch output A[1] and the counter output B[1], the outputs of the NOR circuit 111 and the NAND circuit 112 are constant.

[0045] When the enable signal EN1 is at a low level, the value of the output signal OUT[1] of the NAND circuit 114 shown in Fig. 2 becomes "0". Each of the ten 1-bit comparators 110 includes a NOR circuit 111 shown in Fig. 4 and a NAND circuit 112 shown in Fig. 5. When the enable signal EN1 is at a low level, the match signal Z output from the comparator circuit 30 becomes at a low level. Therefore, the match signal Z becomes a positive pulse signal that becomes at a high level when the latch output A and the counter output B match.

[0046] As described above, the output signal OUT output from the FF circuit 33 becomes the enable signal EN that stops the operation of the comparator element 31. The comparator circuit 30 has a self-gating function that stops the switching operation by the enable signal EN generated by the FF circuit 33. The operation of the comparator element 31 can be stopped at an appropriate timing. After the comparator element 31 outputs a positive pulse, it stops its operation. This makes it possible to reduce power consumption.

[0047] Furthermore, it is possible to prevent a switching operation in the comparator element 31. Therefore, it is possible to suppress noise caused by the switching operation, and therefore it is possible to improve reliability.

[0048] Fig. 6 shows a drive circuit having a comparator circuit 30 according to a comparative example. The basic operations of the latch circuit 10, counter 20, and comparator element 31 are the same as those in Fig. 1, so detailed explanations will be omitted. For example, the comparator element 31 outputs a match signal Z indicating that the latch output A and the counter output B match. The match signal Z is a positive pulse.

[0049] 6, the output signal from the FF circuit 33 is not used as an enable signal. Therefore, the comparator element 31 continues to perform a comparison operation even after the latch output A and the counter output B match. Therefore, the power consumption of the comparator element 31 increases more than that of the configuration shown in FIG.

[0050] 1, the comparator element 31 stops operating in response to the enable signal EN from the comparator circuit 30. This makes it possible to reduce the power consumption of the comparator circuit 30.

[0051] The comparator circuit 30 and the drive circuit 100 according to this embodiment make it possible to reduce the power consumption of a liquid crystal display device. For example, assume that the drive circuit 100 is applied to a WUXGA LCOS (Liquid Crystal On-Silicon) device at a frame rate of 120 Hz. In this case, the power consumption of the device can be reduced from 1188 mW to 1126 mW. In other words, it is possible to reduce the power consumption by 5.3% (=62 mW).

[0052] The configuration of a liquid crystal display device 200 in which the comparator circuit 30 is applied to a drive circuit will be described with reference to Fig. 7. The liquid crystal display device 200 is an LCOS display. Fig. 7 is a block diagram showing the backplane of the LCOS display.

[0053] The liquid crystal display device 200 includes a pixel display section 50, a vertical drive circuit 2, and a horizontal drive circuit 3. The horizontal drive circuit 3 includes the drive circuit 100 shown in Fig. 1. Specifically, the horizontal drive circuit 3 includes m (m is an integer of 2 or more) drive circuits 100 corresponding to the number of pixels in one line.

[0054] The pixel display section 50 is provided with a plurality of data lines 6, a plurality of gate lines 8, and a plurality of pixels 42. The plurality of data lines 6 are arranged parallel to one another. The plurality of gate lines 8 are arranged parallel to one another. The plurality of data lines 6 and the plurality of gate lines 8 are arranged so as to intersect with one another. The gate lines 8 serve as row scanning lines.

[0055] The liquid crystal display device 200 includes a plurality of sets of data lines 6, two in one set. The liquid crystal display device 200 inverts and drives the pixels 42 using one set of data lines 6. Hereinafter, the positive data line 6 in one set of data lines 6 will be referred to as data line 6a, and the negative data line 6 will be referred to as data line 6b. Similarly, the switch 1 and the video signal line 5 will be identified by their polarities as switch 1a, switch 1b, and video signal lines 5a, 5b. To invert the polarity, two systems of data lines 6, switches 1, and video signal lines 5 are provided.

[0056] Pixels 42 are arranged at the intersections of data lines 6 and gate lines 8. The pixels 42 are arranged in a matrix. Each pixel 42 is driven by one set of data line 6 and one gate line 8. For example, if there are n gate lines 8 and 2m data lines 6, the pixels 42 are arranged in a matrix of n rows and m columns. Note that m and n are each an integer of 2 or more. The pixels 42 include a pixel driving circuit for driving the liquid crystal, pixel electrodes, and the like.

[0057] The vertical drive circuit 2 performs vertical drive by selecting a plurality of gate lines 8 for each horizontal scanning period. The vertical drive circuit 2 supplies scanning signals to the plurality of gate lines 8. In other words, the vertical drive circuit 2 supplies scanning signals to sequentially select the gate lines 8 from the first row to the nth row. This causes the pixels 42 to be selected row by row. All the gate lines 8 are selected within one vertical scanning period. Video signals can be written to the pixels 42 of the selected row.

[0058] The horizontal drive circuit 3 performs horizontal direction drive by driving a plurality of switches 1 within a horizontal scanning period. This causes a video signal to be supplied to a plurality of data lines 6. As described above, two data lines 6a, 6b are connected to pixels 42 as a set. Therefore, two data lines 6a, 6b are commonly connected to one row of pixels 42.

[0059] The data line 6a is connected to the video signal line 5a via a switch 1a. The data line 6b is connected to the video signal line 5b via a switch 1b. A positive video signal RAMP+ is supplied to the video signal line 5a. A negative video signal RAMP- is supplied to the video signal line 5b. The horizontal drive circuit 3 controls the switches 1a and 1b.

[0060] Therefore, a positive video signal RAMP+ is supplied to one data line 6a of a pair of data lines 6a and 6b, and a negative video signal RAMP- is supplied to the other data line 6b. The positive video signal RAMP+ is a positive voltage with respect to the common potential of the common electrode line, and the negative video signal RAMP- is a negative voltage with respect to the common potential of the common electrode line. The horizontal drive circuit 3 can supply the positive video signal RAMP+ and the negative video signal RAMP- to the pixels 42 of a selected row. The horizontal drive circuit 3 turns on and off each switch 1 multiple times within a horizontal scanning period. Therefore, the positive video signal RAMP+ and the negative video signal RAMP- are alternately supplied to the pixels 42.

[0061] Specifically, the horizontal drive circuit 3 includes a latch circuit 310, a counter 320, a comparator circuit 330, a shift register 360, and a buffer 370. The latch circuit 310 corresponds to the latch circuit 10 in Fig. 1. That is, the latch circuit 310 includes latch circuits 10 for m columns. The latch circuit 310 holds image data DATA of the pixels 42 in the 1st to mth columns.

[0062] The comparator circuit 330 corresponds to the comparator circuit 30 in Fig. 1. That is, the comparator circuit 330 has m columns of comparator circuits 30. An output signal OUT from the comparator circuit 30 shown in Fig. 1 controls the switch 1. The counter 320 corresponds to the counter 20 in Fig. 1. Therefore, the counter 320 performs a counting operation according to the counter clock signal CNT_CLOCK.

[0063] The shift register 360 sequentially transmits image data DATA for m columns in response to the horizontal clock HCLOCK. After holding image data DATA for m columns, the shift register 360 outputs the image data DATA to the latch circuit 310. The latch circuit 310 holds the image data DATA for each column in response to the latch signal LATCH.

[0064] As shown in FIG. 1, the comparator circuit 330 compares the latch output A with the counter output B. The comparator circuit 330 controls the pair of switches 1a and 1b. The pair of switches 1a and 1b opens and closes according to the output signal of the comparator circuit 330. At first, all the pairs of switches 1 are closed, so that no video signal is supplied to the pixel 42. When the output signal of the comparator circuit 330 is asserted, the corresponding switch 1 opens. As a result, a positive video signal RAMP+ and a negative video signal RAMP- are alternately applied to the pixel 42. The liquid crystal display device 200 can perform gradation display according to the image data DATA.

[0065] The buffer 370 buffers various signals output from an external controller. Since the pixel display unit 50 has a large number of columns, the buffer 370 is used to drive a heavy load. For example, the horizontal clock signal HCLOCK is input to the shift register 360 via the buffer 370. Similarly, the latch signal LATCH is input to the latch circuit 310 via the buffer 370. The counter output from the counter 320 is input to the comparator circuit 330 via the buffer 370. The comparator clock signal CMP_CLOCK is input to the comparator circuit 330 via the buffer 370.

[0066] In this embodiment, the comparator circuit 330 includes the comparator circuit 30 shown in Fig. 1. This makes it possible to reduce the power consumption of the comparator circuit 330. Furthermore, since noise can be suppressed, reliability can be improved.

[0067] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0068] 1 Switch 2 Vertical drive circuit 3 Horizontal drive circuit 6 Data lines 8 Gate Lines 42 pixels 50 pixel display 100 Drive circuit 10 Latch Circuit 20 Counter 30 Comparator Circuit 31 Comparator element 33 FF circuit 34 Inverter 35 OR Circuit 36 Internal signal generation circuit 200 LCD display device 310 Latch Circuit 320 Counter 330 Comparator Circuit 360 Shift Register 370 Buffer

Claims

1. a comparator element that outputs a match signal indicating whether a value of the first input signal matches a value of the second input signal; a flip-flop circuit that holds data at a data input terminal based on a comparator clock signal and outputs an enable signal corresponding to the data for stopping the operation of the comparator element; an internal signal generating circuit that outputs an internal signal to the data input terminal based on the match signal and an output signal from the flip-flop circuit.

2. 2. The comparator circuit according to claim 1, wherein an inverted output signal from an inverted output terminal of said flip-flop circuit serves as said enable signal.

3. The internal signal generating circuit includes: an inverter to which the inverted output signal is input; 3. The comparator circuit according to claim 2, further comprising: an OR circuit that outputs a logical sum of the signal from said inverter and said coincidence signal.

4. the comparator element comprises a PMOS transistor and an NMOS transistor connected in series between a power supply potential and a ground; 4. The comparator circuit according to claim 1, wherein the PMOS transistor and the NMOS transistor operate in response to the enable signal.

5. A comparator circuit according to any one of claims 1 to 4; a latch circuit that holds image data and outputs the image data to the comparator element as the first input signal; a counter that performs a counting operation in response to a counter clock signal and outputs a counter value as the second input signal.

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