Semiconductor device and semiconductor system

Abstract

The invention relates to a semiconductor device and a semiconductor system. The semiconductor device includes first and second power supply voltage lines to which a power supply voltage is supplied, a first impedance element provided between the first and second power supply voltage lines, first and second reference voltage lines to which a reference voltage is supplied, and a second impedance element provided between the first and second power supply voltage lines. A second impedance element provided between the first reference voltage line and the second reference voltage line, electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined process on an input signal, and first transistor as a P-channel MOS transistor provided in series between the second power supply voltage line and the second reference voltage line and having a gate connected to a drain, and method thereof and the second transistor is an N-channel MOS transistor.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-207599, filed on December 8, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a semiconductor system equipped with the semiconductor device, and more particularly, to a semiconductor device and a semiconductor system suitable for achieving low power consumption. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-332705

[0006] There is a need to reduce power consumption in semiconductor systems. In particular, in recent years, there has been a need to reduce standby power consumption in systems such as keyless entry systems installed in vehicles and alarm systems installed in vehicles. That is, in recent years, there has been a need to reduce standby power consumption of semiconductor systems and semiconductor devices installed therein. An example of a technology related to a keyless entry system is disclosed in Patent Document 1. Summary of the Invention

[0007] As described above, there is a need to reduce standby power consumption in semiconductor devices and semiconductor systems equipped with them. Other objects and novel features will become apparent from the description of this specification and the drawings.

[0008] The semiconductor device according to the present disclosure includes a first power supply voltage line supplied with a power supply voltage, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line supplied with a reference voltage, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined process on an input signal, and a first transistor as a P-channel MOS transistor and a second transistor as an N-channel MOS transistor that are serially provided between the second power supply voltage line and the second reference voltage line and each have a gate connected to its drain.

[0009] The present disclosure can provide a semiconductor device and a semiconductor system equipped with the semiconductor device that can achieve low power consumption. Brief Description of the Drawings

[0010] Figure 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment.

[0011] Figure 2 is a waveform diagram showing the operation of the semiconductor device shown Figure 1 in the figure.

[0012] Figure 3 is a diagram showing a configuration example of a semiconductor device according to a second embodiment.

[0013] Figure 4 is a diagram showing a configuration example of a semiconductor system according to a third embodiment.

[0014] Figure 5 is a diagram showing the simulation result of the EYE opening in a comparative example of a semiconductor system.

[0015] Figure 6 is a diagram showing Figure 4 the simulation result of the EYE opening in the semiconductor system shown in the figure.

[0016] Figure 7 is a diagram showing a configuration example of a semiconductor system according to a fourth embodiment.

[0017] Figure 8 is a diagram showing the specific configuration example of the first pseudo-impedance circuit provided in Figure 7 the semiconductor system shown in the figure.

[0018] Figure 9 is a diagram showing the specific configuration example of the second pseudo-impedance circuit provided in Figure 7 the semiconductor system shown in the figure.

[0019] Figure 10 is a diagram showing Figure 7 the simulation result of the EYE opening in the semiconductor system shown in the figure.

[0020] Figure 11 is a diagram showing the AC analysis result of the semiconductor system shown in the figure when noise is applied to the power supply voltage VDD Figure 7 in the figure.

[0021] Figure 12 is a diagram showing Figure 7 a modified example of the semiconductor system shown in the figure.

[0022] Figure 13 is a diagram showing a configuration example of a pre-reviewed semiconductor device.

[0023] Figure 14 is a diagram showing Figure 13 the waveform diagram of the operation of the semiconductor device shown in the figure. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments will be described with reference to the accompanying drawings. The technical scope of the embodiments should not be narrowly interpreted based on the descriptions of the drawings because the drawings are simplified. Also, the same reference numerals are assigned to the same elements, and redundant descriptions are omitted.

[0025] For convenience, when necessary, the following embodiments are described in multiple sections or divided into different embodiments. However, unless otherwise clearly stated, they are not mutually independent; one can be related to another in whole or in part in the form of modification, application, detailed explanation, supplementary explanation, etc. Also, in the following embodiments, when referring to the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.), it is not limited to a specific number, but can be not less than or equal to the specific number, except in cases where the number is clearly indicated and is clearly limited to the specific number in principle.

[0026] In addition, in the following embodiments, unless specifically specified and unless it is considered clearly necessary in principle, the constituent elements (including operation steps, etc.) are not necessarily required. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is assumed that these shapes, etc. are basically approximate or similar to these shapes, etc., except in cases where they are specifically specified and in cases where it is considered obvious in principle, etc. This also applies to the above-mentioned quantities, etc., including quantities, numerical values, amounts, ranges, etc.

[0027] (Preliminary Examination by the Inventor)

[0028] First, a semiconductor device subjected to the preliminary examination by the inventor will be described. Figure 13 is a diagram showing a configuration example of the semiconductor device 50 subjected to the preliminary examination.

[0029] As Figure 13 shown, the semiconductor device 50 includes a power supply voltage terminal to which an external power supply voltage VDD is supplied, a reference voltage terminal to which an external reference voltage GND is supplied, an input terminal to which an external input signal IN is supplied, and a logic circuit (electronic circuit) 51.

[0030] For example, the power supply voltage VDD indicates 3.3V, and the reference voltage GND indicates 0V. Hereinafter, the line to which the power supply voltage VDD is supplied is referred to as the first power supply voltage line VDD, and the line to which the reference voltage GND is supplied is referred to as the first reference voltage line GND. The logic circuit 51 is provided between the first power supply voltage line VDD and the first reference voltage line GND, and performs a predetermined process on the input signal IN. In other words, the logic circuit 51 is driven by the power supply voltage VDD and the reference voltage GND, and performs a predetermined process on the input signal IN.

[0031] Here, the lower the average power consumption current (dark current) of the logic circuit 51, the more the power consumption of the semiconductor device 50 is suppressed. For example, if the semiconductor device 50 is installed in a vehicle as part of a keyless entry system, the lower the dark current of the logic circuit 51, the more the power consumption stored in the vehicle battery is suppressed.

[0032] Figure 14 is a waveform diagram showing the operation of the semiconductor device 50. In Figure 14 it, the scale of the logic circuit 51 is equivalent to 2K gates in terms of NAND gates, the frequency of the main clock signal supplied to the logic circuit 51 is 16 MHz, and the operation rate of the logic circuit 51 is assumed to be 50%. In this case, the peak current of the logic circuit 51 is indicated as 225 mA, and the average power consumption current (dark current) of the logic circuit 51 is indicated as 4.8 mA. In recent years, there has been a demand to further reduce the average power consumption of the logic circuit 51.

[0033] Therefore, a semiconductor device 1 capable of achieving low power consumption has been found.

[0034] (First Embodiment)

[0035] Figure 1 is a diagram showing a configuration example of the semiconductor device 1 according to the first embodiment. For example, the semiconductor device 1 is applicable to a keyless entry system installed in a vehicle or an alarm system installed in a vehicle.

[0036] As Figure 1 shown, the semiconductor device 1 includes a power supply voltage terminal supplied with an external power supply voltage VDD, a reference voltage terminal supplied with an external reference voltage GND, an input terminal supplied with an external input signal IN, a resistance element (first impedance element) R1, a resistance element (second impedance element) R2, a transistor (first transistor) MP1 as a P-channel MOS transistor, a transistor (second transistor) MN1 as an N-channel MOS transistor, and a logic circuit (electronic circuit) 10.

[0037] For example, the power supply voltage VDD indicates 3.3 V, and the reference voltage GND indicates 0 V. Hereinafter, the line supplied with the power supply voltage VDD is referred to as the first power supply voltage line VDD, and the line supplied with the reference voltage GND is referred to as the first reference voltage line GND. The resistance element R1 is provided between the first power supply voltage line VDD and the second power supply voltage line VDD2. The resistance element R2 is provided between the first reference voltage line GND and the second reference voltage line GND2.

[0038] The logic circuit 10 is provided between the second power supply voltage line VDD2 and the second reference voltage line GND2, and performs a predetermined process on the input signal IN. In other words, the logic circuit 10 is driven by the power supply voltage of the second power supply voltage line VDD2 (hereinafter referred to as the power supply voltage VDD2) and the reference voltage of the second reference voltage line GND2 (hereinafter referred to as the reference voltage GND2), and performs a predetermined process on the input signal IN. The source and back gate of each P-channel MOS transistor provided in the logic circuit 10 are connected to the second power supply voltage line VDD2. In addition, the source and back gate of each N-channel MOS transistor provided in the logic circuit 10 are connected to the second reference voltage line GND2.

[0039] The transistors MP1 and MN1 are serially provided between the second power supply voltage line VDD2 and the second reference voltage line GND2. Specifically, in the transistor MP1, the source and back gate are connected to the second power supply voltage line VDD2, and the gate and drain are connected to the gate and drain of the transistor MN1. In the transistor MN1, the source and back gate are connected to the second reference voltage line GND2. By providing the transistors MP1 and MN1, the power supply voltage of the second power supply voltage line VDD2 and the reference voltage of the second reference voltage line GND2 are stabilized.

[0040] Here, the smaller the dark current of the logic circuit 10, the more the power consumption of the semiconductor device 1 is suppressed. For example, when the semiconductor device 1 is mounted in a vehicle, the smaller the dark current of the logic circuit 10, the more the power consumption stored in the vehicle battery is suppressed.

[0041] Figure 2 is a waveform diagram showing the operation of the semiconductor device 1. In Figure 2 the scale of the logic circuit 10 is 2K gates when converted to a NAND gate, the frequency of the main clock signal supplied to the logic circuit 10 is 16 MHz, and the operation rate of the logic circuit 10 is assumed to be 50%. In this case, the average current consumption of the logic circuit 10 is shown as 1.4 mA, which is an improvement over the case of the logic circuit 51.

[0042] Specifically, if the gate charge-discharge current of the operation transistor provided in the logic circuit 10 is represented as I_sw, and the through current of the operation transistor provided in the logic circuit 10 is represented as I_leak, then the average current consumption of the logic circuit 10 (i.e., the dark current I_dark of the logic circuit 10) is represented by the following equation (1).

[0043] I_dark = I_sw + I_leak...(1)

[0044] In addition, if the frequency of the main clock signal supplied to the logic circuit 10 is represented as f, the gate capacitance of the operation transistors provided in the logic circuit 10 is represented as C, and the amplitude of the clock signal is represented as Vf, then the gate charge-discharge current I_sw is represented by the following equation (2).

[0045] I_sw = f x C x Vf...(2)

[0046] Here, if the power supply voltage VDD is represented as VDD, and the resistance values of the resistance elements R1 and R2 are represented as R1 and R2, then the amplitude of the clock signal Vf is represented by the following equation (3).

[0047] Vf = VDD - (I_dark x (R1 + R2))...(3)

[0048] If the threshold voltage of each transistor is represented as Vt, then by equation (3), equation (4) holds.

[0049] I_leak ∝ (Vf - Vt)^2...(4)

[0050] That is, the direct current I_leak is proportional to (Vf - Vt)^2.

[0051] For example, in the logic circuit 51 provided in the semiconductor device 50 shown in Figure 13 , the amplitude of the clock signal Vf is VDD = 3.3V, while in the logic circuit 10 provided in the semiconductor device 1 shown in Figure 1 , the amplitude of the clock signal Vf is VDD - (I_dark x (R1 + R2)) < 3.3V. That is, in the logic circuit 10 provided in the semiconductor device 1, compared with the case of the logic circuit 51 provided in the semiconductor device 50, the amplitude of the clock signal Vf is smaller, resulting in a smaller gate charge-discharge current I_sw and a smaller direct current I_leak, and thus the dark current I_dark is reduced. Designers and the like can effectively suppress the dark current I_dark of the logic circuit 10 provided in the semiconductor device 1 by previously understanding the maximum value of the dark current I_dark and, for example, adjusting the resistance values of the resistance elements R1 and R2 so that the amplitude Vf of the clock signal becomes smaller within the operable range of the logic circuit 10.

[0052] Therefore, the semiconductor device 1 according to the present embodiment includes a second power supply voltage line VDD2 connected to the first power supply voltage line VDD via a resistance element R1 and a second reference voltage line GND2 connected to the first reference voltage line GND via a resistance element R2. A logic circuit 10 and transistors MP1 and MN1 connected in series are provided therebetween. Therefore, the semiconductor device 1 according to the present embodiment can reduce the amplitude Vf of the clock signal supplied to the logic circuit 10 within the operable range of the logic circuit 10, thereby reducing the dark current of the logic circuit 10. In other words, the semiconductor device 1 according to the present embodiment can achieve low power consumption.

[0053] (Second Embodiment)

[0054] Figure 3 FIG. is a diagram showing a configuration example of a semiconductor device 2 according to the second embodiment.

[0055] As Figure 3 shown, compared with the semiconductor device 1, the semiconductor device 2 includes a logic circuit 20 instead of the logic circuit 10. The back gate of each P-channel MOS transistor provided in the logic circuit 20 is connected to the first power supply voltage line VDD instead of the second power supply voltage line VDD2. The back gate of each N-channel MOS transistor provided in the logic circuit 20 is connected to the first reference voltage line GND instead of the second reference voltage line GND2. Other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1, and thus the description thereof is omitted.

[0056] When simulation is performed under the same conditions as those of the semiconductor device 1, the average current consumption (dark current) of the logic circuit 20 is shown to be 679 μA, which is an improvement over the case of the logic circuit 10. This is because, as shown in the above equation (4), due to the back gate effect, the threshold voltage Vt of each transistor increases, resulting in a smaller leakage current I_leak.

[0057] Therefore, the semiconductor device 2 can achieve an effect equal to or greater than that of the semiconductor device 1.

[0058] In the present embodiment, as an example, the case where all the back gates of the P-channel MOS transistors in the logic circuit 20 are connected to the first power supply voltage line VDD and all the back gates of the N-channel MOS transistors are connected to the first reference voltage line GND is described, but it is not limited thereto. It is only necessary that at least some of the back gates of the P-channel MOS transistors in the logic circuit 20 are connected to the first power supply voltage line VDD and at least some of the back gates of the N-channel MOS transistors are connected to the first reference voltage line GND.

[0059] (Third Embodiment)

[0060] Figure 4This is a diagram showing a configuration example of the semiconductor system 3 according to the third embodiment. The semiconductor system 3 applies the configuration of the semiconductor device 1. The semiconductor system 3 is used, for example, in a keyless entry system installed in a vehicle.

[0061] Specifically, the semiconductor system 3 includes a semiconductor device 1a, a crystal oscillator 13, a capacitive element (first capacitive element) Cxi, and a capacitive element (second capacitive element) Cxo. In addition, in addition to the components of the semiconductor device 1, the semiconductor device 1a further includes a feedback resistor Rf, a buffer 11, and an inverter 12.

[0062] In the semiconductor device 1a, the gates of the transistors MP1 and MN1 are respectively connected to the external terminal XI, and the drains of the transistors MP1 and MN1 are respectively connected to the external terminal XO. Outside the semiconductor device 1a, the crystal oscillator 13 is provided between the external terminal XI and the external terminal XO of the semiconductor device 1a. That is, the crystal oscillator 13 is provided between the gates and the drains of the transistors MP1 and MN1 via the external terminals XI and XO of the semiconductor device 1a.

[0063] Outside the semiconductor device 1a, the capacitive element Cxi is provided between the external terminal XI of the semiconductor device 1a and the reference voltage terminal GND. Outside the semiconductor device 1a, the capacitive element Cxo is provided between the external terminal XO of the semiconductor device 1a and the reference voltage terminal GND.

[0064] In the semiconductor device 1a, the feedback resistor Rf is provided between the gates and the drains of the transistors MP1 and MN1. The buffer 11 is a so-called Schmitt buffer that drives and outputs the output signal of the drains of the transistors MP1 and MN1. The inverter 12 outputs the inverted signal of the output signal of the buffer 11. The output signal of the inverter 12 is supplied as a clock signal to the logic circuit 10.

[0065] Figure 5 This is a diagram showing the simulation results of the EYE opening (EYE pattern) in the semiconductor system of the comparative example. In the semiconductor system of the comparative example, compared with the semiconductor system 3, the resistance values of the resistance elements R1 and R2 are set to 0 Ω. Therefore, the power supply voltage VDD2 of the second power supply voltage line VDD2 indicates the same 3.3 V as the power supply voltage VDD. In addition, the power supply voltage GND2 of the second reference voltage line GND2 indicates the same 0 V as the reference voltage GND.

[0066] In Figure 5Among them, the oscillation frequency of the crystal oscillator 13 is 16 MHz. When converted to NAND gates, the scale of the logic circuit 10 is 40 K gates, the frequency of the main clock signal supplied to the logic circuit 10 is 16 MHz, and the operation rate of the logic circuit 10 is assumed to be 50%. In addition, in Figure 5 it is assumed that the amplitude of the external noise is 3.3 V ± 100 mV, and the frequency of the external noise is assumed to be 40 MHz.

[0067] In this case, the semiconductor system of the comparative example shows a jitter of 6.52 nsec / 100 mV.

[0068] Figure 6 is a diagram showing the simulation result of the EYE opening in the semiconductor system 3. In Figure 6 when the power supply voltage VDD of the first power supply voltage line VDD indicates 3.3 V, due to the voltage drop I_dark × R1, the power supply voltage VDD2 of the second power supply voltage line VDD2 indicates 2.7 V. Moreover, in Figure 6 when the reference voltage GND of the first reference voltage line GND indicates 0 V, due to the voltage rise I_dark × R2, the reference voltage GND2 of the second reference voltage line GND2 indicates 0.5 V.

[0069] In the semiconductor system 3, when simulation is performed under the same conditions as the comparative example semiconductor system, except for the resistance values of the resistance elements R1 and R2, the jitter shows 2.74 nsec / 100 mV. That is, in the semiconductor system 3, compared with the case of the comparative example semiconductor system, the jitter is suppressed to about 42%.

[0070] In recent years, in the automotive industry, IEC62132-4 (DPI method) has attracted attention as an EMC test for ICs (integrated circuits) standardized by the IEC (International Electrotechnical Commission) standard. In this DPI method, even if noise of about ±600 mV is superimposed on the 3.3 V power supply voltage VDD supplied to the local pin based on 50 Ω conversion, it is required that the IC does not malfunction. The local pin refers to a pin that is not connected to the outside of the ECU but is connected to a component including other ICs inside the ECU.

[0071] Here, there is a proportional relationship between the amount of noise superimposed on the power supply voltage VDD and the jitter. Therefore, in order to examine whether the comparative example semiconductor system meets the requirements of the DPI method, in Figure 5 the simulation conditions, when the amplitude of the external noise (i.e., the amount of noise superimposed on the power supply voltage VDD) is set to 3.3 V ± 600 mV, the jitter shows 39.12 nsec / 100 mV (= 6.52 x 6 nsec / 100 mV), and the EYE opening becomes narrow.

[0072] In contrast, in order to examine whether the semiconductor system 3 meets the requirements of the DPI method, under the simulation conditions of Figure 6 when the amplitude of the external noise (i.e., the amount of noise superimposed on the power supply voltage VDD) is set to 3.3V ± 600mV, the jitter shows 16.44 nsec / 100mV (= 2.74x6 nsec / 100mV), and the EYE opening is maintained in a wide state. That is, the semiconductor system 3 can maintain the EYE opening in a wide state without using external components such as an external low-pass filter. In other words, the semiconductor system 3 can achieve low jitter.

[0073] More specifically, the low jitter achieved by the semiconductor system 3 is explained. For example, when +100mV of noise is superimposed on the power supply voltage VDD, the power supply voltage VDD2 also instantaneously increases by ΔVDD. At this time, the gate-source voltage of each of the transistors MP1 and MN1 instantaneously increases, and current flows through the transistors MP1, MN1, and the resistance element R2, causing the reference voltage GND2 to also instantaneously increase by ΔGND. Therefore, even when noise appears, the potential difference between the power supply voltage VDD2 and the reference voltage GND2 remains almost constant. That is, the semiconductor system 3 can achieve low jitter because it is less affected by noise.

[0074] Therefore, the semiconductor system 3 having the configuration of the oscillating circuit applying the semiconductor device 1 can not only achieve low power consumption similar to that of the semiconductor device 1, but also maintain a wide EYE opening without using external components such as an external low-pass filter, thereby achieving low jitter.

[0075] (Fourth Embodiment)

[0076] Figure 7 FIG. is a diagram showing a configuration example of a semiconductor system 4 according to the fourth embodiment. Compared with the semiconductor system 3, the semiconductor system 4 includes a semiconductor device 1b instead of the semiconductor device 1a. The semiconductor device 1b includes pseudo-inductance circuits L1 and L2 instead of the resistance elements R1 and R2. The pseudo-inductance circuits L1 and L2 are configured to form pseudo-inductance circuits by using transistors or the like instead of coils. Therefore, the semiconductor device 1b can suppress an increase in circuit size more than when using coils. The other configurations of the semiconductor system 4 are the same as those of the semiconductor system 3, and thus their descriptions are omitted.

[0077] Figure 8 FIG. is a diagram showing a specific example of the configuration of the pseudo-inductance circuit L1. As Figure 8 shown, the pseudo-inductance circuit L1 includes transistors MU1 to MU4, a capacitor element CU1, and a resistance element RU1. The transistor MU1 is a P-channel MOS transistor, and the transistors MU2 to MU4 are N-channel MOS transistors.

[0078] In the transistor MU1, the source is connected to the first power supply voltage line VDD, and the drain is connected to the second power supply voltage line VDD2. The capacitive element CU1 is disposed between the gate of the transistor MU1 and the first reference voltage line GND. In the transistor MU2, the source is connected to the gate of the transistor MU1, the drain is connected to the first power supply voltage line VDD, and the gate is connected to the second power supply voltage line VDD2. In the transistor MU3, the source is connected to the first reference voltage line GND, and the drain is connected to the source of the transistor MU2. The resistive element RU1 is disposed between the first power supply voltage line VDD and the gate of the transistor MU3. In the transistor MU4, the source is connected to the first reference voltage line GND, and the drain and the gate are connected to the gate of the transistor MU3.

[0079] Figure 9 is a diagram showing a specific example of the configuration of the pseudo-inductive circuit L2. As Figure 9 shown, the pseudo-inductive circuit L2 includes transistors ML1 to ML4, a capacitive element CL1, and a resistive element RL1. The transistor ML1 is an N-channel MOS transistor, and the transistors ML2 to ML4 are P-channel MOS transistors.

[0080] In the transistor ML1, the source is connected to the first reference voltage line GND, and the drain is connected to the second reference voltage line GND2. The capacitive element CL1 is disposed between the gate of the transistor ML1 and the first power supply voltage line VDD. In the transistor ML2, the source is connected to the gate of the transistor ML1, the drain is connected to the first reference voltage line GND, and the gate is connected to the second reference voltage line GND2. In the transistor ML3, the source is connected to the first power supply voltage line VDD, and the drain is connected to the source of the transistor ML2. The resistive element RL1 is disposed between the first reference voltage line GND and the gate of the transistor ML3. In the transistor ML4, the source is connected to the first power supply voltage line VDD, and the drain and the gate are connected to the gate of the transistor ML3.

[0081] Figure 10 is a diagram showing the simulation result of the EYE opening in the semiconductor system 4. When the simulation is performed under the same conditions as those in the semiconductor system 3 in the semiconductor system 4, the jitter shows 1.03 nsec / 100 mV. That is, in the semiconductor system 4, the jitter is further suppressed compared to the semiconductor system 3.

[0082] In addition, in order to examine whether the semiconductor system 4 meets the requirements of the DPI method, in Figure 10In the simulation conditions, when the amplitude of the noise superimposed on the power supply voltage VDD (i.e., the amplitude of the external noise) is set to 3.3V ± 600mV, the jitter shows 6.18nsec / 100mV (= 1.03x6nsec / 100mV), and the EYE opening is maintained in a wide state. That is, compared with the semiconductor system 3, the semiconductor system 4 can maintain the EYE opening in a wider state. In other words, compared with the semiconductor system 3, the semiconductor system 4 can further reduce the jitter.

[0083] Figure 11 is a diagram showing the AC analysis results of the semiconductor system 4 when noise is applied to the power supply voltage VDD. In Figure 11 it, the vertical axis represents 20Log(GND2 / VDD2), and the horizontal axis represents the frequency in logarithmic notation. As Figure 11 shown, in the semiconductor system 4, since the pseudo-inductance circuits L1 and L2 are provided instead of the resistance elements R1 and R2, for frequencies above 10MHz, the followability of the reference voltage GND2 to the power supply voltage VDD2 is improved. Therefore, compared with the semiconductor system 3, the semiconductor system 4 can further reduce the jitter.

[0084] In this embodiment, as an example, the case where the semiconductor system 4 is equipped with the pseudo-inductance circuits L1 and L2 instead of the resistance elements R1 and R2 is described, but it is not limited thereto. As Figure 12 shown, the semiconductor system 4 can be equipped with impedance elements Z1 and Z2 that can achieve functions equivalent to those of the resistance elements R1 and R2 or the pseudo-inductance circuits L1 and L2.

[0085] Figure 12 is a diagram showing a modified example of the semiconductor system 4 as the semiconductor system 4a. Compared with the semiconductor system 4, the semiconductor system 4a is equipped with the semiconductor device 1c instead of the semiconductor device 1b. The semiconductor device 1c is equipped with the impedance elements Z1 and Z2 instead of the resistance elements R1 and R2. The other configurations of the semiconductor system 4a are the same as those of the semiconductor system 4, so their descriptions are omitted.

[0086] As described above, the semiconductor device according to the present disclosure includes a second power supply voltage line VDD2 connected to the first power supply voltage line VDD via a resistance element R1 and a second reference voltage line GND2 connected to the first reference voltage line GND via a resistance element R2, and a logic circuit and transistors MP1 and MN1 connected in series therebetween. Therefore, the semiconductor device according to the present disclosure can reduce the amplitude Vf of the clock signal supplied to the logic circuit within the operating range of the logic circuit, thereby reducing the dark current of the logic circuit. In other words, the semiconductor device according to the present disclosure can achieve low power consumption.

[0087] In addition, a semiconductor system having an oscillation circuit configured with the semiconductor device disclosed herein can not only achieve low power consumption, but also maintain a wide EYE opening without using external components such as an external low-pass filter, thereby achieving low jitter.

[0088] Although the present invention made by the present inventor has been specifically described based on embodiments, the present invention is not limited to the described embodiments, and needless to say, various modifications can be made without departing from its gist.

[0089] For example, in the present disclosure, the case where the semiconductor device 1 includes the resistance elements R1 and R2 is described as an example, but is not limited thereto. The semiconductor device 1 can be appropriately modified to a configuration including impedance elements Z1 and Z2 (such as pseudo-inductance circuits L1 and L2) instead of the resistance elements R1 and R2. Similarly, in the present disclosure, the case where the semiconductor device 2 includes the resistance elements R1 and R2 is described as an example, but is not limited thereto. The semiconductor device 2 can be appropriately modified to a configuration including impedance elements Z1 and Z2 (such as pseudo-inductance circuits L1 and L2) instead of the resistance elements R1 and R2.

[0090] Moreover, in the present disclosure, the case where the semiconductor system 3 includes the semiconductor device 1 is described as an example, but is not limited thereto. The semiconductor system 3 can be appropriately modified to a configuration including the semiconductor device 2 instead of the semiconductor device 1. In other words, the semiconductor system 3 can be appropriately modified to a configuration including the logic circuit 20 instead of the logic circuit 10. Similarly, in the present disclosure, the case where the semiconductor system 4 includes the semiconductor device 1 is described as an example, but is not limited thereto. The semiconductor system 4 can be appropriately modified to a configuration including the semiconductor device 2 instead of the semiconductor device 1. In other words, the semiconductor system 4 can be appropriately modified to a configuration including the logic circuit 20 instead of the logic circuit 10.

[0091] In addition, the present disclosure can be implemented by executing a computer program on a CPU to execute some or all of the processes of a semiconductor system including the semiconductor device 1, the semiconductor device 2, or any one of them.

[0092] When loaded into a computer, the above program includes a set of instructions (or software code) for causing the computer to perform one or more functions described in the embodiments. The program can be stored on a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the non-transitory computer-readable medium or tangible storage medium can include RAM (Random Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid State Drive) or other memory technologies, CD-ROM, DVD (Digital Versatile Disc), Blu-ray (registered trademark) disc or other optical disc storage devices, magnetic tape cartridges, tapes, magnetic disk storage devices or other magnetic storage devices. The program can also be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or communication medium can include electrical, optical, acoustic or other forms of propagated signals.

Claims

1. A semiconductor device, comprising: a first power supply voltage line supplied with a power supply voltage; a second power supply voltage line; A first impedance element is arranged between the first power supply voltage line and the second power supply voltage line; a first reference voltage line supplied with a reference voltage; a second reference voltage line; A second impedance element is arranged between the first reference voltage line and the second reference voltage line; an electronic circuit disposed between the second power supply voltage line and the second reference voltage line and configured to perform predetermined processing on an input signal; as well as A first transistor being a P-channel MOS transistor and a second transistor being an N-channel MOS transistor, both of which are arranged in series between the second power supply voltage line and the second reference voltage line, and each of the first transistor and the second transistor has a gate connected to its respective drain in the semiconductor device.

2. The semiconductor device according to claim 1, The first impedance element and the second impedance element are both resistance elements.

3. The semiconductor device according to claim 1, The first impedance element is composed of a first pseudo-inductor circuit, The first pseudo-inductor circuit comprises: A first upper transistor as a P-channel MOS transistor, disposed between the first power supply voltage line and the second power supply voltage line; A first upper capacitor element is provided between the gate of the first upper transistor and the first reference voltage line; A second upper transistor as an N-channel MOS transistor, provided between the first power supply voltage line and the gate of the first upper transistor, the gate of the second upper transistor being connected to the second power supply voltage line; a third upper transistor as an N-channel MOS transistor, disposed between the source of the second upper transistor and the first reference voltage line; A first upper resistance element is provided between the first power supply voltage line and the gate of the third upper transistor; a fourth upper transistor as an N-channel MOS transistor, disposed between the gate of the third upper transistor and the first reference voltage line, the gate of the fourth upper transistor being connected to the gate of the third upper transistor; and The second impedance element is constituted by a second pseudo inductor circuit, and the second pseudo inductor circuit includes: a first lower transistor as an N-channel MOS transistor, which is arranged between the first reference voltage line and the second reference voltage line; a first lower capacitor element provided between the gate of the first lower transistor and the first power supply voltage line; a second lower transistor as a P-channel MOS transistor, disposed between the first reference voltage line and the gate of the first lower transistor, the gate of the second lower transistor being connected to the second reference voltage line; a third lower transistor as a P-channel MOS transistor, disposed between the source of the second lower transistor and the first power supply voltage line; A first lower resistance element is provided between the first reference voltage line and the gate of the third lower transistor; A fourth low-side transistor, which is a P-channel MOS transistor, is provided between the gate of the third low-side transistor and the first power supply voltage line, and the gate of the fourth low-side transistor is connected to the gate of the third low-side transistor.

4. The semiconductor device according to claim 1, wherein in the first transistor, the source and back gate are connected to the second power supply voltage line, and the gate and drain are connected to the gate and drain of the second transistor; In the second transistor, the source and the back gate are connected to the second reference voltage line.

5. The semiconductor device according to claim 1, The back gate of each P-channel MOS transistor provided in the electronic circuit is connected to the second power supply voltage line, and the back gate of each N-channel MOS transistor provided in the electronic circuit is connected to the second reference voltage line.

6. The semiconductor device according to claim 1, The back gates of some of the multiple P-channel MOS transistors arranged in the electronic circuit are connected to the first power supply voltage line, and the back gates of some of the multiple N-channel MOS transistors arranged in the electronic circuit are connected to the first reference voltage line.

7. The semiconductor device according to claim 1, The back gates of all the plurality of P-channel MOS transistors provided in the electronic circuit are connected to the first power supply voltage line, and the back gates of all the plurality of N-channel MOS transistors provided in the electronic circuit are connected to the first reference voltage line.

8. A semiconductor system comprising: The semiconductor device according to claim 1; a crystal oscillator disposed between the gate and the drain of both the first transistor and the second transistor; and A first capacitance element and a second capacitance element are provided between both ends of the crystal oscillator and a reference voltage terminal; The semiconductor device further includes a feedback resistor arranged in parallel with the crystal oscillator, a buffer driving and outputting the output signal of the drains of both the first transistor and the second transistor, and an inverter outputting the inverted signal of the output signal of the buffer as a clock signal supplied to the electronic circuit.

9. The semiconductor system according to claim 8, The buffer is a Schmitt buffer. 10 . The semiconductor system according to claim 8 , applied to a keyless entry system mounted on a vehicle.

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