Transmitter circuit, electronic control unit, and vehicle

Abstract

This transmission circuit comprises: a first terminal configured so that a first voltage is applied; a second terminal; a third terminal; and a fourth terminal configured so that a second voltage lower than the first voltage is applied. The transmission circuit further comprises: a first variable resistance unit provided between the first terminal and the second terminal and configured so as to vary a resistance value; a first current-limiting unit provided between the first terminal and the second terminal and configured so as to limit the current flowing from the first terminal to the second terminal; a second variable resistance unit provided between the third terminal and the fourth terminal and configured so as to vary a resistance value; a second current-limiting unit provided between the third terminal and the fourth terminal and configured so as to limit the current flowing from the third terminal to the fourth terminal; and a control unit configured so as to control the resistance values of the first variable resistance unit and the second variable resistance unit on the basis of transmission data.

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a transmission circuit that transmits a differential signal, and an electronic control unit and a vehicle that include the transmission circuit. [Background technology]

[0002] Vehicles such as automobiles are equipped with a large number of electronic control units (ECUs). For example, CAN (Controller Area Network) communication is used for communication between the large number of ECUs (see, for example, Patent Document 1).

[0003] The transmit signal and receive signal in CAN communication are both differential signals. The differential signal, which is composed of the first signal and the second signal, can be decomposed into a common mode component and a differential mode component. The common mode component is the average of the first signal and the second signal, and the differential mode component is the difference between the first signal and the second signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 61-195453 Summary of the Invention [Problem to be solved by the invention]

[0005] When the symmetry between the first and second signals constituting a differential signal is lost, noise occurs in the common mode component. The noise occurring in the common mode component (common mode noise) deteriorates EMC (Electromagnetic Compatibility) characteristics. Therefore, suppressing common mode noise is an issue in transceiver circuits that include a transmitting circuit that transmits differential signals and a receiving circuit that receives differential signals.

[0006] Furthermore, even if a circuit capable of suppressing common-mode noise can be provided in a transceiver circuit that transmits and receives differential signals, if an overcurrent flows through the circuit capable of suppressing common-mode noise, new problems may arise, such as excessive power consumption in the circuit capable of suppressing common-mode noise or failure of the circuit capable of suppressing common-mode noise. [Means for solving the problem]

[0007] The transmission circuit disclosed in this specification includes a first terminal configured to receive a first voltage, a second terminal, a third terminal, a fourth terminal configured to receive a second voltage lower than the first voltage, a first variable resistance unit provided between the first terminal and the second terminal and configured to vary a resistance value, a first current limiting unit provided between the first terminal and the second terminal and configured to limit a current flowing from the first terminal to the second terminal, a second variable resistance unit provided between the third terminal and the fourth terminal and configured to vary a resistance value, a second current limiting unit provided between the third terminal and the fourth terminal and configured to limit a current flowing from the third terminal to the fourth terminal, and a control unit configured to control the resistance values ​​of the first variable resistance unit and the second variable resistance unit based on transmission data.

[0008] The electronic control unit disclosed in this specification is configured to include the transmission circuit configured as described above, and a computer that sends the transmission data to the transmission circuit.

[0009] The vehicle disclosed in this specification is configured to include a communication bus and a plurality of electronic control units of the above configuration connected to the communication bus. Effect of the Invention

[0010] According to the invention disclosed in this specification, it is possible to provide a transmission circuit that suppresses common-mode noise and overcurrent. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is an external view of a vehicle according to an embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a CAN communication system. [Diagram 3] FIG. 3 is a diagram illustrating an example of the configuration of the ECU. [Figure 4] FIG. 4 is a diagram illustrating an example of a configuration of a transceiver circuit. [Diagram 5] FIG. 5 is a time chart showing a differential signal. [Figure 6] FIG. 6 is a diagram illustrating an example of a configuration of the first variable resistance section. [Figure 7] FIG. 7 is a diagram illustrating an example of a configuration of the second variable resistance section. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In this specification, a MOS transistor refers to a transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOS transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0013] In this specification, a constant current means a current that is constant under ideal conditions, but in reality may fluctuate slightly due to temperature changes and the like.

[0014] In this specification, a constant voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0015] <Vehicle and CAN communication system> 1 is an external view of a vehicle X according to an embodiment. The vehicle X includes a plurality of ECUs 1 (not shown in FIG. 1). The vehicle X also includes a battery (not shown).

[0016] Fig. 2 is a schematic diagram of a CAN communication system provided in a vehicle X. The CAN communication system shown in Fig. 2 includes a plurality of ECUs 1, a first bus line BL1, a second bus line BL2, and resistors R101 and R102.

[0017] One end of a resistor R101 is connected to one end of a first bus line BL1, and one end of a resistor R102 is connected to the other end of the first bus line BL1. The other end of the resistor R101 is connected to one end of a second bus line BL2, and the other end of the resistor R102 is connected to the other end of the second bus line BL2. Each of the multiple ECUs 1 is connected to the first bus line BL1 and the second bus line BL2. A voltage VBAT output from a battery is supplied to each of the multiple ECUs 1. Each of the multiple ECUs 1 is connected to a ground potential. The multiple ECUs 1 use the voltage VBAT as a power supply voltage.

[0018] <ecu> 3 is a diagram showing an example of the configuration of the ECU 1. The ECU 1 of the example configuration shown in FIG.

[0019] A voltage VBAT is supplied to the terminal T1. The anode of the diode 5 is connected to the terminal T1. The cathode of the diode 5 is connected to the input terminal of the power supply circuit 2 and the capacitor 6.

[0020] The output terminal of the power supply circuit 2 is connected to the power supply voltage input terminal of the microcomputer 3, a terminal VCC of the transceiver circuit 4, and one end of a capacitor 7. A constant voltage is output from the output terminal of the power supply circuit 2.

[0021] The microcomputer 3 sends transmission data to a terminal TXD of the transceiver circuit 4, and receives reception data from a terminal RXD of the transceiver circuit 4. The transmission data and reception data are each a single signal.

[0022] The terminal CANH of the transceiver circuit 4 is connected to the terminal T2, and the terminal CANL of the transceiver circuit 4 is connected to the terminal T3. The terminal T2 is connected to the first bus line BL1 shown in FIG. 2, and the terminal T3 is connected to the second bus line BL2 shown in FIG.

[0023] The transceiver circuit 4 converts transmission data into a differential signal (CAN signal) composed of a first signal SCANH (see FIG. 5 described later) and a second signal SCANL (see FIG. 5 described later) and outputs the converted data. The transceiver circuit 4 also converts the differential signal (CAN signal) composed of the first signal and the second signal into reception data and outputs the reception data. That is, the transceiver circuit 4 includes a transmission circuit that transmits the differential signal and a reception circuit that receives the differential signal. The first signal is transmitted by the first bus line BL1, and the second signal is transmitted by the second bus line BL2.

[0024] The ground terminal of the power supply circuit 2 is connected to the other end of the capacitor 6, the terminal T4, the terminal GND of the transceiver circuit 4, the ground terminal of the microcomputer 3, and the other end of the capacitor 7. The terminal T4 is connected to the ground potential.

[0025] <Transceiver circuit> Fig. 4 is a diagram showing an example of the configuration of the transceiver circuit 4. The transceiver circuit 4 of the example configuration shown in Fig. 4 includes a terminal VCC, a terminal GND, a terminal TXD, a terminal RXD, a terminal CANH, and a terminal CANL.

[0026] The transceiver circuit 4 of the configuration example shown in FIG. 4 further includes a first variable resistance unit VR1, a second variable resistance unit VR2, a P-channel MOS transistor (PMOS transistor) Q1 which is a first current limiting unit, an N-channel MOS transistor (NMOS transistor) Q7 which is a second current limiting unit, and a control unit CNT1.

[0027] The transceiver circuit 4 of the configuration example shown in FIG. 4 further includes a pull-up resistor R1, a pull-down resistor R2, diodes D1 and D3 for preventing reverse current, and a PMOS transistor Q2 and an NMOS transistor Q6 which are clamp elements.

[0028] The pull-up resistor R1 stabilizes the potential of the node N1 (the connection point between the first variable resistance section VR1 and the diode D1) when the first variable resistance section VR1 is in a high impedance state. The pull-down resistor R2 stabilizes the potential of the node N2 (the connection point between the second variable resistance section VR2 and the NMOS transistor Q6) when the second variable resistance section VR2 is in a high impedance state.

[0029] The PMOS transistor Q2 and the NMOS transistor Q6 are double-diffused MOS transistors with a high breakdown voltage. The PMOS transistor Q2 clamps the source potential of the PMOS transistor Q2, and the NMOS transistor Q6 clamps the source potential of the NMOS transistor Q6.

[0030] The transceiver circuit 4 of the configuration example shown in FIG. 4 includes a receiver circuit RCV1, a diode D2, a PMOS transistor Q3, an NMOS transistor Q4, an NMOS transistor Q5, and a Zener diode ZD1.

[0031] The terminal VCC is connected to the source of the PMOS transistor Q1 and one end of the pull-up resistor R1. A bias voltage Vbp, which is a constant voltage, is supplied to the gate of the PMOS transistor Q1. Therefore, the PMOS transistor Q1 serves as a constant current source. If the terminal CANH is short-circuited to a voltage equal to or lower than the voltage applied to the terminal GND, the PMOS transistor Q1 limits the current flowing from the terminal VCC to the terminal CANH. This makes it possible to suppress overcurrent flowing from the terminal VCC to the terminal CANH.

[0032] The drain of the PMOS transistor Q1 is connected to one end of a first variable resistance section VR1, the other end of which is connected to the other end of the pull-up resistor R1 and the anode of the diode D1.

[0033] The cathode of the diode D1 is connected to the source of a PMOS transistor Q2, the drain of which is connected to the terminal CANH and to a first input terminal of the receiver circuit RCV1.

[0034] A gate drive signal generating circuit composed of a PMOS transistor Q3, an NMOS transistor Q4, an NMOS transistor Q5, a diode D2, and a Zener diode ZD1 generates a gate drive signal for the PMOS transistor Q2. An internal voltage VREG1 generated inside the transceiver circuit 4 is applied to the source of the PMOS transistor Q3. The drain of the PMOS transistor Q3 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the anode of the Zener diode ZD1 and the drain of the NMOS transistor Q4. The cathode of the Zener diode ZD1 is connected to the source of the PMOS transistor Q1. An enable signal EN is supplied to each gate of the PMOS transistor Q3 and the NMOS transistor Q4. When the enable signal EN is at a high level, the transceiver circuit 4 is enabled. On the other hand, when the enable signal EN is at a low level, the transceiver circuit 4 is disabled. The source of the NMOS transistor Q4 is connected to the drain of the NMOS transistor Q5. The source of the NMOS transistor Q5 is connected to the ground potential. A bias voltage Vbn1, which is a constant voltage, is supplied to the gate of the NMOS transistor Q5.

[0035] The anode of the diode D3 is connected to the terminal CANL and the second input terminal of the receiver circuit RCV1. The cathode of the diode D3 is connected to the drain of the NMOS transistor Q6. The source of the NMOS transistor Q6 is connected to one end of the second variable resistance section VR2 and one end of the pull-down resistor R2. An enable signal EN is supplied to the gate of the NMOS transistor Q6.

[0036] The other end of the second variable resistor section VR2 is connected to the drain of an NMOS transistor Q7. The source of the NMOS transistor Q7 is connected to the other end of the pull-down resistor R2 and the terminal GND. A bias voltage Vbp2, which is a constant voltage, is supplied to the gate of the NMOS transistor Q7. Therefore, the NMOS transistor Q7 serves as a constant current source. If the terminal CANL is short-circuited to a voltage equal to or higher than the voltage supplied to the terminal VCC, the NMOS transistor Q7 limits the current flowing from the terminal CANL to the terminal GND. This makes it possible to suppress overcurrent flowing from the terminal CANL to the terminal GND.

[0037] The control unit CNT1 receives transmission data supplied to a terminal TXD, and controls the resistance values ​​of the first variable resistance unit VR1 and the second variable resistance unit VR2 based on the transmission data.

[0038] The above-mentioned first signal SCANH is a binary signal of V1 and (V1+V2) as shown in Fig. 5, and the above-mentioned second signal SCANL is a binary signal of V1 and (V1-V2) as shown in Fig. 5. A differential signal (CAN signal) constituted by the first signal SCANH and the second signal SCANL can be decomposed into a common mode component COM which is the average of the first signal SCANH and the second signal SCANL, and a differential mode component DIFF which is the difference between the first signal SCANH and the second signal SCANL.

[0039] When a time difference (skew) occurs between the first signal SCANH and the second signal SCANL, noise occurs in the common mode component COM. However, by making the first signal SCANH and the second signal SCANL signals with waveforms that have small high-frequency components, it is possible to suppress the common mode noise caused by the skew.

[0040] 4, the resistance value of the first variable resistance unit VR1 is gradually decreased in a first transition period in which the voltage value of the first signal SCANH transitions from V1 to (V1+V2) and in a second transition period in which the voltage value of the second signal SCANL transitions from V1 to (V1-V2), and the resistance value of the first variable resistance unit VR1 is gradually increased in a third transition period in which the voltage value of the first signal SCANH transitions from (V1+V2) to V1 and in a fourth transition period in which the voltage value of the second signal SCANL transitions from (V1-V2) to V1, making the first signal SCANH and the second signal SCANL signals with waveforms with small high-frequency components. In addition, in periods other than the above-mentioned transition periods, the control unit CNT1 sets the resistance value of the first variable resistance unit VR1 to a maximum value.

[0041] Similarly, in the transceiver circuit 4 of the configuration example shown in Fig. 4, the resistance value of the second variable resistance unit VR2 is gradually decreased in a first transition period in which the voltage value of the first signal SCANH transitions from V1 to (V1+V2) and in a second transition period in which the voltage value of the second signal SCANL transitions from V1 to (V1-V2), and the resistance value of the second variable resistance unit VR2 is gradually increased in a third transition period in which the voltage value of the first signal SCANH transitions from (V1+V2) to V1 and in a fourth transition period in which the voltage value of the second signal SCANL transitions from (V1-V2) to V1, making the first signal SCANH and the second signal SCANL signals with waveforms with small high-frequency components. Note that, except for the above-mentioned transition periods, the control unit CNT1 sets the resistance value of the second variable resistance unit VR2 to a maximum value.

[0042] FIG. 6 is a diagram showing an example of the configuration of the first variable resistance section VR1, and FIG. 7 is a diagram showing an example of the configuration of the second variable resistance section VR2.

[0043] The first variable resistance unit VR1 in the configuration example shown in Fig. 6 includes PMOS transistors M1-M60, which are switches, and resistors Z1-Z60, and is a circuit in which 60 series circuits of resistors and switches are connected in parallel. The PMOS transistors M1-M60 are controlled to be turned on / off by control signals S1-S60 output from the control unit CNT1. The number of the series circuits may be any number other than 60. In the configuration example shown in Fig. 6, the resistance value of the first variable resistance unit VR1 is determined by the combined resistance of the resistors Z1-Z60, so that the resistance value of the first variable resistance unit VR1 can be controlled with high precision.

[0044] The second variable resistance unit VR2 in the configuration example shown in Fig. 7 includes NMOS transistors M101-M160, which are switches, and resistors Z101-Z160, and is a circuit in which 60 series circuits of resistors and switches are connected in parallel. The NMOS transistors M101-M160 are controlled to be turned on / off by control signals S101-S160 output from the control unit CNT1. The number of the series circuits may be any number other than 60. In the configuration example shown in Fig. 7, the resistance value of the second variable resistance unit VR2 is determined by the combined resistance of the resistors Z101-Z160, so that the resistance value of the second variable resistance unit VR2 can be controlled with high precision.

[0045] <Points to note> In addition to the above-described embodiment, the configuration of the present invention can be modified in various ways without departing from the spirit of the invention. The above-described embodiment is illustrative in all respects and should be considered as not limiting, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0046] For example, in the above embodiment, the communication performed by the transceiver circuit is CAN communication, but the communication performed by the transceiver circuit may be communication other than CAN communication.

[0047] Furthermore, for example, each of the first variable resistance unit VR1 and the second variable resistance unit VR2 may be configured with a transistor, and the on-resistance of the transistor may be adjusted by a control signal supplied to a control terminal of the transistor.

[0048] Also, for example, a resistor may be used as the first current limiting section instead of a constant current source. It is desirable that the resistance value of the resistor used as the first current limiting section is smaller than the minimum resistance value of the first variable resistance section VR1. This makes it possible to suppress the influence of the resistor used as the first current limiting section on each waveform of the first signal SCANH and the second signal SCANL. Similarly, a resistor may be used as the second current limiting section instead of a constant current source. It is desirable that the resistance value of the resistor used as the second current limiting section is smaller than the minimum resistance value of the second variable resistance section VR2. This makes it possible to suppress the influence of the resistor used as the second current limiting section on each waveform of the first signal SCANH and the second signal SCANL.

[0049] The transmission circuit (4) described above has a configuration (first configuration) including a first terminal (VCC) configured to receive a first voltage, a second terminal (CANH), a third terminal (CANL), a fourth terminal (GND) configured to receive a second voltage lower than the first voltage, a first variable resistance unit (VR1) provided between the first terminal and the second terminal and configured to vary a resistance value, a first current limiting unit (Q1) provided between the first terminal and the second terminal and configured to limit a current flowing from the first terminal to the second terminal, a second variable resistance unit (VR2) provided between the third terminal and the fourth terminal and configured to vary a resistance value, a second current limiting unit (Q7) provided between the third terminal and the fourth terminal and configured to limit a current flowing from the third terminal to the fourth terminal, and a control unit (CNT1) configured to control the resistance values ​​of the first variable resistance unit and the second variable resistance unit based on transmission data.

[0050] The transmission circuit of the first configuration can suppress an overcurrent flowing from the first terminal to the second terminal by the first current limiting unit. Also, the transmission circuit of the first configuration can suppress an overcurrent flowing from the third terminal to the fourth terminal by the second current limiting unit. Furthermore, the transmission circuit of the first configuration can suppress common mode noise caused by skew by controlling the resistance values ​​of the first variable resistance unit and the second variable resistance unit by the control unit.

[0051] In the transmission circuit of the above first configuration, a configuration (second configuration) may be used in which, when a resistance value between the second terminal and the third terminal is smaller than normal, the first current limiting unit limits the current flowing from the first terminal to the second terminal, and the second current limiting unit limits the current flowing from the third terminal to the fourth terminal, when a voltage between the first terminal and the second terminal is larger than normal, the first current limiting unit limits the current flowing from the first terminal to the second terminal, and when a voltage between the third terminal and the fourth terminal is larger than normal, the second current limiting unit limits the current flowing from the third terminal to the fourth terminal.

[0052] The transmission circuit of the second configuration described above can appropriately suppress overcurrent by the first current limiting section and the second current limiting section.

[0053] In the transmission circuit of the above-mentioned second configuration, when the second terminal and the third terminal are short-circuited, the first current limiting unit limits the current flowing from the first terminal to the second terminal, and the second current limiting unit limits the current flowing from the third terminal to the fourth terminal; when the second terminal and the fourth terminal are short-circuited, the first current limiting unit limits the current flowing from the first terminal to the second terminal; and when the first terminal and the third terminal are short-circuited, the second current limiting unit limits the current flowing from the third terminal to the fourth terminal (third configuration).

[0054] The transmission circuit of the third configuration described above can appropriately suppress more serious overcurrents by the first current limiting section and the second current limiting section.

[0055] In the transmission circuit of any of the above first to third configurations, the first variable resistance section and the second variable resistance section may each be configured as a circuit in which a plurality of series circuits of a resistor and a switch are connected in parallel (fourth configuration).

[0056] The transmission circuit of the fourth configuration described above can control the resistance values ​​of the first variable resistance section and the second variable resistance section with high precision.

[0057] In the transmission circuit of any one of the above first to fourth configurations, the first current limiting section and the second current limiting section may each be a constant current source (fifth configuration).

[0058] The transmission circuit of the fifth configuration described above can suppress the influence of the first current limiting section and the second current limiting section on the waveforms of the signals output from the second terminal and the third terminal.

[0059] In the transmission circuit of the above-mentioned fifth configuration, the first current limiting section may be a P-channel MOS transistor provided between the first terminal and the first variable resistance section and having a gate to which a first constant voltage is applied, and the second current limiting section may be an N-channel MOS transistor provided between the second variable resistance section and the fourth terminal and having a gate to which a second constant voltage lower than the first constant voltage is applied (sixth configuration).

[0060] In the transmission circuit of the sixth configuration, the first current limiting section and the second current limiting section have simple configurations, so that it is possible to achieve size reduction and cost reduction.

[0061] In the transmission circuit of any one of the first to sixth configurations, a pull-up resistor and a pull-down resistor are provided, and one end of the pull-up resistor is connected to the first terminal. child the other end of the pull-up resistor is connected to one end of the first variable resistor section that is closer to the second terminal, one end of the pull-down resistor is connected to one end of the second variable resistor section that is closer to the third terminal, and the other end of the pull-down resistor is connected to the fourth terminal child The seventh configuration may be such that the signal is connected to the

[0062] The transmission circuit of the seventh configuration can stabilize the potential of the second terminal side end of the first variable resistance unit by the pull-up resistor when the first variable resistance unit is in a high impedance state. Also, the transmission circuit of the seventh configuration can stabilize the potential of the third terminal side end of the second variable resistance unit by the pull-down resistor when the second variable resistance unit is in a high impedance state.

[0063] The electronic control unit (1) described above has a configuration (eighth configuration) including a transmission circuit of any one of the first to seventh configurations and a computer (3) that sends the transmission data to the transmission circuit.

[0064] The electronic control unit of the eighth configuration can suppress common mode noise and overcurrent in the transmission circuit.

[0065] The vehicle (X) described above has a configuration (ninth configuration) including communication buses (BL1, BL2) and a plurality of electronic control units of the eighth configuration connected to the communication buses.

[0066] The vehicle having the ninth configuration described above can suppress common mode noise and overcurrent in the transmission circuit. [Explanation of symbols]

[0067] 1 ECU 2 Power circuit 3. Microcomputer 4 Transceiver Circuit 5. D1~D3 Diodes 6, 7 Capacitor CNT1 control unit BL1 1st Bus Line BL2 2nd Bus Line M1~M60 PMOS transistors M101~M160 NMOS transistors Q1 PMOS transistor (an example of the first current limiter) Q7 NMOS transistor (an example of the second current limiter) Q3 PMOS transistor Q4~Q6 NMOS transistors R1 Pull-up resistor R2 Pull-down resistor R101, R102, Z1~Z60, Z101~Z160 Resistor RCV1 Receiver circuit T1~T4, VCC, GND, TXD, RXD, CANH, CANL terminal VR1 First variable resistor VR2 Second variable resistor X Vehicle ZD1 Zener diode< / ecu>

Claims

1. a first terminal configured to receive a first voltage; A second terminal; A third terminal; a fourth terminal configured to receive a second voltage lower than the first voltage; a first variable resistance unit provided between the first terminal and the second terminal and configured to vary a resistance value; A first current limiting unit provided between the first terminal and the second terminal and configured to limit a current flowing from the first terminal to the second terminal; a second variable resistance unit provided between the third terminal and the fourth terminal and configured to vary a resistance value; A second current limiting unit provided between the third terminal and the fourth terminal and configured to limit a current flowing from the third terminal to the fourth terminal; a control unit configured to control the resistance values ​​of the first variable resistance unit and the second variable resistance unit based on transmission data; A transmission circuit comprising:

2. when a resistance value between the second terminal and the third terminal is smaller than a normal state, the first current limiting unit limits a current flowing from the first terminal to the second terminal, and the second current limiting unit limits a current flowing from the third terminal to the fourth terminal; When a voltage between the first terminal and the second terminal is higher than a normal voltage, the first current limiting unit limits a current flowing from the first terminal to the second terminal; The transmission circuit according to claim 1 , wherein when a voltage between the third terminal and the fourth terminal is higher than normal, the second current limiting unit limits the current flowing from the third terminal to the fourth terminal.

3. When the second terminal and the third terminal are short-circuited, the first current limiting unit limits the current flowing from the first terminal to the second terminal, and the second current limiting unit limits the current flowing from the third terminal to the fourth terminal, When the second terminal and the fourth terminal are short-circuited, the first current limiting unit limits a current flowing from the first terminal to the second terminal; The transmission circuit according to claim 2 , wherein when the first terminal and the third terminal are short-circuited, the second current limiting unit limits the current flowing from the third terminal to the fourth terminal.

4. 4. The transmission circuit according to claim 1, wherein the first variable resistance section and the second variable resistance section are each a circuit in which a plurality of series circuits of a resistor and a switch are connected in parallel.

5. 5. The transmission circuit according to claim 1, wherein the first current limiting section and the second current limiting section are each a constant current source.

6. the first current limiting unit is a P-channel MOS transistor provided between the first terminal and the first variable resistance unit and having a gate to which a first constant voltage is applied, 6. The transmission circuit according to claim 5, wherein the second current limiting section is an N-channel MOS transistor provided between the second variable resistance section and the fourth terminal and having a gate to which a second constant voltage lower than the first constant voltage is applied.

7. A pull-up resistor and a pull-down resistor are provided, one end of the pull-up resistor is connected to the first terminal, the other end of the pull-up resistor is connected to one end of the first variable resistor section that is closer to the second terminal; one end of the pull-down resistor is connected to one end of the second variable resistor section that is closer to the third terminal, 7. The transmission circuit according to claim 1, wherein the other end of the pull-down resistor is connected to the fourth terminal.

8. A transmission circuit according to any one of claims 1 to 7; a computer that sends the transmission data to the transmission circuit.

9. A communication bus; A plurality of electronic control units according to claim 8 connected to the communication bus; A vehicle comprising:

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