PIXEL DRIVE CIRCUIT, PIXEL DRIVE METHOD, AND DISPLAY PANEL

Abstract

This application discloses a pixel driving circuit, a pixel driving method and a display panel, the pixel driving circuit includes a first thin film transistor (M1), a second thin film transistor (M2), a third thin film transistor (M3), a fourth thin film transistor (M4), a fifth thin film transistor (M5), a sixth thin film transistor (M6) and a capacitor (C). A first light emitting element (D1) and a second light emitting element (D2) adjacent to each other on the same column can share one pixel driving circuit, and can compensate for the voltage drop of the threshold voltage of the fourth thin film transistor (M4) and the power supply voltages (Vss1, Vss2).

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed on November 2, 2022, bearing application number 202211359796.0, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of pixel driving, and in particular to a pixel driving circuit, a pixel driving method and a display panel. [Background technology]

[0003] Currently, display panels that use light-emitting elements as pixels must have one pixel driving circuit for each light-emitting element. However, in order to compensate for the threshold voltage of the driving thin-film transistor, six or more thin-film transistors must often be used for each existing pixel driving circuit, which affects the transmittance of the display panel. Summary of the Invention [Problem to be solved by the invention]

[0004] The main objective of the present application is to provide a pixel driving circuit for solving the problem of low transmittance of a self-luminous display panel. [Means for solving the problem]

[0005] In order to achieve the above object, a pixel driving circuit proposed by the present application is applied to a display panel, the display panel is provided with a pixel array, the pixel array includes a first light-emitting element and a second light-emitting element adjacent to each other on the same column, the first light-emitting element has an anode connected to a first node and a cathode to which a first power supply voltage is input, the second light-emitting element has an anode connected to a third node and a cathode to which a second power supply voltage is input, The pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a capacitor; the first thin film transistor has a controlled terminal to which a first control signal is input, a first terminal to which a first power supply voltage is input, and a second terminal connected to a first node; the second thin film transistor has a controlled terminal to which a second control signal is input, a first terminal connected to a fourth node, and a second terminal connected to a second terminal of the first thin film transistor; The second thin film transistor has a controlled terminal to which a scanning signal is input, a first terminal connected to a data signal, and a second terminal connected to a second node; the fourth thin film transistor has a controlled terminal connected to a fourth node, a first terminal connected to the first node, and a second terminal connected to a third node; the fifth thin film transistor has a controlled terminal to which a third control signal is input, a first terminal connected to a fourth node, and a second terminal connected to a third node; the sixth thin film transistor, a controlled terminal of which receives a fourth control signal, a first terminal of which is connected to the second terminal of the fifth thin film transistor, and a second terminal of which receives a second power supply voltage; The capacitor has one terminal connected to the second node and the other terminal connected to a fourth node.

[0006] The present application further proposes a pixel driving method to be applied to the pixel driving circuit as described above, the pixel driving circuit comprising: Entering a first reset stage, controlling the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor to be turned on, and controlling the data signal, the first power supply voltage and the second power supply voltage to be at low potential; entering a first sampling stage, controlling the second thin film transistor and the sixth thin film transistor to be turned on, controlling the first thin film transistor, the third thin film transistor and the fifth thin film transistor to be turned off, so that the potential of the fourth node becomes a difference between the second power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor, controlling the data signal to be at a low potential, and controlling the first power supply voltage and the second power supply voltage to be at a high potential; entering a first data writing stage, controlling the second thin film transistor to be turned on, controlling the first thin film transistor, the fifth thin film transistor and the sixth thin film transistor to be turned off, controlling the third thin film transistor to be turned on in a preset sub-stage and controlling the third thin film transistor to be turned off other than the preset sub-stage, and controlling the data signal, the first power supply voltage and the second power supply voltage to be at high potentials, so that the potential of the fourth node becomes the sum of a difference between a second power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor and a data signal; Entering a first light emitting stage, controlling the sixth thin film transistor to be turned on, controlling the first thin film transistor, the second thin film transistor, the third thin film transistor and the fifth thin film transistor to be turned off, controlling the first power supply voltage to be a negative potential, controlling the second power supply voltage to be a high potential, and controlling the data signal to be a low potential, so that the first light emitting element emits light; Entering a second reset stage, controlling the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor to be turned on, and controlling the data signal, the first power supply voltage and the second power supply voltage to be at low potential; entering a second sampling stage, controlling the first thin film transistor, the third thin film transistor and the fifth thin film transistor to be turned on, controlling the second thin film transistor and the sixth thin film transistor to be turned off, controlling the data signal to be at a low potential, and controlling the first power supply voltage and the second power supply voltage to be at a high potential, so that the potential of the fourth node is a difference between a first power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor; entering a second data writing stage, controlling the fifth thin film transistor to be turned on, controlling the first thin film transistor, the second thin film transistor and the sixth thin film transistor to be turned off, controlling the third thin film transistor to be turned on in a preset sub-stage and controlling the third thin film transistor to be turned off other than the preset sub-stage, and controlling the data signal, the first power supply voltage and the second power supply voltage to be at high potentials, so that the potential of the fourth node becomes the sum of a difference between a first power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor and a data signal; entering a second light-emitting stage, controlling the first thin film transistor to be turned on, controlling the second thin film transistor, the third thin film transistor, the fifth thin film transistor and the sixth thin film transistor to be turned off, controlling the first power supply voltage to be at a high potential, controlling the second power supply voltage to be at a negative potential, and controlling the data signal to be at a low potential, so that the second light-emitting element emits light.

[0007] The present application further proposes a display panel, the display panel comprising: a pixel array including a first light-emitting element and a second light-emitting element adjacent to each other on the same column; and the pixel driving circuit described above, connected to the first light emitting element and the second light emitting element.

[0008] (Beneficial Effects) The technical solution of the present application uses a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor and a capacitor to form a pixel driving circuit with a 3T0.5C circuit configuration. It allows two adjacent light-emitting elements on the same column to share one pixel driving circuit, and compensates for the threshold voltage of the driving thin film transistor and the voltage drop of the power supply voltage, so that the influence of the defect of the threshold voltage of the driving thin film transistor and the voltage drop of the power supply voltage on the passing current of the light-emitting element can be eliminated, which is favorable for improving the display uniformity of the self-luminous display panel, and the number of thin film transistors is greatly reduced compared with at least 12 thin film transistors required for providing two pixel driving circuits separately, so that the transmittance of the panel can be greatly improved. In addition, the pixel driving circuit of the present application can also put the first light-emitting element and the second light-emitting element into a reverse bias state to reduce the aging speed of the light-emitting element, which is favorable for extending the service life of the self-luminous display panel.

[0009] In order to more clearly describe the technical solutions of the embodiments of the present application and the prior art, the following will briefly describe the accompanying drawings required for the description of the embodiments or the prior art. It is obvious that the accompanying drawings in the following description are only some of the embodiments of the present application, and those skilled in the art can obtain other accompanying drawings based on the structures shown in these accompanying drawings without creative work. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic circuit diagram of a pixel driving circuit according to a first embodiment of the present application. [Diagram 2] FIG. 2 is a schematic timing diagram of a pixel driving circuit according to a first embodiment of the present application. [Diagram 3] FIG. 2 is a schematic pathway diagram of a first sampling stage of a pixel driving circuit according to a first embodiment of the present application. [Figure 4] FIG. 2 is a schematic pathway diagram of a pixel driving circuit in a first data stage according to a first embodiment of the present application; [Diagram 5] FIG. 2 is a schematic pathway diagram of a first emission writing stage of the pixel driving circuit according to the first embodiment of the present application. [Figure 6] FIG. 4 is a schematic pathway diagram of a second sampling stage of the pixel driving circuit according to the first embodiment of the present application. [Figure 7] FIG. 2 is a schematic pathway diagram of a pixel driving circuit in a second data stage according to a first embodiment of the present application; [Figure 8] FIG. 4 is a schematic pathway diagram of a second light-emitting stage of the pixel driving circuit according to the first embodiment of the present application. [Figure 9] FIG. 6 is a schematic step diagram of a pixel driving method according to a second embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The realization of the object, the function features and advantages of the present invention will be further explained in combination with the embodiments with reference to the attached drawings.

[0012] The following will clearly and completely describe the technical solutions in the embodiments of the present application in combination with the drawings in the embodiments of the present application. It is clear that the described embodiments are not all the embodiments of the present application, but only some of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can obtain without performing creative work fall within the scope of protection of the present application.

[0013] In addition, the descriptions such as "first" and "second" in the embodiments of the present application are used for explanatory purposes only and should not be understood as indicating or implying the relative importance thereof or implicitly specifying the number of technical features presented. Therefore, a feature defined as "first" or "second" may include at least one of the feature, either explicitly or implicitly. In addition, the technical solutions of each embodiment may be combined with each other as long as it can be realized by a person skilled in the art. If a combination of technical solutions causes a contradiction or cannot be realized, it should be understood that such combination of technical solutions does not exist and is not within the scope of the application.

[0014] (First embodiment) The present application proposes a pixel driving circuit applicable to a display panel.

[0015] The display panel may include a pixel layer, a light-emitting layer, a driving circuit layer, and an array substrate, which are stacked in order. The driving circuit layer is provided on the array substrate. The pixel layer may include a plurality of pixels arranged in an array, and the light-emitting layer is provided with a light-emitting element corresponding to each pixel. The driving circuit layer may include a plurality of pixel driving circuits, each of which is connected to a light-emitting element, and each pixel driving circuit is used to drive the light emission of the light-emitting element of the corresponding pixel, thereby realizing the self-luminous display of the display panel. The light-emitting element may be an organic light-emitting diode (OLED), a mini light-emitting diode (MINI-LED), or a micro light-emitting diode (MICRO-LED), and is not limited here. In the embodiments of the present application, a case in which the light-emitting element is an organic light-emitting diode will be described as an example.

[0016] In practical applications, the pixel driving circuit may be provided with one driving thin film transistor for controlling the current flowing through the light emitting element, and there is a non-uniformity problem in the threshold voltage of the driving thin film transistor, and this threshold voltage may further drift as the operation time increases, which may cause moire due to uneven brightness in the display panel. In the prior art, in order to eliminate the above-mentioned defects in the threshold voltage, the number of thin film transistors is usually increased and a storage capacitor C is added, so that the number of thin film transistors in each pixel driving circuit is six or more, and as can be seen from the position of the driving circuit layer in the display panel where the pixel driving circuit is located, the more thin film transistors there are in each pixel driving circuit, the less light is transmitted from the light emitting layer through the driving circuit layer, and the lower the transmittance of the display panel. In addition, the pixel driving circuit also needs to input a power supply voltage through a power supply line to drive the corresponding light emitting element, and since the power supply line itself has a certain degree of internal resistance, there is a voltage drop in the power supply voltage actually transmitted to the light emitting element. In addition, since the voltage drop of the power supply voltage of different display elements is different, the light emitting brightness of each light emitting element is non-uniform. Furthermore, since the light emitting elements in the pixel driving circuit are in a forward bias state, aging of the light emitting elements is accelerated, and the service life of the self-luminous display panel is shortened.

[0017] To address the above problem, the present application proposes a pixel driving circuit for driving two adjacent light-emitting elements on the same column in a pixel array, where a first light-emitting element D1 may be a light-emitting element in an odd row and a second light-emitting element D2 may be a light-emitting element in an even row.

[0018] Referring to FIG. 1, the pixel driving circuit of the present application includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6 and a capacitor C. The first thin film transistor M1 and the second thin film transistor M2 are used to control the emission of the first light-emitting element D1 and the discharge of the charge of the first node A1. The third thin film transistor M3 is a data writing thin film transistor. The fourth thin film transistor M4 is simultaneously used as the driving thin film transistor of the first light-emitting element D1 and the second light-emitting element D2. The fifth thin film transistor M5 and the sixth thin film transistor M6 are used to control the emission of the second light-emitting element D2 and the discharge of the charge of the third node A3. The capacitor C can be a storage capacitor C. Here, the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, and the sixth thin film transistor M6 may all be oxide semiconductor thin film transistors, low temperature polysilicon thin film transistors, or amorphous silicon thin film transistors, that is, the types of the thin film transistors T1 to T7 may all be indium gallium zinc oxide (IGZO), low temperature polysilicon (LTPS), or amorphous silicon (A-Si). Of course, different types of thin film transistors may be adopted for the thin film transistors M1 to M6, and various combinations are possible, so the description will be omitted here. In this embodiment, the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, and the sixth thin film transistor M6 may all be P-type thin film transistors. The controlled terminal of the thin film transistor may be a gate, one of the first terminal and the second terminal may be a source, and the other terminal may be a drain. The thin film transistor can connect the first terminal and the second terminal when it is turned on, and can disconnect the first terminal and the second terminal when it is turned off.

[0019] The first thin-film transistor M1 has a controlled terminal to which a first control signal Ctr1 is input, a first terminal to which a first power supply voltage Vss1 is input, and a second terminal connected to a first node A1; The second thin-film transistor M2 has a controlled terminal to which the second control signal Ctr2 is input, a first terminal connected to the fourth node A4, and a second terminal connected to the second terminal of the first thin-film transistor M1; The second thin-film transistor M2 has a controlled terminal to which the scan signal Scan is input, a first terminal connected to the data signal Data, and a second terminal connected to the second node A2; a fourth thin-film transistor M4, a controlled terminal connected to the fourth node A4, a first terminal connected to the first node A1, and a second terminal connected to the third node A3; The fifth thin-film transistor M5 has a controlled terminal to which the third control signal Ctr3 is input, a first terminal connected to the fourth node A4, and a second terminal connected to the third node A3; The sixth thin-film transistor M6 has a controlled terminal to which the fourth control signal Ctr4 is input, a first terminal connected to the second terminal of the fifth thin-film transistor M5, and a second terminal to which the second power supply voltage Vss2 is input; The capacitor C has one terminal connected to the second node A2 and the other terminal connected to the fourth node A4.

[0020] The first light-emitting element D1 has an anode connected to the first node A1 and a cathode to which the first power supply voltage Vss1 is input, and the second light-emitting element D2 has an anode connected to the third node A3 and a cathode to which the second power supply voltage Vss2 is input.

[0021] In the first reset stage T1, the first sampling stage T2, the first data writing stage T3, the first light emitting stage T4, the second reset stage, the second sampling stage T6, the second data writing stage T7, and the second light emitting stage T8, the scanning signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2, and the data signal Data are controlled to be at different potentials, respectively, so that the pixel driving circuit of the present application can sequentially drive the first light emitting element D1 and the second light emitting element D2 to emit light. In other words, the pixel driving circuit of the present application can be regarded as a 3T0.5C circuit configuration.

[0022] In addition, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the scanning signal Scan and the data signal Data can all be output and obtained from an external timing controller, and the first power supply voltage Vss1 and the second power supply voltage Vss2 can be output and obtained from an external common voltage generating circuit.

[0023] In this way, two adjacent light-emitting elements on the same column can share one pixel driving circuit, and the threshold voltage of the fourth thin film transistor M4 and the voltage drop of the power supply voltage can be compensated for, so that the influence of the threshold voltage defect of the driving thin film transistor and the voltage drop of the power supply voltage on the passing current of the light-emitting element can be eliminated, which is favorable for improving the display uniformity of the self-luminous display panel, and the number of thin film transistors is greatly reduced compared with the at least 12 thin film transistors required for providing two separate pixel driving circuits, so that the transmittance of the panel can be greatly improved. In addition, the pixel driving circuit of the present application can also put the first light-emitting element D1 and the second light-emitting element D2 into a reverse bias state to reduce the aging speed of the light-emitting element, which is favorable for extending the service life of the self-luminous display panel.

[0024] In one embodiment, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2, the scan signal Scan and the data signal Data are combined to sequentially correspond to a first reset stage T1, a first sampling stage T2, a first data write stage T3, a first light emitting stage T4, a second reset stage T5, a second sampling stage T6, a second data write stage T7 and a second light emitting stage T8. Here, in the first light emitting stage T4, the first light emitting element D1 emits light, and in the second light emitting stage T8, the second light emitting element D2 emits light.

[0025] 1 and 2, FIG. 1 may also be a schematic pathway diagram of the first reset stage T1 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the first reset stage T1, the scan signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at low potential, so as to control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be all turned on. At this time, the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are at low potential. In the present application, the pixel driving circuit erases residual charges, thereby resetting the terminal-to-terminal voltage of the capacitor C and the potential value of the controlled terminal of the fourth thin-film transistor M4 to the 0 level, so that the low potentials of the data signal Data, the first power supply voltage Vss1, and the second power supply voltage Vss2 are 0V.

[0026] 1, 2 and 3, FIG. 3 is a schematic pathway diagram of the first sampling stage T2 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the first sampling stage T2, the second control signal Ctr2 and the fourth control signal Ctr4 are all at low potential to control the second thin film transistor M2 and the sixth thin film transistor M6 to be turned on. The first control signal Ctr1, the scan signal Scan and the third control signal Ctr3 are all at high potential to control the first thin film transistor M1, the third thin film transistor M3 and the fifth thin film transistor M5 to be turned off. At this time, the data signal Data is at a low potential, the first power supply voltage Vss1 and the second power supply voltage Vss2 are at a high potential, and due to the coupling effect of the capacitor C, the terminal voltage of the capacitor C is still 0V. However, the controlled terminal potential of the fourth thin film transistor M4, i.e., the potential of the fourth node A4, can be charged to the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4, which can be expressed by the formula: V G =V S2 -|V TH |, where V G is the potential value of the controlled terminal of the fourth thin-film transistor M4, V S2 is the potential value of the second power supply voltage Vss2, V TH is the threshold voltage of the fourth thin film transistor M4. In order to improve the aging of the first light emitting element D1 by making the first light emitting element D1 in a reverse bias state, the potential value of the first node A1 is lower than the high potential of the first power supply voltage Vss1.

[0027] 1, 2 and 4, FIG. 4 is a schematic pathway diagram of the first data writing stage T3 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the first data writing stage T3, the second control signal Ctr2 is at a low potential to control the second thin film transistor M2 to be turned on. In the first data writing stage T3, the first control signal Ctr1, the third control signal Ctr3 and the fourth control signal Ctr4 are all at a high potential to control the first thin film transistor M1, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be turned off. In the preset sub-stage T31, the scanning signal Scan is at a low potential. In the preset sub-stage T31, the scanning signal Scan is at a high potential during the period other than the preset sub-stage T31 of the first data writing stage T3 to control the third thin film transistor M3 to be turned on during the period other than the preset sub-stage T31. At this time, the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are all at a high potential so that the data signal Data is written to the second node A2 through the third thin film transistor M3. Due to the coupling effect of the capacitor C, the potential of the fourth node A4 is the sum of the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4 and the data signal Data, which can be expressed by the formula: V G =V S2 -|V TH |+V DATA where V DATA is the potential of the data signal Data. Note that, for two first light-emitting elements D1 that are closest to each other on the same column, the rising edge (signal edge changing from low potential to high potential) of the scanning signal Scan(n) at the end of the preset sub-stage T31 of the first light-emitting element D1 that emits light first corresponds to the falling edge (signal edge changing from high potential to low potential) of the scanning signal Scan(n+2) at the start of the preset sub-stage T32 of the element that emits light later.

[0028] 1, 2 and 5, FIG. 5 is a schematic pathway diagram of the first light-emitting stage T4 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the first light-emitting stage T4, the fourth control signal Ctr4 is at a low potential to control the sixth thin film transistor M6 to be turned on. In order to control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3 and the fifth thin film transistor M5 to be turned off, the first control signal Ctr1, the second control signal Ctr2, the scan signal Scan and the third control signal Ctr3 are all at a high potential. At this time, the first power supply voltage Vss1 is at a negative potential, the second power supply voltage Vss2 is at a high potential, and the data signal Data is at a low potential. Note that the negative potential of the first power supply voltage Vss1 is smaller than its low potential. In this way, the potential of the third node A3 can be pulled up to the high potential of the second power supply voltage Vss2, and the fourth thin film transistor M4 is turned on to generate a passing current of the first light emitting element D1, thereby driving the first light emitting element D1 to emit light. The expression of the passing current of the first light emitting element D1 is as follows:

number

[0029] 1 and 2, FIG. 1 may also be a schematic pathway diagram of the second light emission stage T5 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the second reset stage T5, the scan signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at low potential, so as to control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be all turned on. At this time, the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are at low potential, so as to reset the voltage between the terminals of the capacitor C and the potential value of the controlled terminal of the fourth thin film transistor M4 to 0 level again by the pixel driving circuit erasing the residual charge.

[0030] 1, 2 and 6, FIG. 6 is a schematic pathway diagram of the second sampling stage T6 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the second sampling stage T6, the first control signal Ctr1, the scan signal Scan and the third control signal Ctr3 are all at low potentials to control the first thin film transistor M1, the third thin film transistor M3 and the fifth thin film transistor M5 to be turned on. The second control signal Ctr2 and the fourth control signal Ctr4 are all at high potentials to control the second thin film transistor M2 and the sixth thin film transistor M6 to be turned off. At this time, the data signal Data is at a low potential, the first power supply voltage Vss1 and the second power supply voltage Vss2 are at a high potential, and due to the coupling effect of the capacitor C, the terminal voltage of the capacitor C is still 0V. However, the controlled terminal potential of the fourth thin film transistor M4, that is, the potential of the fourth node A4, can be charged to the difference between the first power supply voltage Vss1 and the absolute value of the threshold voltage of the fourth thin film transistor M4, which can be expressed by the formula: V G =V S1 -|V TH |, where V S1is the potential value of the first power supply voltage Vss1. In order to improve the aging of the second light-emitting element D2 by making the second light-emitting element D2 in a reverse bias state, the potential value of the third node A3 is lower than the high potential of the second power supply voltage Vss2.

[0031] 1, 2 and 7, FIG. 7 is a schematic pathway diagram of the second data writing stage T7 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the second data writing stage T7, the third control signal Ctr3 is at a low potential to control the fifth thin film transistor M5 to be turned on. In the second data writing stage T7, the first control signal Ctr1, the second control signal Ctr2 and the fourth control signal Ctr4 are all at a high potential to control the first thin film transistor M1, the second thin film transistor M2 and the sixth thin film transistor M6 to be turned off. In the preset sub-stage T71, the scan signal Scan is at a low potential. In the preset sub-stage T71, the scan signal Scan is at a high potential during the period other than the preset sub-stage T71 of the first data writing stage T3 to control the third thin film transistor M3 to be turned on during the period other than the preset sub-stage T71 to control the third thin film transistor M3 to be turned off during the period other than the preset sub-stage T71. At this time, the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are all at a high potential so that the data signal Data is written to the second node A2 through the third thin film transistor M3. Due to the coupling effect of the capacitor C, the potential of the fourth node A4 is the sum of the difference between the first power supply voltage Vss1 and the absolute value of the threshold voltage of the fourth thin film transistor M4 and the data signal Data, which can be expressed by the formula: V G =V S1 -|V TH |+V DATAFor the two second light-emitting elements D2 that are closest to each other on the same row, the rising edge (signal edge changing from low potential to high potential) of the scanning signal Scan(n+1) at the end of the preset sub-stage T71 of the second light-emitting element D2 that emits light first corresponds to the falling edge (signal edge changing from high potential to low potential) of the scanning signal Scan(n+3) at the start of the preset sub-stage T72 of the element that emits light later.

[0032] 1, 2 and 8, FIG. 8 is a schematic pathway diagram of the second light-emitting stage T8 of the pixel driving circuit of the present application in the driving timing shown in FIG. 2. In the second light-emitting stage T8, the first control signal Ctr1 is at a low potential to control the first thin film transistor M1 to be turned on. The second control signal Ctr2, the fourth control signal Ctr4, the third control signal Ctr3 and the scanning signal Scan are all at a high potential to control the second thin film transistor M2, the sixth thin film transistor M6, the fifth thin film transistor M5 and the third thin film transistor M3 to be turned off. At this time, the first power supply voltage Vss1 is at a high potential, the second power supply voltage Vss2 is at a negative potential, and the data signal Data is at a low potential. Note that the negative potential of the second power supply voltage Vss2 is smaller than its low potential. In this way, the potential of the first node A1 can be pulled up to the high potential of the first power supply voltage Vss1, and the fourth thin film transistor M4 is turned on to generate a passing current of the second light emitting element D2, thereby driving the second light emitting element D2 to emit light. The expression of the passing current of the second light emitting element D2 is as follows:

number

[0033] As can be seen from this, the passing current of the second light-emitting element D2 when it emits light is similarly correlated only with the data signal Data, and is unrelated to the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, that is, it does not change with the changes in the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, so that the influence of defects in the threshold voltage of the fourth thin film transistor M4 and voltage drops in the power supply voltage on the passing current of the second light-emitting element D2 can be eliminated.

[0034] (Second Example) Referring to FIG. 9, the present application further proposes a pixel driving method, which can be applied to a pixel driving circuit, and the specific configuration of the pixel driving circuit is referred to the above-mentioned first embodiment, and since the pixel driving method adopts all the technical solutions of the above-mentioned first embodiment, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned first embodiment, and the description is omitted here.

[0035] The first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the scanning signal Scan and the data signal Data are combined to sequentially correspond to a first reset stage T1, a first sampling stage T2, a first data writing stage T3, a first light-emitting stage T4, a second reset stage T5, a second sampling stage T6, a second data writing stage T7 and a second light-emitting stage T8.

[0036] Here, the pixel driving method includes the following steps.

[0037] In step S1, the pixel driver circuit enters a first reset stage T1, and controls the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be turned on, and controls the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be at low potential. In this stage, the scan signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at low potential. In this way, the pixel driver circuit can reset the voltage across the capacitor C and the potential value of the controlled terminal of the fourth thin film transistor M4 to 0 level by erasing the residual charge.

[0038] In step S2, enter the first sampling stage T2, control the second thin film transistor M2 and the sixth thin film transistor M6 to be turned on, control the first thin film transistor M1, the third thin film transistor M3 and the fifth thin film transistor M5 to be turned off, so that the potential of the fourth node A4 is the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4, control the data signal Data to be at a low potential, and control the first power supply voltage Vss1 and the second power supply voltage Vss2 to be at a high potential. In this stage, the second control signal Ctr2 and the fourth control signal Ctr4 are all at a low potential, and the first control signal Ctr1, the scanning signal Scan and the third control signal Ctr3 are all at a high potential. In this way, the controlled terminal potential of the fourth thin film transistor M4, i.e., the potential of the fourth node A4, can be charged to the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4, which can be expressed by the formula: V G =V S2 -|V TH |, and in order to realize improvement in aging of the first light-emitting element D1 by placing the first light-emitting element D1 in a reverse bias state, the potential value of the first node A1 is lower than the high potential of the first power supply voltage Vss1.

[0039] In step S3, enter the first data writing stage T3, control the second thin film transistor M2 to be turned on, control the first thin film transistor M1, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be turned off, control the third thin film transistor M3 to be turned on in a preset sub-stage T31, control the third thin film transistor M3 to be turned off outside the preset sub-stage T31, and control the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be at high potential, so that the potential of the fourth node A4 becomes the sum of the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4 and the data signal Data. In this stage, the second control signal Ctr2 is at a low potential, the first control signal Ctr1, the third control signal Ctr3, and the fourth control signal Ctr4 are all at a high potential, and the scan signal Scan is at a low potential in the preset sub-stage T31 and at a high potential during the period other than the preset sub-stage T31 of the first data write stage T3. Thus, the data signal Data can be written to the second node A2 through the third thin film transistor M3, and due to the coupling effect of the capacitor C, the potential of the fourth node A4 is the sum of the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4 and the data signal Data, which can be expressed by the formula: V G =V S2 -|V TH |+V DATA It becomes.

[0040] In step S4, the first light-emitting stage T4 is entered, and the sixth thin film transistor M6 is controlled to be turned on, the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3 and the fifth thin film transistor M5 are controlled to be turned off, the first power supply voltage Vss1 is controlled to be a negative potential, the second power supply voltage Vss2 is controlled to be a high potential, and the data signal Data is controlled to be a low potential. In this stage, the fourth control signal Ctr4 is at a low potential, and the first control signal Ctr1, the second control signal Ctr2, the scanning signal Scan and the third control signal Ctr3 are all at a high potential. Thus, the potential of the third node A3 can be pulled up to the high potential of the second power supply voltage Vss2, and the fourth thin film transistor M4 is turned on to generate a passing current of the first light-emitting element D1, thereby realizing the driving of the first light-emitting element D1 to emit light. In addition, as can be seen from the expression of the passing current of the first light-emitting element D1, the passing current of the first light-emitting element D1 during emission of light is correlated only with the data signal Data, and is unrelated to the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, that is, it does not change with the changes of the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, so that the influence of the defect of the threshold voltage of the fourth thin film transistor M4 and the voltage drop of the power supply voltage on the passing current of the first light-emitting element D1 can be eliminated.

[0041] In step S5, the pixel driving circuit enters a second reset stage T5, and controls the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be turned on, and controls the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be at low potential. In this stage, the scanning signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at low potential. Thus, the pixel driving circuit erases the residual charge, thereby resetting the voltage across the capacitor C and the potential value of the controlled terminal of the fourth thin film transistor M4 to 0 level again.

[0042] In step S6, enter the second sampling stage T6, control the first thin film transistor M1, the third thin film transistor M3 and the fifth thin film transistor M5 to be turned on, control the second thin film transistor M2 and the sixth thin film transistor M6 to be turned off, control the data signal Data to be at a low potential, and control the first power supply voltage Vss1 and the second power supply voltage Vss2 to be at a high potential, so that the potential of the fourth node A4 is the difference between the first power supply voltage Vss1 and the absolute value of the threshold voltage of the fourth thin film transistor M4. In this stage, the first control signal Ctr1, the scan signal Scan and the third control signal Ctr3 are all at a low potential, and the second control signal Ctr2 and the fourth control signal Ctr4 are all at a high potential. In this way, the controlled terminal potential of the fourth thin film transistor M4, i.e., the potential of the fourth node A4, can be charged to the difference between the first power supply voltage Vss1 and the absolute value of the threshold voltage of the fourth thin film transistor M4, which can be expressed by the formula: V G =V S1 -|V TH |, and in order to realize improvement in aging of the second light-emitting element D2 by placing the second light-emitting element D2 in a reverse bias state, the potential value of the third node A3 is lower than the high potential of the second power supply voltage Vss2.

[0043] In step S7, enter into a second data writing stage T7, control the fifth thin film transistor M5 to be turned on, control the first thin film transistor M1, the second thin film transistor M2 and the sixth thin film transistor M6 to be turned off, control the third thin film transistor M3 to be turned on in a preset sub-stage T71, control the third thin film transistor M3 to be turned off outside the preset sub-stage T71, and control the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be at high potential, so that the potential of the fourth node A4 becomes the sum of the difference between the first power supply voltage Vss1 and the absolute value of the threshold voltage of the fourth thin film transistor M4 and the data signal Data. In this stage, the third control signal Ctr3 is at a low potential, the first control signal Ctr1, the second control signal Ctr2, and the fourth control signal Ctr4 are all at a high potential, and the scanning signal Scan is at a low potential in the preset sub-stage T71 and at a high potential during the period other than the preset sub-stage T71 of the first data writing stage T3. In this way, the data signal Data is written to the second node A2 through the third thin film transistor M3, and the potential of the fourth node A4 is the sum of the difference between the first power supply voltage Vss1 and the absolute value of the threshold voltage of the fourth thin film transistor M4 and the data signal Data, which can be expressed by the formula: V G =V S1 -|V TH |+V DATA It becomes.

[0044] In step S8, the second light-emitting stage T8 is entered, and the first thin film transistor M1 is controlled to be turned on, the second thin film transistor M2, the third thin film transistor M3, the fifth thin film transistor M5 and the sixth thin film transistor M6 are controlled to be turned off, the first power supply voltage Vss1 is controlled to be at a high potential, the second power supply voltage Vss2 is controlled to be at a negative potential, and the data signal Data is controlled to be at a low potential, so that the second light-emitting element D2 emits light. In this stage, the first control signal Ctr1 is at a low potential, and the second control signal Ctr2, the fourth control signal Ctr4, the third control signal Ctr3 and the scanning signal Scan are all at a high potential. Thus, the potential of the first node A1 can be pulled up to the high potential of the first power supply voltage Vss1, and the fourth thin film transistor M4 is turned on to generate a passing current of the second light-emitting element D2, thereby realizing the driving of the second light-emitting element D2 to emit light. In addition, as can be seen from the current expression of the second light-emitting element D2, the passing current of the second light-emitting element D2 when it emits light is similarly correlated only with the data signal Data, and is unrelated to the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, that is, it does not change with the changes in the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, so that the influence of the defect in the threshold voltage of the fourth thin film transistor M4 and the voltage drop of the power supply voltage on the passing current of the second light-emitting element D2 can be eliminated.

[0045] (Third Example) The present application further proposes a display panel including a pixel array and a pixel driving circuit, and the specific configuration of the pixel driving circuit is referred to the above-mentioned first embodiment. Since the pixel driving method adopts all the technical solutions of the above-mentioned first embodiment, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned first embodiment, and thus the description is omitted here.

[0046] Here, the pixel array includes a first light-emitting element D1 and a second light-emitting element D2 adjacent to each other on the same column. The pixel driving circuit is connected to the first light-emitting element D1 and the second light-emitting element D2, and is used to sequentially drive the first light-emitting element D1 and the second light-emitting element D2 to emit light according to the potentials of the input scanning signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2, and the data signal Data.

[0047] The above are merely some embodiments of the present application, and do not limit the scope of the patent of the present application. Under the concept of the present application, the equivalent structural transformation made by using the contents of the specification and the accompanying drawings of the present application, or the direct / indirect application to other related technical fields, are all included in the scope of protection of the patent of the present application.

Claims

1. A pixel driving circuit for use in a display panel, comprising: The display panel is provided with a pixel array, the pixel array including a first light-emitting element (D1) and a second light-emitting element (D2) adjacent to each other on the same column, the first light-emitting element (D1) having an anode connected to a first node (A1) and a first power supply voltage input to a cathode, the second light-emitting element (D2) having an anode connected to a third node (A3) and a second power supply voltage input to a cathode, The pixel driving circuit includes a first thin film transistor (M1), a second thin film transistor (M2), a third thin film transistor (M3), a fourth thin film transistor (M4), a fifth thin film transistor (M5), a sixth thin film transistor (M6) and a capacitor (C); The first thin film transistor (M1) has a controlled terminal to which a first control signal (Ctr1) is input, a first terminal to which a first power supply voltage is input, and a second terminal connected to a first node (A1); The second thin film transistor (M2) has a controlled terminal to which a second control signal (Ctr2) is input, a first terminal connected to a fourth node (A4), and a second terminal connected to the second terminal of the first thin film transistor (M1); The third thin film transistor (M3) has a controlled terminal to which a scan signal (Scan) is input, a first terminal connected to a data signal (Data), and a second terminal connected to a second node (A2); The fourth thin film transistor (M4) has a controlled terminal connected to a fourth node (A4), a first terminal connected to the first node (A1), and a second terminal connected to a third node (A3); The fifth thin film transistor (M5) has a controlled terminal to which a third control signal (Ctr3) is input, a first terminal connected to a fourth node (A4), and a second terminal connected to a third node (A3); The sixth thin film transistor (M6) has a controlled terminal to which a fourth control signal (Ctr4) is input, a first terminal connected to a second terminal of the fifth thin film transistor (M5), and a second terminal to which a second power supply voltage is input; The capacitor (C) has one terminal connected to the second node (A2) and the other terminal connected to the fourth node (A4). Pixel driving circuit.

2. The first thin film transistor (M1) and the second thin film transistor (M2) are used to control the emission of the first light emitting element (D1) and the erasure of the charge of the first node (A1); the third thin film transistor (M3) is a data writing thin film transistor; the fourth thin film transistor (M4) is simultaneously a driving thin film transistor of the first light emitting element (D1) and the second light emitting element (D2); the fifth thin film transistor (M5) and the sixth thin film transistor (M6) are used to control the emission of the second light emitting element (D2) and the erasure of the charge of the third node (A3); The capacitor (C) is a storage capacitor.

2. A pixel driving circuit as claimed in claim 1.

3. The controlled terminals of the first thin film transistor (M1), the second thin film transistor (M2), the third thin film transistor (M3), the fourth thin film transistor (M4), the fifth thin film transistor (M5) and the sixth thin film transistor (M6) are all gates.

2. A pixel driving circuit as claimed in claim 1.

4. The first control signal (Ctr1), the second control signal (Ctr2), the third control signal (Ctr3), the fourth control signal (Ctr4), the scan signal (Scan) and the data signal (Data) are all output from an external timing controller, and the first power supply voltage (Vss1) and the second power supply voltage (Vss2) are output from an external common voltage generating circuit.

2. A pixel driving circuit as claimed in claim 1.

5. the first control signal (Ctr1), the second control signal (Ctr2), the third control signal (Ctr3), the fourth control signal (Ctr4), the first power supply voltage, the second power supply voltage, the scanning signal (Scan), and the data signal (Data) are combined to sequentially correspond to a first reset step (T1), a first sampling step (T2), a first data write step (T3), a first light emission step (T4), a second reset step (T5), a second sampling step (T6), a second data write step (T7), and a second light emission step (T8); In the first light emitting step (T4), the first light emitting element (D1) emits light, and in the second light emitting step (T8), the second light emitting element (D2) emits light.

2. A pixel driving circuit as claimed in claim 1.

6. In the first reset step (T1) and the second reset step (T5), the first thin film transistor (M1), the second thin film transistor (M2), the third thin film transistor (M3), the fourth thin film transistor (M4), the fifth thin film transistor (M5) and the sixth thin film transistor (M6) are turned on; The data signal (Data), the first power supply voltage, and the second power supply voltage are at low potential.

6. A pixel driving circuit according to claim 5.

7. In the first sampling step (T2), the second thin film transistor (M2) and the sixth thin film transistor (M6) are turned on, the first thin film transistor (M1), the third thin film transistor (M3) and the fifth thin film transistor (M5) are turned off, the data signal (Data) is at a low potential, the first power supply voltage and the second power supply voltage are at a high potential, and the potential of the fourth node (A4) is a difference between the second power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor (M4); In the second sampling step (T6), the first thin film transistor (M1), the third thin film transistor (M3), and the fifth thin film transistor (M5) are turned on, the second thin film transistor (M2) and the sixth thin film transistor (M6) are turned off, the data signal (Data) is at a low potential, the first power supply voltage and the second power supply voltage are at a high potential, and the potential of the fourth node (A4) is a difference between the first power supply voltage and the absolute value of the threshold voltage of the fourth thin film transistor (M4).

6. A pixel driving circuit as claimed in claim 5.

8. In the first sampling step (T2), the first light emitting element (D1) is in a reverse bias state; In the second sampling step (T6), the second light emitting element (D2) is in a reverse bias state.

8. A pixel driving circuit as claimed in claim 7.

9. In the first data writing step (T3), the second thin film transistor (M2) is turned on, the first thin film transistor (M1), the fifth thin film transistor (M5) and the sixth thin film transistor (M6) are turned off, the third thin film transistor (M3) is turned on in a sub-step set in advance, the third thin film transistor (M3) is turned off in a sub-step other than the sub-step set in advance, the data signal (Data), the first power supply voltage and the second power supply voltage are at high potentials, and the potential of the fourth node (A4) is a difference between the second power supply voltage and the absolute value of the threshold voltage of the fourth thin film transistor (M4) and the data signal ( Data) and In the second data writing step (T7), the fifth thin film transistor (M5) is turned on, the first thin film transistor (M1), the second thin film transistor (M2) and the sixth thin film transistor (M6) are turned off, the third thin film transistor (M3) is turned on in a sub-step set in advance, the third thin film transistor (M3) is turned off in a sub-step other than the sub-step set in advance, the data signal (Data), the first power supply voltage and the second power supply voltage are at high potentials, and the potential of the fourth node (A4) is the sum of a difference between the first power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor (M4) and the data signal (Data).

6. A pixel driving circuit as claimed in claim 5.

10. In the first light-emitting stage (T4), the sixth thin film transistor (M6) is turned on, the first thin film transistor (M1), the second thin film transistor (M2), the third thin film transistor (M3) and the fifth thin film transistor (M5) are turned off, the first power supply voltage is a negative potential, the second power supply voltage is a high potential, and the data signal (Data) is a low potential; In the second light-emitting stage (T8), the first thin film transistor (M1) is turned on, the second thin film transistor (M2), the third thin film transistor (M3), the fifth thin film transistor (M5) and the sixth thin film transistor (M6) are turned off, the first power supply voltage is at a high potential, the second power supply voltage is at a negative potential, and the data signal (Data) is at a low potential.

6. A pixel driving circuit as claimed in claim 5.

11. The passing current of the first light emitting element (D1) and the second light emitting element (D2) during light emission does not change with the change in the threshold voltage of the fourth thin film transistor (M4).

11. A pixel driving circuit according to claim 10.

12. A pixel driving method applied to a pixel driving circuit, comprising: The pixel driving circuit is applied to a display panel, and the display panel is provided with a pixel array, the pixel array including a first light-emitting element and a second light-emitting element adjacent to each other on the same column, the first light-emitting element having an anode connected to a first node and a cathode to which a first power supply voltage is input, the second light-emitting element having an anode connected to a third node and a cathode to which a second power supply voltage is input, The pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a capacitor; The first thin film transistor has a controlled terminal to which a first control signal is input, a first terminal to which a first power supply voltage is input, and a second terminal connected to a first node; the second thin film transistor has a controlled terminal to which a second control signal is input, a first terminal connected to a fourth node, and a second terminal connected to the second terminal of the first thin film transistor; the third thin film transistor has a controlled terminal to which a scanning signal is input, a first terminal connected to a data signal, and a second terminal connected to a second node; the fourth thin film transistor has a controlled terminal connected to a fourth node, a first terminal connected to the first node, and a second terminal connected to a third node; the fifth thin film transistor has a controlled terminal to which a third control signal is input, a first terminal connected to a fourth node, and a second terminal connected to a third node; the sixth thin film transistor has a controlled terminal to which a fourth control signal is input, a first terminal connected to the second terminal of the fifth thin film transistor, and a second terminal to which a second power supply voltage is input; the capacitor has one terminal connected to the second node and the other terminal connected to a fourth node; The pixel driving method includes: A step (S1) of entering a first reset stage, controlling the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor to be turned on, and controlling the data signal, the first power supply voltage and the second power supply voltage to be at low potential; a step (S2) of entering a first sampling stage, controlling the second thin film transistor and the sixth thin film transistor to be turned on, controlling the first thin film transistor, the third thin film transistor, and the fifth thin film transistor to be turned off, so that the potential of the fourth node becomes a difference between the second power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor, controlling so that the data signal becomes a low potential, and controlling so that the first power supply voltage and the second power supply voltage become a high potential; a step of entering a first data writing step, controlling the second thin film transistor to be turned on, controlling the first thin film transistor, the fifth thin film transistor, and the sixth thin film transistor to be turned off, controlling the third thin film transistor to be turned on in a sub-step set in advance, controlling the third thin film transistor to be turned off in a sub-step other than the sub-step set in advance, and controlling so that the data signal, the first power supply voltage, and the second power supply voltage are at high potentials, so that the potential of the fourth node becomes the sum of a difference between a second power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor, P (S3) and Step (S4) of entering a first light emitting stage, controlling the sixth thin film transistor to be turned on, controlling the first thin film transistor, the second thin film transistor, the third thin film transistor and the fifth thin film transistor to be turned off, controlling the first power supply voltage to be a negative potential, controlling the second power supply voltage to be a high potential, and controlling the data signal to be a low potential, so that the first light emitting element emits light; A step (S5) of entering a second reset stage, controlling the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor to be turned on, and controlling the data signal, the first power supply voltage and the second power supply voltage to be at low potential; entering a second sampling stage, controlling the first thin film transistor, the third thin film transistor, and the fifth thin film transistor to be turned on, controlling the second thin film transistor and the sixth thin film transistor to be turned off, controlling the data signal to be at a low potential, and controlling the first power supply voltage and the second power supply voltage to be at a high potential, so that the potential of the fourth node becomes a difference between a first power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor (S6); a step (S7) of entering a second data writing step, controlling the fifth thin film transistor to be turned on, controlling the first thin film transistor, the second thin film transistor and the sixth thin film transistor to be turned off, controlling the third thin film transistor to be turned on in a sub-step set in advance, controlling the third thin film transistor to be turned off in a sub-step other than the sub-step set in advance, and controlling the data signal, the first power supply voltage and the second power supply voltage to be at high potentials, so that the potential of the fourth node becomes the sum of a difference between a first power supply voltage and an absolute value of a threshold voltage of the fourth thin film transistor and a data signal; Entering a second light emitting stage, controlling the first thin film transistor to be turned on, controlling the second thin film transistor, the third thin film transistor, the fifth thin film transistor and the sixth thin film transistor to be turned off, controlling the first power supply voltage to be at a high potential, controlling the second power supply voltage to be at a negative potential, and controlling the data signal to be at a low potential so that the second light emitting element emits light (S8); A pixel driving method comprising:

13. The step (S2) of entering the first sampling stage, controlling the second thin film transistor and the sixth thin film transistor to be turned on, controlling the first thin film transistor, the third thin film transistor, and the fifth thin film transistor to be turned off, so that the potential of the fourth node becomes the difference between the second power supply voltage and the absolute value of the threshold voltage of the fourth thin film transistor, controlling so that the data signal becomes a low potential, and controlling so that the first power supply voltage and the second power supply voltage become a high potential, the second control signal and the fourth control signal are all at a low potential, the first control signal, the scanning signal, and the third control signal are all at a high potential, and the potential value of the first node is lower than the high potential of the first power supply voltage.

13. A pixel driving method according to claim 12.

14. The step (S4) of entering the first light emitting stage, controlling the sixth thin film transistor to be turned on, controlling the first thin film transistor, the second thin film transistor, the third thin film transistor and the fifth thin film transistor to be turned off, controlling the first power supply voltage to be a negative potential, controlling the second power supply voltage to be a high potential, and controlling the data signal to be a low potential so that the first light emitting element emits light, the fourth control signal is at a low potential, and the first control signal, the second control signal, the scanning signal, and the third control signal are all at a high potential.

13. A pixel driving method according to claim 12.

15. a pixel array including a first light-emitting element (D1) and a second light-emitting element (D2) adjacent to each other on the same column; a pixel driving circuit in which an anode of the first light-emitting element (D1) is connected to a first node (A1), a first power supply voltage is input to a cathode of the first light-emitting element (D1), an anode of the second light-emitting element (D2) is connected to a third node (A3), and a second power supply voltage is input to a cathode of the second light-emitting element (D2), The pixel driving circuit includes a first thin film transistor (M1), a second thin film transistor (M2), a third thin film transistor (M3), a fourth thin film transistor (M4), a fifth thin film transistor (M5), a sixth thin film transistor (M6) and a capacitor (C); The first thin film transistor (M1) has a controlled terminal to which a first control signal (Ctr1) is input, a first terminal to which a first power supply voltage is input, and a second terminal connected to a first node (A1); The second thin film transistor (M2) has a controlled terminal to which a second control signal (Ctr2) is input, a first terminal connected to a fourth node (A4), and a second terminal connected to the second terminal of the first thin film transistor (M1); The third thin film transistor (M3) has a controlled terminal to which a scan signal (Scan) is input, a first terminal connected to a data signal (Data), and a second terminal connected to a second node (A2); The fourth thin film transistor (M4) has a controlled terminal connected to a fourth node (A4), a first terminal connected to the first node (A1), and a second terminal connected to a third node (A3); The fifth thin film transistor (M5) has a controlled terminal to which a third control signal (Ctr3) is input, a first terminal connected to a fourth node (A4), and a second terminal connected to a third node (A3); The sixth thin film transistor (M6) has a controlled terminal to which a fourth control signal (Ctr4) is input, a first terminal connected to a second terminal of the fifth thin film transistor (M5), and a second terminal to which a second power supply voltage is input; The capacitor (C) has one terminal connected to the second node (A2) and the other terminal connected to the fourth node (A4); The pixel driving circuit is connected to the first light emitting element (D1) and the second light emitting element (D2). Display panel.

Images