Display device

Abstract

An object is to reduce the number of transistors connected to a capacitive element. 【Solution means】 It has a capacitive element and one transistor. One electrode of the capacitive element is connected to a wiring and the other electrode of the capacitive element is connected to the gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor via the capacitive element. Then, the conduction state of the transistor is controlled by a signal synchronized with the clock signal, and the transistor repeats a period of being on and a period of being off. In this way, deterioration of the transistor can be suppressed. Thus, deterioration of the transistor can be suppressed.

Description

[Technical field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device and a display device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a liquid crystal display device, a driving method for the device, or an electronic device having the device. Regarding. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single crystal semiconductors are used to form a pixel region. The technology of configuring driving circuits such as gate drivers on a substrate is expected to contribute greatly to reducing costs and improving reliability. Development is underway actively to contribute significantly to the

[0003] However, transistors made of non-single crystal semiconductors have a higher threshold voltage and When the degradation of this transistor progresses, the driving circuit stops working. This causes a problem that the image cannot be displayed due to the difficulty in adjusting the brightness. The present invention discloses a shift register configuration that can suppress the degradation of transistors. In Patent Document 1, one electrode of the capacitance element is connected to a wiring to which a clock signal is input, The other electrode of the capacitance element is connected to the gates of the two transistors. The potential of the capacitor is increased or decreased in synchronization with the clock signal. Using this combination, a signal synchronized with the clock signal is generated at the gates of the two transistors. Then, a signal synchronized with this clock signal is used to control the on and off of the transistor. Then, the period during which the transistor is on and the period during which the transistor is off are repeated, so that deterioration of the transistor can be suppressed. [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-24350 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] However, in Patent Document 1, since the other electrode of the capacitive element is connected to the gates of two transistors, there is a problem that the parasitic capacitance of the node connected to the capacitive element increases. For this reason, there is a problem that the potential of the H level of the signal synchronized with the clock signal becomes low. In this case, when the threshold voltage of the transistor increases, there is a problem that the time when the transistor cannot turn on becomes earlier. That is, there is a problem that the life of the shift register becomes short. Or, since the parasitic capacitance connected to the capacitive element is large, there is a problem that the capacitance value of the capacitive element must be increased. For this reason, since it is necessary to increase the area where one electrode and the other electrode of the capacitive element overlap, there is a problem that the layout area of the capacitive element becomes large.

[0006] Or, in Patent Document 1, since it is necessary to increase the area of the capacitive element, there is a problem that one electrode and the other electrode are likely to be short-circuited by dust or the like. As a result, there are problems such as a decrease in yield and an increase in cost.

[0007] Alternatively, in Patent Document 1, since it is necessary to increase the capacitance value of the capacitive element, there is a problem that the delay or smear of the signal (for example, a clock signal or an inverted clock signal) supplied to the capacitive element increases. Or, there is a problem that the power consumption increases.

[0008] Alternatively, as a circuit that outputs a signal supplied to the capacitive element, since it is necessary to use a circuit having a large current driving ability, there is a problem that the external circuit (hereinafter also referred to as an external circuit) becomes large. Or, there is a problem that the display device becomes large.

[0009] Alternatively, in Patent Document 1, there is a period during which the gate of the pull-up transistor Tu is in a floating state. Therefore, the potential of the gate of the pull-up transistor Tu is not stable, and noise and the like occur. Therefore, there is a problem that the shift register malfunctions.

[0010] In view of the above problems, it is an object to reduce the number of transistors connected to the capacitive element. Or, it is an object to reduce the parasitic capacitance of the transistor connected to the capacitive element. Or, it is an object to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is an object to reduce the layout area. Or, it is an object to increase the lifespan. It is an object to reduce the delay or smear of the signal. Or, it is an object to reduce the power consumption. Or, it is an object to reduce the influence of noise. Also, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. The problems are as follows. Or, it is an object to reduce the current driving ability of an external circuit. Also it is an object to reduce the size of the external circuit. Or, it is an object to reduce the size of the display device The description of these problems does not prevent the existence of other problems.

Means for Solving the Problems

[0011] It has a capacitive element and one transistor. One electrode of the capacitive element is connected to a wiring, and the other electrode of the capacitive element is connected to the gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor via the capacitive element. Then, the conduction state of the transistor is controlled by a signal synchronized with the clock signal, and the transistor repeats a period of being on and a period of being off. Thus, deterioration of the transistor can be suppressed.

[0012] An exemplary aspect of the present invention has a driving circuit and a pixel. The pixel has a liquid crystal element, and the driving circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitive element. A first terminal of the first transistor is electrically connected to a first wiring, a second terminal of the first transistor is electrically connected to a second wiring, a first terminal of the second transistor is electrically connected to the second wiring, a second terminal of the second transistor is electrically connected to the gate of the first transistor, the gate of the second transistor is electrically connected to the first wiring, a first terminal of the third transistor is electrically connected to a third wiring, and the third transistor The second terminal of the transistor is electrically connected to the gate of the first transistor, and the The first terminal of the fourth transistor is electrically connected to the third wiring, and the fourth The second terminal of the transistor is electrically connected to the gate of the third transistor, and the The gate of the fourth transistor is electrically connected to the gate of the first transistor, One electrode of the capacitor element is electrically connected to the first wiring, and the other electrode of the capacitor element is electrically connected to the gate of the third transistor, which is a liquid crystal display device.

[0013] Note that switches can be of various forms. Examples include electrical switches and mechanical switches. That is, any device that can control the flow of current is acceptable and is not limited to a specific type. For example, as a switch, transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semicon ductor) diodes, diode-connected transistors, etc.) can be used. Or, a logic circuit combining these can be used as a switch.

[0014] Examples of mechanical switches include switches using MEMS (Micro-Electro-Mechanical System) technology, such as digital micromirror devices (DMDs).

[0015] Note that both N-channel transistors and P-channel transistors are used to form CMOS. An S-shaped switch may be used as the switch.

[0016] In addition, when it is explicitly described that A and B are connected, it shall include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, but shall also include those other than the connection relationship shown in the figure or the text. For example, as the case where A and B are electrically connected, one or more elements (for example, switches, transistors, capacitor elements, inductors, resistance elements, diodes, etc.) that enable the electrical connection between A and B may be connected between A and B. Alternatively, as the case where A and B are functionally connected, a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (circuit that can increase the signal amplitude or current amount, operational amplifier, differential amplification circuit, source follower circuit, buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between A and B may be connected between A and B. For example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, A and B are considered to be functionally connected.

[0017] ​​​​​​​​​​​​​​​​

[0018] In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected.

[0019] In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to electromagnetic action. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). ) and surface-conduction electron-emitter display (SED) flat panel displays, etc., display devices using liquid crystal elements, and as for display devices using liquid crystal elements, there are liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), and as for display devices using electronic ink or electrophoretic elements, there is electronic paper.

[0020] Note that a liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal, and is composed of a pair of electrodes and liquid crystal. Note that the optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Note that as liquid crystal elements, there are nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals, low molecular weight liquid crystals high molecular weight liquid crystals, polymer dispersed liquid crystals (PDLC), ferroelectric liquid crystals, antiferroelectric liquid crystals, main chain liquid crystals side chain type high molecular weight liquid crystals, plasma addressed liquid crystals (PALC), banana type liquid crystals, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Microcell) mode, ro-cell) mode, OCB (Optical Compensated Bire fringence) mode, ECB (Electrically Controlle d Birefringence) mode, FLC (Ferroelectric Li quid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Disperse d Liquid Crystal) mode, guest-host mode, blue Phase) mode, etc. can be used. However, it is not limited to this, and various types of liquid crystal elements can be used.

[0021] In addition, for display devices that require a light source, such as liquid crystal displays (transmissive liquid crystal displays , transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection type liquid crystal displays), display devices using a grating light valve (GLV), display devices using a digital micromirror device (DMD), etc., as the light source, electroluminescence, cold cathode tubes, hot cathode tubes, LEDs, laser light sources, mercury lamps, etc. can be used . However, it is not limited to this, and various types of light sources can be used .

[0022] In addition, as the transistor, various forms of transistors can be used. Therefore , there is no limitation on the type of transistor used. For example, thin film transistors (TFTs) having an amorphous semiconductor film represented by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used . can be achieved.

[0023] When manufacturing microcrystalline silicon, by using a catalyst (such as nickel), the crystallinity can be further improved, and it becomes possible to manufacture transistors with good electrical characteristics. At this time, without performing laser irradiation, it is also possible to improve the crystallinity only by applying heat treatment. As a result, a part of the source driver circuit (such as an analog switch) and the gate driver circuit (scanning line driving circuit) can be integrally formed on the substrate. Furthermore, when laser irradiation is not performed for crystallization, it is possible to suppress the unevenness of the crystallinity of silicon. Therefore, it is possible to display an image with improved image quality.

[0024] However, it is possible to manufacture polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

[0025] Alternatively, transistors can be formed using a semiconductor substrate, an SOI substrate, or the like. With these, transistors with little variation in characteristics, size, shape, etc., high current supply capacity, and small size can be manufactured. Using these transistors, it is possible to achieve low power consumption of the circuit or high integration of the circuit.

[0026] Alternatively, transistors having a compound semiconductor or an oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO can be used, and further, thin film transistors obtained by thinning these compound semiconductors or oxide semiconductors can be used. With these, the manufacturing temperature can be lowered, for example, it is possible to manufacture transistors at room temperature. As a result, it becomes possible to directly form transistors on substrates with low heat resistance, such as plastic substrates or film substrates. In addition to using these compound semiconductors or oxide semiconductors for the channel portion of the transistor, they can also be used for other applications. For example, these compound semiconductors or oxide semiconductors can be used as resistive elements, pixel electrodes, or electrodes with translucency. Moreover, since they can be formed simultaneously with the transistor or formed together, the cost can be reduced. Alternatively, it is possible to use transistors formed by inkjet or printing methods. With these methods, it becomes possible to manufacture at room temperature, at low vacuum, or on a large substrate.

[0027] Since it is possible to manufacture without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since there is no need to use a resist, the material cost can be reduced and the number of processes can be decreased. Moreover, since the film is applied only to the necessary parts, the material is not wasted and the cost can be reduced compared to the manufacturing method of etching after depositing the film over the entire surface. Alternatively, it is possible to use transistors having an organic semiconductor or carbon nanotubes. With these, it becomes possible to form transistors on a substrate that can be bent. A semiconductor device using such a substrate can be made resistant to impact. Furthermore, transistors with various structures can be used.

[0028] For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as the transistor. As a result, it becomes possible to form transistors on a substrate that can be bent. A semiconductor device using such a substrate can be made resistant to impact.

[0029] Furthermore, transistors with various structures can be used. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as the transistor. It becomes possible. By using MOS transistors, the size of the transistors can be reduced. It becomes possible. Therefore, a large number of transistors can be mounted. By using bipolar transistors, a large current can be made to flow. Therefore, the circuit can be operated at high speed.

[0030] Note that MOS transistors, bipolar transistors, etc. may be mixed and formed on a single substrate. Thereby, low power consumption, miniaturization, high-speed operation, etc. can be realized.

[0031] In addition, various transistors can be used.

[0032] Note that the transistors can be formed using various substrates. The type of substrate is not limited to a specific one. As the substrate, for example, a single-crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a stainless-steel substrate, a substrate having a stainless-steel foil, etc. can be used.

[0033] Note that the configuration of the transistors can take various forms and is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes can be applied. With a multi-gate structure, since the channel regions are connected in series, a configuration in which a plurality of transistors are connected in series is obtained.

[0034] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. Note that by adopting a configuration in which gate electrodes are arranged above and below the channel, a configuration in which a plurality of transistors are connected in parallel is obtained. ​​​​​​​​

[0035] A structure in which a gate electrode is disposed above the channel region, a structure in which a gate electrode is disposed below the channel region A structure, a positive stagger structure, a reverse stagger structure, a structure in which the channel region is divided into a plurality of regions A structure in which the channel regions are connected in parallel, or a configuration in which the channel regions are connected in series is also applicable. Further, a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof) is also applicable. Alternatively, a structure provided with an LDD region is applicable.

[0036] Note that various types of transistors can be used, and they can be formed using various substrates. Therefore, all of the circuits necessary to realize a predetermined function can be formed on the same substrate. For example, all of the circuits necessary to realize a predetermined function can be formed using various substrates such as a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. Alternatively, a part of the circuits necessary to realize a predetermined function can be formed on a certain substrate, and another part of the circuits necessary to realize a predetermined function can be formed on another substrate. That is, all of the circuits necessary to realize a predetermined function do not necessarily have to be formed using the same substrate. For example, a part of the circuits necessary to realize a predetermined function is formed by transistors on a glass substrate, and another part of the circuits necessary to realize a predetermined function is formed on a single crystal substrate. An IC chip composed of transistors formed using the single crystal substrate is connected to the glass substrate by COG (Chip On Glass), and the IC chip can be disposed on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate by TAB (Tape Automate On Glass) and the IC chip is disposed on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate by TAB (Tape Automate ​​​​​​​​​​​​It is also possible to connect the glass substrate using, for example, wire bonding or a printed circuit board. Alternatively, since the circuits in the portions with high drive voltage and high drive frequency consume a large amount of power, such circuits in those portions are not formed on the same substrate. Instead, for example, the circuit of that portion is formed on a single crystal substrate, and an IC chip composed of that circuit is used, so that an increase in power consumption can be prevented.

[0037] Note that a transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region, and current can flow through the drain region, the channel region, and the source region. Here, since the source and the drain change depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which is the source or the drain. Therefore, the regions that function as the source and the drain may not be called the source or the drain. In that case, as an example, they may be denoted as the first terminal and the second terminal, respectively. Alternatively, they may be denoted as the first electrode and the second electrode, respectively. Alternatively, there are cases where they are denoted as the first region and the second region.

[0038] Note that a transistor may be an element having at least three terminals including a base, an emitter, and a collector. Also in this case, the emitter and the collector may be denoted as the first terminal, the second terminal, etc.

[0039] Note that a semiconductor device refers to a device having a circuit including semiconductor elements (such as transistors, diodes, thyristors). Furthermore, a device that can function by utilizing semiconductor characteristics​ The whole may be referred to as a semiconductor device. Or, a device having a semiconductor material is called a semiconductor device as well.

[0040] Note that a display device refers to a device having display elements. Note that the display device may include a plurality of pixels including the display elements Note that the display device may include a peripheral drive circuit for driving the plurality of pixels Note that the peripheral drive circuit for driving the plurality of pixels may be formed on the same substrate as the plurality of pixels. Note that the display device may include a peripheral drive circuit arranged on the substrate by wire bonding, bumping, etc., that is, an IC chip connected by so-called chip on glass (COG) Note that the display device may include an IC chip, a resistor element, a capacitor element, an inductor, a transistor, etc. attached to a flexible printed circuit (FPC). Note that the display device may include a printed wiring board (PWB) to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, etc. are attached via a flexible printed circuit (FPC) or the like. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate Note that the display device may include an illumination device, a housing, an audio input / output device, an optical sensor, etc. Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc. Note that a light-emitting device refers to a device having a light-emitting element or the like. As a display element emitting Note that the display device may include a printed wiring board (PWB) to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, etc. are attached via a flexible printed circuit (FPC) or the like. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate Note that the display device may include an illumination device, a housing, an audio input / output device, an optical sensor, etc. Note that the display device may include an illumination device, a housing, an audio input / output device, an optical sensor, etc.

[0041] Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc. Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc. Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc.

[0042] Note that a light-emitting device refers to a device having a light-emitting element or the like. As a display element When the light emitting device has a light element, the light emitting device is a specific example of a display device.

[0043] The reflecting device is a device having a light reflecting element, a light diffractive element, a light reflecting electrode, etc. It is said.

[0044] Note that the liquid crystal display device refers to a display device having a liquid crystal element. There are direct-view, projection, transmissive, reflective, and semi-transmissive types.

[0045] In addition, a driving device refers to a device that has semiconductor elements, electric circuits, and electronic circuits. For example, a transistor that controls the input of a signal from a source signal line to a pixel (selection transistor) (sometimes called a transistor for switching, etc.) and supplies a voltage or current to the pixel electrode. The transistors that supply a voltage or current to the light-emitting element are Furthermore, a circuit for supplying a signal to the gate signal line (a gate driver, A circuit that supplies signals to the source signal lines (sometimes called a source line driver circuit, etc.) A pixel driver (sometimes called a pixel driver or a source line driver circuit) is an example of a driver device.

[0046] In addition, the present invention is applicable to display devices, semiconductor devices, lighting devices, cooling devices, light-emitting devices, reflecting devices, driving devices, etc. For example, a display device may include a semiconductor device and a light emitting device. Alternatively, the semiconductor device may include a display device and a driving device. This may be the case.

[0047] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed directly on A. If not, that is, it shall also include the case where another object is interposed between A and B. Here, it is assumed that A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers , etc.).

[0048] Therefore, for example, when it is explicitly described that layer B is formed on (or above) layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed on layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed on layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed on layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed on layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer.

[0049] Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to B being directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to B being directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to B being directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to B being directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to B being directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to B being directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to B being directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer.

[0050] In addition, when it is explicitly described that B is formed on A, on A, or above A, the case where B is formed obliquely above shall also be included. In addition, when it is explicitly described that B is formed on A, on A, or above A, the case where B is formed obliquely above shall also be included. In addition, when it is explicitly described that B is formed on A, on A, or above A, the case where B is formed obliquely above shall also be included.

[0051] In addition, the same applies to the case where B is under A or below A.

[0052] In addition, for those described explicitly as singular, it is desirable to be singular. . However, it is not limited thereto, and it is also possible to be plural. Similarly, for those described explicitly as plural, it is desirable to be plural. However, it is not limited thereto, and it is also possible to be singular.

[0053] In the figures, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0054] The figures schematically show ideal examples and are not limited to the shapes or values shown in the figures. For example, it can include variations in shape due to manufacturing techniques, variations in shape due to errors, signals, voltages, or current variations due to noise, or signal, voltage, or current variations due to timing deviations.

[0055] Technical terms are often used for the purpose of describing specific embodiments or examples, etc., and are not limited thereto.

[0056] For words not defined (including scientific and technical words such as technical terms or academic terms), they can be used with a meaning equivalent to the general meaning understood by those skilled in the art. Words defined by a dictionary, etc., are preferably interpreted in a meaning that does not conflict with the background of the related technology.

[0057] Terms such as first, second, third, etc., are used to describe various elements, members, regions, layers, areas separately from others. Therefore, terms such as first, second, third, etc., do not necessarily indicate any order or importance among the elements or parts. It does not limit the number of materials, regions, layers, areas, etc. Further, for example, "first" can be replaced with "second", "third", etc. It is possible to replace "second" or "third", etc.

Advantages of the Invention

[0058] The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or sag of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the degradation of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or sag of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the degradation of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller.

Brief Description of the Drawings

[0059]

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Embodiments for Carrying Out the Invention

[0060] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, this embodiment is not to be construed as being limited to the described content. In the configurations described below, the same reference numerals are used to denote the same components in different drawings, and detailed descriptions of the same parts or parts having the same function are omitted.

[0061] Note that the content described in one embodiment (even some of the content) can be applied to, combined with, or replaced with the content described in another part (even some of the content) described in that embodiment, and / or the content described in one or more other embodiments (even some of the content). That is, operations such as application, combination, or replacement can be performed.

[0062] Note that the content described in the embodiments refers to the content described using various drawings in each embodiment, or the content described using the text described in the specification. That is, it is the content described using the text described in the specification.

[0063] Note that the figure (which may be a part) described in a certain embodiment can be combined with another part of that figure, the figure (which may be a part) described in that embodiment, and / or one or more other figures (which may be a part) described in other embodiments to form even more figures.

[0064] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. Note that the semiconductor device can be referred to as a drive circuit or a flip-flop.

[0065] First, an example of the semiconductor device of this embodiment will be described with reference to FIG. 1(A). The semiconductor device in FIG. 1 (A) includes a circuit 100, transistors 101, 102, transistors 103, 104, a capacitive element 105, and a capacitive element 106. The transistors 101 to 104 are each assumed to be N-channel type, and are assumed to turn on when the potential difference (Vgs) between the gate and the source exceeds the threshold voltage (Vth). However, it is not limited to this, and the transistors 101 to 104 can each be P-channel type. A P-channel type transistor is assumed to turn on when the potential difference (Vgs ) between the gate and the source is lower than the threshold voltage (Vth).

[0066] The connection relationship of the semiconductor device in FIG. 1(A) will be described. The first terminal of the transistor 101 is connected to the wiring 123B, and the second terminal of the transistor 101 is connected to the wiring 121. The first terminal of the transistor 102 is connected to the gate of the transistor 101, and the second terminal of the transistor 102 is connected to the wiring 121, and the gate of the transistor 102 is connected to wiring 123C. The first terminal of transistor 103 is connected to wiring 122A continuously, and the second terminal of transistor 103 is connected to the gate of transistor 101 . The first terminal of transistor 104 is connected to wiring 122B, and the second terminal of transistor 104 is connected to the gate of transistor 103. One electrode of capacitor element 105 is connected to the gate of transistor 101, and the other electrode of capacitor element 105 is connected to wiring 12 1. One electrode of capacitor element 106 is connected to wiring 123, and the other electrode of capacitor element 10 6 is connected to the gate of transistor 103.

[0067] Note that the connection point of the gate of transistor 101, the first terminal of transistor 102, the second terminal of transistor 1 03, or the gate of transistor 104 is indicated as node A. Thus, the connection point of the gate of transistor 103, the second terminal of transistor 104, or the other electrode of capacitor element 106 is indicated as node B. However, it is possible to indicate node A and node B as wires. Note that it is possible to indicate wiring 121, wiring 123A, wiring 123B, wiring 123C, wiring 122A, wiring 1 22B as terminals.

[0068] Note that it is possible to input something (for example, a signal, a voltage, or a current, etc.) that can be input to each wiring (wiring 121, wiring 122A~122B, wiring 123A~123C). However, the content described below is an example and is not limited thereto. Various other things can be input to each wiring in addition to those described below, and each wiring can be in a floating state (hereinafter, a floating state).

[0069] An example of something (for example, a signal, a voltage, or a current, etc.) that can be input to each wiring (wiring 121, wiring 122A~122B, wiring 123A~123C) will be described. However, the content described below is an example and is not limited thereto. Various other things can be input to each wiring in addition to those described below, and each wiring can be in a floating state (hereinafter, a floating state). the content described below is an example and is not limited thereto. In addition to those described below, various other things can be input to each wiring, and each wiring can be in a floating state (hereinafter referred to as a floating state). It is possible.

[0070] As an example, it is assumed that a signal S1 is output from the wiring 121. Therefore, the wiring 121 can function as a signal line. In particular, when the wiring 121 is connected to a pixel or when the wiring 121 is arranged to extend into the pixel portion, the wiring 121 can function as a gate line, a scanning line, or a capacitance line. The signal S1 is an output signal of the semiconductor device and is often a digital signal having an H level and an L level, and can function as an output signal, a selection signal, a gate signal, or a scanning signal.

[0071] As an example, it is assumed that a voltage V1 is supplied to the wirings 122A to 122B. Therefore, the wirings 122A to 122B can function as power supply lines. The voltage V1 is often a value approximately equal to the L level of the signal S1 and can function as a ground voltage, a power supply voltage, or a negative power supply voltage. However, it is not limited thereto, and a signal such as a clock signal can be input to the wirings 122A to 122B. In this case, the wirings 12 2A to 122B can function as a signal line or a clock signal line. Also it is possible for different voltages or different signals to be input to the wirings 122A to 122B .

[0072] Note that "approximately" includes various errors such as errors due to noise, errors due to process variations, errors due to variations in the device fabrication process step, and / or measurement errors.

[0073] As an example, it is assumed that a signal S2 is input to the wirings 123A to 123C. Therefore, Wires 123A to 123C can function as signal lines. Signal S2 is often a digital signal that repeats between H level and L level at a constant period and can function as a clock signal (CK). However, it is not limited to this, and a power supply voltage can be supplied to wires 123A to 123C. In this case, wires 123A to 12 3C can function as power supply lines. Alternatively, different voltages or different signals can be input to wires 123A to 123B.

[0074] In this embodiment, as an example, let the potential of the L level of the signal be V1 and the potential of the H level of the signal be V2, and assume that V2 > V1. However, it is not limited to this.

[0075] Note that voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential). Therefore, it is possible to interchangeably refer to voltage, potential, and potential difference as potential, voltage, and voltage difference, respectively.

[0076] An example of the functions of circuit 100, transistors 101 to 104, capacitor element 105, and capacitor element 106 will be described. However, the content described below is an example and is not limited to this. Circuit 100 and each element may have various functions in addition to the functions described below, or may not have the functions described below.

[0077] Circuit 100 has a function of controlling the potential or state of node A and a function of controlling the potential or state of wiring 121. For example, circuit 100 has a function of increasing the potential of node A or the potential of wiring 12 1, and a function of decreasing the potential of node A or the potential of wiring 121. and / or has a function of floating node A or wiring 121. Tran The transistor 101 has a function of increasing the potential of wiring 12 1 in response to a signal (for example, signal S2) input to wiring 123B. The transistor 102 controls the timing at which wiring 121 and node A are conducted in response to a signal input to wiring 123C (for example, signal S2) and functions as a switch. The transistor 103 controls the timing at which wiring 122A and node A are conducted in response to the potential of node B and functions as a switch. The transistor 104 controls the timing at which wiring 122B and node B are conducted in response to the potential of node A and functions as a switch. The capacitor element 105 has a function of increasing the potential of node A in response to the potential of wiring 126 and / or a function of holding the potential difference between the gate and the second terminal of the transistor 101. The capacitor element 106 controls the potential of node B in response to a signal (for example, signal S2) input to wiring 123A.

[0078] Next, the operation of the semiconductor device in Fig. 1(A) will be described with reference to Figs. 1(B), 2(A) to (E). Fig. 1(B) is an example of a timing chart for explaining the operation of the semiconductor device and has periods T1, T2, T3, T4, and T5. And Fig. 1(B) shows the signal S1, signal S2, the potential Va of node A, and the potential Vb of node B. Fig. 2(A) shows a schematic diagram of the operation of the semiconductor device in Fig. 1(A) during period T1. Fig. 2(B) shows a schematic diagram of the operation of the semiconductor device in Fig. 1(A) during period T2. Fig. 2(C Fig. 1(A) shows a schematic diagram of the operation of the semiconductor device in period T4. Fig. 2(E) shows a schematic diagram of the operation of the semiconductor device in period T 5 of Fig. 1(A).

[0079] When the potential of node A rises, the semiconductor device sequentially performs the operations in period T1, period T2 operations, and operations in period T3. After that, until the potential of node A rises again the semiconductor device sequentially repeats the operations in period T4 and the operations in period T5 .

[0080] First, in period T1, signal S2 becomes the L level. Then, since transistor 102 turns off nodes A and 121 are in a non-conducting state. At the same time, the potential of node B decreases due to the capacitive coupling of capacitor element 106. When the potential of node B at this time is lower than the sum (V1 + V th106) of the potential of wiring 122A (V1) and the threshold voltage (Vth106) of transistor 103, transistor 103 turns off. Therefore, wiring 122A and node A are in a non-conducting state. On the other hand, circuit 100 starts to raise the potential of node A. When the potential of node A reaches the sum (V1 + Vth104) of the potential of wiring 122B (V1) and the threshold voltage (Vth104) of transistor 1 04, transistor 104 turns on. Then, wiring 122B and node B become conducting states. Thus voltage V1 is supplied from wiring 122B to node B, so the potential of node B becomes V1 and transistor 103 remains off, so wiring 122A and node A remain in a non-conducting state. Similarly, when the potential of node A reaches the sum (V1 + Vth101) of the potential of wiring 123B (V1) and the threshold voltage (Vth101) of transistor 101 and transistor 101 turns on, voltage V1 is supplied from wiring 123B to node B, so the potential of node B becomes V1 and transistor 103 remains off, so wiring 122A and node A remain in a non-conducting state. And when the potential of node A reaches the sum (V1 + Vth101) of the potential of wiring 123B (V1) and the threshold voltage (Vth101) of transistor 101 Meanwhile, transistor 101 turns on. Then, wiring 123B and wiring 121 become conductive. Therefore, an L-level signal S2 is supplied from wiring 123B to wiring 121. As a result, the potential of wiring 121 becomes approximately equal to the potential of wiring 123B (the L level of signal S2, or V1). After that, when the circuit 100 raises the potential of node A to a certain value (for example, V1 + Vth101 or higher and V2 or lower), the supply of the signal to node A is stopped. Therefore, the circuit 100 and node A become non-conductive. Thus, node A becomes a floating state, and the potential of node A is maintained at a high value. The potential difference between node A and wiring 121 at this time is held in the capacitive element 105. Note that during period T1, the circuit 100 can supply voltage V1 or an L-level signal to wiring 121. Alternatively, the circuit 100 can make the circuit 100 and wiring 121 non-conductive by not supplying a signal or the like to wiring 121.

[0081] Thus, the circuit 100 can make wiring 121 a floating state.

[0082] Next, during period T2, since the potential of node A is maintained at a high value, transistor 104 remains on. Therefore, wiring 122B and node B remain conductive, so the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. Similarly, since the potential of node A is maintained at a high value, transistor 101 remains on. Therefore, wiring 123B and wiring 121 remain conductive. At this time, whether signal S2 is at the L level or... It rises to the H level. Then, since the wiring 123B and the wiring 121 remain in a conductive state, the potential of the wiring 121 starts to rise. At the same time, since the transistor 102 turns on, the node A and the wiring 121 become conductive. However, when the potential of the wiring 121 rises to the value (V2 - Vth 102) obtained by subtracting the threshold voltage (Vth102) of the transistor 102 from the potential of the wiring 123C (V2), the transistor 102 turns off. Therefore, the wiring 121 and the node A become non-conductive. Here, the capacitive element 105 remains holding the potential difference between the wiring 1 21 and the node A during the period T1. Therefore, when the potential of the wiring 121 rises, the potential of the node A rises to V2 + Vth101 + α (α is a positive number) due to the capacitive coupling of the capacitive element 105. This is a so-called bootstrap operation. Therefore, the potential of the wiring 121 rises until it becomes equal to the potential of the wiring 123B (the H level of the signal S2, or V1).

[0083] Note that during the period T2, in many cases, the circuit 100 does not supply a signal or the like to the node A, so in many cases, the circuit 100 and the node A are in a non-conductive state. Thus, the circuit 100 often makes the node A in a floating state.

[0084] Note that during the period T2, in many cases, the circuit 100 does not supply a signal or the like to the wiring 121, so in many cases, the circuit 100 and the wiring 121 are in a non-conductive state.

[0085] Next, during the period T3, after the signal S2 decreases from the H level to the L level, the circuit 100 decreases the potential of the node A so as to be V1. Therefore, when the potential of the node A reaches the potential of the wiring ​Until the sum (V1 + Vth101) of the potential (V1) of 123B and the threshold voltage (Vth101) of transistor 101 is reached, transistor 101 is on. Therefore, since the signal S2 of the L level is supplied from wiring 123B to wiring 121, the potential of wiring 121 decreases to the potential (V1) of wiring 123B. Similarly, until the sum (V1 + Vth104) of the potential of node A and the threshold voltage (Vth104) of transistor 104 is reached, transistor 104 is on. Therefore, since voltage V1 is supplied from wiring 122B to node B, the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. Until the sum (V1 + Vth101) of the potential (V1) of 123B and the threshold voltage (Vth101) of transistor 101 is reached, transistor 101 is on. Therefore, since the signal S2 of the L level is supplied from wiring 123B to wiring 121, the potential of wiring 121 decreases to the potential (V1) of wiring 123B. Until the sum (V1 + Vth101) of the potential (V1) of 123B and the threshold voltage (Vth101) of transistor 101 is reached, transistor 101 is on. Therefore, since the signal S2 of the L level is supplied from wiring 123B to wiring 121, the potential of wiring 121 decreases to the potential (V1) of wiring 123B. Similarly, until the sum (V1 + Vth104) of the potential of node A and the threshold voltage (Vth104) of transistor 104 is reached, transistor 104 is on. Therefore, since voltage V1 is supplied from wiring 122B to node B, the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. Until the sum (V1 + Vth101) of the potential (V1) of 123B and the threshold voltage (Vth101) of transistor 101 is reached, transistor 101 is on. Therefore, since the signal S2 of the L level is supplied from wiring 123B to wiring 121, the potential of wiring 121 decreases to the potential (V1) of wiring 123B. Similarly, until the sum (V1 + Vth104) of the potential of node A and the threshold voltage (Vth104) of transistor 104 is reached, transistor 104 is on. Therefore, since voltage V1 is supplied from wiring 122B to node B, the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. Until the sum (V1 + Vth104) of the potential of node A and the threshold voltage (Vth104) of transistor 104 is reached, transistor 104 is on. Therefore, since voltage V1 is supplied from wiring 122B to node B, the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. Until the sum (V1 + Vth104) of the potential of node A and the threshold voltage (Vth104) of transistor 104 is reached, transistor 104 is on. Therefore, since voltage V1 is supplied from wiring 122B to node B, the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. Until the sum (V1 + Vth104) of the potential of node A and the threshold voltage (Vth104) of transistor 104 is reached, transistor 104 is on. Therefore, since voltage V1 is supplied from wiring 122B to node B, the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106.

[0086] During period T3, circuit 100 can supply voltage V1 or an L-level signal to wiring 121. Alternatively, circuit 100 can make circuit 100 and wiring 121 non-conductive by not supplying a signal or the like to wiring 121. Thus, circuit 100 can make wiring 121 in a floating state. During period T3, circuit 100 can supply voltage V1 or an L-level signal to wiring 121. Alternatively, circuit 100 can make circuit 100 and wiring 121 non-conductive by not supplying a signal or the like to wiring 121. Thus, circuit 100 can make wiring 121 in a floating state. During period T3, circuit 100 can supply voltage V1 or an L-level signal to wiring 121. Alternatively, circuit 100 can make circuit 100 and wiring 121 non-conductive by not supplying a signal or the like to wiring 121. Thus, circuit 100 can make wiring 121 in a floating state. During period T3, circuit 100 can supply voltage V1 or an L-level signal to wiring 121. Alternatively, circuit 100 can make circuit 100 and wiring 121 non-conductive by not supplying a signal or the like to wiring 121. Thus, circuit 100 can make wiring 121 in a floating state.

[0087] Next, during period T4, signal S2 rises from the L level to the H level. At this time, since the potential of node A remains at V1, transistors 101 and 104 remain off. Therefore, since node B remains in a floating state, the potential of node B rises due to the capacitive coupling of capacitor element 106. When the potential of node B reaches the potential (V1) of wiring 122A Next, during period T4, signal S2 rises from the L level to the H level. At this time, since the potential of node A remains at V1, transistors 101 and 104 remain off. Therefore, since node B remains in a floating state, the potential of node B rises due to the capacitive coupling of capacitor element 106. Next, during period T4, signal S2 rises from the L level to the H level. At this time, since the potential of node A remains at V1, transistors 101 and 104 remain off. Therefore, since node B remains in a floating state, the potential of node B rises due to the capacitive coupling of capacitor element 106. When the potential of node B reaches the potential (V1) of wiring 122A Next, during period T4, signal S2 rises from the L level to the H level. At this time, since the potential of node A remains at V1, transistors 101 and 104 remain off. Therefore, since node B remains in a floating state, the potential of node B rises due to the capacitive coupling of capacitor element 106. When the potential of node B reaches the potential (V1) of wiring 122A Higher than the sum (V1 + Vth103) with the threshold voltage (Vth103) of transistor 103 If it becomes higher, transistor 103 turns on. Then, wiring 122A and node A become conductive. Therefore, since voltage V1 is supplied from wiring 122A to node A, the potential of node A is maintained at V1. At the same time, since transistor 102 turns on, wiring 121 and node A become conductive. At this time, voltage V1 is supplied to node A from wiring 122 A. Therefore, voltage V1 is supplied from wiring 122A to wiring 121, and the potential of wiring 121 is maintained at V1.

[0088] Note that in period T4, circuit 100 can supply voltage V1, or a signal of L level, etc. to node A. Or, circuit 100 can make circuit 100 and node A non-conductive by not supplying a signal or the like to node A. And, circuit 100 can make node A in a floating state.

[0089] Note that in period T5, circuit 100 can supply voltage V1, or a signal of L level, etc. to wiring 121. Or, circuit 100 can make circuit 100 and wiring 121 non-conductive by not supplying a signal or the like to wiring 121. Then, circuit 100 can make wiring 121 in a floating state.

[0090] Next, in period T5, signal S2 decreases from the H level to the L level. At this time, since the potential of node A remains at V1, transistors 101 and 104 remain off. Therefore, the potential of node B decreases due to the capacitive coupling of capacitor element 106. When the potential of node B becomes lower than the sum (V1 + Vth103) of the potential of wiring 122A (V1) and the threshold voltage (Vth103) of transistor 103, transistor 103 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. 3 turns off. Thus, wiring 122A and node A are in a non-conducting state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conducting state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, even when circuit 100 does not supply an L-level signal or voltage V1 to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1.

[0091] In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitor element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitor element 106, that is, the parasitic capacitance of node B can be reduced. Note that the parasitic capacitance refers to the combined capacitance of the gate capacitance of the transistor, the parasitic capacitance between the gate and the source of the transistor, the parasitic capacitance between the gate and the drain of the transistor, and / or the wiring capacitance, etc. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitor element 106. In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitor element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitor element 106, that is, the parasitic capacitance of node B can be reduced. Note that the parasitic capacitance refers to the combined capacitance of the gate capacitance of the transistor, the parasitic capacitance between the gate and the source of the transistor, the parasitic capacitance between the gate and the drain of the transistor, and / or the wiring capacitance, etc. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitor element 106. In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitor element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitor element 106, that is, the parasitic capacitance of node B can be reduced. Note that the parasitic capacitance refers to the combined capacitance of the gate capacitance of the transistor, the parasitic capacitance between the gate and the source of the transistor, the parasitic capacitance between the gate and the drain of the transistor, and / or the wiring capacitance, etc. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitor element 106. In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitor element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitor element 106, that is, the parasitic capacitance of node B can be reduced. Note that the parasitic capacitance refers to the combined capacitance of the gate capacitance of the transistor, the parasitic capacitance between the gate and the source of the transistor, the parasitic capacitance between the gate and the drain of the transistor, and / or the wiring capacitance, etc. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitor element 106. In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitor element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitor element 106, that is, the parasitic capacitance of node B can be reduced. Note that the parasitic capacitance refers to the combined capacitance of the gate capacitance of the transistor, the parasitic capacitance between the gate and the source of the transistor, the parasitic capacitance between the gate and the drain of the transistor, and / or the wiring capacitance, etc. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitor element 106. In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitor element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitor element 106, that is, the parasitic capacitance of node B can be reduced. Note that the parasitic capacitance refers to the combined capacitance of the gate capacitance of the transistor, the parasitic capacitance between the gate and the source of the transistor, the parasitic capacitance between the gate and the drain of the transistor, and / or the wiring capacitance, etc. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitor element 106. In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitor element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitor element 106, that is, the parasitic capacitance of node B can be reduced. Note that the parasitic capacitance refers to the combined capacitance of the gate capacitance of the transistor, the parasitic capacitance between the gate and the source of the transistor, the parasitic capacitance between the gate and the drain of the transistor, and / or the wiring capacitance, etc. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitor element 106.

[0092] Alternatively, in the semiconductor device of FIG. 1(A), since the parasitic capacitance of node B can be reduced, the capacitance value of the capacitor element 106 can be made smaller than that of the conventional technology. Therefore, the capacitor element Alternatively, in the semiconductor device of FIG. 1(A), since the parasitic capacitance of node B can be reduced, the capacitance value of the capacitor element 106 can be made smaller than that of the conventional technology. Therefore, the capacitor element Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent the short circuit between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of the signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of the external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on-resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104 can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent the short circuit between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of the signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of the external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on-resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent the short circuit between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of the signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of the external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104

[0093] Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on-resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104 can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent the short circuit between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of the signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of the external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on-resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent the short circuit between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of the signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of the external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104

[0094] Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104 can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent the short circuit between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of the signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of the external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. It can be lowered. As a result, the characteristics of transistor 101 and transistor 104 can be suppressed from deteriorating. Or, it can be suppressed that transistor 101 and transistor 104 are destroyed. Or, as the transistor, a transistor with a thin gate insulating film and improved mobility can be used. When using such a transistor, the channel width (W) of the transistor can be made smaller. Therefore, the layout area can be reduced.

[0095] Or, in the semiconductor device of FIG. 1(A), it is possible to make all the transistors N-channel type or all the transistors P-channel type. Therefore, compared with a CMOS circuit, the number of processes can be reduced, the yield can be improved, or the cost can be reduced. In particular, when all the transistors are N-channel type, as the semiconductor layer of the transistor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor can be used. Therefore, the number of processes can be reduced, the yield can be improved, or the cost can be reduced, etc. However, it is not limited to this, and the semiconductor device of FIG. 1(A) can be configured by a CMOS circuit combining a P-channel type transistor and an N -channel type transistor.

[0096] Or, in the semiconductor device of FIG. 1(A), in at least one of period T4 and period T5, transistors 101 to 104 are turned off. Therefore, since the transistors do not stay on throughout one operation period, it is possible to suppress the deterioration of the characteristics of the transistors such as the increase in the threshold voltage or the decrease in the mobility.

[0097] In particular, when using an amorphous semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor as the semiconductor layer of the transistor, the characteristic degradation of the transistor becomes remarkable. However, in the semiconductor device of Fig. 1(A), since the characteristic degradation of the transistor can be suppressed, an amorphous semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor can be used as the semiconductor layer of the transistor. However, it is not limited thereto, and a polycrystalline semiconductor or single-crystalline semiconductor can be used as the semiconductor layer.

[0098] Note that the period T2 can be indicated as the selection period, and the other periods (period T1, period T3, period T4, and period T5) can be indicated as non-selection periods. Or, period T1, period T2, period T3, period T4, and period T5 can be indicated as a set period, an output period, a reset period, a first non-selection period, and a second non-selection period, respectively.

[0099] Note that the channel width (W) of transistor 101 can be larger than the channel widths of transistor 102, transistor 1 03, and / or transistor 104. Or, among the transistors included in the semiconductor device, the channel width of transistor 101 can be the largest. In this case, since the on-resistance of transistor 101 becomes small, the rise time and fall time of the signal output from wiring 121 (for example, signal S1) become short. Therefore, in period T2, the timing at which transistor 102 turns off becomes earlier. Thus, it is possible to suppress the potential of node A from decreasing too much and the semiconductor device from malfunctioning. However, it is not limited thereto, and the channel width of transistor 101 ... ... is smaller than the channel width of any one of transistors 102 to 104, or smaller than the channel width of any one of the transistors included in the semiconductor device. It is possible.

[0100] Note that when referring to the channel width of a transistor, it can be rephrased as the W / L (L: channel length) ratio of the transistor. It is possible.

[0101] Note that the L-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be lower than V1. In this case, since a reverse bias can be applied to the transistor, deterioration of the transistor characteristics can be mitigated. In particular, since the time when transistor 102 is turned on is long, the L-level potential of the signal input to wiring 123C is preferably lower than V1. However, it is not limited to this, and the L-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V1. It is possible. It is possible. In particular, since the time when transistor 102 is turned on is long, the L-level potential of the signal input to wiring 123C is preferably lower than V1. However, it is not limited to this, and the L-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V1. It is possible. It is possible.

[0102] Note that the H-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be lower than V2. In this case, since the Vgs of the transistor becomes small, deterioration of the transistor characteristics can be suppressed. In particular, since the time when transistor 102 is turned on is long, the H-level potential of the signal input to wiring 123C is preferably lower than V2. However, it is not limited to this, and the H-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V2. It is possible. It is possible. In particular, since the time when transistor 102 is turned on is long, the H-level potential of the signal input to wiring 123C is preferably lower than V2. However, it is not limited to this, and the H-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V2. It is possible. It is possible.

[0103] Note that the amplitude of the signal input to wiring 123A, wiring 123B, and / or wiring 123C The voltage can be smaller than V2 - V1. In particular, since the time for transistor 103 to turn on is long, it is preferable to make the amplitude of the signal input to wiring 123A smaller than V2 - V1. Thus, the Vgs of transistor 103 can be made small, and deterioration of the characteristics of transistor 103 can be suppressed. However, it is not limited to this. The amplitude voltage of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be larger than V2 - V1.

[0104] Note that it is possible to input a signal to wiring 122A and / or wiring 122B. In this way, since voltage V1 can be omitted, the number of power supplies can be reduced. Or, since a reverse bias can be applied to the transistor, deterioration of the characteristics of the transistor can be alleviated. In particular, to wiring 122A, it is possible to input a signal that becomes an L level during the period when transistor 103 is on (for example, period T1, period T3, period T5). As an example, there is an inverted signal of signal S2 (hereinafter, also referred to as an inverted clock signal). To wiring 122B, it is possible to input a signal that becomes an L level during the period when transistor 104 is on (for example, period T3, period T4, period T5).

[0105] Note that it is possible to supply a voltage (for example, voltage V2 ) to wiring 123A, wiring 123B, and / or wiring 123C. By doing so, the semiconductor device can function as an inverter circuit , or a buffer circuit.

[0106] Note that, as shown in FIG. 3(A), since the same voltage (e.g., voltage V1) is often supplied to wiring 122A and wiring 122B, it is possible to share wiring 122A and wiring 122B. For this reason, the first terminal of transistor 103 and the first terminal of transistor 104 are connected to wiring 122. Wiring 122 corresponds to wiring 122A or wiring 122B, and it is possible to input the same as these wirings to wiring 122.

[0107] Note that sharing a plurality of wirings means connecting the elements or circuits connected to the plurality of wirings to the same wiring. Or it means connecting the plurality of wirings to each other.

[0108] Note that, as shown in FIG. 3(B), since the same signal (e.g., signal S2) is often input to wirings 123A to 123C, it is possible to share wirings 123A to 123C. For this reason, the first terminal of transistor 101, the gate of transistor 102, and one electrode of capacitor element 106 are connected to wiring 123. Wiring 123 corresponds to wirings 123A to 123C, and it is possible to input the same as these wirings to wiring 123. However, it is not limited to this, and it is possible to share only any two or more of wirings 123A to 123C.

[0109] Note that, similar to FIG. 3(B), in FIG. 3(A) as well, it is possible to share wirings 123A to 123C.

[0110] Note that, as shown in FIG. 3(C), by combining FIG. 3(A) and FIG. 3(B), wiring 122 ​​​​​​​​​​​​​It is possible to share A and wiring 122B, and further share wirings 123A to 123C. For example, the first terminal of transistor 103 and the first terminal of transistor 104 are connected to wiring 122, and the first terminal of transistor 101, the gate of transistor 102 and one electrode of capacitor element 106 can be connected to wiring 123.

[0111] In addition, as shown in Fig. 3(D), the gate of transistor 104 can be connected to wiring 121. By connecting the gate of transistor 104 to wiring 121, when transistor 104 is turned on, the gate voltage becomes V1, which is lower than the gate voltage (V1 + Vth101 + α) when transistor 104 is turned on in Fig. 1(A). Therefore, breakdown of transistor 104 or deterioration of the characteristics of transistor 104 can be suppressed.

[0112] Similar to Fig. 3(D), in Figs. 3(A) to (C) as well, the gate of transistor 104 can be connected to wiring 121.

[0113] In addition, as shown in Fig. 3(E), the second terminal of transistor 103 can be connected to wiring 121. By connecting the second terminal of transistor 103 to wiring 121, during period T4, voltage V1 is supplied from wiring 122A to wiring 121, so it becomes easier to maintain the potential of wiring 121 at V1.

[0114] Similar to Fig. 3(E), in Figs. 3(A) to (D) as well, the second terminal of transistor 103 can be connected to wiring 121. ​​​

[0115] Incidentally, as shown in FIG. 4(A), it is possible to omit the capacitive element 105. In this case , the parasitic capacitance between the gate of the transistor 101 and the second terminal can be used as the capacitive element 105 .

[0116] Incidentally, in FIG. 4(A), when the parasitic capacitance between the gate of the transistor 101 and the second terminal is used as the capacitive element 105, in the transistor 101, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal . Therefore, in the transistor 101, the overlapping area between the conductive layer functioning as the gate electrode and the conductive layer functioning as the source electrode or the drain electrode is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto .

[0117] Incidentally, similar to FIG. 4(A), in FIGS. 3(A) to 3(E) as well, it is possible to omit the capacitive element 105 .

[0118] Incidentally, as shown in FIG. 4(B), it is possible to use a MOS capacitor as the capacitive element 105 . In an example of FIG. 4(B), a transistor 105a is used as the capacitive element 105 . The transistor 105a is of the N-channel type. The first terminal and the second terminal of the transistor 105a are connected to the wiring 121, and the gate of the transistor 105a is connected to the node A. By doing so, during the periods (periods T1 and T2) when it is necessary to function as a capacitive element, since the potential of the node A is high, the gate capacitance of the transistor 105a can be increased. On the other hand, during the periods when it is not necessary to function as a capacitive element (for example ), the potential of the node A is high, so the gate capacitance of the transistor 105a can be increased. On the other hand, during the periods when it is not necessary to function as a capacitive element (for example ), ​​During periods T3, T4, and T5, since the potential of node A is low, the gate capacitance of transistor 105 a can be reduced. However, it is not limited to this. Transistor 1 05a can be of P-channel type. Or, one of the first terminal and the second terminal of transistor 105a can be in a floating state. Or, the gate of transistor 105a is connected to wiring 121, and the first terminal and the second terminal of transistor 105a can be connected to node A. Or, impurities can be added to the channel region of transistor 105a.

[0119] Similar to FIG. 4(B), in FIGS. 3(A) to (E) and FIG. 4(A) as well, transistor 105a can be used as capacitor element 105, and the first terminal and the second terminal of transistor 105a are connected to wiring 121, and the gate of transistor 105a is connected to node A. This is possible.

[0120] As shown in FIG. 4(C), it is possible to use a MOS capacitor as capacitor element 106. In an example of FIG. 4(C), transistor 106a is used as capacitor element 106. Transistor 106a is of N-channel type. The first terminal and the second terminal of transistor 106a are connected to node B, and the gate of transistor 106a is connected to wiring 123A. However, it is not limited to this. Transistor 106a can be of P-channel type. Or, one of the first terminal and the second terminal of transistor 106a can be in a floating state. Or, the gate of transistor 106a is connected to node B and the first terminal and the second terminal of transistor 106a are connected to wiring 123A.​ It is possible. Or, impurities can be added to the channel region of the transistor 106a It is possible.

[0121] Similar to FIG. 4(C), in FIGS. 3(A) to (E) and FIGS. 4(A) to (B) as well, the transistor 106a is used as the capacitor element 106, and the first terminal of the transistor 106a and the second terminal are connected to the node B, and the gate of the transistor 106a can be connected to the wiring 123A It is possible.

[0122] Similar to FIG. 4(D), the transistor 103 can be replaced with the diode 103a The diode 103a corresponds to the transistor 103. And the diode 103a has a function of reducing the potential of the node A when the potential of the node B is lower than the potential of the node A, and a function of making the node A and the node B in a non-conducting state when the potential of the node B is higher than the potential of the node A. One terminal of the diode 103a (hereinafter also referred to as the input terminal or the anode) is connected to the node A, and the other terminal of the diode 103a (hereinafter also referred to as the output terminal or the cathode) is connected to the node B. (hereinafter also referred to as the output terminal or the cathode) is connected to the node B.

[0123] In FIG. 4(D), when the transistor 103 is replaced with the diode 103a the voltage V2 can be supplied to the wiring 122B. Or, an inverted signal of the signal S2 (for example, an inverted clock signal) can be input to the wiring 123A It is possible.

[0124] Similar to FIG. 4(D), in FIGS. 3(A) to (E) and FIGS. 4(A) to (C) as well, the transistor 103 is replaced with the diode 103a, and one terminal of the diode 103a It is possible that one terminal of the diode 103a is connected to the node A and the other terminal of the diode 103a is connected to the node B. It is possible.

[0125] As shown in Fig. 4(E), it is possible to replace the transistor 104 with a diode 104a. In an example of Fig. 4(E), an example is shown in the case where not only the transistor 104 but also the transistor 103 is replaced with a diode. The diode 104a corresponds to the transistor 104. And the diode 104a has a function of raising the potential of the node B when the potential of the node A is higher than the potential of the node B, and a function of making the nodes A and B in a non-conductive state when the potential of the node A is lower than the potential of the node B. One terminal of the diode 104a is connected to the node A, and the other terminal of the diode 104a is connected to the node B. It is possible. An example is shown in the case where not only the transistor 104 but also the transistor 103 is replaced with a diode. The diode 104a corresponds to the transistor 104. And the diode 104a has a function of raising the potential of the node B when the potential of the node A is higher than the potential of the node B, and a function of making the nodes A and B in a non-conductive state when the potential of the node A is lower than the potential of the node B. One terminal of the diode 104a is connected to the node A, and the other terminal of the diode 104a is connected to the node B. It is possible that one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B. It is possible that one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B. It is possible that one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B. It is possible that one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B. It is possible that one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B.

[0126] Similar to Fig. 4(E), in Figs. 3(A) to (E) and Figs. 4(A) to (D) as well, it is possible to replace the transistor 104 with a diode 104a, and one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B. Similar to Fig. 4(E), in Figs. 3(A) to (E) and Figs. 4(A) to (D) as well, it is possible to replace the transistor 104 with a diode 104a, and one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B. Similar to Fig. 4(E), in Figs. 3(A) to (E) and Figs. 4(A) to (D) as well, it is possible to replace the transistor 104 with a diode 104a, and one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B. It is possible that one terminal of the diode 104a is connected to the node A and the other terminal of the diode 104a is connected to the node B.

[0127] As shown in Fig. 4(F), it is possible to use a diode-connected transistor as a diode. The diode-connected transistor 103 and the diode-connected transistor 104 respectively correspond to the diodes 103a and 104a. The first terminal of the transistor 103 is connected to the node B, and the second terminal and the gate of the transistor 103 are connected to the node A. The first terminal and the gate of the transistor 104 are connected to the node A. As shown in Fig. 4(F), it is possible to use a diode-connected transistor as a diode. The diode-connected transistor 103 and the diode-connected transistor 104 respectively correspond to the diodes 103a and 104a. The first terminal of the transistor 103 is connected to the node B, and the second terminal and the gate of the transistor 103 are connected to the node A. The first terminal and the gate of the transistor 104 are connected to the node A. As shown in Fig. 4(F), it is possible to use a diode-connected transistor as a diode. The diode-connected transistor 103 and the diode-connected transistor 104 respectively correspond to the diodes 103a and 104a. The first terminal of the transistor 103 is connected to the node B, and the second terminal and the gate of the transistor 103 are connected to the node A. The first terminal and the gate of the transistor 104 are connected to the node A. As shown in Fig. 4(F), it is possible to use a diode-connected transistor as a diode. The diode-connected transistor 103 and the diode-connected transistor 104 respectively correspond to the diodes 103a and 104a. The first terminal of the transistor 103 is connected to the node B, and the second terminal and the gate of the transistor 103 are connected to the node A. The first terminal and the gate of the transistor 104 are connected to the node A. As shown in Fig. 4(F), it is possible to use a diode-connected transistor as a diode. The diode-connected transistor 103 and the diode-connected transistor 104 respectively correspond to the diodes 103a and 104a. The first terminal of the transistor 103 is connected to the node B, and the second terminal and the gate of the transistor 103 are connected to the node A. The first terminal and the gate of the transistor 104 are connected to the node A. One end is connected to node A, and the second terminal of transistor 104 is connected to node B. However, without being limited thereto, the gate of transistor 103 can be connected to node B, and the gate of transistor 104 can be connected to node B.

[0128] Similar to FIG. 4(F), in FIGS. 3(A) to (E) and FIGS. 4(A) to (E) as well, the first terminal of transistor 103 can be connected to node B, the second terminal of transistor 103 can be connected to node A, and the gate of transistor 103 can be connected to node A. Alternatively, the first terminal of transistor 104 can be connected to node A, the second terminal of transistor 104 can be connected to node B, and the gate of transistor 104 can be connected to node A. However, without being limited thereto, the gate of transistor 103 can be connected to node B, and the gate of transistor 104 can be connected to node B. is possible.

[0129] In addition, as shown in FIG. 5(A), it is possible to newly add diode 107. When an L-level signal is input to wiring 123A, diode 107 has a function of reducing the potential of node B, and when an H-level signal is input to wiring 123A, it has a function of making wiring 12 3A and node B non-conductive. One terminal of diode 107 is connected to node B, and the other terminal of diode 107 is connected to wiring 123A. However without being limited thereto, the other terminal of diode 107 can be connected to a wiring different from wiring 123A. is possible.

[0130] Similar to FIG. 5(A), in FIGS. 3(A) to (E) and FIGS. 4(A) to (F) as well, A new diode 107 is added, and one terminal of the diode 107 is connected to node B , and the other terminal of the diode 107 can be connected to the wiring 123A.

[0131] In addition, as shown in Fig. 5(B), it is possible to newly add a transistor 107a connected by a diode. The transistor 107a connected by a diode corresponds to the diode 1 07 and is of the N-channel type. The first terminal of the transistor 107a is connected to the wiring 123 A, and the second terminal and the gate of the transistor 107a are connected to node B . However, it is not limited thereto, and the transistor 107a can be of the P-channel type . Or, the gate of the transistor 107a can be connected to the wiring 123A .

[0132] In addition, similar to Fig. 5(B), in Figs. 3(A) to (E), Figs. 4(A) to (F), and Fig. 5(A) , it is also possible to newly add a transistor 107a, and the first terminal of the transistor 107a is connected to the wiring 123A, and the second terminal and the gate of the transistor 107a are connected to node B . However, it is not limited thereto, and the gate of the transistor 107a can be connected to node B.

[0133] In addition, as shown in Fig. 5(C), it is possible to omit the transistor 102.

[0134] In addition, similar to Fig. 5(C), in Figs. 3(A) to (E), Figs. 4(A) to (F), and Fig. 5(A) to (B), it is also possible to omit the transistor 102.

[0135] Note that, as shown in FIG. 5(D), it is possible to omit circuit 100.

[0136] Note that, similar to FIG. 5(D), in FIGS. 3(A) to (E), FIGS. 4(A) to (F), and FIG. 5(A) to (C) as well, it is possible to omit circuit 100.

[0137] Note that, as shown in FIG. 5(E), transistors 101, 102, transistors 103, and transistor 104 can be replaced with transistors 101p, 102p, t ransistors 103p, and transistor 104p. Transistors 101p to 104p each c orrespond to transistors 101 to 104 and are assumed to be P-channel type.

[0138] Note that in FIG. 5(E), the potential relationships are often opposite to those of the semiconductor device in FIG. 1(A). For example, voltage V2 can be supplied to wirings 122A to 122B, and an inverted signal of signal S2 can be input to wirings 123A to 123B. Similarly, an inverted signal of signal S1 is often output from wiring 121 .

[0139] Note that in FIG. 5(E), circuit 100 often has a function of decreasing the potential of node A during period T1. Or, circuit 100 often has a function of increasing the potential of node A to V2 during period T3.

[0140] Note that, similar to FIG. 5(E), in FIGS. 3(A) to (E), FIGS. 4(A) to (F), and FIG. 5(A) to (D) as well, P-channel type transistors can be used as transistors 101 to 104.

[0141] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. The semiconductor device of this embodiment is a specific example of the semiconductor device described in Embodiment 1. In particular, in this embodiment, the specific example of circuit 100 will be described. Note that the content described in Embodiment 1 can be applied to the semiconductor device of this embodiment.

[0142] A specific example of circuit 100 will be described with reference to FIG. 6(A). However, FIG. 6(A) is only an example and is not limited thereto. As circuit 100, various configurations of circuits other than those in FIG. 6(A) can be used. Note that the same parts as those in FIG. 1(A) are denoted by the same reference numerals, and the description thereof will be omitted.

[0143] Circuit 100 includes transistor 131, transistor 132, transistor 133, transistor 134, and transistor 135. Transistors 131 to 135 are each assumed to be N-channel type. However, transistors 131 to 135 can be P-channel type.

[0144] The connection relationship of the transistors included in circuit 100 will be described. The first terminal of transistor 131 is connected to wiring 125, the second terminal of transistor 131 is connected to node A, and the gate of transistor 131 is connected to wiring 125. The first terminal of transistor 132 is connected to wiring 125, the second terminal of transistor 132 is connected to node A, and the gate of transistor 132 is connected to wiring 124A. The first terminal of transistor 133 is connected to wiring 122E, the second terminal of transistor 133 is connected to wiring 121, is connected, and the gate of transistor 133 is connected to wiring 124B. The first terminal of transistor 134 is connected to wiring 122C, and the second terminal of transistor 134 is connected to node A is continued, and the gate of transistor 134 is connected to wiring 126. The first terminal of transistor 135 is connected to wiring 122D, and the second terminal of transistor 135 is connected to wiring 121 is connected, and the gate of transistor 135 is connected to wiring 126.

[0145] An example of something (such as a signal, voltage, or current) that can be input to wirings 122C to 122E, wirings 124A to 124B, wiring 125, and wiring 126 will be described. However, the content described below is an example and is not limited thereto. Various things other than those described below can be input to each wiring, and each wiring can be in a floating state (hereinafter, floating state). state). Let it be assumed that a voltage V1 is supplied to wirings 122C to 122E in the same manner as wirings 122A and 122B. Therefore, wirings 122C to 122E can function as power supply lines. However, it is not limited to this, and any signal such as a clock signal can be input to wirings 122C to 122E. In this case, wirings 122C to 122E can function as signal lines. Or, different voltages can be supplied to wirings 122C to 122E.

[0146] Let it be assumed that a voltage V1 is supplied to wirings 122C to 122E, similar to wirings 122A and 122B. Thus, wirings 122C to 122E can function as power supply lines. However, it is not limited to this, and any signal, such as a clock signal, can be input to wirings 122C to 122E. In this case, wirings 122C to 122E can function as signal lines. Or, different voltages can be supplied to wirings 122C to 122E.

[0147] As an example, let it be assumed that a signal S3 is input to wirings 124A to 124B. Thus, wirings 124A to 124B can function as signal lines. Signal S3 ​​​​​​​In many cases, it is a signal that is the inverted signal of signal S2 or a signal whose phase is approximately 180° offset from signal S2, and it can function as an inverted clock signal (CKB). However, it is not limited to this, and it is possible to supply voltage to wirings 124A to 124B. In this case, wirings 124A to 124B can function as power supply lines. Or, it is possible to input different signals to wirings 124A to 124B. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line.

[0148] For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. For example, let's assume that signal S4 is input to wiring 125. Therefore, wiring 125 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line.

[0149] For example, let's assume that signal S5 is input to wiring 126. Therefore, wiring 126 can function as a signal line. Signal S5 is often a digital signal having an L level and an H level, and functions as a reset signal (RE) or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 126. In this case, wiring 126 can function as a power supply line. For example, let's assume that signal S5 is input to wiring 126. Therefore, wiring 126 can function as a signal line. Signal S5 is often a digital signal having an L level and an H level, and functions as a reset signal (RE) or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 126. In this case, wiring 126 can function as a power supply line. For example, let's assume that signal S5 is input to wiring 126. Therefore, wiring 126 can function as a signal line. Signal S5 is often a digital signal having an L level and an H level, and functions as a reset signal (RE) or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 126. In this case, wiring 126 can function as a power supply line. For example, let's assume that signal S5 is input to wiring 126. Therefore, wiring 126 can function as a signal line. Signal S5 is often a digital signal having an L level and an H level, and functions as a reset signal (RE) or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 126. In this case, wiring 126 can function as a power supply line. For example, let's assume that signal S5 is input to wiring 126. Therefore, wiring 126 can function as a signal line. Signal S5 is often a digital signal having an L level and an H level, and functions as a reset signal (RE) or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 126. In this case, wiring 126 can function as a power supply line.

[0150] An example of the functions of transistors 131 to 135 will be described. However, the content described below is an example and is not limited to this. Transistors 131 to 135 are as described below. An example of the functions of transistors 131 to 135 will be described. However, the content described below is an example and is not limited to this. Transistors 131 to 135 are as described below. In addition to the functions it has, it is also possible to have various other functions, and it is also possible not to have the functions described below. It is also possible.

[0151] Transistor 131 has a function of raising the potential of node A in response to a signal (for example, signal S4) input to wiring 125 and functions as a diode. Transistor 132 has a function of controlling the timing at which wiring 125 and node A conduct in response to a signal (for example, signal S3) input to wiring 124A and functions as a switch. Transistor 1 has a function of controlling the timing at which wiring 122E and wiring 121 conduct in response to a signal (for example, signal S3) input to wiring 124B and functions as a switch. Transistor 133 has a function of controlling the timing at which wiring 122E and wiring 121 conduct in response to a signal (for example, signal S3) input to wiring 124B and functions as a switch. Transistor 134 has a function of controlling the timing at which wiring 122C and node A conduct in response to a signal (for example, signal S5) input to wiring 126 and functions as a switch. Transistor 135 has a function of controlling the timing at which wiring 122D and wiring 121 conduct in response to a signal (for example, signal S5) input to wiring 126 and functions as a switch. has a function of controlling the timing at which wiring 122C and node A conduct in response to a signal (for example, signal S5) input to wiring 126 and functions as a switch. has a function of controlling the timing at which wiring 122D and wiring 121 conduct in response to a signal (for example, signal S5) input to wiring 126 and functions as a switch. has a function of controlling the timing at which wiring 122D and wiring 121 conduct in response to a signal (for example, signal S5) input to wiring 126 and functions as a switch. functions.

[0152] Next, the operation of the semiconductor device in Fig. 6(A) will be described with reference to Fig. 6(B), Figs. 7(A) to (C), and Figs. 8(A) to (B). Fig. 6(B) is an example of a timing chart for explaining the operation of the semiconductor device and has a period T1, a period T2, a period T3, a period T4, and a period T5. Fig. 7(A) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) in period T1. Fig. 7(B) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) in period T2. Fig. 7(C) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) in period T3. Fig. 7(C) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) in period T3. Fig. 7(C) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) in period T3. FIG. 8(A) shows a schematic diagram of the operation of the semiconductor device of FIG. 6(A) in period T4. FIG. 8( B) shows a schematic diagram of the operation of the semiconductor device of FIG. 6(A) in period T5. Note that the parts common to the operation of the semiconductor device of FIG. 1( A) are not described herein for the sake of brevity.

[0153] First, in period T1, since signal S5 is at the L level, transistor 134 and transistor 135 turn off. Thus, wiring 122C and node A are in a non-conductive state, and wiring 122D and wiring 121 are in a non-conductive state. At the same time, since signals S3 and signal S4 become at the H level, transistors 131, transistor 132, and transistor 13 3 turn on. Then, wiring 125 and node A become conductive, and wiring 122E and wiring 121 become conductive. Therefore, the signal (H-level signal S 4) input to wiring 125 is supplied from wiring 125 to node A, so the potential of node A starts to rise. Further more, since wiring 122E and wiring 121 are in a conductive state, voltage V1 is supplied from wiring 122E to wiring 121. After that, when the potential of node A rises to a value (V1 - Vth131) obtained by subtracting the threshold voltage (Vth131) of transistor 133 from the H-level potential (V1) of signal S4 up to, transistor 131 turns off. Similarly, when the potential of node A rises to a value (V1 - Vth132) obtained by subtracting the threshold voltage (Vth132) of transistor 132 from the H-level potential (V1) of signal S3 up to, transistor 132 turns off . When transistors 131 and transistor 132 turn off, no charge is supplied to node A. Thus, the potential of node A becomes a high value (at least V1 + Vth101 or more ). . When transistors 131 and transistor 132 turn off, no charge is supplied to node A. Thus, the potential of node A becomes a high value (at least V1 + Vth101 or more ). ) While remaining maintained at this state, node A becomes a floating state. Here, for convenience, when the potential of node A becomes V1 - Vth131, it is assumed that transistor 131 and transistor 132 turn off. Therefore, wiring 125 and node A become a non - conductive state. At this time, the potential of node A remains at V1 - Vth131, and node A becomes a floating state.

[0154] Next, in period T2, since signal S4 becomes the L level, transistor 131 remains off. And since signal S3 becomes the L level, transistor 132 remains off, and transistor 133 turns off. Therefore, wiring 125 and node A remain in a non - conductive state, and wiring 122E and wiring 121 become a non - conductive state. At this time, since signal S5 remains at the L level, transistor 134 and transistor 135 remain off. Therefore, wiring 122C and node A remain in a non - conductive state, and wiring 122D and wiring 121 remain in a non - conductive state.

[0155] Next, in period T3, since signal S4 remains at the L level, transistor 131 remains off. And since signal S5 becomes the H level, transistor 134 and transistor 135 turn on. Then, wiring 122C and node A become a conductive state, and wiring 122D and wiring 121 become a conductive state. Therefore, voltage V1 is supplied from wiring 122C to node A, so the potential of node A decreases to V1. Similarly, voltage V1 is supplied from wiring 122D to wiring 121, so the potential of wiring 121 decreases to V1. At the same time, since signal S3 becomes the H level, transistor 132 and transistor Stage 133 is turned on. Then, wiring 125 and node A are in a conductive state, and wiring 12 2E and wiring 121 are in a conductive state. Thus, an L-level signal S4 is supplied to node A , and the potential of node A decreases to V1. Similarly, since voltage V1 is supplied to wiring 121 , the potential of wiring 121 decreases to V1.

[0156] Next, in period T4, since signal S4 remains at the L level, transistor 131 remains off . And since signal S5 becomes the L level, transistor 134 and transistor 135 turn off. Thus, wiring 122C and node A are in a non-conductive state, and wiring 122D and wiring 121 are in a non-conductive state. At this time, since signal S4 becomes the L level , transistor 132 and transistor 133 turn off. Thus, wiring 125 and node A are in a non-conductive state, and wiring 122E and wiring 121 are in a non-conductive state.

[0157] Next, in period T5, since signal S4 remains at the L level, transistor 131 remains off . And since signal S5 remains at the L level, transistor 134 and transistor 135 remain off. Thus, wiring 122C and node A remain in a non-conductive state , and wiring 122D and wiring 121 remain in a non-conductive state. At this time, since signal S4 becomes the H level, transistor 132 and transistor 133 turn on . Then, wiring 125 and node A are in a conductive state, and wiring 122E and wiring 121 are conductive state. Thus, an L-level signal S4 is supplied from wiring 125 to node A, so , the potential of node A is maintained at V1. Similarly, voltage V1 is from wiring 122E to wiring 121 Since it is supplied to, the potential of the wiring 121 is maintained at V1.

[0158] In the semiconductor device of Fig. 6(A), in periods T4 and T5, an L-level signal or the voltage V1 is supplied to node A, so the noise of node A can be reduced. Therefore, malfunctions can be prevented.

[0159] Alternatively, in the semiconductor device of Fig. 6(A), in period T1, since both the transistor 131 and the transistor 132 are turned on, the potential of node A can be raised quickly. Alternatively, the channel width of the transistor 131, or the channel width of the transistor 132 can be made smaller smaller.

[0160] Note that the channel width of the transistor 131 can be larger than the channel width of the transistor 134, or the channel width of the tra nsistor 103. Similarly, the channel width of the transistor 13 2 can be larger than the channel width of the transistor 134, or the channel width of the transistor 103. This is because, in period T2, it is preferable that the potential of node A rises faster, and in period T3, it is preferable that the potential of node A decreases slower because. That is, in period T2, if the potential of node A rises quickly, improvements in drive frequency , suppression of through-current, reduction of power consumption, etc. can be achieved. On the other hand, in period T 3, if the potential of node A decreases slowly, the on-time of the transistor 101 becomes longer , so the fall time of the signal (e.g., signal S1) output from the wiring 121 can be shortened shortened. Therefore, a transistor having a function of raising the potential of node A in period T2 ​The channel width of the transistor that decreases the potential of node A during period T3 is preferably larger than the channel width of the transistor. However, it is not limited to this, and the channel width of transistor 1 31 can be smaller than the channel width of transistor 134 or the channel width of transistor 103. Similarly, the channel width of transistor 132 can be smaller than the channel width of transistor 134 or the channel width of transistor 103.

[0161] Note that the sum of the channel width of transistor 131 and the channel width of transistor 134 can be larger than the channel width of transistor 134 or the channel width of transistor 103. This is because, during period T2, the H-level signal S4 is supplied from wiring 12 5 to node A through two transistors connected in parallel, namely transistor 13 1 and transistor 132. However, it is not limited to this, and the sum of the channel width of transistor 131 and the channel width of transistor 134 can be smaller than the channel width of transistor 134 or the channel width of transistor 103.

[0162] Note that the channel width of transistor 134 can be smaller than the channel width of transistor 133. Similarly, the channel width of transistor 132 can be smaller than the channel width of transistor 133. Similarly, the channel width of transistor 103 can be smaller than the channel width of transistor 102. This is because the load of wiring 1 21 (for example, wiring resistance, parasitic capacitance, connected transistors, etc.) is at node A ​​​​​​​​​​This is because it is often greater than the load of Therefore, the channel width of the transistor having the function of supplying a signal or voltage to node A is preferably smaller than the channel width of the transistor that supplies a signal or voltage to wiring 121. However, it is not limited to this, and the channel width of transistor 134 can be larger than the channel width of transistor 133. Similarly, the channel width of transistor 132 can be larger than the channel width of transistor 133. Similarly, the channel width of transistor 103 can be larger than the channel width of transistor 102. It is possible. In addition, the channel width of transistor 103 can be larger than the channel width of transistor 132. This is because transistor 103 has the function of maintaining the potential of node A at V1 during period T4, while transistor 132 has the function of maintaining the potential of node A at V1 during period T5. Specifically, in period T4, the signal input to wiring 123B (for example, signal S2) becomes the H level. At this time, if the potential of node A rises and transistor 101 turns on, the potential of wiring 121 will rise. Therefore, transistor 103 is required to maintain the potential of node A at V1 and keep transistor 101 off, so the channel width of transistor 103 is preferably large. On the other hand, in period T5, the signal input to wiring 123B (for example, signal S2) becomes the L level, so even if transistor 101 turns on, the potential of wiring 121 will not rise. That is, even if the potential of node A rises or decreases from V1, wiring 12 The potential does not rise.

[0163] Note that the channel width of transistor 103 can be larger than the channel width of transistor 132. Because transistor 103 has the function of maintaining the potential of node A at V1 during period T4, while transistor 132 has the function of maintaining the potential of node A at V1 during period T5. Specifically, in period T4, the signal input to wiring 123B (for example, signal S2) becomes the H level. At this time, if the potential of node A rises and transistor 101 turns on, the potential of wiring 121 will rise. Therefore, transistor 103 is required to maintain the potential of node A at V1 and keep transistor 101 off, so the channel width of transistor 103 is preferably large. On the other hand, in period T5, the signal input to wiring 123B (for example, signal S2) becomes the L level, so even if transistor 101 turns on, the potential of wiring 121 will not rise. That is, even if the potential of node A rises or decreases from V1, wiring 12 The potential does not rise. The potential of node A is maintained at V1, while transistor 132 has the function of maintaining the potential of node A at V1 during period T5. Therefore, the channel width of transistor 103 can be larger than the channel width of transistor 132. Specifically, in period T4, the signal input to wiring 123B (for example, signal S2) becomes the H level. At this time, if the potential of node A rises and transistor 101 turns on, the potential of wiring 121 will rise. Therefore, transistor 103 is required to maintain the potential of node A at V1 and keep transistor 101 off, so the channel width of transistor 103 is preferably large. On the other hand, in period T5, the signal input to wiring 123B (for example, signal S2) becomes the L level, so even if transistor 101 turns on, the potential of wiring 121 will not rise. That is, even if the potential of node A rises or decreases from V1, wiring 12 The potential does not rise. When the potential of node A rises and transistor 101 turns on, the potential of wiring 121 will rise. Therefore, transistor 103 is required to maintain the potential of node A at V1 and keep transistor 101 off, so the channel width of transistor 103 is preferably large. Therefore, transistor 103 is required to maintain the potential of node A at V1 and keep transistor 101 off, so the channel width of transistor 103 is preferably large. On the other hand, in period T5, the signal input to wiring 123B (for example, signal S2) becomes the L level, so even if transistor 101 turns on, the potential of wiring 121 will not rise. That is, even if the potential of node A rises or decreases from V1, wiring 12 The potential does not rise. For example, signal S2) becomes the L level, so even if transistor 101 turns on, the potential of wiring 121 will not rise. That is, even if the potential of node A rises or decreases from V1, wiring 12 The potential does not rise. The potential of 1 does not increase. Therefore, the necessity of reducing the on-resistance of transistor 132 is low, so the channel width of transistor 132 is preferably small. However, this is not limited thereto, and the channel width of transistor 103 can be smaller than the channel width of transistor 132 because transistor 132 has the function of raising the potential of node A during period T1 . By increasing the channel width of transistor 132, the potential of node A can be raised faster .

[0164] In addition, the channel width of transistor 102 can be smaller than the channel width of transistor 133 because if the channel width of transistor 102 is increased too much, the potential of node A will decrease too much during period T2, resulting in malfunction of the semiconductor device . Specifically, both transistor 102 and transistor 133 have the function of maintaining the potential of wiring 1 21 at V1. However, during period T2, until the potential of wiring 121 rises from the potential of wiring 123C (V1) by the threshold voltage (Vth102) of transistor 102 to the value (V1 - Vth102), transistor 102 is on . Therefore, in order to prevent the potential of node A from decreasing too much during period T2, the channel width of transistor 102 is preferably small. On the other hand, the channel width of transistor 133 is preferably large in order to maintain the potential of wiring 121 at V1. However, this is not limited thereto, and the channel width of transistor 102 can be larger than the channel width of transistor 133 . Because during period T4, signal S2 is at H level ​This is because when it turns into a loop, the potential of wiring 121 is likely to increase. Therefore, by increasing the channel width of transistor 102, the increase in the potential of wiring 121 can be more easily suppressed.

[0165] Note that, similar to Embodiment 1, the L-level potential of the signal input to wiring 124A, wiring 124B, wiring 125, and / or wiring 126 can be lower than V1. In particular, since transistors 132 and 133 are on for a long time, it is preferable that the L-level potential of the signal input to wiring 124A and wiring 124B is lower than V1.

[0166] Note that, similar to Embodiment 1, the H-level potential of the signal input to wiring 124A, wiring 124B, wiring 125, or wiring 126 can be lower than V2. In particular, since transistors 132 and 133 are prone to deterioration, it is preferable that the H-level potential of the signal input to wiring 124A and wiring 124B is lower than V2.

[0167] Note that, similar to Embodiment 1, it is possible to input a signal to wiring 122C, wiring 122D, or wiring 122E. For example, to wiring 122C, it is possible to input a signal that becomes an L level during the period when transistor 134 is on (for example, period T3). Examples of such a signal include signal S2 or signal S4. To wiring 122D, it is possible to input a signal that becomes an L level during the period when transistor 135 is on (for example, period T3). Examples of such a signal include signal S2 or signal S4. To wiring 122E, to the tra During the period when transistor 133 is turned on (for example, period T1, period T3, period T5), a signal having an L level can be input. As an example, there are signal S2, signal S3, etc. .

[0168] Note that in FIG. 13(C), as an example, the first terminal of transistor 103 is connected to wiring 124B , the first terminal of transistor 104 is connected to wiring 126, the first terminal of transistor 1 33 is connected to wiring 123A, the first terminal of transistor 134 is connected to wiring 1 23A, and the first terminal of transistor 135 is connected to wiring 123A. However, the present invention is not limited to this, and the first terminal of transistor 103 can be connected to wiring 12 4A or wiring 125. Alternatively, the first terminal of transistor 133, the first terminal of transistor 134, or the first terminal of transistor 135 can be connected to wiring 121, wiring 123B, wiring 123C, or wiring 126. .

[0169] Note that, similar to Embodiment 1, voltage (for example, voltage V1 or voltage V2) can be supplied to wiring 124A, wiring 124B, and / or wiring 126. By doing so, the semiconductor device can function as an inverter circuit or a buffer circuit. .

[0170] Note that, as shown in FIG. 9(A), since the same signal (for example, signal S3) is input to wiring 124A and wiring 124B, it is possible to share wiring 124A and wiring 124B. For this reason, the gates of transistor 132 and transistor 133 are . It is connected to wiring 124. Wiring 124 corresponds to wiring 124A or wiring 124B, and it is possible to input something similar to these wirings.

[0171] Note that FIG. 9(C) shows the configuration when FIGS. 3(C) and 9(A) are combined. For example, the first terminal of transistor 101, the gate of transistor 102, and one electrode of capacitor element 106 are connected to wiring 123. The gate of transistor 132 and the gate of transistor 133 are connected to wiring 124. The first terminal of transistor 103, the first terminal of transistor 104, the first terminal of transistor 133, the first terminal of transistor 134, and the first terminal of transistor 135 are connected to wiring 122.

[0172] Note that as shown in FIG. 9(C), the gate of transistor 131 can be connected to wiring 127. As an example, a voltage V2 is supplied to wiring 127, and it can function as a power supply line. However, it is not limited to this, and various things such as current, voltage, and signal can be input to wiring 127. For example, the signal input to wiring 127 preferably becomes high level during period T1 and low level during period T2, so it is possible to input signal S3 to wiring 127. In this case, wiring 127 can be connected to wiring 124A or wiring 124B and can function as a signal line.

[0173] Note that in FIG. 9(C), the gate of transistor 131 is shown as being connected to wiring 127, but it is not limited to this. For example, the first terminal of transistor 131 can be connected to wiring 127. ​​​​​​​​​​​​​​Subsequently, the gate of transistor 131 can be connected to wiring 125.

[0174] Similar to FIG. 9(C), in FIGS. 9(A) to 9(B) as well, the gate of transistor 131 can be connected to wiring 127.

[0175] Note that, as shown in FIG. 10(A), transistor 131 can be omitted. Even if transistor 131 is omitted, in period T1, transistor 132 turns on , so the potential of node A rises.

[0176] Similar to FIG. 10(A), in FIGS. 9(A) to 9(C) as well, transistor 131 can be omitted.

[0177] Note that, as shown in FIG. 10(B), transistor 132 can be omitted. Even if transistor 132 is omitted, in period T5, node A becomes floating, so the potential of node A is maintained at V1.

[0178] Similar to FIG. 10(B), in FIGS. 9(A) to 9(C) and FIG. 10(A) as well, transistor 132 can be omitted.

[0179] Note that, as shown in FIG. 10(C), transistor 134 and transistor 135 can be omitted. Or, either one of transistor 134 and transistor 135 can be omitted. Even if transistor 134 is omitted, in period T3, transistor 132 turns on, so the potential of node A decreases to V1. Similarly, even if transistor 135 is omitted, in period T3, transistor 133 turns on Therefore, the potential of the wiring 121 decreases to be V1.

[0180] Similar to FIG. 10(C), in FIGS. 9(A) to (C) and FIGS. 10(A) to (B), it is also possible to omit the transistor 134 and the transistor 135.

[0181] As shown in FIG. 11(A), it is possible to omit the transistor 133. When the transistor 133 is omitted, in the period T5, since the wiring 121 becomes a floating state, the potential of the wiring 121 is maintained at V1.

[0182] Similar to FIG. 11(A), in FIGS. 9(A) to (C) and FIGS. 10(A) to (C), it is also possible to omit the transistor 133.

[0183] As shown in FIG. 11(B), it is possible to omit the transistor 102. When the transistor 102 is omitted, in the period T4, since the wiring 121 becomes a floating state, the potential of the wiring 121 is maintained at V1.

[0184] Similar to FIG. 11(B), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), and FIG. 11 (A), it is also possible to omit the transistor 102.

[0185] As shown in FIG. 11(C), it is possible to omit the transistor 103, the transistor 104, and the capacitor element 106. Even when the transistor 103, the transistor 104, and the capacitor element 106 are omitted, in the period T4, since the wiring 121 becomes a floating state, the potential of the wiring 121 is maintained at V1.

[0186] Note that, similar to FIG. 11(C), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), and FIGS. 11 (A) to (B) as well, the transistor 103, the transistor 104, and the capacitor element 1 06 can be omitted.

[0187] Note that, as shown in FIG. 12(A), the transistor 133 can be replaced with a diode 133a. The diode 133a corresponds to the transistor 133. The diode 133a has a function of reducing the potential of the wiring 121 when an L-level signal is input to the wiring 124B, and a function of making the wiring 124B and the wiring 121 non-conductive when an H-level signal is input to the wiring 124B. One terminal of the diode 133a (hereinafter also referred to as the input terminal or the anode) is connected to the wiring 121, and the other terminal of the diode 133a (hereinafter also referred to as the output terminal or the cathode) is connected to the wiring 124B.

[0188] Note that, in FIG. 12(A), when the transistor 133 is replaced with the diode 133a, it is possible to input the signal S2 to the wiring 124B. Therefore, it is possible to connect the wiring 124B to the wirings 123A to 123C and share the wiring 124B and the wirings 123A to 123C.

[0189] Note that, similar to FIG. 12(A), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), and FIGS. 11 (A) to (C) as well, the transistor 133 can be replaced with the diode 133a, and one terminal of the diode 133a can be connected to the wiring 121, and the other terminal of the diode 133a can be connected to the wiring 124B.

[0190] ​​​​​Note that, as shown in FIG. 12(B), the transistor 133 can be diode-connected. The diode-connected transistor 133 corresponds to the diode 133a. The first terminal of the transistor 133 is connected to the wiring 124B, and the second terminal of the transistor 133 is connected to the wiring 121, and the gate of the transistor 133 is connected to the wiring 121. However, it is not limited thereto, and the gate of the transistor 133 can be connected to the wiring 124B.

[0191] Note that, similar to FIG. 12(B), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A ) to (C), and FIG. 12(A) as well, the first terminal of the transistor 133 can be connected to the wiring 12 4B, the second terminal of the transistor 133 can be connected to the wiring 121, and the gate of the transistor 133 can be connected to the wiring 121. However, it is not limited thereto, and the gate of the transistor 133 can be connected to the wiring 124B.

[0192] Note that, as shown in FIG. 12(C), the transistor 134 can be replaced with the diode 134a, and the transistor 135 can be replaced with the diode 135a. The diode 134a corresponds to the transistor 134, and the diode 135a corresponds to the transistor 135. When an L-level signal is input to the wiring 126, the diode 134a has a function of reducing the potential of the node A, and when an H-level signal is input to the wiring 126, it has a function of making the wiring 126 and the node A in a non-conducting state. When an L-level signal is input to the wiring 126, the diode 135a has a function of reducing the potential of the wiring 121, and When an H-level signal is input to wiring 126, it has a function of making wiring 126 and wiring 121 non-conductive. One terminal of diode 134a (hereinafter also referred to as the input terminal or anode) is connected to node A, and the other terminal of diode 134a (hereinafter also referred to as the output terminal or cathode) is connected to wiring 126. One terminal of diode 135a (hereinafter also referred to as the input terminal or anode) is connected to wiring 121, and the other terminal of diode 135a ( hereinafter also referred to as the output terminal or cathode) is connected to wiring 126.

[0193] In addition, in FIG. 12(C), when transistors 134 and 135 are replaced with diodes, a reverse signal of signal S5 is input to wiring 126 as an example. This is possible.

[0194] In addition, in FIG. 12(C), it is possible to replace only one of transistors 134 and 135 with a diode.

[0195] Similar to FIG. 12(C), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A ) to (C), and FIGS. 12(A) to (B), it is also possible to replace transistor 134 with diode 1 34a, with one terminal of diode 134a connected to node A and the other terminal of diode 134a connected to wiring 126. Or, it is possible to replace transistor 135 with diode 135a, with one terminal of diode 135a connected to wiring 12 1 and the other terminal of diode 135a connected to wiring 126. This is possible.

[0196] In addition, as shown in FIG. 13(A), transistors 134 and 135 are di It is possible to make an anode connection. The diode-connected transistor 134 and the diode-connected transistor 135 respectively correspond to the diodes 134a and 135a. The first terminal of the transistor 134 is connected to the wiring 126, the second terminal of the transistor 134 is connected to the node A, and the gate of the transistor 134 is connected to the node A. And the first terminal of the transistor 135 is connected to the wiring 126, the second terminal of the transistor 135 is connected to the wiring 121, and the gate of the transistor 135 is connected to the wiring 121. However, it is not limited to this, and the gate of the transistor 134 can be connected to the wiring 126, and the gate of the transistor 135 can be connected to the wiring 126. -d-connected transistor 135 respectively correspond to the diodes 134a and 135a. The first terminal of the transistor 134 is connected to the wiring 126, the second terminal of the transistor 1 34 is connected to the node A, and the gate of the transistor 134 is connected to the node A . And the first terminal of the transistor 135 is connected to the wiring 126, the tra nsistor 135's second terminal is connected to the wiring 121, and the gate of the transistor 135 is , connected to the wiring 121. However, it is not limited to this, and the gate of the transistor 134 is , can be connected to the wiring 126, and the gate of the transistor 135 can be connected to the wiring 12 6.

[0197] Note that, similar to FIG. 13(A), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A ) to (C), and FIGS. 12(A) to (C), the first terminal of the transistor 134 is connected to the wiring 126, the second terminal of the transistor 134 is connected to the node A, and the tra nsistor 134's gate can be connected to the node A. Or, the first terminal of the transistor 135 is connected to the wiring 126, the second terminal of the transistor 135 is connected to the wiring 1 21, and the gate of the transistor 135 can be connected to the wiring 121. However, it is not limited to this, and the gate of the transistor 134 can be connected to the wiring 126 . It is possible, and the gate of the transistor 135 can be connected to the wiring 126. able.

[0198] Note that, as shown in FIG. 13(B), the transistors 137 and 138 are newly added It can be added to. Assume that transistors 137 and 138 are of the N-channel type. However, it is not limited to this, and transistors 137 and 138 can be of the P-channel type. The first terminal of transistor 137 is connected to wiring 122F, the second terminal of transistor 137 is connected to wiring 121, and the gate of transistor 137 is connected to wiring 128. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A, and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. type. However, it is not limited to this, and transistors 137 and 138 can be of the P-channel type. The first terminal of transistor 137 is connected to wiring 122F, the second terminal of transistor 137 is connected to wiring 121, and the gate of transistor 137 is connected to wiring 128. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A, and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. type. The first terminal of transistor 137 is connected to wiring 122F, the second terminal of transistor 137 is connected to wiring 121, and the gate of transistor 137 is connected to wiring 128. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A, and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. The first terminal of transistor 137 is connected to wiring 122F, the second terminal of transistor 137 is connected to wiring 121, and the gate of transistor 137 is connected to wiring 128. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A, and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. The first terminal of transistor 137 is connected to wiring 122F, the second terminal of transistor 137 is connected to wiring 121, and the gate of transistor 137 is connected to wiring 128. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A, and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A, and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A, and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. Therefore, wiring 128 can function as a signal line. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. Signal S6 is often a digital signal having an H level and an L level, and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G.

[0199] Note that in FIG. 13(B), signal S6 can be at the H level during the period before the semiconductor device starts operating. Or, the semiconductor device shown in FIG. 13(B) can shift. during the period before the semiconductor device starts operating. When used in a register, signal S6 can be at the H level during the period before the shift register starts scanning, or during the period after the shift register finishes scanning. Therefore, as signal S6, the start pulse of the shift register, or the output signal of the last stage of the shift register, etc. can be used. However, an example of this embodiment is not limited to this. In addition, in FIG. 13(B), it is possible to newly add only one of transistor 137 and transistor 138. Note that, similar to FIG. 13(B), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A

[0200] ) to (C), FIGS. 12(A) to (C), and FIG. 13(A), it is also possible to newly add transistor 137, connect the first terminal of transistor 137 to wiring 122F, connect the second terminal of transistor 137 to wiring 121, and connect the gate of transistor 137 to wiring 1

[0201] 28. Or, it is possible to newly add transistor 138, connect the first terminal of transistor 138 to wiring 122G, and connect the second terminal of transistor 138 to node A, and connect the gate of transistor 138 to wiring 128. In addition, in FIG. 13(B), it is possible to newly add only one of transistor 137 and transistor 138. Note that, similar to FIG. 13(B), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A ) to (C), FIGS. 12(A) to (C), and FIG. 13(A), it is also possible to newly add transistor 137, connect the first terminal of transistor 137 to wiring 122F, connect the second terminal of transistor 137 to wiring 121, and connect the gate of transistor 137 to wiring 1 28. Or, it is possible to newly add transistor 138, connect the first terminal of transistor 138 to wiring 122G, and connect the second terminal of transistor 138 to node A, and connect the gate of transistor 138 to wiring 128.

[0202] (Embodiment 3) In this embodiment, an example of a shift register will be described. The shift register of this embodiment can have the semiconductor devices of Embodiment 1 and Embodiment 2. Note that , the shift register can be shown as a semiconductor device or a gate driver. Note that, actually The content described in Embodiment 1 and Embodiment 2 can be applied to the shift register of this embodiment. It is applicable.

[0203] First, an example of the shift register will be described with reference to FIG. 14(A). The shift register 220 is connected to wirings 201_1 to 201_N (N is a natural number), wiring 202, wiring 203, wiring 204, wiring 205, and wiring 206.

[0204] Wiring 202 corresponds to wiring 123 (wiring 123A to 123C) or wiring 124 (wiring 124A to 124B) described in Embodiment 1 and Embodiment 2, and can function as a signal line or a clock signal line. And it is assumed that a signal GS2 is input to wiring 202 from circuit 221. The signal GS2 corresponds to the signal S2 or signal S3 described in Embodiment 1 and Embodiment 2, and can function as a clock signal.

[0205] Wiring 203 corresponds to wiring 123 (wiring 123A to 123C) or wiring 124 (wiring 124A to 124B) described in Embodiment 1 and Embodiment 2, and can function as a signal line or a clock signal line. And it is assumed that a signal GS3 is input to wiring 203 from circuit 221. The signal GS3 corresponds to the signal S2 or signal S3 described in Embodiment 1 and Embodiment 2, and can function as an inverted clock signal.

[0206] Wiring 204 corresponds to wiring 122 (wiring 122A to 122G) described in Embodiment 1 and Embodiment 2, and can function as a power supply line. And wiring 20 ​ Assume that a voltage V1 is supplied from circuit 221 to 4.

[0207] Wiring 205 corresponds to wiring 125 described in Embodiment 1 and Embodiment 2, and can function as a signal line. A signal GS4 is input to wiring 205 from circuit 221. Signal GS4 corresponds to signal S4 described in Embodiment 1 and Embodiment 2, and can function as a start signal (hereinafter, start pulse) or a vertical synchronization signal.

[0208] Wiring 206 corresponds to wiring 126 described in Embodiment 1 and Embodiment 2, and can function as a signal line. A signal GS5 is input to wiring 206 from circuit 221. Signal GS5 corresponds to signal S5 described in Embodiment 1 and Embodiment 2, and can function as a reset signal.

[0209] However, it is not limited thereto, and various things such as signals, voltages, or currents can be input to wirings 202 to 206, and each wiring can be in a floating state.

[0210] As shown in FIG. 6(C), as signal S2 or signal S3, an unbalanced clock signal can be used. In this case, as an example, signal S3 can have a phase shifted by 180° with respect to signal S2. By doing so, when the semiconductor device of the present embodiment is used as a shift register, it is possible to prevent the selection signal of a certain stage from overlapping with the selection signals of the stages before and after it.

[0211] The wirings 201_1 to 201_N correspond to the wiring 121 described in Embodiment 1 and Embodiment 2, and can function as gate lines or scanning lines. And from the wirings 201_1 to 201_N, signals GS1_1 to GS1_N are output respectively. The signals GS1_1 to GS1_N correspond to the signal S1 described in Embodiment 1 and Embodiment 2, and can function as output signals, selection signals, scanning signals, or gate signals. And from the wirings 201_1 to 201_N, signals GS1_1 to GS1_N are output respectively. The signals GS1_1 to GS1_N correspond to the signal S1 described in Embodiment 1 and Embodiment 2, and can function as output signals, selection signals, scanning signals, or gate signals. And from the wirings 201_1 to 201_N, signals GS1_1 to GS1_N are output respectively. The signals GS1_1 to GS1_N correspond to the signal S1 described in Embodiment 1 and Embodiment 2, and can function as output signals, selection signals, scanning signals, or gate signals.

[0212] As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order. As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order. As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order. As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order. As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order. As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order. As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order.

[0213] The circuit 221 supplies a signal, voltage, etc. to the shift register 220 and has a function of controlling the shift register 220, and can function as a control circuit, a controller, etc. In the present embodiment, the circuit 211 supplies the signal GS2, the signal GS3, the voltage V1, the signal GS4, and the signal GS5 to the wiring 202, the wiring 203, the wiring 204, the wiring 205, and the wiring 206 respectively. However, it is not limited to this, and the shift register 220 can also supply signals, currents, voltages, etc. to various other circuits and control these circuits. The circuit 221 supplies a signal, voltage, etc. to the shift register 220 and has a function of controlling the shift register 220, and can function as a control circuit, a controller, etc. In the present embodiment, the circuit 211 supplies the signal GS2, the signal GS3, the voltage V1, the signal GS4, and the signal GS5 to the wiring 202, the wiring 203, the wiring 204, the wiring 205, and the wiring 206 respectively. However, it is not limited to this, and the shift register 220 can also supply signals, currents, voltages, etc. to various other circuits and control these circuits. The circuit 221 supplies a signal, voltage, etc. to the shift register 220 and has a function of controlling the shift register 220, and can function as a control circuit, a controller, etc. In the present embodiment, the circuit 211 supplies the signal GS2, the signal GS3, the voltage V1, the signal GS4, and the signal GS5 to the wiring 202, the wiring 203, the wiring 204, the wiring 205, and the wiring 206 respectively. However, it is not limited to this, and the shift register 220 can also supply signals, currents, voltages, etc. to various other circuits and control these circuits. The circuit 221 supplies a signal, voltage, etc. to the shift register 220 and has a function of controlling the shift register 220, and can function as a control circuit, a controller, etc. In the present embodiment, the circuit 211 supplies the signal GS2, the signal GS3, the voltage V1, the signal GS4, and the signal GS5 to the wiring 202, the wiring 203, the wiring 204, the wiring 205, and the wiring 206 respectively. However, it is not limited to this, and the shift register 220 can also supply signals, currents, voltages, etc. to various other circuits and control these circuits. The circuit 221 supplies a signal, voltage, etc. to the shift register 220 and has a function of controlling the shift register 220, and can function as a control circuit, a controller, etc. In the present embodiment, the circuit 211 supplies the signal GS2, the signal GS3, the voltage V1, the signal GS4, and the signal GS5 to the wiring 202, the wiring 203, the wiring 204, the wiring 205, and the wiring 206 respectively. However, it is not limited to this, and the shift register 220 can also supply signals, currents, voltages, etc. to various other circuits and control these circuits. The circuit 221 supplies a signal, voltage, etc. to the shift register 220 and has a function of controlling the shift register 220, and can function as a control circuit, a controller, etc. In the present embodiment, the circuit 211 supplies the signal GS2, the signal GS3, the voltage V1, the signal GS4, and the signal GS5 to the wiring 202, the wiring 203, the wiring 204, the wiring 205, and the wiring 206 respectively. However, it is not limited to this, and the shift register 220 can also supply signals, currents, voltages, etc. to various other circuits and control these circuits. It is capable. For example, circuit 221 can supply signals or voltages to components such as signal line driving circuits, scanning line driving circuits, and / or pixels, and can control these circuits.

[0214] Circuit 221 has, for example, circuit 222 and circuit 223. Circuit 222 has a function of generating power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage, and can function as a power supply circuit or a regulator. Circuit 223 has a function of generating various signals such as a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a video signal, and can function as a timing generator. However, it is not limited thereto, and in addition to circuit 222 and circuit 223, circuit 221 can also have various circuits or various elements. For example, circuit 221 can have an oscillator, a level shift circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, an operational amplifier, a shift register, a look-up table, a coil, a transistor, a capacitance element, a resistance element, and / or a frequency divider, etc.

[0215] Next, an example of the shift register 220 will be described with reference to FIG. 15. The shift register in FIG. 15 has a plurality of flip-flops 200_1 to 200_N (N is a natural number). The flip-flops 200_1 to 200_N respectively correspond to the semiconductor devices described in Embodiment 1 and Embodiment 2. In FIG. 15, as an example, the configuration when the semiconductor device in FIG. 9(B) is used as a flip-flop is shown.

[0216] The connection relationship of the shift register will be described. First, as an example, the flip-flop 20 The connection relationship of 0_i will be described. In the flip-flop 200_i, the wiring 121 , the wiring 122, the wiring 123, the wiring 124, the wiring 126, and the wiring 127 are respectively the wiring 2 01_i, the wiring 204, the wiring 202, the wiring 203, the wiring 201_i - 1, the wiring 201_i +1. However, in many cases, the connection destinations of the wiring 123 and the wiring 124 are reversed between the odd-stage flip-flops and the even-stage flip-flops. For example, in the odd-stage flip-flop, assume that the wiring 123 is connected to the wiring 202 and the wiring 124 is connected to the wiring 2 03. In this case, in the even-stage flip-flop, the wiring 123 is connected to the wiring 2 03 and the wiring 124 is connected to the wiring 202. On the other hand, assume that in the odd-stage flip-flop the wiring 123 is connected to the wiring 203 and the wiring 124 is connected to the wiring 202 . In this case, in the even-stage flip-flop, the wiring 123 is connected to the wiring 202 and the wiring 124 is connected to the wiring 203. In addition, in the flip-flop 200_1, the wiring 125 is connected to the wiring 205.

[0217] In addition, in the flip-flop 200_N, the wiring 126 is connected to the wiring 206.

[0218] In addition, in the flip-flop 200_N, the wiring 126 is connected to the wiring 206.

[0219] Next, an example of the operation of the shift register in FIG. 15 will be described with reference to the timing chart of FIG. 14(B). Note that the parts common to the operations of the semiconductor devices in Embodiment 1 and Embodiment 2 will be omitted from the description.

[0220] ​The operation of flip-flop 200_i will be described. First, when signal GS1_i-1 becomes H level it becomes a bell. Then, flip-flop 200_i starts operating in period T1, and signal G S1_i becomes L level. After that, signals GS2 and GS3 are inverted. Then, flip-flop 200_i starts operating in period T2, and signal GS1_i becomes H level Signal GS1_i is input as a reset signal to flip-flop 200_i-1 and as a start signal to flip-flop 200_i+1. Therefore , flip-flop 200_i-1 starts operating in period T3, and flip-flop 200_i+1 starts operating in period T1. After that, signals GS2 and signal GS3 are inverted again. Then, flip-flop 200_i+1 starts operating in period T2, and signal GS1_i+1 becomes H level. Signal GS1_i+1 is input as a reset signal to flip-flop 200_i. Therefore, flip-flop 200_i starts operating in period T3, and signal GS1_i becomes L level. After that, until signal GS1_i-1 becomes H level again, flip-flop 200_i repeats the operations in period T4 and period T5 every time signals GS2 and signal GS3 are inverted. Note that in flip-flop 200_1, instead of the output signal of the previous-stage flip-flop, signal GS4 is input from an external circuit via wiring 205. Therefore, when signal GS4 becomes H level, flip-flop 200_1 starts operating in period T1.

[0221]

[0222] ​​​​​​Note that in flip-flop 200_N, instead of the output signal of the flip-flop in the next stage the signal GS5 is input from an external circuit via wiring 206. Therefore, when the signal GS5 becomes H level, flip-flop 200_N starts operating in period T3.

[0223] By using the semiconductor devices of Embodiment 1 and Embodiment 2 in the shift register of the present embodiment it is possible to obtain the same advantages as those of the semiconductor device.

[0224] Note that it is possible to omit wiring 206. In this case, as an example, as flip-flop 200_N, a configuration in which transistors 134 and 135 shown in FIG. 10(C) are omitted can be used.

[0225] Note that in flip-flops 200_1 to 200_N, when a signal is used instead of voltage V1 it is possible to omit wiring 204.

[0226] Note that signal GS4 can be input to wiring 206 in the same manner as wiring 205. In this case, by connecting wiring 206 to wiring 205, it is possible to share wiring 205 and wiring 206. Alternatively, signal GS2 can be input to wiring 206 in the same manner as wiring 202. In this case, by connecting wiring 206 to wiring 202 it is possible to share wiring 206 and wiring 202. Alternatively, signal GS3 can be input to wiring 206 in the same manner as wiring 203. In this case, by connecting wiring 206 to wiring 203, it is possible to share wiring 206 and wiring 203. Or, the voltage V1 can be input to the wiring 206 in the same manner as the wiring 204. In this case, by connecting the wiring 206 to the wiring 204, it is possible to share the wiring 206 and the wiring 2 04.

[0227] Note that when a configuration that requires the signal S6 as shown in FIG. 13(B) is used for the flip-flops 200_1 to 200_N, it is possible to add the wiring 207 as shown in FIG. 16. The signal GS6 is input to the wiring 207. The signal GS6 corresponds to the signal S6 described in the second embodiment and can function as a full-stage reset signal. Thus, the wiring 207 corresponds to the wiring 128 in FIG. 13(B) and can function as a signal line. However, it is not limited to this, and by sharing the wiring 207 with another wiring, the number of wirings, or the number of signals or power supply voltages can be reduced. For example, the signal GS4 can be input to the wiring 207 in the same manner as the wiring 205. Therefore, by connecting the wiring 207 to the wiring 205, it is possible to share the wiring 207 and the wiring 205. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N.

[0228] However, it is not limited to this, and by sharing the wiring 207 with another wiring, the number of wirings, or the number of signals or power supply voltages can be reduced. For example, the signal GS4 can be input to the wiring 207 in the same manner as the wiring 205. Therefore, by connecting the wiring 207 to the wiring 205, it is possible to share the wiring 207 and the wiring 205. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N. However, it is not limited to this, and by sharing the wiring 207 with another wiring, the number of wirings, or the number of signals or power supply voltages can be reduced. For example, the signal GS4 can be input to the wiring 207 in the same manner as the wiring 205. Therefore, by connecting the wiring 207 to the wiring 205, it is possible to share the wiring 207 and the wiring 205. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N.

[0229] ​​​​In addition, when a configuration that requires voltage V2 is used for the flip-flops 200_1 to 200_N, as shown in FIG. 9(C), it is possible to newly add wiring. Voltage V2 is supplied to the wiring. And the wiring corresponds to the wiring 127 in FIG. 9(C) and can function as a power supply line. When a configuration that requires voltage V2 is used for the flip-flops 200_1 to 200_N, as shown in FIG. 9(C), it is possible to newly add wiring. Voltage V2 is supplied to the wiring. And the wiring corresponds to the wiring 127 in FIG. 9(C) and can function as a power supply line. When a configuration that requires voltage V2 is used for the flip-flops 200_1 to 200_N, as shown in FIG. 9(C), it is possible to newly add wiring. Voltage V2 is supplied to the wiring. And the wiring corresponds to the wiring 127 in FIG. 9(C) and can function as a power supply line. When a configuration that requires voltage V2 is used for the flip-flops 200_1 to 200_N, as shown in FIG. 9(C), it is possible to newly add wiring. Voltage V2 is supplied to the wiring. And the wiring corresponds to the wiring 127 in FIG. 9(C) and can function as a power supply line.

[0230] In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the characteristic degradation of the transistor, when a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the characteristic degradation of the transistor, when a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the characteristic degradation of the transistor, when a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the characteristic degradation of the transistor, when a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the characteristic degradation of the transistor, when a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line.

[0231] As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in FIG. 17(A), the shift register can have circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 have a function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 have a function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. It is connected to P. Thus, it is possible to input a signal with a small amplitude into the shift register so that the driving voltage of the external circuit can be reduced. Therefore, reduction of the cost of the external circuit , reduction of power consumption, etc. can be achieved.

[0232] In addition, in Fig. 17(A), the shift register can have any one , or only two or more of circuits 212 to 216.

[0233] In addition, as shown in Fig. 17(B), the shift register can have circuits 211_1 to 211_N . Circuits 211_1 to 211_N have a function of enhancing the current capacity of the input signal, a function of increasing the amplitude voltage of the input signal, or a function of inverting the input signal, and can function as a buffer circuit, a level shift circuit, or an inverter circuit. Circuits 211_1 to 211_N are each connected between flip-flops 200_1 to 200_N and wirings 201_1 to 201_N. For example, circuit 211_i is connected between flip-flop 200_i and wiring 201_i. And the signal GS1_i, which is the output signal of flip-flop 200 _i, is output from wiring 201_i through circuit 211_i. Thus, the driving voltage of each flip-flop can be reduced, so that reduction of power consumption , suppression of characteristic deterioration of transistors, etc. can be achieved. Or, by reducing the channel width of the transistors (particularly, transistor 101) included in each flip-flop , it is possible to reduce the layout area. In addition, in an example of Fig. 17(B), a reset signal and are applied to flip-flop 200_i-1 .

[0234] Thus, the signal GS1_i is input via the circuit 211_i. Therefore, in the flip-flop 200_i-1, during the period T3, the period when the transistor 101 is turned on becomes longer so that the fall time of the signal GS_i-1, which is the output signal of the flip-flop 200_i-1, can be shortened. On the other hand, in the flip-flop 200_i+1, as a start signal, the signal GS1_i is input without passing through the circuit 211_i. Therefore, in the flip- flop 200_i+1, during the period T1, the potential of the node A can be raised quickly so that the driving frequency can be improved. However, it is not limited to this, and the signal GS1_i can be input to the flip-flop 200_i-1 as a reset signal without passing through the circuit 211 _i. Or, the signal GS1_i can be input to the flip-flop 200_i+1 as a start signal through the circuit 211_i .

[0235] In the shift register of FIG. 14(A), the signals S1_1 to S1_N are shifted by 1 / 2 cycles of the signal S2, or 1 / 2 cycle of the signal S3 at a time. However, it is not limited to this, and the signals S1_1 to S1_N can be shifted by 1 / 2×M (M is a natural number) cycles of the signal S2, or 1 / 2×M cycles of the signal S3 at a time. That is, in the signals S1_1 to S1_N, the period when the signal of a certain row becomes the H level and the period when the signal of another row becomes the H level can overlap. To achieve this, it is possible to input a 2×M-phase clock signal to the shift register.

[0236] Regarding a specific example, it will be described with reference to the shift register of FIG. 24. FIG. 24 shows a flip-flop ​​​Only the ropes 200_i + 1 to 200_i + 2M + 1 are shown. Flip-flop 200_i The wirings 123 of flip-flops 200_i + 1 to 200_i + M are each connected to the wirings 203_1 to 203_M, and the wirings 124 of flip-flops 200_i + 1 to 200_i + M are each connected to the wirings 204_ 1 to 204_M. The wirings 123 of flip-flops 200_i + M + 1 to 200_i + 2M are each connected to the wirings 204_1 to 204_M, and the wirings 124 of flip-flops 20 0_i + M + 1 to 200_i + 2M are each connected to the wirings 203_1 to 203_M respectively. And the wiring 125 of flip-flop 200_i + 1 is connected to the wiring 121 of flip-flop 200_i . The wiring 126 of flip-flop 200_i + 1 is connected to the wiring 121 of flip-flop 200_i + M + 1. Note that the wirings 20 3_1 to 203_M correspond to the wiring 203. The wirings 204_1 to 204_M correspond to the wiring 2 04. As shown in Fig. 25(A), signals GS2_1 to GS2_M are respectively input to the wirings 203_1 to 203_M . Signals GS3_1 to GS3_M are respectively input to the wirings 204_1 to 204_M. The signals GS2_1 to GS2_M are M clock signals whose phases are shifted by 1 / 2 M periods each and correspond to the signal GS2. The signals GS3_1 to GS3_M are inverted signals of the signals GS2_1 to GS2_M and correspond to the signal GS3. In this way, it becomes possible to shift by 1 / 2×M (M is a natural number) periods of the signal S2 or by 1 / 2 ×M periods of the signal S3 each. Note that in Fig. 24, the wiring 125 of flip-flop 200_i + 1 may be connected to any one of the wirings 121 of flip-flops 200_i - M + 1 to 200_i - 1 .

[0237] Note that in Fig. 24, the wiring 125 of flip-flop 200_i + 1 may be connected to any one of the wirings 121 of flip-flops 200_i - M + 1 to 200_i - 1 . This is possible. By doing so, in flip-flop 200_i+1, the timing at which transistor 131 turns on can be advanced, so that the timing at which the potential of node A rises can be advanced. Therefore, the drive frequency can be increased. Or, since the channel width of transistor 131 or transistor 132 can be reduced, the layout area can be reduced. In FIG. 24, wiring 126 of flip-flop 200_i+1 can be connected to any one of wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so that the fall time of signal S1_i+1 can be shortened. In FIG. 24, wiring 126 of flip-flop 200_i+1 can be connected to any one of wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, while reducing power consumption, the drive frequency can be increased. In FIG. 24, it is preferable that M≦4. More preferably, it is preferable that M≦2. This is because when the shift register of FIG. 23 is used in the scanning line drive circuit of a display device, if M is too large, a plurality of types of video signals are written to the pixels.

[0238] In FIG. 24, wiring 126 of flip-flop 200_i+1 can be connected to any one of wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so that the fall time of signal S1_i+1 can be shortened. In FIG. 24, wiring 126 of flip-flop 200_i+1 can be connected to any one of wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so that the fall time of signal S1_i+1 can be shortened.

[0239] In FIG. 24, wiring 126 of flip-flop 200_i+1 can be connected to any one of wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, while reducing power consumption, the drive frequency can be increased.

[0240] In FIG. 24, it is preferable that M≦4. More preferably, it is preferable that M≦2. This is because when the shift register of FIG. 23 is used in the scanning line drive circuit of a display device, if M is too large, a plurality of types of video signals are written to the pixels. when the period during which an illegal video signal is input to the pixel becomes long and the display quality deteriorates This is because there is [a certain situation]. As an example, FIG. 25(B) shows an example of a timing chart when M = 2.

[0241] (Embodiment 4) In this embodiment, an example of a semiconductor device and a shift register having the semiconductor device will be described. Note that the content described in Embodiments 1 to 3 can be applied to the semiconductor device and the shift register of this embodiment.

[0242] First, the semiconductor device of this embodiment will be described with reference to FIG. 19(A). Note that the parts common to FIG. 1(A) are denoted by the same reference numerals, and the description thereof will be omitted.

[0243] The semiconductor device in FIG. 19(A) includes a circuit 100, transistors 101, 102, 103, 104, capacitor elements 105, 106, and a transistor 301. Transistor 301 corresponds to transistor 101 and has the same function as transistor 101. Transistor 301 is an N-channel type. However, transistor 301 can be a P-channel type.

[0244] The first terminal of transistor 301 is connected to wiring 123D, the second terminal of transistor 301 is connected to wiring 311, and the gate of transistor 301 is connected to node A.

[0245] Wiring 123D corresponds to wirings 123A to 123C, and a signal S2 is input thereto. ​​​​​​​​​Therefore, similarly to FIG. 3(D), it is possible to share the wiring 123D with the wirings 123A to 123C. In this case, the first terminal of the transistor 301 is connected to the wiring 123. Assume that the signal S7 is output from the wiring 311. The signal S7 corresponds to the signal S1.

[0246] Next, the operation of the semiconductor device in FIG. 19(A) will be described with reference to the timing chart in FIG. 19(B). Note that the description of the parts common to the operation in FIG. 1(A) will be omitted.

[0247] First, in the period T1, the potential of the node A starts to rise. Then, similarly to the transistor 101, when the potential of the node A becomes the sum (V1 + Vth301) of the potential (V1) of the wiring 123D and the threshold voltage (Vth301) of the transistor 301, the transistor 301 turns on. Then, the wiring 123D and the wiring 311 become conductive. Therefore, since the signal S2 of the L level is supplied from the wiring 123D to the wiring 311, the potential of the wiring 311 decreases to V1.

[0248] Next, in the period T2, since the potential of the node A becomes V1 + Vth101 + α, the transistor 301 remains on. Then, the wiring 123D and the wiring 311 remain conductive. Therefore, since the signal S2 of the H level is supplied from the wiring 123D to the wiring 311, the potential of the wiring 311 rises to V2.

[0249] Next, in the period T3, the potential of the node A starts to decrease to V1. Similarly to the transistor 101, when the potential of the node A becomes the potential (V1) of the wiring 123D and the threshold voltage of the transistor 301 ​​​​​​​​​​Until it reaches the sum (V1 + Vth301) with the threshold voltage (Vth301), the transistor 301 is on. Therefore, since the L-level signal S1 is shared from the wiring 123D to the wiring 311, the potential of the wiring 311 decreases to V1. After that, when the potential of the node A decreases to V1 + Vth301, the transistor 301 turns off.

[0250] During the period T4 and the period T5, since the potential of the node A is maintained at V1, the transistor 3 01 remains off. Therefore, the wiring 123D and the wiring 311 remain in a non-conductive state.

[0251] In the semiconductor device of FIG. 19(A), the wiring 121 and the wiring 311 can output signals at the same timing. Therefore, one of the signal S1 output from the wiring 121 and the signal S7 output from the wiring 311 can be used to drive a load such as a gate line or a pixel, and the other signal can be used as a signal for driving another circuit such as a transfer signal. By doing so, another circuit can be driven without being affected by signal smear, or delay generated by driving a load or the like.

[0252] Note that a capacitive element can be connected between the gate of the transistor 301 and the second terminal. The capacitive element corresponds to the capacitive element 105.

[0253] Note that, as shown in FIG. 20(A), it is possible to add the transistor 301 to the semiconductor device of FIG. 6(A).

[0254] Note that, as shown in FIG. 20(B), the transistor 302, the transistor 303, and / or ​​​It is possible to add transistor 304. Transistors 302, 303, and 304 respectively correspond to transistors 134, 102, and 133 and have similar functions. The first terminal of transistor 302 is connected to wiring 122H, the second terminal of transistor 302 is connected to wiring 331, and the gate of transistor 302 is connected to wiring 126. The first terminal of transistor 303 is connected to wiring 331, the second terminal of transistor 303 is connected to node A, and the gate of transistor 303 is connected to wiring 123E. The first terminal of transistor 304 is connected to wiring 122I, the second terminal of transistor 304 is connected to wiring 331, and the gate of transistor 304 is connected to wiring 124C. However, it is not limited to this, and it is possible to add only one or two of transistors 302, 303, and 304. Transistors 302, 303, and 304 respectively correspond to transistors 134, 102, and 133 and have similar functions. The first terminal of transistor 302 is connected to wiring 122H, the second terminal of transistor 302 is connected to wiring 331, and the gate of transistor 302 is connected to wiring 126. The first terminal of transistor 303 is connected to wiring 331, the second terminal of transistor 303 is connected to node A, and the gate of transistor 303 is connected to wiring 123E. The first terminal of transistor 30 4 is connected to wiring 122I, the second terminal of transistor 304 is connected to wiring 331, and the gate of transistor 304 is connected to wiring 124C. However it is not limited to this, and it is possible to add only one or two of transistors 302, 303, and 30 4.

[0255] In addition, in FIG. 20(B), since the same signal (signal S2) as that of wirings 123A to 1 23C is input to wirings 123D and 123E, it is possible to share wirings 123D and 123E with wirings 123A to 123C. In this case, the first terminal of transistor 3 01 and the gate of transistor 303 can be connected to wiring 123.

[0256] In addition, in FIG. 20(B), since the same voltage (voltage V1) as that of wirings 122A to 1 22E is supplied to wirings 122H and 122I, it is possible to share wirings 122H and 122I with wirings 122A to 122E. In this case, transistor 3​ The first terminal of 02 and the first terminal of transistor 304 are connected to wiring 122. This is possible.

[0257] In addition, in FIG. 20(B), transistor 302 can be replaced with a diode or a transistor connected in diode connection, similar to transistor 135. Also, transistor 304 can be replaced with a diode or a transistor connected in diode connection, similar to transistor 133. This is possible.

[0258] Next, an example of a shift register having the semiconductor device described above will be described with reference to FIG. 21. Note that the content described in Embodiment 3 is omitted from the description. Alternatively, parts common to FIGS. 14 and 19 are denoted by the same reference numerals and the description thereof is omitted.

[0259] The shift register includes a plurality of flip - flops 320_1 to 320_N. Flip - flops 320_1 to 320_N correspond to flip - flops 200_1 to 200_N in FIG. 14. Alternatively, flip - flops 320_1 to 320_N correspond to the semiconductor devices in FIGS. 19(A), 20(A), or 20(B). FIG. 21 shows an example when the semiconductor device in FIG. 20(A) is used as an example.

[0260] In flip - flop 320_i, wiring 311 is connected to wiring 321_i. Then, wiring 126 is connected to wiring 321_i - 1.

[0261] Signals GS7_1 to GS7_N are respectively output from wirings 321_1 to 321_N. Let it be so. The signals GS7_1 to GS7_N correspond to the signal S7 and can function as transfer signals, output signals , selection signals, scanning signals, or gate signals.

[0262] Next, the operation of the shift register in FIG. 21 will be described with reference to the timing chart of FIG. 14(B). For reference.

[0263] The operation of the flip-flop 320_i will be described. First, the signal GS7_i - 1 becomes a high level. Then, the flip-flop 320_i starts operating in the period T2, and the signals GS1_i and GS7_i become low levels. After that, the signals GS2 and GS S3 are inverted. Then, the flip-flop 320_i starts operating in the period T2, and the signals GS1_i and GS7_i become high levels. The signal GS1_i is input as a reset signal to the flip flop 320_i - 1, and the signal GS7_i is input as a start signal to the flip flop 320_i + 1. Therefore, the flip-flop 3 20_i - 1 starts operating in the period T3, and the flip-flop 320_i + 1 starts operating in the period T1. After that, the signals GS2 and GS3 are inverted again. Then, the flip-flop 320_i + 1 starts operating in the period T2, and the signal GS 1_i + 1 becomes a high level. The signal GS1_i + 1 is input as a set signal to the flip-flop 320_i. Therefore, the flip-flop 320_i starts operating in the period T3, and the signals GS1_i and GS7_i become low levels. After that, until the signal GS7_i - 1 becomes high level again, the flip-flop 320_i is in the signal 1_i + 1 is input as a set signal to the flip-flop 320_i. Therefore, the flip-flop 320_i starts operating in the period T3, so the signals GS1_i and GS7_i become low levels. After that, until the signal GS7_i - 1 becomes high level again, the flip-flop 320_i is in the signal GS1_i, and signal GS7_i are at low levels. After that, until the signal GS7_i - 1 becomes high level again, the flip-flop 320_i is in the signal Every time GS2 and signal GS3 are inverted, the operations in period T4 and the operations in period T5 are repeated. Repeat.

[0264] In the shift register of this embodiment, since signals GS7_1 to GS7_N are used as start signals, the delay times of signals S1_1 to S1_N can be shortened. This is because signals GS7_1 to GS7_N are not input to gate lines, pixels, etc., so the delay or distortion is small compared to signals S1_1 to S1_N. Since signals GS7_1 to GS7_N are used as start signals, the delay times of signals S1_1 to S1_N can be shortened. Because signals GS7_1 to GS7_N are not input to gate lines or pixels, etc., the delay or distortion is small compared to signals S1_1 to S1_N. Since signals GS7_1 to GS7_N are not input to gate lines, pixels, etc., the delay or distortion is small compared to signals S1_1 to S1_N. That is why.

[0265] Alternatively, in the shift register of this embodiment, since signals GS1_1 to GS1_N are used as reset signals, in the operation of each flip-flop in period T3, the time that transistor 101 is turned on can be lengthened. Therefore, the fall times of signals S1_1 to S1_1 and signals GS7_1 to GS7_N can be shortened. Since signals GS1_1 to GS1_N are used as reset signals in the shift register of this embodiment, in the operation of each flip-flop in period T3, the time that transistor 101 is turned on can be lengthened. Therefore, the fall times of signals S1_1 to S1_1 and signals GS7_1 to GS7_N can be shortened. Since signals GS1_1 to GS1_N are used as reset signals, in the operation of each flip-flop in period T3, the time that transistor 101 is turned on can be lengthened. Therefore, the fall times of signals S1_1 to S1_1 and signals GS7_1 to GS7_N can be shortened. That is, the fall times of signals S1_1 to S1_1 and signals GS7_1 to GS7_N can be shortened.

[0266] Note that signals GS1_1 to GS1_N can be input as start signals to the flip-flops in the next stage. For example, signal GS1_i can be input as a start signal to flip-flop 320_i + 1. Note that signals GS1_1 to GS1_N can be input as start signals to the flip-flops in the next stage. For example, signal GS1_i can be input as a start signal to flip-flop 320_i + 1. For example, signal GS1_i can be input as a start signal to flip-flop 320_i + 1.

[0267] Note that signals GS7_1 to GS7_N can be input as reset signals to the flip-flops in the previous stage. For example, signal GS7_i can be input as a reset signal to flip-flop 320_i - 1. Note that signals GS7_1 to GS7_N can be input as reset signals to the flip-flops in the previous stage. For example, signal GS7_i can be input as a reset signal to flip-flop 320_i - 1. For example, signal GS7_i can be input as a reset signal to flip-flop 320_i - 1.

[0268] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0269] First, with reference to FIG. 22(A), an example of the system block of a liquid crystal display device will be described. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_ 2, a pixel portion 5364, a circuit 5365, and an illumination device 5366. In the pixel portion 5364, a plurality of wirings 5371 extend from the circuit 5362 and are arranged, and a plurality of wirings 5372 extend from the circuits 5363_1 and 5363_2 and are arranged. And in the intersection regions of the plurality of wirings 5 371 and the plurality of wirings 5372, pixels 5367 each having a display element such as a liquid crystal element are arranged in a matrix.

[0270] The circuit 5361 has a function of outputting a signal or a voltage, etc. to the circuit 5362, the circuit 5363_1, the circuit 5 363_2, and the circuit 5365 in response to the video signal 5360, and can function as a controller, a control circuit, a timing generator, or a regulator, etc.

[0271] As an example, the circuit 5361 outputs signals such as a start signal (SSP) for a signal line driving circuit, a clock signal (SCK) for a signal line driving circuit, an inverted clock signal (SCKB) for a signal line driving circuit, data (DATA) for a video signal, and a latch signal (LAT) to the circuit 5362. The circuit 5362 has a function of outputting a video signal to the plurality of wirings 5372 in response to these signals and functions as a signal line driving circuit.

[0272] Note that when a video signal is input to the plurality of wirings 5371, the plurality of wirings 5371 can function as signal lines, video signal lines, or source lines, etc.

[0273] The circuit 5361 outputs signals such as a start signal (GSP) for a scanning line driving circuit, a clock signal (GCK) for a scanning line driving circuit, and a clock signal (GCKB) for an inverted scanning line driving circuit, as an example, to the circuits 5363_1 and 5363_2. The circuits 5363_1 and 5363_2 have a function of outputting a scanning signal to a plurality of wirings 5371 according to these signals and function as a scanning line driving circuit. When a scanning signal is input to the plurality of wirings 5372, the plurality of wirings 5372 can function as signal lines, scanning lines, gate lines, or the like. Since the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2, the scanning signals output from the circuit 5363_1 to the plurality of wirings 5367 and the scanning signals output from the circuit 5363_2 to the plurality of wirings 5367 are generally at approximately the same timing. Therefore, the loads driven by the circuits 5363_1 and 5363_2 can be reduced. Thus, the display device can be enlarged. Or, the display device can be made high-definition. Or, since the channel width of the transistors included in the circuits 5363_1 and 5363_2 can be reduced, a display device with a narrow bezel can be obtained.

[0274] The circuit 5361 outputs a backlight control signal (BLC) to the circuit 5365, as an example. The circuit 5365 has a function of controlling the amount or time of power supplied to the lighting device 5366 according to the backlight control signal (BLC), thereby controlling the luminance (or average luminance) of the lighting device 5366 and functions as a power supply circuit.

[0275] The circuit 5361 outputs a backlight control signal (BLC) to the circuit 5365, as an example. The circuit 5365 has a function of controlling the amount or time of power supplied to the lighting device 5366 according to the backlight control signal (BLC), thereby controlling the luminance (or average luminance) of the lighting device 5366 and functions as a power supply circuit. Since the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2, the scanning signals output from the circuit 5363_1 to the plurality of wirings 5367 and the scanning signals output from the circuit 5363_2 to the plurality of wirings 5367 are generally at approximately the same timing. Therefore, the loads driven by the circuits 5363_1 and 5363_2 can be reduced. Thus, the display device can be enlarged. Or, the display device can be made high-definition. Or, since the channel width of the transistors included in the circuits 5363_1 and 5363_2 can be reduced, a display device with a narrow bezel can be obtained. The circuit 5361 outputs a backlight control signal (BLC) to the circuit 5365, as an example. The circuit 5365 has a function of controlling the amount or time of power supplied to the lighting device 5366 according to the backlight control signal (BLC), thereby controlling the luminance (or average luminance) of the lighting device 5366 and functions as a power supply circuit. Since the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2, the scanning signals output from the circuit 5363_1 to the plurality of wirings 5367 and the scanning signals output from the circuit 5363_2 to the plurality of wirings 5367 are generally at approximately the same timing. Therefore, the loads driven by the circuits 5363_1 and 5363_2 can be reduced. Thus, the display device can be enlarged. Or, the display device can be made high-definition. Or, since the channel width of the transistors included in the circuits 5363_1 and 5363_2 can be reduced, a display device with a narrow bezel can be obtained.

[0276] The circuit 5361 outputs a backlight control signal (BLC) to the circuit 5365, as an example. The circuit 5365 controls the amount of power supplied to the lighting device 5366 or the time, etc., according to the backlight control signal (BLC), thereby controlling the luminance (or average luminance) of the lighting device 5366 and functions as a power supply circuit. When a scanning signal is input to the plurality of wirings 5372, the plurality of wirings 5372 can function as signal lines, scanning lines, gate lines, or the like. Since the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2, the scanning signals output from the circuit 5363_1 to the plurality of wirings 5367 and the scanning signals output from the circuit 5363_2 to the plurality of wirings 5367 are generally at approximately the same timing.

[0277] Note that it is possible to omit one of circuit 5363_1 and circuit 5363_2.

[0278] Note that it is possible to newly arrange wirings such as capacitance lines, power supply lines, and scanning lines in pixel section 5364. And circuit 5361 can output signals or voltages or the like to these wirings. Or, a circuit similar to circuit 5363_1 or circuit 5363_2 can be newly added, and this newly added circuit can output signals such as scanning signals to the newly added wirings.

[0279] Note that pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in Fig. 22(B), since the display element emits light, circuit 5365 and lighting device 5366 can be omitted. And, in order to supply power to the display element, it is possible to arrange a plurality of wirings 5373 that can function as power supply lines in pixel section 5364. Circuit 5361 can supply a power supply voltage called voltage (ANO) to wiring 5373. This wiring 5373 can be connected separately for each color element of the pixel, or can be commonly connected to all pixels.

[0280] Note that in Fig. 22(B), as an example, circuit 5361 shows an example of the case of supplying different signals to circuit 5363_1 and circuit 5363_2. Circuit 5361 outputs signals such as a start signal (GSP1) for a scanning line driving circuit, a clock signal (GCK1) for a scanning line driving circuit, and a clock signal (GCKB1) for an inverted scanning line driving circuit to circuit 5363_1. Thus, circuit 5361 outputs signals such as a start signal (GSP2) for the scanning line driving circuit, a clock signal (GCK2) for the scanning line driving circuit, and an inverted clock signal (GCKB2) for the inverted scanning line driving circuit to circuit 5363_2. In this case, circuit 5363_1 scans only the wiring of the odd-numbered rows among the plurality of wirings 5372, and circuit 5363_2 can scan only the wiring of the even-numbered rows among the plurality of wirings 5372. Therefore, the driving frequency of circuits 5363_1 and 5363_2 can be reduced, so that power consumption can be reduced. Or, the area where one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. Or, the display device can be made larger.

[0281] Note that, as in FIG. 22(B), also in FIG. 22(A), circuit 5361 can supply separate signals to circuit 5363_1 and circuit 5363_2.

[0282] Next, an example of the configuration of the display device will be described with reference to FIGS. 23(A), (B), (C), (D), and (E).

[0283] In FIG. 23(A), circuits (for example, circuits 5362, 5363_1, and 5363_2, etc.) having the function of outputting signals to pixel section 5364 are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, the number of external components is reduced, so that cost can be reduced. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of connections between substrate ​The number of connections can be reduced. Thus, it is possible to improve reliability or yield. It can be done.

[0284] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate can be mounted on an FPC (Flexible Printed Circuit) by the TAB (Tape Automated Bonding) method. Or, the substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. Printed Circuit) by the TAB (Tape Automated Bonding) method. Or, the substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. Printed Circuit) by the TAB (Tape Automated Bonding) method. Or, the substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. The substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. The substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method.

[0285] When the circuit is formed on a substrate different from the pixel portion 5364, transistors using single crystal semiconductors can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain merits such as an improvement in drive frequency, an improvement in drive voltage, and a reduction in variation of output signals. When the circuit is formed on a substrate different from the pixel portion 5364, transistors using single crystal semiconductors can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain merits such as an improvement in drive frequency, an improvement in drive voltage, and a reduction in variation of output signals. When the circuit is formed on a substrate different from the pixel portion 5364, transistors using single crystal semiconductors can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain merits such as an improvement in drive frequency, an improvement in drive voltage, and a reduction in variation of output signals. The substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method.

[0286] In many cases, signals, voltages, currents, etc. are input from an external circuit via the input terminal 5381. In many cases, signals, voltages, currents, etc. are input from an external circuit via the input terminal 5381.

[0287] In FIG. 23(B), circuits with low drive frequencies (for example, circuit 5363_1, circuit 5363_ 2) are formed on the same substrate 5380 as the pixel portion 5364. And, circuit 5361 and circuit 5362 are formed on a substrate different from the pixel portion 5364. Thus, it becomes possible to configure the circuit formed on the substrate 5380 with transistors having a small mobility, so It becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, etc. as the semiconductor layer of the transistor. Therefore, the size of the display device can be increased and the number of processes can be reduced. It becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, etc. as the semiconductor layer of the transistor. Therefore, the size of the display device can be increased and the number of processes can be reduced. It becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, etc. as the semiconductor layer of the transistor. Therefore, the size of the display device can be increased and the number of processes can be reduced. It is possible to achieve reduction, cost reduction, or improvement in yield, etc.

[0288] As shown in FIG. 23(C), a part of circuit 5362 (circuit 5362a) is formed on the same substrate 5380 as pixel section 53 64, and the remaining circuit 5362 (circuit 5362b) can be formed on a substrate different from pixel section 5 364. Circuit 5362a is often a circuit (for example, a shift register, a selector, a switch, etc.) that can be constituted by transistors with low mobility. And circuit 5362b is preferably a circuit (for example, a shift register, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, etc.) that can be constituted by transistors with high mobility and small characteristic dispersion. By doing so, as in FIG. 23(B), it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor, and further reduction of external components can be achieved. In FIG. 23(D), circuits having a function of outputting a signal to pixel section 5364 (for example, circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.), and circuits having a function of controlling these circuits (for example, circuit 5361) are formed on a substrate different from pixel section 5364. Thus, since it becomes possible to form the pixel section and its peripheral circuits on separate substrates,

[0289] it is possible to improve the yield.

[0290] In FIG. 23(E), a part of circuit 5361 (circuit 5361a) is formed on the same substrate 5380 as pixel section 5364, and the remaining circuit 5361 (circuit 5361b) is different from pixel section 5364. It is formed on a substrate. Circuit 5361a is composed of transistors with low mobility. There are many cases where it has circuits (such as switches, selectors, level shift circuits, etc.) that can be configured. And circuit 5361b is preferably composed of transistors with high mobility and small variation. There are many cases where it has circuits (such as shift registers, timing generators, oscillators, regulators, or analog buffers, etc.).

[0291] Note that as circuit 5363_1 and circuit 5363_2, the semiconductor devices of Embodiments 1 to 4, or a shift register can be used. In this case, when circuit 5363_ 1 and circuit 5363_2 are formed on the same substrate as the pixel portion, it is possible to make the polarities of all the transistors formed on the substrate N-channel type or P-channel type. Thus, it is possible to reduce the number of processes, improve the yield, or reduce the cost. In particular, by making the polarities of all the transistors N-channel type, it becomes possible to use a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc. as the semiconductor layer of the transistor. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield.

[0292] Note that transistors using a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc. as the semiconductor layer often cause characteristic degradation such as an increase in the threshold voltage or a decrease in mobility. However, the semiconductor devices of Embodiments 1 to 4, or the shift register can suppress the characteristic degradation of the transistor, so the life of the display device can be extended.

[0293] Note that as part of circuit 5362, the semiconductor devices of Embodiments 1 to 4, or a shift register can be used. For example, circuit 5362a shown in Fig. 23(C) can have the semiconductor devices of Embodiments 1 to 4, or a shift register.

[0294] (Embodiment 6) In this embodiment, a layout diagram of a shift register (hereinafter also referred to as a top view) will be described. In this embodiment, as an example, the layout diagram of the shift register in Fig. 15 will be described. Note that the content described in this embodiment can also be applied to the semiconductor devices, shift registers, or display devices of Embodiments 1 to 5, in addition to the shift register in Fig. 15. It should be noted that the layout diagram of this embodiment is an example and is not limited thereto.

[0295] The layout diagram of this embodiment will be described with reference to Figs. 30 and 31. Fig. 30 shows an example of a partial layout diagram of the shift register, and Fig. 31 shows, as an example, the layout diagram of flip-flop 200_i.

[0296] The transistors, capacitive elements, or wirings shown in Figs. 30 and 31 are formed by conductive layer 401, semi- conductor layer 402, conductive layer 403, conductive layer 404, and contact hole 405. However, it is not limited thereto, and another conductive layer, insulating film, or another contact hole can be formed newly. For example, a contact hole for connecting conductive layer 401 and conductive layer 403 can be newly added.

[0297] ​​​The conductive layer 401 can include a portion that functions as a gate electrode or a wiring. Half The semiconductor layer 402 can include a portion that functions as a semiconductor layer of a transistor. The conductive layer 403 can include a portion that functions as a wiring, a source, or a drain. The conductive layer 404 can include a portion that functions as a transparent electrode, a pixel electrode, or a wiring. The contact hole 405 can be used to connect the conductive layer 401 and the conductive layer 404, or to connect the conductive layer 403 and the conductive layer 404.

[0298] In an example of FIG. 30, the wiring 202 has an opening 411, and the wiring 203 has an opening 412. In this way, by having the openings in the wiring 202 and the wiring 203, the parasitic capacitance can be reduced. Or, the breakdown of the transistor caused by electrostatic breakdown can be suppressed. However, it is not limited to this, and like the wiring 204, the opening 411 or the opening 412 can be omitted. Or, an opening can be provided in the wiring 204 in the same way as the wiring 202 or the wiring 203.

[0299] In an example of FIG. 30, by providing an opening at a part of the intersection of the wiring 202 or the wiring 203 and another wiring, the crosstalk capacitance of the wiring can be reduced. Therefore, noise reduction, or reduction of signal delay or distortion can be achieved.

[0300] In an example of FIG. 30, the conductive layer 404 is formed on a part of the conductive layer 403 included in the wiring 204. And the conductive layer 404 is connected to the conductive layer 4 03 through the contact hole 405. In this way, the wiring resistance can be reduced, so the reduction of voltage drop , or the delay or attenuation of the signal can be reduced. However, it is not limited to this, and the conductive layer 404 and the contact hole 405 can be omitted. Or , similar to the wiring 204, in the wiring 202 or the wiring 203, a part of the conductive layer 403 has a conductive layer 404 formed thereon, and the conductive layer 404 can be connected to the conductive layer 403.

[0301] Here, in an example of FIG. 30, the wiring widths of the wiring 202, the wiring 203, and the wiring 2 04 are respectively shown as the wiring width 421, the wiring width 422, and the width 423. And the opening widths of 411, the length of the opening 411, the width of the opening 412, and the length of the opening 412 are respectively , shown as the width 424, the length 425, the width 426, and the length 427.

[0302] The signals input to the wiring 202 and the wiring 203 are often signals inverted from each other. Therefore, it is preferable that the wiring resistance or parasitic capacitance of the wiring 202 is set to be approximately equal to the wiring resistance or parasitic capacitance of the wiring 203. Accordingly, it is preferable that the wiring 202 includes a portion approximately equal to the wiring width 422. Or, the opening 411 preferably includes a portion approximately equal to the width 426 or the length 427 of the opening 412. However, it is not limited to this, and the wiring width 421, the wiring width 422, the width 424 of the opening 411, the length 425 of the opening 411, or the length 427 of the opening 412 can be set to various values. For example, assuming that the cross-capacitance between the wiring 202 and other wirings is larger than the cross-capacitance between the wiring 203 and other wirings. In this case, by reducing the wiring resistance of the wiring 202, the delay or attenuation of the signals input to the wiring 202 and the wiring 203 can be approximately reduced. It is possible to set them to be equal. For this purpose, the wiring 202 can include a portion larger than the wiring width 42 2. Or, the opening 411 can include a portion smaller than the width 426 of the opening 412. Or, the opening 411 can include a portion shorter than the length 427 of the opening 4 12. On the other hand, when the mutual capacitance between the wiring 202 and other wirings is smaller than the mutual capacitance between the wiring 203 and other wirings, the wiring 202 can include a portion smaller than the wiring width 422. Or, the opening 411 can include a portion larger than the width 426 of the opening 412. Or, the opening 411 can include a portion longer than the length 427 of the opening 412.

[0303] When the wiring 204 does not have an opening, the wiring 204 preferably includes a portion with a wiring width 421 or smaller than the wiring width 42 2. This is because the wiring 204 does not have an opening, so the wiring resistance of the wiring 204 is small. However, it is not limited to this, and the wiring 2 04 can include a portion larger than the wiring width 421 or the wiring width 422.

[0304] In an example of FIG. 31, in the capacitor element 105 and the capacitor element 106, one electrode is formed by the conductive layer 401, and the other electrode is formed by the conductive layer 403. By doing so, the capacitance value per unit area can be increased, so the layout area can be reduced . However, it is not limited to this, and it is possible to dispose the semiconductor layer 402 between the conductive layer 401 and the conductive layer 403. By doing so, it is possible to suppress the conductive layer 401 and the conductive layer 403 from short-circuiting. Or, the capacitor element ​​​​​​ 105 or the capacitive element 106 can be a MOS capacitor.

[0305] In an example of FIG. 31, in transistors 101, 103, 104, 131, 132, 133, 134, and 135, the overlapping area of the conductive layer 401 and the conductive layer 403 of the second terminal is preferably smaller than the overlapping area of the conductive layer 401 and the conductive layer 403 of the first terminal. By doing so, the gate of the transistor 101 or the noise of the wiring 201_i can be reduced. Or, since the concentration of the electric field on the second terminal can be suppressed, the deterioration or destruction of the transistor can be suppressed. In addition, a semiconductor layer 402 can be formed in the overlapping portion of the conductive layer 401 and the conductive layer 403. By doing so, the parasitic capacitance between the conductive layer 401 and the conductive layer 403 can be reduced, so that noise can be reduced. For the same reason, a semiconductor layer 402 or a conductive layer 403 can be formed in the overlapping portion of the conductive layer 401 and the conductive layer 404.

[0306] Note that a semiconductor layer 402 can be formed in the overlapping portion of the conductive layer 401 and the conductive layer 403. By doing so, the parasitic capacitance between the conductive layer 401 and the conductive layer 403 can be reduced, so that noise can be reduced. For the same reason, a semiconductor layer 402 or a conductive layer 403 can be formed in the overlapping portion of the conductive layer 401 and the conductive layer 404. Note that the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405. By doing so, the wiring resistance can be reduced. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 can be connected to another contact hole 405.

[0307] Note that the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405. By doing so, the wiring resistance can be reduced. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 can be connected to another contact hole 405. In this way, the wiring resistance can be reduced. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 can be connected to another contact hole 405. and the conductive layer 404, and the conductive layer 401 is connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 is connected to another contact hole 405. In this way, the wiring resistance can be reduced. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 can be connected to another contact hole 405. It can be connected to the conductive layer 404. By doing so, the wiring resistance can be further reduced. Lowered further.

[0308] Note that the conductive layer 404 is formed on a part of the conductive layer 403, and the conductive layer 403 can be connected to the conductive layer 404 via the contact hole 405. By doing so, the wiring resistance can be reduced. Note that the conductive layer 404 is formed on a part of the conductive layer 403, and the conductive layer 403 can be connected to the conductive layer 404 via the contact hole 405. By doing so, the wiring resistance can be reduced. Lowered further.

[0309] Note that the conductive layer 401 or the conductive layer 403 is formed under a part of the conductive layer 404, and the conductive layer 404 can be connected to the conductive layer 401 or the conductive layer 403 via the contact hole 405. By doing so, the wiring resistance can be reduced. Note that the conductive layer 401 or the conductive layer 403 is formed under a part of the conductive layer 404, and the conductive layer 404 can be connected to the conductive layer 401 or the conductive layer 403 via the contact hole 405. By doing so, the wiring resistance can be reduced. Lowered further. 。

[0310] Note that when the capacitor element 105 is omitted, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. An example of the layout diagram of the transistor 101 in this case is shown in FIG. 18. In an example of FIG. 18, the width of the conductive layer 403 that can function as the first electrode of the transistor 101 is shown as width 431, and the width of the conductive layer 403 that can function as the second electrode of the transistor 101 is shown as width 432. Then, the width 431 can be larger than the width 432. By doing so, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. However, it is not limited to this. Note that when the capacitor element 105 is omitted, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. An example of the layout diagram of the transistor 101 in this case is shown in FIG. 18. In an example of FIG. 18, the width of the conductive layer 403 that can function as the first electrode of the transistor 101 is shown as width 431, and the width of the conductive layer 403 that can function as the second electrode of the transistor 101 is shown as width 432. Then, the width 431 can be larger than the width 432. By doing so, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. However, it is not limited to this. Lowered further. An example of the layout diagram of the transistor 101 in this case is shown in FIG. 18. In an example of FIG. 18, the width of the conductive layer 403 that can function as the first electrode of the transistor 101 is shown as width 431, and the width of the conductive layer 403 that can function as the second electrode of the transistor 101 is shown as width 432. An example of the layout diagram of the transistor 101 in this case is shown in FIG. 18. In an example of FIG. 18, the width of the conductive layer 403 that can function as the first electrode of the transistor 101 is shown as width 431, and the width of the conductive layer 403 that can function as the second electrode of the transistor 101 is shown as width 432. Then, the width 431 can be larger than the width 432. By doing so, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. Then, the width 431 can be larger than the width 432. By doing so, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. Lowered further. Note that when the capacitor element 105 is omitted, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. An example of the layout diagram of the transistor 101 in this case is shown in FIG. 18. In an example of FIG. 18, the width of the conductive layer 403 that can function as the first electrode of the transistor 101 is shown as width 431, and the width of the conductive layer 403 that can function as the second electrode of the transistor 101 is shown as width 432. Then, the width 431 can be larger than the width 432. By doing so, as described in Embodiment 1, the parasitic capacitance between the gate of the transistor 101 and the second terminal can be made larger than the parasitic capacitance between the gate of the transistor 101 and the first terminal. However, it is not limited to this. Lowered further.

[0311] (Embodiment 7) In this embodiment, an example of a signal line driving circuit will be described. Note that the signal line driving circuit can be represented as a semiconductor device or a signal generation circuit.

[0312] An example of the signal line driving circuit will be described with reference to FIG. 26(A). The signal line driving circuit includes a plurality of circuits 502_1 to 502_N (N is a natural number), a circuit 500, and a circuit 501. The circuits 502_1 to 502_N each include a plurality of transistors 503_1 to 503_k (k is a natural number). The transistors 503_1 to 503_k are assumed to be N-channel type. However, the present invention is not limited to this, and the transistors 503_1 to 503_k can be P-channel type or CMOS type switches.

[0313] The connection relationship of the signal line driving circuit will be described by taking the circuit 502_1 as an example. The first terminals of the transistors 503_1 to 503_k are connected to the wiring 505_1. The second terminals of the transistors 503_1 to 503_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 503_1 to 503_k are connected to the wirings 504_1 to 504_k, respectively. For example, the first terminal of the transistor 503_1 is connected to the wiring 505_1, the second terminal of the transistor 503_1 is connected to the wiring S1, and the gate of the transistor 503_1 is connected to the wiring 504_1.

[0314] The circuit 500 has a function of supplying signals to the circuits 502_1 to 502_N via the wirings 504_1 to 504_k, and can function as a shift register, a decoder, or the like. ​​​​​​​​​​​​It is. The signal is often a digital signal and can function as a selection signal. And the wirings 504_1 to 504_k can function as signal lines.

[0315] The circuit 501 has a function of outputting a signal to the circuits 502_1 to 502_N and can function as a video signal generation circuit or the like. For example, the circuit 501 supplies a signal to the circuit 502_1 via the wiring 505_1. At the same time, it supplies a signal to the circuit 502_2 via the wiring 505_2. The signal is often an analog signal and can function as a video signal. And the wirings 505_1 to 505_N can function as signal lines.

[0316] The circuits 502_1 to 502_k have a function of selecting to which wiring the output signal of the circuit 501 is output and can function as a selector circuit. For example, the circuit 502_1 has a function of selecting to which of the wirings S1 to Sk the signal output by the circuit 501 to the wiring 505_1 is output.

[0317] The transistors 503_1 to 503_N each have a function of controlling the conduction state between the wiring 505_1 and the wirings S1 to Sk according to the output signal of the circuit 500 and function as switches.

[0318] Next, the operation of the signal line driving circuit in Fig. 26(A) will be described with reference to the timing chart in Fig. 26(B). In Fig. 26(B), the signal 514_1 input to the wiring 504_1, the signal 514_2 input to the wiring 504_2, and the signal 514 input to the wiring 504_k ​​​​​​​​​​​​​_k, the signal 515_1 input to the wiring 505_1, and the letter An example of 515_2 input to the wiring 505_2 is shown.

[0319] Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The one gate selection period refers to a period during which the pixels belonging to a certain row are selected and a video signal can be written to the pixels. That is what it means.

[0320] Note that the one gate selection period is divided into a period T0, a period T1, and up to a period Tk. The period T0 is a period for simultaneously applying a precharge voltage to the pixels belonging to the selected row, and can function as a precharge period. The periods T1 to Tk are each a period for writing a video signal to the pixels belonging to the selected row, and can function as a writing period.

[0321] For the sake of convenience, the operation of the circuit 502_1 is taken as an example to explain the operation of the signal line driving circuit.

[0322] First, in the period T0, the circuit 500 outputs a signal of H level to the wirings 504_1 to 504_k. Then, since the transistors 503_1 to 503_k are turned on, the wiring 50 5_1 and the wirings S1 to Sk are in a conductive state. At this time, since the circuit 501 supplies the precharge voltage Vp to the wiring 505_ 1, the precharge voltage Vp is output to the wirings S1 to Sk through the transistors 503_1 to 503_k, respectively. And the pre charge voltage Vp is written to the pixels belonging to the selected row, so the pixels belonging to the selected row are precharged.

[0323] ​Next, during period T1, circuit 500 outputs a signal of H level to wiring 504_1. Then, since transistor 503_1 is turned on, wiring 505_1 and wiring S1 are electrically connected. And wiring 505_1 and wiring S2~Sk are in a non-conductive state. At this time , assuming that circuit 501 outputs signal Data(S1) to wiring 505_1, signal Data(S1) is output to wiring S1 via transistor 503_1. In this way , signal Data(S1) is written to the pixels belonging to the selected row among the pixels connected to wiring S1.

[0324] Next, during period T2, circuit 500 outputs a signal of H level to wiring 504_2. Then, since transistor 503_2 is turned on, wiring 505_2 and wiring S2 are electrically connected. And wiring 505_1 and wiring S1 are in a non-conductive state, and wiring 505_1 and wiring S3~Sk remain in a non-conductive state. At this time, assuming that circuit 501 outputs signal Data (S2) to wiring 505_1, signal Data(S2) is output to wiring S2 via transistor 503_2. In this way, signal Data(S2) is written to the pixels belonging to the selected row among the pixels connected to wiring S2.

[0325] Thereafter, until period Tk, circuit 500 outputs signals of H level to wirings 504_1~504_k in sequence. Therefore, similar to period T1 and period T2, from period T3 to period Tk, circuit 5 00 outputs signals of H level to wirings 504_3~504_k in sequence. Thus, transistors 503_3~503_k are turned on in sequence, so transistors 503_1~503 _N is turned on in sequence. Therefore, the signal output from circuit 501 is output to wirings S1 to Sk in sequence. In this way, it becomes possible to write signals to the pixels belonging to the selected row in sequence.

[0326] Since the signal line driving circuit of the present embodiment has a circuit that functions as a selector, the number of signals , or the number of wirings can be reduced. Or, before writing the video signal to the pixel (period T 0), a voltage for pre-charge is written to the pixel, so the writing time of the video signal can be shortened. Therefore, it is possible to increase the size of the display device and increase the definition of the display device . However, it is not limited to this, and it is possible to omit period T0 and not perform pre-charge on the pixel .

[0327] If k is too large, the writing time to the pixel becomes short, so there may be a case where the writing of the video signal to the pixel is not completed within the time. Therefore, it is preferable that k ≤ 6 . More preferably, it is preferable that k ≤ 3. Even more preferably, it is preferable that k = 2 .

[0328] In particular, when the color elements of the pixel are divided into n (n is a natural number) pieces, it is possible to set k = n . For example, when the color elements of the pixel are divided into three: red (R), green (G), and blue (B) , it is possible that k = 3. In this case, one gate selection period is divided into period T0, period T1 , period T2, and period T3. And in period T1, period T2, and period T3, respectively , it is possible to write the video signal to the red (R) pixel, the green (G) pixel, and the blue (B) pixel . However, it is not limited to this, and the order of period T1, period T2, and period T3 can be arbitrarily set .

[0329] In particular, when a pixel is divided into n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or auxiliary pixels), it is possible to set k = n. For example, when a pixel is divided into two sub-pixels, k = 2 is possible. In this case, one gate selection period is divided into a period T0, a period T1, and a period T2. Then, in the period T1, a video signal can be written to one of the two sub-pixels, and in the period T2, a video signal can be written to the other of the two sub-pixels. When divided, it is possible to set k = 2. In this case, one gate selection period is divided into period T0, period T1, and period T2. And in period T1, a video signal is written to one of the two sub-pixels, and in period T2, a video signal is written to the other of the two sub-pixels. When divided, it is possible to set k = 2. In this case, one gate selection period is divided into period T0, period T1, and period T2. And in period T1, a video signal is written to one of the two sub-pixels, and in period T2, a video signal is written to the other of the two sub-pixels. When divided, it is possible to set k = 2. In this case, one gate selection period is divided into period T0, period T1, and period T2. And in period T1, a video signal is written to one of the two sub-pixels, and in period T2, a video signal is written to the other of the two sub-pixels. When divided, it is possible to set k = 2. In this case, one gate selection period is divided into period T0, period T1, and period T2. And in period T1, a video signal is written to one of the two sub-pixels, and in period T2, a video signal is written to the other of the two sub-pixels. When divided, it is possible to set k = 2. In this case, one gate selection period is divided into period T0, period T1, and period T2. And in period T1, a video signal is written to one of the two sub-pixels, and in period T2, a video signal is written to the other of the two sub-pixels.

[0330] Since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, the circuit 500 and the circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Furthermore, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, the circuit 500 and the circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Furthermore, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, the circuit 500 and the circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Furthermore, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, the circuit 500 and the circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Furthermore, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, the circuit 500 and the circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Furthermore, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, the circuit 500 and the circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Furthermore, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced.

[0331] As the circuit 500, it is possible to use the semiconductor device or the shift register of Embodiments 1 to 4. In this case, it is possible to make all the transistors of the circuit 500 N-channel type or P-channel type. Therefore, the number of processes can be reduced, the yield can be improved, or the cost can be reduced. As the circuit 500, it is possible to use the semiconductor device or the shift register of Embodiments 1 to 4. In this case, it is possible to make all the transistors of the circuit 500 N-channel type or P-channel type. Therefore, the number of processes can be reduced, the yield can be improved, or the cost can be reduced. As the circuit 500, it is possible to use the semiconductor device or the shift register of Embodiments 1 to 4. In this case, it is possible to make all the transistors of the circuit 500 N-channel type or P-channel type. Therefore, the number of processes can be reduced, the yield can be improved, or the cost can be reduced. As the circuit 500, it is possible to use the semiconductor device or the shift register of Embodiments 1 to 4. In this case, it is possible to make all the transistors of the circuit 500 N-channel type or P-channel type. Therefore, the number of processes can be reduced, the yield can be improved, or the cost can be reduced.

[0332] In addition to the circuit 500, it is also possible to make all the transistors of the circuits 502_1 to 502_N N-channel type or P-channel type. Therefore, the circuit 5 In addition to the circuit 500, it is also possible to make all the transistors of the circuits 502_1 to 502_N N-channel type or P-channel type. Therefore, the circuit 5 00, and when circuits 502_1 to 502_N are formed on the same substrate as the pixel portion, the number of processes can be reduced, the yield can be improved, or the cost can be reduced. In particular, by making the polarity of all transistors N-channel type, as the semiconductor layer of the transistor, a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor can be used. Naturally, the driving frequencies of circuits 500 and 502_1 to 502_N are often low because of this.

[0333] (Embodiment 8) In this embodiment, the configuration and operation of pixels applicable to a liquid crystal display device will be described.

[0334] FIG. 27(A) is a diagram showing an example of a pixel configuration applicable to a liquid crystal display device. Pixel 508 0 has a transistor 5081, a liquid crystal element 5082, and a capacitor element 5083. The gate of transistor 5081 is electrically connected to wiring 5085. The first terminal of transistor 508 1 is electrically connected to wiring 5084. The second terminal of transistor 5081 is electrically connected to the first terminal of liquid crystal element 5082. The second terminal of liquid crystal element 5082 is connected to wiring 5087 electrically. The first terminal of capacitor element 5083 is electrically connected to the first terminal of liquid crystal element 5082. The second terminal of capacitor element 5083 is electrically connected to wiring 5086 and connected.

[0335] Wiring 5084 can function as a signal line. The signal line is a wiring for transmitting a signal voltage input from outside the pixel to pixel 5080. Wiring 5085 can function as a scanning line and can control the on / off of transistor 5081. It is a wiring. The wiring 5086 can function as a capacitance line. The capacitance line is a wiring for applying a predetermined voltage to the second terminal of the capacitance element 5083. The transistor 5081 can function as a switch. The capacitance element 5083 can function as a holding capacitance . The holding capacitance is a capacitance element for allowing the signal voltage to continue to be applied to the liquid crystal element 5 even when the switch is off. The wiring 5087 can function as a counter electrode. The counter electrode is a wiring for applying a predetermined voltage to the second terminal of the liquid crystal element 5082 . Note that the functions that each wiring can have are not limited to this, and it can have various functions. For example, by changing the voltage applied to the capacitance line , the voltage applied to the liquid crystal element can also be adjusted. Note that since the transistor 5081 only needs to function as a switch, the polarity of the transistor 5081 can be P-channel type or N-channel type.

[0336] Figure 27(B) is a diagram showing an example of a pixel configuration applicable to a liquid crystal display device. The pixel configuration example shown in Figure 27(B ) is the same configuration as the pixel configuration example shown in Figure 27(A), except that the wiring 5087 is omitted , and the second terminal of the liquid crystal element 5082 and the second terminal of the capacitance element 5083 are electrically connected . The pixel configuration example shown in Figure 27(B) is applicable particularly when the liquid crystal element is in the horizontal electric field mode (including the IPS mode and the FFS mode). This is because when the liquid crystal element is in the horizontal electric field mode, the second terminal of the liquid crystal element 5082 and the second terminal of the capacitance element 5083 Since they can be formed on the same substrate, it is easy to electrically connect the second terminal of the liquid crystal element 5082 and the second terminal of the capacitor element 5 083. By adopting the pixel configuration shown in FIG. 27(B), the wiring 5087 can be omitted, so that the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0337] The pixel configurations shown in FIGS. 27(A) and 27(B) can be arranged in a matrix. By doing so, a display portion of a liquid crystal display device is formed, and various images can be displayed . FIG. 27(C) is a diagram showing a circuit configuration when the pixel configurations shown in FIG. 27(A) are arranged in a matrix . The circuit configuration shown in FIG. 27(C) is a diagram showing four pixels extracted from among a plurality of pixels included in the display portion . A pixel located at the i-th column and j-th row (i and j are natural numbers) is denoted as pixel 5080_i,j, and the wiring 5084_i, the wiring 5085_j, and the wiring 5086_j are electrically connected to the pixel 5080_i,j, respectively. Similarly, for the pixel 5080_i+1,j, the wiring 5084_i+1, the wiring 5 085_j, and the wiring 5086_j are electrically connected . Similarly, for the pixel 5080_i,j+ 1, the wiring 5084_i, the wiring 5085_j+1, and the wiring 5086_j+1 are electrically connected. Similarly, for the pixel 5080_i+1,j+1, the wiring 5084_i +1, the wiring 5085_j+1, and the wiring 5086_j+1 are electrically connected . Each wiring can be shared by a plurality of pixels belonging to the same column or row . In the pixel configuration shown in FIG. 27(C), the wiring 5087 is a counter electrode, and the counter electrode is provided for all pixels Since it is common in [the above], for wiring 5087, it will not be denoted by natural number i or j. Note tha...

Claims

1. a gate driver including a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first clock signal line via a first conductive layer intersecting the second clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the gate line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate line; a second conductive layer having a function as the first clock signal line has a region in contact with the first conductive layer in a first contact hole; the second conductive layer has a region in contact with a third conductive layer having a region disposed above the second conductive layer in a second contact hole having an area larger than that of the first contact hole in a plan view; the first contact hole and the second contact hole are disposed in the gate driver; Display device.

2. a gate driver including a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first clock signal line via a first conductive layer intersecting the second clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the gate line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate line; a second conductive layer having a function as the first clock signal line has a region in contact with the first conductive layer in a first contact hole; the second conductive layer has a region in contact with a third conductive layer having a region disposed above the second conductive layer in a second contact hole having an area larger than that of the first contact hole in a plan view; a fourth conductive layer having a function as the second clock signal line and intersecting the first conductive layer does not overlap with the third conductive layer; the first contact hole and the second contact hole are disposed in the gate driver; Display device.

3. In claim 2, the fourth conductive layer has a plurality of stacked conductive layers; Display device.

4. a gate driver including a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first clock signal line via a first conductive layer intersecting the second clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the gate line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate line; a second conductive layer having a function as the first clock signal line has a region in contact with the first conductive layer in a first contact hole; the second conductive layer has a region in contact with a third conductive layer having a region disposed above the second conductive layer in a second contact hole having an area larger than that of the first contact hole in a plan view; the fifth conductive layer having a function as the power supply line has a region in contact with a sixth conductive layer disposed above the fifth conductive layer in a third contact hole having an area larger in a plan view than the first contact hole; the first contact hole, the second contact hole, and the third contact hole are disposed in the gate driver; Display device.

5. a gate driver including a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor; one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first clock signal line via a first conductive layer intersecting the second clock signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the gate line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the power supply line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate line; a second conductive layer having a function as the first clock signal line has a region in contact with the first conductive layer in a first contact hole; the second conductive layer has a region in contact with a third conductive layer having a region disposed above the second conductive layer in a second contact hole having an area larger than that of the first contact hole in a plan view; a fourth conductive layer having a function as the second clock signal line and intersecting the first conductive layer does not overlap with the third conductive layer; the fifth conductive layer having a function as the power supply line has a region in contact with a sixth conductive layer disposed above the fifth conductive layer in a third contact hole having an area larger in a plan view than the first contact hole; the first contact hole, the second contact hole, and the third contact hole are disposed in the gate driver; Display device.

6. In claim 5, the fourth conductive layer has a plurality of stacked conductive layers; Display device.

7. In any one of claims 4 to 6, The fifth conductive layer has a plurality of stacked conductive layers. Display device.

8. In any one of claims 4 to 7, The sixth conductive layer has a plurality of stacked conductive layers. Display device.

9. In any one of claims 1 to 8, The gate line is always electrically connected to the gate of the transistor of the pixel. Display device.

10. In any one of claims 1 to 8, the second conductive layer has a region extending along a first direction; the third conductive layer has a region extending along the first direction; Display device.

11. In any one of claims 1 to 10, The second conductive layer has a plurality of laminated conductive layers. Display device.

12. In any one of claims 1 to 11, The third conductive layer has a plurality of stacked conductive layers. Display device.

Images