Imaging device and control method thereof

Abstract

To prevent a reduction in framing performance in an imaging apparatus that can switch a display unit that displays moving images.SOLUTION: An imaging apparatus has: an image pickup device that photographs moving images and still images; a plurality of displays including a first display and a second display; selection means that selects one of the plurality of displays as a display destination for displaying the moving images; display control means that performs control to display the moving images on the display selected by the selection means according to a second synchronization signal; generation means that, when the second display displays the moving images, generates a third synchronization signal matching the second synchronization signal; and control means that, when receiving an operation, controls to shift the timing of assertion of the third synchronization signal by a predetermined shift amount.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to an imaging device and a control method thereof.

Background Art

[0002] Some digital cameras and electronic devices equipped with a camera function (hereinafter referred to as an imaging device) have a live view (LV) function. The LV function is a function of shooting a video and sequentially displaying the images of each obtained frame (hereinafter referred to as "LV images") on a display unit in parallel with the shooting. If the LV image is displayed in the viewfinder, the user can adjust while checking the shooting range for still image shooting or video shooting. Hereinafter, this adjustment operation of the shooting range is referred to as "framing". And the ease of framing (framing performance) decreases as the time (display delay) from the start of shooting the LV image to the display on the display unit increases.

[0003] Therefore, a technique for shortening this display delay has been devised. For example, in Patent Document 1, a method of generating a first vertical synchronization signal for imaging and a second vertical synchronization signal whose timing is shifted based on this, and displaying an image in accordance with the second vertical synchronization signal is described. Further, in Patent Document 2, a method of controlling an imaging unit at a period synchronized with the frame period of a display unit that is displaying an image among two display units is described.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Furthermore, some imaging devices have multiple display units. During continuous shooting of still images (continuous shooting), it is common practice to switch the display unit (display destination) that shows the LV image. In this case, the time from the start of LV image capture to its display on the display unit (display delay) may increase due to the time from the instruction to start continuous shooting to the start of shooting, and the differences in the frame cycles of each display unit.

[0006] In this regard, the technology described in Patent Document 1 does not mention switching control between display units when multiple display units are provided. Furthermore, in the technology described in Patent Document 2, when switching between display units that display an image among multiple display units, it is necessary to resynchronize the imaging with the frame period of the display unit, which results in a display delay. This has led to the problem of reduced ease of framing (framing performance).

[0007] Therefore, the present invention aims to suppress a decrease in framing performance in an imaging device that can switch the display unit for displaying video. [Means for solving the problem]

[0008] A first aspect of the present invention is: An image sensor that operates according to a first synchronization signal and captures video and still images, A plurality of display devices, including a first display device and a second display device, A selection means for selecting one of the plurality of display devices as a display destination for displaying the video, A display control means that controls the display device selected by the selection means to display the video according to a second synchronization signal, A means for receiving instructions to take continuous still images, A generation means that generates a third synchronization signal that matches the second synchronization signal when the second display device displays the video, Upon receiving the aforementioned operation, a control means controls the assertion timing of the third synchronization signal to shift by a predetermined amount, This imaging device is characterized by having [a certain feature].

[0009] A second aspect of the present invention is: An image sensor that operates according to a first synchronization signal and captures video and still images, A plurality of display devices, including a first display device and a second display device, A selection means for selecting one of the plurality of display devices as a display destination for displaying the video, A display control means that controls the display device selected by the selection means to display the video according to a second synchronization signal, A means for receiving instructions to take continuous still images, During the continuous shooting of the aforementioned still images, if the second display device displays a video, the assertion timing of the second synchronization signal is shifted by a predetermined amount during the period in which the second display device displays the video. If the second display device is displaying the video at the end of continuous shooting of the still images, and the selection means switches the display destination of the video from the second display device to the first display device after the end of continuous shooting of the still images, the control means controls the stopping of shifting the assertion timing of the second synchronization signal by the predetermined amount. This imaging device is characterized by having [a certain feature].

[0010] A third aspect of the present invention is: An image sensor that operates according to a first synchronization signal and captures video and still images, A plurality of display devices, including a first display device and a second display device, A selection means for selecting one of the plurality of display devices as a display destination for displaying the video, A display control means controls the display of the video on the display device selected by the selection means according to a second synchronization signal, and when a display update instruction is notified, it controls the display of the video to be updated at the assertion timing of the second synchronization signal. A means for receiving instructions to take continuous still images, Notification means for notifying the display update instruction, wherein during continuous shooting of still images, the timing of notifying the display update instruction differs depending on whether the instruction is to be notified to the first display device or to the second display device. During continuous shooting of the still images, when the second display device displays a video, the control means controls the assertion timing of the second synchronization signal to be shifted by a predetermined amount during the period in which the second display device displays the video. This imaging device is characterized by having [a certain feature].

[0011] A fourth aspect of the present invention is: A control method for an imaging device having an image sensor that operates according to a first synchronization signal and captures video and still images, and a plurality of display devices including a first display device and a second display device, A selection step of selecting one of the plurality of display devices as the display destination for displaying the video, A display control step that controls the display device selected in the selection step to display the video according to a second synchronization signal, A reception process for accepting requests for continuous shooting of still images, A generation step of generating a third synchronization signal that matches the second synchronization signal when the second display device displays the video, Upon receiving the aforementioned operation, a control step is performed to control the assertion timing of the third synchronization signal to shift by a predetermined amount; This is a control method characterized by having [a certain feature].

[0012] A fifth aspect of the present invention is: A control method for an imaging device having an image sensor that operates according to a first synchronization signal and captures video and still images, and a plurality of display devices including a first display device and a second display device, A selection step of selecting one of the plurality of display devices as the display destination for displaying the video, A display control step of controlling to display the video on the display device selected in the selection step in accordance with the second synchronization signal; A reception step of receiving an operation of continuously shooting still images; During continuous shooting of the still images, when the second display device displays a video, the assertion timing of the second synchronization signal is shifted by a predetermined shift amount during the period in which the second display device displays the video; When the second display device is displaying the video at the end of continuous shooting of the still images, when the display destination of the video is switched from the second display device to the first display device after the end of continuous shooting of the still images, a control step of controlling to stop shifting the assertion timing of the second synchronization signal by the predetermined shift amount; A control method characterized by comprising the above.

[0013] A sixth aspect of the present invention is A control method for an imaging device having an imaging element that operates in accordance with a first synchronization signal and shoots videos and still images, and a plurality of display devices including a first display device and a second display device, comprising: A selection step of selecting any one of the plurality of display devices as a display destination for displaying the video; A display control step of displaying the video on the display device selected in the selection step in accordance with a second synchronization signal, and controlling to update the display of the video at the assertion timing of the second synchronization signal when a display update instruction is notified; A reception step of receiving an operation of continuously shooting still images; A notification step of notifying the display update instruction, wherein during continuous shooting of the still images, the timing of notifying the display update instruction is made different between the case of notifying the display update instruction to the first display device and the case of notifying the display update instruction to the second display device; During continuous shooting of the still images, when the second display device displays a video, a control step of controlling to shift the assertion timing of the second synchronization signal by a predetermined shift amount during the period in which the second display device displays the video; This is a control method characterized by having [a certain feature]. [Effects of the Invention]

[0014] According to the present invention, in an imaging device that can switch the display unit for displaying video, it is possible to suppress a decrease in framing performance. [Brief explanation of the drawing]

[0015] [Figure 1] This is a configuration diagram of the imaging device according to Embodiment 1. [Figure 2] This is a circuit diagram of the image sensor according to Embodiment 1. [Figure 3] This is a diagram showing the configuration of the pulse generation circuit according to Embodiment 1. [Figure 4] This is a timing chart for the display destination switching process according to Embodiment 1. [Figure 5] This is a timing chart for the display destination switching process according to Embodiment 1. [Figure 6] This is a flowchart of the imaging process during continuous shooting according to Embodiment 1. [Figure 7] This is a flowchart of the display processing during continuous shooting according to Embodiment 1. [Figure 8] This is a timing chart for the display destination switching process according to Embodiment 2. [Figure 9] This is a timing chart for the display destination switching process according to Embodiment 2. [Figure 10] This is a flowchart of the imaging process after continuous shooting according to Embodiment 2. [Figure 11] This is a flowchart of the display processing after continuous shooting according to Embodiment 2. [Modes for carrying out the invention]

[0016] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the following embodiments do not limit the invention as defined in the claims. While multiple features are described in the embodiments, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the accompanying drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0017] <Embodiment 1> Figure 1 is a block diagram showing the configuration of the imaging device 1 according to Embodiment 1. In Figure 1, the first lens 100 is positioned at the front of the imaging optical system 104. The aperture 101 adjusts the amount of light during imaging by adjusting the aperture diameter of the aperture 101. The second lens 102 and the third lens 103 are driven by the focus actuator 121 and adjust the focus of the imaging optical system 104 by moving forward and backward in the optical axis direction.

[0018] The focal-plane shutter 105 adjusts the exposure time (exposure period) when capturing still images. However, if an electronic shutter capable of slit-rolling readout is used to adjust the exposure time, the focal-plane shutter 105 does not adjust the exposure time. In slit-rolling readout, the image sensor 107 is exposed one or more rows, or one or more columns at a time, and the signal charge is temporarily stored in the memory element before being read out sequentially. The low-pass filter 106 is used to reduce false colors and moiré patterns in the captured image.

[0019] The image sensor 107 converts the optical image of the subject formed by the imaging optical system 104 into an electrical signal using photoelectric conversion. The image sensor 107 can also operate as an electronic shutter and acquire an image signal by slit-rolling readout. The image sensor 107 captures (images of) the subject by operating in synchronization with the synchronization signal input from the pulse generation circuit 111.

[0020] The DSP108 (Digital Signal Processor) acquires image signals from the image sensor 107 and other sources, performs image processing on the image signals, and outputs them as images (still images or videos). In addition to image processing, the DSP108 also calculates information used to drive the focus lenses (second lens 102 and third lens 103) based on information from the image sensor 107.

[0021] RAM109 operates as a data storage unit that stores image data processed by DSP108, and also as work memory when the CPU110 is operating. In this embodiment, the operation as a data storage unit and work memory is performed using RAM109. While this is achievable, other types of memory can also be used, provided that the access speed is sufficiently fast and does not cause operational problems. Furthermore, in this embodiment, the RAM 109 is located outside the DSP 108 and CPU 110, but the DSP 108 or CPU 110 may incorporate part or all of the RAM 109.

[0022] The CPU 110 comprehensively controls the operation of the imaging device 1. For example, the CPU 110 selects a display unit from the main display unit 114 and the sub-display unit 115 that displays video, and controls the display of video on the selected display unit. The CPU 110 executes programs to control each part of the imaging device 1. The CPU 110 controls the readout from the image sensor 107 by making various settings on the image sensor 107. The CPU 110 also communicates with the pulse generation circuit 111 and controls (sets) the generation timing of each timing pulse to control the operation of each part, as described later. Furthermore, the CPU 110 can also control the focus actuator 121 using the calculation results output from the DSP 108 to adjust the focus of the imaging optical system 104.

[0023] The pulse generation circuit 111 generates multiple synchronization signals based on the clock signals input from the first clock generation unit 112 and the second clock generation unit 113. The pulse generation circuit 111 supplies the generated multiple synchronization signals to the image sensor 107, the main display unit 114, and the sub-display unit 115. In this embodiment, the pulse generation circuit 111 generates four types of synchronization signals based on multiple clock signals (see Figure 3). However, the pulse generation circuit 111 may generate four types of synchronization signals based on one clock signal, or it may generate five or more types of synchronization signals based on multiple clock signals.

[0024] The main display unit 114 and the sub-display unit 115 are display devices that display video captured by the image sensor 107 under the display control of the CPU 110. In this embodiment, only one of the main display unit 114 and the sub-display unit 115 (selected according to user operation) displays video, and while one is displaying video, the other does not display video. The main display unit 114 and the sub-display unit 115 update the displayed image (LV image; live view image) by operating in synchronization with the synchronization signal input from the pulse generation circuit 111. In addition to video processed by the DSP 108, the main display unit 114 and the sub-display unit 115 can also display still images and menus. In this embodiment, the main display unit 114 is a rear display (TFT), and the sub-display unit 115 is an electronic viewfinder (EVF). By displaying the captured LV image on the EVF at the same time as shooting, the user can easily perform framing to adjust the shooting range for still image shooting and video shooting.

[0025] The operation unit 116 is a reception unit that receives user input. The operation unit 116 includes various operating components such as buttons and levers. In this embodiment, the operation unit 116 includes a mode switching dial and a still image capture button for instructing the capture of still images. The operation unit 116 acquires various instructions in response to user operations on the various operating components and outputs control signals corresponding to those instructions to the CPU 110. Alternatively, the main display unit 114, which is integrated with the touch panel, may display items for operation, and the operation unit 116 may acquire various instructions in response to user operations on the touch panel.

[0026] The CPU 110 acquires a control signal in response to the pressing of the still image capture button (detects the pressing of the still image capture button), and after a certain period of time (release time lag) including the preparation period for still image capture has elapsed, it takes a still image. Furthermore, after the start of still image capture, the CPU 110 takes continuous still images (burst shooting) as long as the still image capture button is continuously pressed. Detailed information regarding the operation of still image capture will be described in detail later using the timing charts in Figures 4 and 5.

[0027] The recording medium 117 records still image data and video data. The recording medium 117 is detachable from the imaging device 1. The ROM 118 stores programs that the CPU 110 reads and executes to control the operation of each part.

[0028] The shutter drive circuit 119 drives and controls the focal plane shutter 105. The focus drive circuit 120 is a focus position changing unit that changes the focal position of the imaging optical system 104. The focus drive circuit 120 controls the focus actuator 121 based on the output of the CPU 110 and adjusts the focus by driving the focus lenses (second lens 102, third lens 103) forward and backward in the optical axis direction. The aperture drive circuit 122 controls the aperture actuator 123 to control the aperture opening of the aperture 101.

[0029] (Circuit configuration of the image sensor) Next, the circuit configuration of the image sensor 107 will be described with reference to Figures 2A and 2B.

[0030] First, Figure 2A will be used to explain the detailed configuration of a unit pixel 206, which is one pixel of the image sensor 107. The PD200 (photodiode section) converts incident light into electricity to generate charge and stores the generated charge. The transfer switch 201 is controlled by the control signal φtx. If the control signal φtx is in the High state (hereinafter referred to as "H"), the transfer switch 201 transfers the charge stored in the PD200 to the FD202 (floating diffusion section).

[0031] The reset switch 203 is used to initialize the FD202 and is controlled by the control signal φres. When the control signals φtx and φres are simultaneously set to the high state, and the voltages of the PD200 and FD202 are set to the power supply voltage (VDD), the pixels are reset.

[0032] When the control signal φsel of the selection switch 205 enters the high state, the transistor 204 for the pixel amplifier is electrically connected to the constant current source 209 via the vertical output line 208, forming a pixel amplifier. The charge transferred from PD200 to FD202 is then converted by the pixel amplifier into a voltage value corresponding to the amount of charge, and output as an image signal via the vertical output line 208 shown in Figure 2B.

[0033] Referring to Figure 2B, the circuit configuration of the image sensor 107 will be described. The pixel array 207 has multiple unit pixels 206 arranged in a matrix, with (m+1) pixels horizontally and (n+1) pixels vertically. Note that m and n are both natural numbers. The drive pulse generation circuit 210 generates pulse signals for resetting and reading out the unit pixels 206 based on the synchronization signal input from the pulse generation circuit 111. The pulse signals generated by the drive pulse generation circuit 210 are supplied to the pixel drive circuit 212.

[0034] The row selection circuit 211 selects a row of unit pixels 206 to which the pulse signal generated by the drive pulse generation circuit 210 will be supplied, and sets the selected row to the pixel drive circuit 212. The pixel drive circuit 212 supplies the pulse signal generated by the drive pulse generation circuit 210 as a control signal to the row of unit pixels 206 set by the row selection circuit 211.

[0035] When a control signal is supplied from the pixel driving circuit 212 to the unit pixel 206 of the selected row, an image signal is output from the unit pixel 206 of the selected row to the vertical output line 208. The constant current source 209, in combination with the transistor 204, forms a source follower circuit.

[0036] The ADC213 (AD conversion circuit) converts the analog image signal (voltage value) output to the vertical output line 208 into a digital value corresponding to its signal level. The image signals (digital signals) converted to digital values ​​are sequentially selected by the horizontal scanning circuit 214 and transferred to the output unit 215.

[0037] Furthermore, by changing the drive of the pixel array 207 by the row selection circuit 211, the image signal can be read out using multiple different reading methods. In this embodiment, as a reading method for generating a still image, the image signal is read from the pixels of the top row, then the image signal of the pixels of the next row is read, and this is repeated until the bottom row is read out.

[0038] Furthermore, in this embodiment, as a method for reading the image signal when generating a video, the image signal is read from the top row of pixels, then the image signal of pixels in rows skipping several rows (for example, two rows) is read, and this process is repeated until the pixels in the bottom row are read. When generating a video, reading the image signal in this way reduces the vertical resolution of the LV image, but it allows for the reading of one frame of image signal in a short time and with low power consumption. In addition, various other reading methods are also possible for reading the image signal.

[0039] In this embodiment, an example was described in which the pixel driving circuit 212 and ADC213 are built into the image sensor 107, but the pixel driving circuit 212 and ADC213 may be provided on a chip separate from the image sensor 107.

[0040] (Internal configuration of the pulse generation circuit) Next, the internal configuration of the pulse generation circuit 111 will be explained using Figure 3. The pulse generation circuit 111 includes a reference generation circuit 300, a first generation circuit 301, a second generation circuit 302, and a third generation circuit 303.

[0041] The CPU 110 is connected to the reference generation circuit 300, the first generation circuit 301, and the third generation circuit 303, and can record information on the assertion timing (activation timing) of the synchronization signals of each generation circuit. From the recorded information, the CPU 110 can calculate the time difference in assertion timing between the reference generation circuit 300 and the first generation circuit 301, or between the first generation circuit 301 and the third generation circuit 303. In addition, the CPU 110 can generate synchronization signals of various periods by making various settings for the pulse generation circuit 111 (each generation circuit), and can also change the timing of the generation of the synchronization signals.

[0042] The reference generation circuit 300 generates and outputs a reference synchronization signal that is asserted at a constant period. In this embodiment, the second and third synchronization signals, which will be described later, are controlled to synchronize with the reference synchronization signal.

[0043] The first generation circuit 301 generates and outputs a first synchronization signal. The timing of the readout scan of the image sensor 107 (the timing of capturing video and still images) is controlled based on the first synchronization signal.

[0044] The second generation circuit 302 generates and outputs a second synchronization signal. The timing of the display scanning (operation) of the display unit that is displaying video among the main display unit 114 and the sub-display unit 115 is controlled based on the second synchronization signal.

[0045] The third generation circuit 303 generates and outputs a third synchronization signal. The third synchronization signal indicates the scanning timing of the sub-display unit 115, regardless of whether the sub-display unit 115 is scanning or not. Therefore, during the period when the sub-display unit 115 is displaying a video, the second synchronization signal and the third synchronization signal coincide. On the other hand, during the period when the sub-display unit 115 is not displaying a video, The second synchronization signal and the third synchronization signal do not necessarily coincide.

[0046] Furthermore, the first generation circuit 301 operates based on the clock signal CLK1 from the first clock generation unit 112. The reference generation circuit 300, the second generation circuit 302, and the third generation circuit 303 operate based on the clock signal CLK2 from the second clock generation unit 113. However, the operating clocks of all generation circuits may be a single clock or different clocks. Also, all or part of each of the above generation circuits may be circuits independent of the pulse generation circuit 111.

[0047] [Display destination switching process] Referring to the timing charts in Figures 4 and 5 and the flowcharts in Figures 6 and 7, the process of switching the display destination of a video during continuous shooting of still images according to this embodiment will be explained. The imaging device 1 performs continuous shooting of still images according to a shooting instruction that is generated, for example, when the still image shooting button is pressed. In this embodiment, when the sub-display unit 115 displays a video during continuous shooting of still images, the CPU 110 shifts the assertion timing of the second synchronization signal by a predetermined amount during the period when the sub-display unit 115 displays the video. This suppresses the display delay on the sub-display unit 115 during continuous shooting of still images.

[0048] In Figures 4 and 5, the dashed line represents the readout period for video (LV image; one frame of video). The solid line represents the readout period for still images. The dashed line represents the reset scan period corresponding to the readout immediately following the period indicated by the dashed line. In Figures 4 and 5, the rectangle in "Image Update of Display Unit" indicates that the main display unit 114 or the sub-display unit 115 is updating the displayed LV image. The video readout period before capturing a still image (period T0 of the first synchronization signal) and the readout time T3 for still image readout are both 1 / 2 the time interval of the assert timing of the reference synchronization signal. k It is a multiple (where k is a non-negative integer). The video readout period T4 during still image capture is 1 / 2 of the time interval of the assert timing of the reference synchronization signal. n It is a multiple (where n is a natural number). In the following, we assume that T0 = T2 = T3 (where T2 is the exposure time for the still image), and T4 = T0 × 2 = the time interval of the assert timing of the reference synchronization signal.

[0049] Figure 4 shows the timing chart for switching the video display destination from the main display unit 114 (TFT) to the sub-display unit 115 (EVF) during continuous shooting of still images. Figure 5 shows the timing chart for switching the video display destination from the sub-display unit 115 to the main display unit 114 during continuous shooting of still images, and then switching the video display destination back to the main display unit 114.

[0050] Figure 6 is a flowchart of the imaging process during continuous shooting of still images in this embodiment. Figure 7 is a flowchart of the display process during continuous shooting of still images in this embodiment. The processing in the flowchart of Figure 7 is executed at the assertion timing of the second synchronization signal.

[0051] First, the imaging process during continuous shooting of still images and the display process of video will be explained using the flowcharts in Figures 6 and 7. Then, the specific operation of the imaging device 1 will be explained using the timing charts in Figures 4 and 5.

[0052] (Image processing during continuous shooting) The imaging process during continuous still image capture will be explained using Figure 6. Each process in the flowchart of Figure 6 is realized by the CPU 110 executing a program stored in the ROM 118.

[0053] In step S601, the CPU 110 determines whether or not the still image capture button has been pressed. If the still image capture button is pressed (time t404), proceed to step S602. If the still image capture button is not pressed, the process in this flowchart ends.

[0054] In step S602, the CPU 110 calculates the exposure time T2 of the still image.

[0055] In step S603, the CPU 110 calculates the start time of reading the LV image (time t409), which is the start time of the processing in step S611.

[0056] In step S604, the CPU 110 calculates a deviation amount Δu1 (a predetermined deviation amount), which is the amount by which the third synchronization signal is shifted from the reference synchronization signal. The CPU 110 also stores the calculated deviation amount Δu1 information in the RAM 109. Therefore, the CPU 110 also functions as a calculation unit that calculates the deviation amount Δu1.

[0057] Here, the shift amount Δu1 is also the difference between the assertion timing of the first synchronization signal during continuous shooting of still images and the assertion timing of the first synchronization signal before continuous shooting of still images. In other words, the shift amount Δu1 is the difference between the assertion timing of the first synchronization signal when continuous shooting of still images has not started and the assertion timing of the first synchronization signal during continuous shooting when continuous shooting of still images has started. Therefore, the shift amount Δu1 can be calculated from the time tp (time t404) when the still image capture button is pressed, the release time lag T1, the exposure time T2 of the still image (time of the accumulated frame for still image readout), and the readout time T3 for still image readout. Note that the exposure time T2 is a time that changes with each capture. The readout time T3 is the sum of the readout scan time of the still image and the subsequent reset scan time, and changes depending on the exposure time of the LV image during still image capture. In this embodiment, the readout time T3 is assumed to be the same as the image update cycle of the sub-display unit 115.

[0058] For example, the amount of deviation Δu1 can be calculated based on the time ta (time t409) after the release time lag T1, exposure time T2, and readout time T3 have elapsed from time tp, and the time tb (time t405) when the first synchronization signal is asserted immediately after time tp. More specifically, as shown in Equation 1, the amount of deviation Δu1 is the remainder when the time difference between time tb and time ta is divided by the display update cycle time of the sub-display unit 115 (for example, 8.3 ms when the display update cycle is 120 fps). Note that the display update cycle of the sub-display unit 115 is also the period of assertion of the third synchronization signal. Δu1 = (time tb - time ta) % (sub-display update cycle time) ... Equation 1

[0059] In step S605, the CPU 110 determines whether the release time lag T1 has elapsed since the still image capture button was pressed. In other words, it determines whether the start time for still image exposure has been reached. If the release time lag T1 has elapsed, the process proceeds to step S606. If the release time lag T1 has not elapsed, the process in step S605 is repeated.

[0060] In step S606, the CPU 110 starts still image exposure (continuous shooting of still images) by initiating a reset scan for still image exposure at the assertion timing of the first synchronization signal.

[0061] In step S607, the CPU 110 notifies the pulse generation circuit 111 of the deviation amount Δu1. As a result, the CPU 110 shifts the assert timing of the third synchronization signal from the next time onward by the deviation amount Δu1. Thereafter, the third synchronization signal operates with a deviation amount Δu1 relative to the reference synchronization signal. Note that if the video is displayed on the sub-display unit 115, the CPU 110 also shifts the assert timing of the second synchronization signal from the next time onward by the deviation amount Δu1. As a result, if the video is displayed on the sub-display unit 115, the second The synchronization signal and the third synchronization signal can be synchronized.

[0062] In step S608, the CPU 110 determines whether or not exposure time T2 has elapsed since the start time of the previous still image exposure (at the time of S606 or S618). If exposure time T2 has elapsed, the first synchronization signal is asserted and the process proceeds to step S609. If exposure time T2 has not elapsed, the process in step S608 is repeated.

[0063] In step S609, the CPU 110 starts reading and scanning the still images.

[0064] In step S610, the CPU 110 starts a reset scan for exposure of the LV image (time t408).

[0065] In step S611, when the first synchronization signal is asserted, the CPU 110 starts reading the LV image (time t409).

[0066] In step S612, the CPU 110 determines whether the current video is being displayed on the main display unit 114 (TFT) or the sub-display unit 115 (EVF). If the video is being displayed on the sub-display unit 115, the process proceeds to step S613. If the video is being displayed on the main display unit 114, the process proceeds to step S614.

[0067] In step S613, the CPU 110 notifies the sub-display unit 115 of a display update instruction (display update notification) at the same time as the start of reading the LV image in step S611 (assertion of the first synchronization signal). Thus, the CPU 110 is both a control unit that controls the assertion timing of each synchronization signal and a notification unit that notifies each display unit of a display update instruction.

[0068] In step S614, the CPU 110 determines whether the LV image readout scan, which was started in step S611, has finished. If the LV image readout scan is finished, the process proceeds to step S615. If the LV image readout scan is not finished, the process in step S614 is repeated.

[0069] In step S615, the CPU 110 notifies the main display unit 114 of a display update instruction. As described above, when the CPU 110 notifies the main display unit 114 of a display update instruction, it waits from the start of reading the LV image in step S611 until the end of the LV image reading scan, and then notifies the main display unit 114 of the display update instruction. For this reason, the timing of the display update instruction differs depending on whether the main display unit 114 is displaying a video or the sub-display unit 115 is displaying a video. Specifically, when the main display unit 114 is displaying a video, the time from the start of reading the LV image to the notification of the display update instruction is longer than when the sub-display unit 115 is displaying a video. For this reason, the time from capturing the LV image to displaying it when the main display unit 114 is displaying an LV image is longer than the time from capturing the LV image to displaying it when the sub-display unit 115 is displaying an LV image.

[0070] In step S616, the CPU 110 determines whether the interval between consecutive still image captures has elapsed since the previous still image exposure. If the interval has elapsed, the process proceeds to step S617. If the interval has not elapsed, the process returns to step S610.

[0071] In step S617, the CPU 110 determines whether the still image capture button is pressed or not. If the still image capture button is pressed, the process proceeds to step S618. If the still image capture button is not pressed, the process of this flowchart ends.

[0072] In step S618, the CPU 110, similar to step S606, performs still image exposure by initiating a reset scan for still image exposure at the assertion timing of the first synchronization signal. Once the processing in step S618 is complete, the process returns to step S608.

[0073] (Display processing during continuous shooting) Figure 7 illustrates the process of displaying video during continuous shooting of still images. Each step in the flowchart in Figure 7 is implemented by the CPU 110 executing a program stored in the ROM 118.

[0074] In step S701, the CPU 110 determines whether it has notified the pulse generation circuit 111 of the deviation amount Δu1 (i.e., whether the processing in step S607 has been completed). If the deviation amount Δu1 has been notified, the process proceeds to step S702; otherwise, the processing in step S701 is repeated.

[0075] In step S702, the CPU 110 determines whether the video display destination has switched during continuous shooting of still images. If the video display destination has switched, the process proceeds to step S703; otherwise, the process proceeds to step S706.

[0076] In step S703, the CPU 110 determines whether the current display destination of the video is the main display unit 114 or the sub-display unit 115. If the current display destination of the video is the sub-display unit 115, the process proceeds to step S704; if the current display destination of the video is the main display unit 114, the process proceeds to S705.

[0077] In step S704, the CPU 110 sets the pulse generation circuit 111 to shift the assertion timing of the second synchronization signal by a difference of Δu1. In other words, the CPU 110 matches the assertion timing of the second synchronization signal to the assertion timing of the third synchronization signal. This allows the time from capture of the LV image to display (display delay) to be maintained at Δt1.

[0078] In step S705, the CPU 110 sets the assert timing of the second synchronization signal to the pulse generation circuit 111 so that it is the same as the assert timing of the reference synchronization signal (with a deviation of 0).

[0079] In step S706, the display unit currently showing the target image updates the LV image at the assertion timing of the second synchronization signal in response to the display update instruction. The processing in step S706 is implemented by the display control of the CPU 110.

[0080] Thus, when the video is displayed on the sub-display unit 115, the CPU 110 shifts the assertion timing of the second synchronization signal from the reference synchronization signal, but does not shift the assertion timing of the second synchronization signal when the video is displayed on the main display unit 114. This is because, generally, users shoot more frequently by looking through the viewfinder (EVF) than by looking at the TFT, and therefore there is a greater need to suppress display delay in the sub-display unit 115, which is an EVF. Also, the EVF (sub-display unit 115) often has a higher frame rate than the TFT (main display unit 114), which further increases the need to suppress display delay.

[0081] In step S707, the CPU 110 determines whether the continuous shooting of still images has finished. If the continuous shooting of still images has finished, the process in this flowchart ends; otherwise, the process returns to step S702.

[0082] (Switching display destination from TFT to EVF) Next, using Figure 4, we will explain the imaging and display processes in chronological order when switching the display destination of a video from the main display unit 114 (TFT) to the sub-display unit 115 (EVF) during continuous shooting of still images.

[0083] At time t400, the first synchronization signal is asserted, and the reading of the LV image begins. Image processing is also initiated on the LV image read out by the DSP108.

[0084] At time t401, after a period T0 has elapsed since time t400, the first synchronization signal is asserted again, and the LV image readout begins.

[0085] At time t402, the second synchronization signal is asserted simultaneously with the assertion timing of the reference synchronization signal. As a result, the LV image read out at time t401 begins to be displayed on the main display unit 114. Furthermore, since the reading and display of the LV image are repeated with a period T0, the displayed LV image is updated at regular time intervals. Here, a certain delay occurs between the capture and display of the LV image, equal to the time difference Δt1 between time t401 and time t402, so that the captured LV image can be displayed stably. In addition, the third synchronization signal is asserted simultaneously with the second synchronization signal.

[0086] Furthermore, at time t402, the second generation circuit 302 synchronizes itself with the reference synchronization signal input from the reference generation circuit 300. The reference synchronization signal is also input to the CPU 110. When the CPU 110 detects that the reference synchronization signal has been asserted, it reads a value from a counter representing the system time of the CPU 110 and records a count value (reference count value) that represents the time when the reference synchronization signal was asserted.

[0087] At time t403, the first synchronization signal is asserted, and the LV image readout begins. At this time, the first synchronization signal is input to the CPU 110. The CPU 110 records a count value (first count value) representing the system time when the first synchronization signal was asserted. Based on the reference count value and the first count value, the CPU 110 calculates the assertion timing of the first synchronization signal. Then, based on the calculation result, the CPU 110 controls the pulse generation circuit 111 to synchronize the first synchronization signal so that a time difference of a certain time Δt1 is created with respect to the reference synchronization signal. As a result of the above, since both the first and second synchronization signals can be synchronized with respect to the reference synchronization signal, the time difference between the assertion timing of the first synchronization signal and the assertion timing of the second synchronization signal is maintained at a constant time Δt1. At the same time, the first synchronization signal can also maintain a time difference of time Δt1 with respect to the third synchronization signal.

[0088] At time t404, the still image capture button is pressed. When the still image capture button is pressed at time t404 (step S601YES), the CPU 110 performs the processing in steps S602 to S604 to calculate the amount of deviation Δu1.

[0089] At time t405, the first synchronization signal is asserted. After the release time lag T1 has elapsed since the still image capture button was pressed, a reset scan for still image exposure begins, and continuous still image capture starts. At time t406, after the release time lag T1 has elapsed since the still image capture button was pressed (step S605YES) and still image exposure has started (step S606), the reference synchronization signal is asserted. At this time, the pulse generation circuit 111 is notified of a shift amount Δu1 (steps S607; S701YES). As a result, the next assertion timing of the third synchronization signal is shifted by the shift amount Δu1. Then, after the exposure time T2 has elapsed since the reset scan for still image exposure (step S608YES), still image readout begins (step S609).

[0090] At time t407, the third synchronization signal is asserted after a deviation of Δu1 has elapsed from time t406.

[0091] At time t408, the reset scan for exposure of the LV image begins (step S610).

[0092] At time t409, the first synchronization signal is asserted, and the LV image is read out (step S611). Simultaneously, the first synchronization signal is input to the CPU 110, which records a count value (first count value) representing the system time when the first synchronization signal was asserted. Based on the count value (third count value) representing the time when the third synchronization signal was asserted (first count value) and the first count value, the CPU 110 calculates the assertion timing of the first synchronization signal. Based on this calculation result, the CPU 110 controls the pulse generation circuit 111 to synchronize the first synchronization signal with the third synchronization signal by a constant time difference (time Δt1). This ensures that the time difference between the first synchronization signal and the third synchronization signal is maintained at a constant time Δt1, regardless of whether the video is displayed on the main display unit 114 or the sub-display unit 115.

[0093] Thus, at time t405, the time difference between the first and third synchronization signals is kept constant at time Δt1. On the other hand, the start of continuous shooting of still images requires a release time lag T1, causing the time difference between the first and third synchronization signals to change significantly from time Δt1. For this reason, at time t407, the CPU 110 shifts the third synchronization signal by a deviation amount Δu1 relative to the reference synchronization signal, and synchronizes the first and third synchronization signals at time t409. This makes it possible to keep the time difference between the two synchronization signals constant at time Δt1 even during continuous shooting of still images.

[0094] Also, at time t409, the CPU 110 is displaying a video on the main display unit 114 (step S612NO), so it waits for the LV image readout scan to finish (step S614). Then, once the LV image readout scan is finished (step S614YES), the CPU 110 notifies the main display unit 114 of a display update instruction (step S615).

[0095] At time t410, a third synchronization signal is input to the CPU 110. When the CPU 110 detects that the third synchronization signal has been asserted, it records a count value (third count value) that represents the time when the third synchronization signal was asserted.

[0096] At time t411, the second synchronization signal is asserted. Then, since a display update instruction has been notified (step S615), the main display unit 114 (TFT) updates the LV image to be displayed at the timing of the assertion of the second synchronization signal (step S706). In this case, a time difference of time Δt2 greater than time Δt1 is provided as the time difference between capturing the LV image and displaying it.

[0097] Thus, if the second synchronization signal and the first synchronization signal, which represent the display update timing of the main display unit 114, cannot maintain a constant time difference or achieve proper timing alignment, the CPU 110 will not notify the display update instruction until the read scan of the LV image is complete. This allows the LV image to be displayed after the read scan of the LV image is complete, thereby suppressing incorrect displays.

[0098] Here, each time the interval between consecutive still image captures has elapsed since the reset scan for still image exposure (step S616YES), if the still image capture button is pressed (step S617YES), a reset scan for still image exposure is performed (step S618).

[0099] At time t412, the video display destination is switched to the sub-display unit 115. For example, in response to user operation on the mode switching dial, the CPU 110 switches the video display destination (selecting the sub-display unit 115 as the video display destination).

[0100] At time t413, the reference synchronization signal and the second synchronization signal are asserted. At this point, the video display destination has switched to the sub-display unit 115 (step S702YES, and step S703YES). Therefore, the CPU 110 obtains the deviation amount Δu1 from the RAM 109 and sets the pulse generation circuit 111 to shift the assertion timing of the second synchronization signal by the deviation amount Δu1 (step S704).

[0101] At time t414, the second and third synchronization signals are asserted based on the settings for the pulse generation circuit 111. From time t414 onward, the assertion timing of the second synchronization signal coincides with the assertion timing of the third synchronization signal.

[0102] At time t415, the readout scan of the LV image begins at the assertion timing of the first synchronization signal (step S611). Then, since the destination for displaying the video is the sub-display unit 115 (step S612YES), the CPU 110 notifies the sub-display unit 115 of a display update instruction (step S613).

[0103] At time t416, since a display update instruction has been notified, when the second synchronization signal is asserted, the sub-display unit 115 updates the LV image to be displayed (step S706). In this case, the LV image is updated while maintaining a display delay of time Δt1 from the capture of the LV image to its display.

[0104] At time t417, the second synchronization signal is asserted. However, between time t416 and time t417, the first synchronization signal is not asserted, and therefore the display update instruction is not notified. As a result, the LV image is not updated, and at time t417, the LV image displayed at time t416 is displayed on the sub-display unit 115.

[0105] As described above, after the start of continuous shooting of still images (from time t407 onwards), the imaging device 1 synchronizes the first synchronization signal with the third synchronization signal with a time difference of Δt1. Then, when the display destination of the video switches to the sub-display unit 115 at time t412, the imaging device 1 can assert the second synchronization signal at time t414 with a shift of Δu1. As a result, the first synchronization signal is synchronized with the second synchronization signal with a time difference of Δt1, so that even if the display destination of the video switches to the sub-display unit 115 during continuous shooting of still images, the video (LV image) can be displayed stably without degrading the framing performance.

[0106] (Switching display from EVF to TFT) Next, using Figure 5, we will explain the imaging and display processes in chronological order when switching the display destination of a video from the sub-display unit 115 (EVF) to the main display unit 114 (TFT) during continuous shooting of still images. Furthermore, the time chart in Figure 5 will also explain an example of switching the display destination of a video from the main display unit 114 to the sub-display unit 115. Note that only the processes that differ from those in the time chart in Figure 4 will be explained below.

[0107] At time t402, since video is being displayed on the sub-display unit 115 (EVF), the second synchronization signal is asserted simultaneously with the assertion timing of the reference synchronization signal, and the LV image read out at time t401 begins to be displayed on the sub-display unit 115. Also, at the same time as the second synchronization signal is asserted, the third synchronization signal is asserted. Note that at time t406, unlike in the case of Figure 4, in addition to the next assertion timing of the third synchronization signal, the next assertion timing of the second synchronization signal is also shifted by a difference of Δu1 (step S607).

[0108] At time t501, a third synchronization signal is asserted so that it is shifted by an amount Δu1 from the time t406 when the reference synchronization signal was asserted. And because the sub-display unit 115 is showing video, the second synchronization signal is asserted at the same time as the third synchronization signal is asserted.

[0109] At time t409, the sub-display unit 115 is showing a video (step S612YES), so the CPU 110 notifies the sub-display unit 115 of a display update instruction (step S613).

[0110] At time t410, the CPU 110 has received notification of a display update instruction, and when the second synchronization signal is asserted, the sub-display unit 115 updates the LV image to be displayed (step S706). In this case, the LV image is updated with a display delay of time Δt1 from the time the LV image is captured to the time it is displayed. Therefore, the time Δt1 is the difference between time t410 when the second synchronization signal is asserted and time t409 when the first synchronization signal is asserted. For this reason, even after time t409, the time difference between the first synchronization signal and the second synchronization signal is maintained at the same time difference as at time t401 to time t403. Thus, the framing performance before continuous shooting of still images can be maintained even during continuous shooting of still images.

[0111] Here, each time the interval between consecutive still image captures has elapsed since the reset scan for still image exposure (step S616YES), if the still image capture button is pressed (step S617YES), a reset scan for still image exposure is performed (step S618).

[0112] At time t502, the video display destination is switched to the main display unit 114. For example, in response to user operation on the mode selection dial, the CPU 110 switches the video display destination (selecting the main display unit 114 as the video display destination).

[0113] At time t503, the first synchronization signal is asserted. Then, the readout scan of the LV image begins (step S611). After time t503, the destination for displaying the video is the main display unit 114 (step S612NO), so the CPU 110 waits until the readout scan of the LV image is finished (step S614), and then notifies the main display unit 114 of a display update instruction (step S615).

[0114] At time t504, the second synchronization signal is asserted. This is because the video display destination has switched to the main display unit 114 (step S702 YES, and S703 NO). The CPU 110 sets the pulse generation circuit 111 so that the second synchronization signal is asserted at the same timing as the reference synchronization signal (step S705).

[0115] At time t505, based on the settings for the pulse generation circuit 111, the second synchronization signal is asserted, and the display of the main display unit 114 is updated (step S706). In this case, a display delay of time Δt2, which is greater than time Δt1, is provided between the capture and display of the LV image, and the display is updated. This makes it possible to synchronize the timing of the second synchronization signal and the first synchronization signal, and suppress pauses in continuous shooting of still images (continuous shooting not being at a constant interval).

[0116] At time t506, the video display destination is switched from the main display unit 114 to the sub-display unit 115.

[0117] At time t507, the video display destination is switched to the sub-display unit 115 (step S702YES, and step S703YES). Therefore, the CPU 110 shifts the assertion timing of the second synchronization signal by the amount Δu1 in the pulse generation circuit 111. Configure the settings for (step S705).

[0118] At time t508, the second and third synchronization signals are asserted simultaneously based on the settings for the pulse generation circuit 111.

[0119] At time t509, the readout scan of the LV image begins at the assertion timing of the first synchronization signal (step S611). Since the video is displayed on the sub-display unit 115 (step S612 YES), the CPU 110 notifies the sub-display unit 115 of a display update instruction (step S613).

[0120] At time t510, the second synchronization signal is asserted. Since a display update instruction has been notified, the sub-display unit 115 updates the LV image to be displayed (step S706). In this case, the LV image is updated while maintaining a time difference of time Δt1 between the capture of the LV image and its display.

[0121] This ensures that the interval between continuous still image captures remains constant, while maintaining timing consistency between the second synchronization signal, which represents the display update timing, and the first synchronization signal, which represents the shooting timing. Therefore, it is possible to suppress the deterioration of framing performance during continuous still image capture.

[0122] If the display destination is switched (at times t412, t502, t506), the imaging device 1 continues to display the LV image that was displayed immediately before. In this case, if the display image size differs between the main display unit 114 and the sub-display unit 115, the imaging device 1 performs image processing such as resizing on the LV image using the DPS 108 before displaying the LV image.

[0123] Furthermore, while Figures 4 and 5 illustrate exposure reset scans for both still images and video, both for relatively short exposure times, this embodiment is not limited to these. Each exposure reset scan can also be applied for longer exposure times. For example, when long exposures are used to capture still images, the exposure time T2 of the still image becomes longer. However, if the interval between the first synchronization signals becomes longer due to the longer exposure time T2 of the still image, the time Δt1 may become even longer due to the clock difference between the first synchronization signal and the third synchronization signal. In such cases, for example, if the exposure time T2 is longer than the period T0, the first synchronization signal can be asserted multiple times to perform multiple exposures in period T0. Then, the third synchronization signal and the first synchronization signal can be synchronized with a certain time difference. The same applies even when the exposure time of the LV image is long.

[0124] As described above, according to Embodiment 1, the time difference between the third synchronization signal and the first synchronization signal can be maintained at time Δt1 during continuous shooting of still images. As a result, even if the display destination of the video is switched from the main display unit 114 to the sub-display unit 115 during continuous shooting of still images, the time difference between the second synchronization signal, which controls the timing of display updates, and the first synchronization signal can be kept constant at time Δt1. Therefore, a decrease in framing performance can be suppressed.

[0125] <Embodiment 2> In Embodiment 2, the process of switching the display destination of a video after continuous shooting of still images will be explained with reference to the timing charts in Figures 8 and 9 and the flowcharts in Figures 10 and 11. Note that the explanation for times indicated by the same reference numerals as in the timing chart in Figure 5 in the timing charts of Figures 8 and 9 will be omitted.

[0126] Figure 8 shows the state where video is displayed on the sub-display unit 115 (EVF) at the end of continuous shooting of still images, and the state where video is displayed on the main display unit 114 (TFT) after continuous shooting of still images has ended. Figure 9 shows the timing chart for switching destinations. It shows the timing chart for when continuous shooting of still images starts from a state where video is displayed on the sub-display unit 115 (EVF), and then, during continuous shooting of still images, the display destination of the video switches to the main display unit 114 (TFT), and then continuous shooting ends.

[0127] Figure 10 is a flowchart of the imaging process after continuous shooting of still images according to this embodiment. Figure 11 is a flowchart of the display process after continuous shooting of still images according to this embodiment. Note that all processes in the flowchart of Figure 10 except for steps S1005 and S1006 are executed at the assertion timing of the first synchronization signal. Also, the processes in the flowchart of Figure 11 are executed at the assertion timing of the second synchronization signal. Note that the imaging and display processes in Figures 10 and 11 are processes up to the point where the same imaging and display processes as before continuous shooting of still images are performed.

[0128] In Figure 8, it is assumed that the same processing as in the time chart of Figure 5 up to time t410 is performed up to time t410. Similarly, in Figure 9, it is assumed that the same processing as in the time chart of Figure 5 up to time t505 is performed up to time t505.

[0129] (Image processing after continuous shooting of still images) First, the imaging process after continuous shooting of still images will be explained using the flowchart in Figure 10. Each process in the flowchart in Figure 10 is realized by the CPU 110 executing a program stored in the ROM 118.

[0130] In step S1001, the CPU 110 determines whether the video is to be displayed on the main display unit 114 (TFT). If the video is to be displayed on the main display unit 114, the process proceeds to step S1002. If the video is to be displayed on the sub-display unit 115 (EVF), the process proceeds to step S1004.

[0131] In step S1002, the CPU 110 determines whether the LV image has finished being read. If the LV image has finished being read, the process proceeds to step S1003. If the LV image has not finished being read, the process in step S1002 is repeated.

[0132] In step S1003, the CPU 110 sets the pulse generation circuit 111 such that the assertion timing of the first synchronization signal is time Δt1, and the time difference between it and the assertion timing of the reference synchronization signal is time Δt1.

[0133] In step S1004, the CPU 110 notifies the sub-display unit 115 of a display update instruction.

[0134] In steps S1005 and S1006, the CPU 110 performs the display processing after continuous shooting of still images, as shown in Figure 11.

[0135] (Display processing after continuous shooting of still images) First, the display process after continuous shooting of still images will be explained using the flowchart in Figure 11. Each process in the flowchart in Figure 11 is realized by the CPU 110 executing a program stored in the ROM 118.

[0136] In step S1101, the CPU 110 determines whether the video is to be displayed on the sub-display unit 115. If the video is to be displayed on the sub-display unit 115, the process proceeds to step S1102. If the video is not to be displayed on the sub-display unit 115, the process proceeds to step S1105.

[0137] In step S1102, the CPU 110, similar to step S704, sets the pulse generation circuit 111 to shift the assertion timing of the second synchronization signal by a shift amount Δu1.

[0138] In step S1103, the sub-display unit 115 updates the LV image to be displayed under the control of the CPU 110, similar to step S706.

[0139] In step S1104, the CPU 110 determines whether the video display destination has been switched to the main display unit 114. If the video display destination has been switched to the main display unit 114, the processing of this flowchart ends. If the video display destination has not been switched to the main display unit 114, the process returns to step S1101.

[0140] In step S1105, the CPU 110, similar to step S705, sets the pulse generation circuit 111 so that the second synchronization signal is asserted at the same timing as the reference synchronization signal. In other words, the CPU 110 stops (releases) the Δu1 shift in the assertion timing of the second synchronization signal. Once the Δu1 shift in the assertion timing of the second synchronization signal is stopped (released), the imaging and display processes are performed in the same way as before continuous shooting of still images.

[0141] (Processing in the case of Figure 8) Next, using Figure 8, we will explain the imaging and display processes in chronological order when switching the display destination of a video from the sub-display unit 115 (EVF) to the main display unit 114 (TFT) after continuous shooting of still images.

[0142] At time t801, when the still image capture button is released (when the still image capture button is released), continuous still image capture ends. Once continuous still image capture ends, the process shown in the flowchart in Figure 10 begins.

[0143] Then, when the first synchronization signal is asserted, since the destination for displaying the video is the sub-display unit 115 (step S1001NO), the CPU 110 notifies the sub-display unit 115 of a display update instruction to display the read LV image (step S1004).

[0144] Subsequently, the second synchronization signal is asserted. At this time, the video is displayed on the sub-display unit 115 (step S1101YES). Therefore, the CPU 110 sets the pulse generation circuit 111 to maintain a timing shift of Δu1 from the assert timing of the reference synchronization signal for the assertion of the second synchronization signal (step S1102). The CPU 110 also sets the pulse generation circuit 111 to maintain a timing shift of Δu1 from the assertion timing of the reference synchronization signal for the assertion of the third synchronization signal.

[0145] At time t802, a second synchronization signal is asserted after a time Δt1 has elapsed since the start of reading the LV image, so the LV image displayed on the sub-display unit 115 is updated (step S1103). At time t803, the display destination of the video switches from the sub-display unit 115 to the main display unit 114 (step S1104 YES).

[0146] At time t804, the first synchronization signal is asserted. Then, since the destination for displaying the video is the main display unit 114 (step S1001 YES), the CPU 110 waits until the LV image, which was started to be read from time t804, has finished being read (step S1002). Then, the CPU 110 issues a first signal to the pulse generation circuit 111 so that the time difference between the time of time t806, which is the assertion timing of the next first synchronization signal, and the reference synchronization signal is time Δt1. The assertion timing of the synchronization signal is set (step S1003).

[0147] At time t805, the second synchronization signal is asserted. At this point, the CPU 110 sets the pulse generation circuit 111 so that the second synchronization signal is asserted at the same timing as the reference synchronization signal (step S1105), because the video display destination has switched to the main display unit 114 (step S1101NO). At this time, the CPU 110 also sets the pulse generation circuit 111 so that the third synchronization signal is asserted at the same timing as the reference synchronization signal. This completes the processing of the flowcharts in Figures 10 and 11.

[0148] At time t806, the first synchronization signal is asserted. This causes the LV image to be read out.

[0149] At time t807 (a time Δt1 after time t806), the second synchronization signal is asserted, and the LV image displayed on the main display unit 114 is updated.

[0150] In this way, the display delay from capture to display is unified to time Δt1 at time t400 before still image capture, time t409 during continuous still image capture, time t802 after still image capture is complete, and time t807 after the display destination is switched. This suppresses a decrease in framing performance (ease of framing) even if the display destination of the video changes before and after continuous still image capture.

[0151] Furthermore, the imaging device 1 may continue to display the LV image that was displayed at time t803 (the time when the display destination of the video is switched) until time t807 (the time when the assertion timing of the second synchronization signal matches the assertion timing of the reference synchronization signal). If the display image size differs between the main display unit 114 and the sub-display unit 115, the imaging device 1 may resize or perform other image processing on the image displayed at time t803 using the DPS 108 before displaying it. Alternatively, the imaging device 1 may generate a black image (an image in which the grayscale value of each pixel is 0) and display the black image on the main display unit 114 from time t803 to time t807.

[0152] Furthermore, at time t803, when the video display destination switches, the CPU 110 may change the drive of the pixel array 207 by the row selection circuit 211 of the image sensor 107 so that the LV image is read out from the image sensor 107 with the optimal number of pixels according to the display destination. In that case, in step S1003, the CPU 110 sets the assertion timing of the first synchronization signal to the pulse generation circuit 111, taking into account the processing time for changing the drive of the image sensor 107.

[0153] (Processing in the case of Figure 9) Next, using Figure 9, we will explain the imaging and display processes in chronological order when, during continuous shooting of still images, the display destination for video is switched from the sub-display unit 115 (EVF) to the main display unit 114 (TFT), and then continuous shooting of still images is terminated.

[0154] At time t505, the second synchronization signal is read out, and the LV image is displayed on the main display unit 114.

[0155] At time t901, when the still image capture button is released, continuous still image capture ends. Also, when the still image capture button is released, the flowchart in Figure 10 is executed by the CPU 110.

[0156] At time t804, the first synchronization signal is asserted. Then, the CPU 110 determines that the display destination of the LV image is the main display unit 114 (TFT) (step S1001 YES), The CPU 110 waits for the LV image to be read out (step S1002). Then, the CPU 110 sets the assert timing of the first synchronization signal for the pulse generation circuit 111 so that the time difference between the time t806, which is the assert timing of the next first synchronization signal, and the reference synchronization signal is time Δt1 (step S1003).

[0157] At time t805, the second synchronization signal is asserted. At this time, the CPU 110 sets the pulse generation circuit 111 so that the second synchronization signal is asserted at the same timing as the reference synchronization signal, since the video is displayed on the main display unit 114 (step S1101NO) (step S1105). At this time, the CPU 110 also sets the pulse generation circuit 111 so that the third synchronization signal is asserted at the same timing as the reference synchronization signal.

[0158] At time t806, the first synchronization signal is asserted according to the settings for the pulse generation circuit 111. This causes the LV image to be read out.

[0159] At time t807 (a time Δt1 after time t806), the second synchronization signal is asserted, and the main display unit 114 updates the LV image to be displayed.

[0160] Furthermore, between time t901 and time t807, the image that was displayed at time t901 continues to be displayed. Also, when the continuous shooting of still images ends at time t901, the CPU 110 may change the drive of the pixel array 207 by the row selection circuit 211 of the image sensor 107 so as to read out the LV image from the image sensor 107 with the optimal number of pixels according to the display unit that displays the video. In this case, for example, in step S1003, the CPU 110 sets the assertion timing of the first synchronization signal to the pulse generation circuit 111, taking into account the processing time for changing the drive of the image sensor 107.

[0161] In this way, a display delay of time Δt1 can be uniformly set between the capture and display of the LV image at time t400 before continuous still image capture, and at time t802 after continuous still image capture. This allows for stable display of the captured video, and suppresses a decrease in framing performance even if the display destination of the video changes before and after continuous still image capture.

[0162] Furthermore, even if the video display destination switches to the sub-display unit 115 after time t807, the CPU 110 sets the pulse generation circuit 111 so that the first synchronization signal has a time difference of time Δt1 with the reference synchronization signal, just as it did at time t804.

[0163] Furthermore, as explained above, "continuous still image shooting ends when the still image shooting button is released." However, it would also be acceptable to consider continuous still image shooting as ending when the camera transitions to a state where AF processing or other processes are initiated, such as when the button is half-pressed, and the camera is ready to shoot.

[0164] As described above, according to Embodiment 2, even if the display destination of a video switches between the main display unit 114 and the sub-display unit 115 after continuous shooting of still images, the time difference between the first synchronization signal and the second synchronization signal can be maintained at a constant time Δt1. This makes it possible to suppress a decrease in framing performance even after continuous shooting of still images.

[0165] In the above embodiment, an imaging device having two display units was described, but an imaging device having three or more display units may also be used, as long as it is capable of continuous shooting of still images and the display unit for displaying video can be switched.

[0166] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of its gist.

[0167] Furthermore, each functional unit in each of the above embodiments may or may not be individual hardware. The functions of two or more functional units may be implemented by common hardware. Each of the multiple functions of a single functional unit may be implemented by individual hardware. Two or more functions of a single functional unit may be implemented by common hardware. In addition, each functional unit may or may not be implemented by hardware such as ASIC, FPGA, or DSP. For example, the device may have a processor and a memory (storage medium) in which a control program is stored. The functions of at least some of the functional units of the device may be implemented by the processor reading and executing the control program from the memory.

[0168] (Other embodiments) The present invention can also be realized by supplying a program that implements one or more of the functions of the above embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions. [Explanation of Symbols]

[0169] 1: Imaging device, 110: CPU, 111: Pulse generation circuit, 114: Main display unit, 115: Sub-display unit, 116: Operation unit

Claims

1. an image sensor that operates in accordance with a first synchronization signal and captures moving images and still images; a plurality of display devices including a first display device and a second display device; a selection means for selecting one of the plurality of display devices as a display destination for displaying the moving image; a display control means for controlling the display device selected by the selection means to display the moving image in accordance with a second synchronization signal; a receiving means for receiving an operation for continuously capturing still images; a generating means for generating a third synchronization signal that coincides with the second synchronization signal when the second display device displays the moving image; a control means for controlling, upon receiving the operation, to shift the assertion timing of the third synchronization signal by a predetermined amount; An imaging device comprising:

2. the control means controls the first synchronization signal to be synchronized with the third synchronization signal at a fixed time interval during continuous shooting of the still images; 2. The imaging device according to claim 1.

3. The control means When the second display device displays a moving image during the continuous shooting of the still images, the assertion timing of the second synchronization signal is shifted by the predetermined shift amount during a period in which the second display device displays the moving image; and if the second display device is displaying the moving image when the continuous shooting of the still images is completed, when the selection means switches the display destination of the moving image from the second display device to the first display device after the continuous shooting of the still images is completed, the shifting of the assertion timing of the second synchronization signal by the predetermined shift amount is stopped.

3. The imaging device according to claim 1, wherein the imaging device is a lens.

4. an image sensor that operates in accordance with a first synchronization signal and captures moving images and still images; a plurality of display devices including a first display device and a second display device; a selection means for selecting one of the plurality of display devices as a display destination for displaying the moving image; a display control means for controlling the display device selected by the selection means to display the moving image in accordance with a second synchronization signal; a receiving means for receiving an operation for continuously capturing still images; When the second display device displays a moving image during the continuous shooting of the still images, the assertion timing of the second synchronization signal is shifted by a predetermined amount during a period in which the second display device displays the moving image; a control means for controlling, when the second display device is displaying the moving image at the end of the continuous shooting of the still images, to stop shifting the assertion timing of the second synchronization signal by the predetermined amount of shift when the selection means switches the display destination of the moving image from the second display device to the first display device after the end of the continuous shooting of the still images; An imaging device comprising:

5. The display device may further include a notification unit that notifies the display device selected by the selection unit of a display update instruction; when the display update instruction is notified to the display device selected by the selection means, the display control means updates the moving image displayed on the display device selected by the selection means at an assertion timing of the second synchronization signal; The notification means notifies the first display device of the display update instruction during continuous shooting of the still images. a timing for notifying the display update instruction to the first display device is different from a timing for notifying the display update instruction to the second display device; 5. The imaging device according to claim 1, wherein the first and second lenses are arranged parallel to each other.

6. an image sensor that operates in accordance with a first synchronization signal and captures moving images and still images; a plurality of display devices including a first display device and a second display device; a selection means for selecting one of the plurality of display devices as a display destination for displaying the moving image; a display control means for displaying the moving image on the display device selected by the selection means in accordance with a second synchronization signal, and for controlling the display device to update the display of the moving image at the assertion timing of the second synchronization signal when a display update instruction is notified; a receiving means for receiving an operation for continuously capturing still images; a notification means for notifying the display update instruction, wherein, during continuous shooting of the still images, the notification means changes the timing of notifying the display update instruction between when the first display device is notified and when the second display device is notified; a control means for controlling, when the second display device displays a moving image during the continuous shooting of the still images, the assertion timing of the second synchronization signal to be shifted by a predetermined amount during a period when the second display device displays the moving image; An imaging device comprising:

7. The notification means, during continuous shooting of the still images, When notifying the first display device of the display update instruction, the display update instruction is notified at an assertion timing of the first synchronization signal; When the display update instruction is notified to the second display device, the display update instruction is notified at a timing when a read time of the moving image has elapsed from the assertion timing of the first synchronization signal.

7. The imaging device according to claim 5, wherein the imaging device is a lens.

8. a calculation unit configured to, upon receiving the operation, calculate, as the predetermined deviation amount, a deviation amount of timing of the first synchronization signal during continuous shooting of the still images relative to the first synchronization signal before the continuous shooting of the still images; 8. The imaging device according to claim 1, wherein the imaging device is a lens.

9. During continuous shooting of the still images, a time from shooting to displaying one frame of the moving image when the first display device displays one frame of the moving image is longer than a time from shooting to displaying one frame of the moving image when the second display device displays one frame of the moving image.

9. The imaging device according to claim 1, wherein the imaging device is a lens.

10. Before the continuous shooting of the still images, the second synchronization signal is asserted at the assertion timing of a reference synchronization signal that is asserted at a constant cycle; When the second display device displays a moving image during the continuous shooting of the still images, the second synchronization signal is asserted at a timing shifted by the predetermined amount from the assertion timing of the reference synchronization signal.

10. The imaging device according to claim 1, wherein the imaging device is a lens.

11. When the first display device displays a moving image during the continuous shooting of the still images, the second synchronization signal is asserted at the assertion timing of the reference synchronization signal.

11. The imaging device according to claim 10.

12. when the second display device is displaying the moving image at the end of the continuous shooting of the still images, the control means controls the second synchronization signal to be asserted at the assertion timing of the reference synchronization signal when the selection means switches the display destination of the moving image from the second display device to the first display device after the end of the continuous shooting of the still images; The first display device displays a black image during a period from the timing at which the display destination of the moving image is switched from the second display device to the first display device after the continuous shooting of the still images is completed to the timing at which the second synchronization signal is asserted at the assertion timing of the reference synchronization signal.

12. The imaging device according to claim 10 or 11.

13. A control method for an imaging device having an imaging element that operates in accordance with a first synchronization signal and captures moving images and still images, and a plurality of display devices including a first display device and a second display device, the method comprising: a selection step of selecting one of the plurality of display devices as a display destination for displaying the moving image; a display control step of controlling the display device selected in the selection step to display the moving image in accordance with a second synchronization signal; a receiving step for receiving an operation for continuously taking still images; a generating step of generating a third synchronization signal that coincides with the second synchronization signal when the second display device displays the moving image; a control step of, when receiving the operation, controlling the assertion timing of the third synchronization signal so as to shift by a predetermined amount of shift; A control method comprising:

14. A control method for an imaging device having an imaging element that operates in accordance with a first synchronization signal and captures moving images and still images, and a plurality of display devices including a first display device and a second display device, the method comprising: a selection step of selecting one of the plurality of display devices as a display destination for displaying the moving image; a display control step of controlling the display device selected in the selection step to display the moving image in accordance with a second synchronization signal; a receiving step for receiving an operation for continuously taking still images; When the second display device displays a moving image during the continuous shooting of the still images, the assertion timing of the second synchronization signal is shifted by a predetermined amount during a period in which the second display device displays the moving image; a control step of controlling the second display device to stop shifting the assertion timing of the second synchronization signal by the predetermined amount of shift when the second display device is displaying the moving image at the end of the continuous shooting of the still images and the display destination of the moving image is switched from the second display device to the first display device after the end of the continuous shooting of the still images; A control method comprising:

15. A control method for an imaging device having an imaging element that operates in accordance with a first synchronization signal and captures moving images and still images, and a plurality of display devices including a first display device and a second display device, the method comprising: a selection step of selecting one of the plurality of display devices as a display destination for displaying the moving image; a display control step of displaying the moving image on the display device selected in the selection step in accordance with a second synchronization signal, and controlling the display device to update the display of the moving image at the assertion timing of the second synchronization signal when a display update instruction is notified; a receiving step for receiving an operation for continuously taking still images; a notification step of notifying the display update instruction, wherein, during continuous shooting of the still images, the timing of notifying the display update instruction is made different between when notifying the first display device and when notifying the second display device; a control step of controlling, when the second display device displays a moving image during the continuous shooting of the still images, the assertion timing of the second synchronization signal to be shifted by a predetermined amount during a period in which the second display device displays the moving image; A control method comprising:

16. A program for causing a computer to execute each step of the control method according to any one of claims 13 to 15.

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