Display substrate, method for manufacturing the same, and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device, the display substrate comprising a plurality of pixel regions, each pixel region including a display region provided with a pixel electrode and a drive region provided with a pixel circuit, the pixel circuit including at least one pixel transistor having a first pole and a second pole respectively connected to an active layer via a connection via hole, the drive region further including a first pole piece of a storage capacitor overlapping the first pole and the second pole of the pixel transistor in an insulated state in a direction perpendicular to the display substrate, the first pole piece having openings at locations corresponding to at least some of the connection via holes.

Description

Technical Field

[0001] (Cross - reference to related applications) This disclosure claims the priority of Chinese Patent Application No. 201921258054.2, filed with the China National Intellectual Property Administration on August 5, 2019, and incorporates by reference all of the contents of the said Chinese patent application.

[0002] This disclosure belongs to the field of display technologies, and specifically relates to a display substrate and a manufacturing method thereof, and a display device.

Background Art

[0003] In existing display substrates (for example, organic light - emitting diode display substrates), with the increase in resolution, the area of each pixel region is becoming smaller. In order to expand the storage capacitance, it is necessary to increase the area of the magnetic pole piece of the storage capacitance, which may cause the magnetic pole piece to overlap with each pixel transistor in the pixel circuit.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect, this disclosure provides a display substrate, which includes a plurality of pixel regions. Each pixel region includes a display region provided with a light - emitting element and a driving region provided with a pixel circuit. The pixel circuit includes at least one pixel transistor in which a first pole and a second pole are respectively connected to an active layer through connection via holes. In the driving region, a first magnetic pole piece of a storage capacitance that overlaps with the first pole and the second pole of the at least one pixel transistor in an insulating state in a direction perpendicular to the display substrate is further provided. The first magnetic pole piece has an opening at a location corresponding to at least a part of the connection via holes.

[0005] Optionally, in any one of the pixel regions, the first magnetic pole piece is connected to the first electrode of the light-emitting element, the second electrode of the light-emitting element is connected to the second power line, and the at least one pixel transistor includes a switching transistor and a driving transistor. The gate of the switching transistor is connected to a gate line, the first pole is connected to a data line, the second pole is electrically connected to the gate of the driving transistor, the first pole of the driving transistor is connected to the first power line, and the second pole is connected to a pixel electrode.

[0006] Optionally, the first magnetic pole piece has an opening at a location corresponding to at least one of the connection via holes of the first pole of the switching transistor, the connection via holes of the second pole of the switching transistor, and the connection via holes of the first pole of the driving transistor.

[0007] Optionally, the first magnetic pole piece overlaps in an insulating state with the connection via hole of the second pole of the driving transistor in a direction perpendicular to the display substrate, and the first magnetic pole piece has an opening at a location corresponding to the connection via hole of the second pole of the driving transistor.

[0008] Optionally, the first magnetic pole piece overlaps in an insulating state with the connection via hole of the second pole of the driving transistor in a direction perpendicular to the display substrate, and the first magnetic pole piece does not have an opening at a location corresponding to the connection via hole of the second pole of the driving transistor.

[0009] Optionally, the storage capacitor further includes a second magnetic pole piece electrically connected to the second pole of the switching transistor, and the second magnetic pole piece and the first magnetic pole piece overlap in an insulating state in a direction perpendicular to the display substrate to form a first sub-capacitance.

[0010] Optionally, the second magnetic pole piece is provided in the same layer as the active layer of the pixel transistor.

[0011] Optionally, the storage capacitance further includes a third magnetic pole piece electrically connected to the first magnetic pole piece. The third magnetic pole piece is provided in the same layer as the first and second poles of the pixel transistor, and overlaps with the second magnetic pole piece in an insulating state to form a second sub-capacitance.

[0012] Optionally, the light-emitting element is an organic light-emitting diode.

[0013] Optionally, the display substrate further includes a base. The first and second poles of the pixel transistor are located on the side away from the base of the active layer of the pixel transistor, and the first magnetic pole piece is located on the side close to the base of the active layer of the pixel transistor.

[0014] Optionally, the orthographic projection of the opening on the base covers the orthographic projection of the corresponding connection via hole on the base.

[0015] Optionally, the area of the orthographic projection of the opening on the base is greater than or equal to the area of the orthographic projection of the corresponding connection via hole on the base.

[0016] Optionally, the inclination angle of the connection via hole corresponding to the opening is an acute angle, and the inclination angle is the angle between the side wall of the connection via hole and the plane where the display substrate is located.

[0017] Optionally, the inclination angle of the connection via hole corresponding to the opening is 45° to 75°.

[0018] Optionally, the boundary angle of the active layer in the connection via hole corresponding to the opening is an acute angle, and the boundary angle is the angle between the side wall of the active layer and the plane where the display substrate is located.

[0019] Optionally, the inclination angle of the connection via hole corresponding to the opening is an acute angle. (α + β) / 2 > min(α, β) > 1 / 4α α is the inclination angle of any connection via hole corresponding to the opening, β is the boundary angle of the active layer in the connection via hole, the inclination angle is the angle between the side wall of the connection via hole and the plane where the display substrate is located, and the boundary angle is the angle between the side wall of the active layer and the plane where the display substrate is located.

[0020] Optionally, the opening includes a recess located at the edge of the first magnetic pole piece and / or a through hole located inside the first magnetic pole piece.

[0021] In another aspect, a display device including the display substrate described above is provided.

[0022] In another aspect, a method for manufacturing a display substrate is provided. The method includes providing a base and forming a storage capacitor and at least one pixel transistor on the base. The display substrate includes a plurality of pixel regions, and each pixel region includes a display region provided with a pixel electrode and a driving region provided with a pixel circuit. The pixel circuit includes the at least one pixel transistor in which a first pole and a second pole are respectively connected to an active layer through a connection via hole. The first magnetic pole piece of the storage capacitor is located in the driving region. The first magnetic pole piece overlaps with the first pole and the second pole of the pixel transistor in an insulating state in a direction perpendicular to the display substrate. The first magnetic pole piece has an opening in at least some of the connection via holes.

[0023] Optionally, the step of forming a storage capacitor and at least one pixel transistor on the base includes forming a first magnetic pole piece of the storage capacitor on the base, forming a first insulating layer on the first magnetic pole piece, forming a gate and a gate line of a switching transistor on the first insulating layer, forming a second insulating layer on the gate of the switching transistor and the gate line, forming an active layer of the switching transistor, an active layer of a driving transistor, and a second magnetic pole piece of the storage capacitor on the second insulating layer, wherein the second magnetic pole piece and the first magnetic pole piece overlap in an insulating state in a direction perpendicular to the base to form a first sub-capacitance, forming a third insulating layer on the active layer of the switching transistor, the active layer of the driving transistor, and the second magnetic pole piece of the storage capacitor, forming a first pole of the switching transistor, a second pole of the switching transistor, a first pole of the driving transistor, a second pole of the driving transistor, a gate of the driving transistor, a data line, a first power line, and a third magnetic pole piece on the third insulating layer, wherein the third magnetic pole piece is connected to the first magnetic pole piece via a connection via hole and is connected to the second pole of the driving transistor, and the second magnetic pole piece and the third magnetic pole piece overlap in an insulating state in a direction perpendicular to the base to form a second sub-capacitance.

Brief Description of the Drawings

[0024]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying out the Invention

[0025] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below by combining the drawings and specific embodiments.

[0026] It should be understood that the specific embodiments and drawings described in this specification are only for explaining the present disclosure and do not limit the present disclosure.

[0027] It should be understood that each embodiment of the present disclosure and each feature in the embodiment can be combined with each other when there is no contradiction.

[0028] For the sake of easy explanation, it should be understood that only the parts related to the present disclosure are shown in the drawings of the present disclosure, and the parts not related to the present disclosure are not shown.

[0029] It should be understood that each unit and module according to the embodiment of the present disclosure may correspond to only one physical structure, or may be composed of a plurality of physical structures, or a plurality of units and modules may be integrated into one physical structure.

[0030] Noun Explanation In the present disclosure, unless otherwise specified, the following technical terms should be understood according to the following interpretations.

[0031] When a plurality of structures are "provided in the same layer", it means that the plurality of structures are formed from the same material layer, so they are in the same layer in the stacking relationship, which does not mean that their distances from the base are equal, nor does it mean that they are exactly the same as other layer structures between the bases. On the contrary, when a structure is "provided in a different layer", it means that the plurality of structures do not meet the condition of being "provided in the same layer" and are formed from different material layers.

[0032] The "patterning process" is a step of forming a structure having a specific pattern. For example, a photolithography process can be mentioned. The photolithography process includes one or more steps among steps such as the formation of a material layer, the application of a photoresist, exposure, development, etching, and the stripping of the photoresist. Naturally, the patterning process may be other processes such as an imprinting process or an inkjet printing process.

[0033] An "opening" means that the first magnetic pole piece originally has a relatively complete regular shape (for example, a rectangle), but has a deletion (for example, a notch or a hole) at some positions, and the positions where these regular shapes are deleted are the "openings".

[0034] The first and second poles (that is, the source and the drain) of the pixel transistor are usually connected to its active layer through a connection via hole. Since the voltages of most of the first and second poles are different from the voltage of the electrode of the storage capacitor, a voltage difference occurs between the overlapping layers. Therefore, at the position of the above connection via hole, a short-circuit failure is likely to occur between the storage capacitor and the pixel transistor (specifically, between the electrode of the storage capacitor and the first and second poles of the pixel transistor), and the quality of the product deteriorates.

[0035] Therefore, in one aspect of the present disclosure, a display substrate including a plurality of pixel regions is provided. Each pixel region includes a display region provided with a pixel electrode and a driving region provided with a pixel circuit. The pixel circuit includes at least one pixel transistor in which a first electrode and a second electrode are respectively connected to an active layer via connection via holes. In the driving region, a first magnetic pole piece of a storage capacitor that overlaps the first electrode and the second electrode of the pixel transistor in an insulating state in a direction perpendicular to the display substrate is further provided. The first magnetic pole piece has an opening at at least a part of the connection via holes of at least a part of the pixel transistors.

[0036] In the display substrate according to the embodiment of the present disclosure, since the storage capacitor is located in the driving region and overlaps the pixel transistor, its area is relatively large and the storage effect is good. At the same time, the first magnetic pole piece of the storage capacitor has an opening at a location corresponding to the connection via hole, that is, the first magnetic pole piece has no or small overlap with these connection via holes, thereby reducing the risk of occurrence of defects such as short circuit of the first magnetic pole piece in the connection via hole, and improving the quality of the product.

[0037] The display substrate of the present disclosure will be described in detail with reference to FIGS. 1 to 8.

[0038] The display substrate according to the embodiment of the present disclosure includes a plurality of pixel regions 9. Each pixel region 9 includes a display region 92 provided with a pixel electrode 921 and a driving region 91 provided with a pixel circuit. The pixel circuit includes at least one pixel transistor in which a first electrode and a second electrode are respectively connected to an active layer via connection via holes 2.

[0039] The display substrate according to an embodiment of the present disclosure includes a plurality of pixel regions 9, and each pixel region 9 is the smallest unit capable of independently performing display, that is, 1 sub-pixel. Referring to FIG. 1, on the display substrate, a plurality of gate lines GATE and a plurality of data lines DATA that are insulated from each other and intersect may be provided, and each pixel region 9 is an area surrounded by two adjacent gate lines GATE and two adjacent data lines DATA. Here, each pixel region 9 may be located in the active area (AA area) of the display substrate, and the display substrate may further include a fanout area (Fanout area, that is, the uppermost area in FIG. 1) for drawing out leads, etc., but detailed description is omitted here.

[0040] The display substrate may include structures such as a first power supply line VDD and a second power supply line VSS for supplying power to each pixel region 9. However, in FIG. 1, the first power supply line VDD and the second power supply line VSS are not shown in order to clearly show the relationship between the pixel region 9, the gate line GATE, and the data line DATA.

[0041] Referring to FIGS. 1 and 3, each pixel region 9 includes a display region 92 and a driving region 91. A pixel electrode 921 is provided in the display region 92, and by driving the pixel electrode 921 with a data voltage (gray scale voltage), desired content can be displayed in the display region 92. A pixel circuit for driving the display of the display region 92 is provided in the driving region 91.

[0042] The pixel circuit includes at least one transistor (pixel transistor), and the sources and drains (i.e., the first and second electrodes) of these pixel transistors are connected to corresponding active layers via via holes (connection via holes 2).

[0043] A first magnetic pole piece C1 of a storage capacitor C is further provided in the driving region 91. The first magnetic pole piece C1 overlaps the first and second electrodes of the pixel transistor in an insulating state in a direction perpendicular to the display substrate, and has an opening C11 in at least some of the connection via holes 2 of at least some of the pixel transistors.

[0044] That is, a storage capacitor C is further provided in the pixel region 9. At least a part of one magnetic pole piece (the first magnetic pole piece C1) of the storage capacitor C is located in the driving region 91 and overlaps with the first and second poles of the pixel transistor. Therefore, the area of the first magnetic pole piece C1 is relatively large, and the storage performance of the storage capacitor C can be improved. As an example, as shown in FIG. 3, the first magnetic pole piece C1 covers the entire driving region 91.

[0045] At the same time, in the connection via hole 2 corresponding to at least a part of the first and second poles, the first magnetic pole piece C1 has an opening C11, so that there is no overlap or the overlapping area is small with these connection via holes 2. Therefore, the probability of the first magnetic pole piece C1 being short-circuited by the connection via hole 2 can be reduced, and the product quality can be improved.

[0046] Optionally, the display substrate further includes a base 5. The orthographic projection of the opening C11 on the base 5 covers the orthographic projection of the corresponding connection via hole 2 on the base 5. Further, the area of the orthographic projection of the opening C11 on the base 5 is larger than the area of the orthographic projection of the corresponding connection via hole 2 on the base 5. Furthermore, the area of the orthographic projection of the opening C11 on the base 5 is larger than the contact area between the data line, power line, etc. and the active layer in the connection via hole 2.

[0047] Referring to FIGS. 3, 5, and 6, it is preferable that the opening C11 completely covers the corresponding connection via hole 2 so that the first magnetic pole piece C1 does not completely overlap with the connection via hole 2. Further, in order to better avoid short circuits, it is more preferable that the opening C11 protrudes beyond the corresponding connection via hole 2.

[0048] Optionally, the opening C11 includes a recess located at the edge of the first magnetic pole piece C1 and / or a through hole located inside the first magnetic pole piece C1.

[0049] The specific form and position of the opening C11 also vary. When it is located at the edge of the first magnetic pole piece C1, the opening C11 is a recess that is concave inward from the edge of the first magnetic pole piece C1 (for example, the three openings C11 on the left side of FIG. 4). When it is located inside the first magnetic pole piece C1, the opening C11 is a through hole that penetrates the first magnetic pole piece C1 (for example, the opening C11 on the right side of FIG. 4).

[0050] Optionally, the inclination angle α of the connection via hole 2 corresponding to the opening C11 is an acute angle. Furthermore, the inclination angle α of the connection via hole 2 corresponding to the opening C11 is 45° to 75°.

[0051] Referring to FIG. 5, the inclination angle α of the connection via hole 2 is namely the angle between the side wall of the connection via hole 2 and the plane where the base 5 is located. Here, at least the connection via hole 2 corresponding to the opening C11 has an acute inclination angle α, and furthermore, an acute angle of 45° to 75°.

[0052] The inclination angle α of the via hole is related to the process parameters during the formation of the via hole. When the inclination angle α of the via hole is large, over-etching is likely to occur, so a conductive line contact layer is likely to be formed at the via hole position, and the possibility of a short circuit occurring between the via hole position and the conductive layer of other layers is increased.

[0053] Therefore, through research, it has been found that by using an acute inclination angle α in the connection via hole 2, the occurrence probability of a short circuit in the connection via hole 2 can be further reduced.

[0054] Optionally, the first pole and the second pole of the pixel transistor are provided in the same layer, and are located on the side away from the base 5 of the active layer of the pixel transistor, and the first magnetic pole piece C1 is located on the side close to the base 5 of the active layer of the pixel transistor.

[0055] That is, referring to FIGS. 5 and 6, the first and second electrodes of the pixel transistor may be located above the active layer and are connected to the active layer through the connection via hole 2 located below them. At the same time, the first magnetic pole piece C1 is located below the active layer. Since such a first magnetic pole piece C1 is more likely to cause a short circuit with the connection via hole 2, it is more preferable to adopt the opening C11 in the embodiment of the present disclosure.

[0056] According to one aspect of the embodiment of the present disclosure, the first magnetic pole piece C1 is electrically connected to the pixel electrode 921. The pixel electrode 921 is the first electrode of the light-emitting element L, and the second electrode of the light-emitting element L is connected to the second power supply line VSS. The pixel transistor includes a switching transistor T1 and a driving transistor T2. Here, the gate T13 of the switching transistor is connected to the gate line GATE, the first electrode T11 is connected to the data line DATA, and the second electrode T12 is electrically connected to the gate T23 of the driving transistor. The first electrode T21 of the driving transistor is connected to the first power supply line VDD, and the second electrode is connected to the pixel electrode 921. Optionally, the light-emitting element L is an organic light-emitting diode.

[0057] That is, referring to FIG. 3, the pixel circuit may specifically be in a form in which the writing of the data voltage is controlled through the switching transistor T1, and the emission luminance of the light-emitting element L is controlled by controlling the voltage of the gate T23 of the driving transistor. At this time, the light-emitting element L may be an organic light-emitting diode (OLED), the first electrode (pixel electrode 921) may be either a cathode or an anode, and the second electrode may be the other.

[0058] Note that FIG. 3 shows the most basic form (2T1C) of the above pixel circuit, that is, the pixel circuit includes at least two pixel transistors, namely the switching transistor T1 and the driving transistor T2, and one storage capacitor C. However, it is also possible that the pixel circuit includes other structures such as other pixel transistors.

[0059] According to the above pixel circuit, of the two electrodes of the storage capacitor, one electrode should be electrically connected to the pixel electrode 921 (or the second electrode T22 of the driving transistor), and the other electrode should be electrically connected to the second electrode T12 of the switching transistor (or the gate T23 of the driving transistor). At this time, the first magnetic pole piece C1 of the storage capacitor C belongs to one electrode electrically connected to the pixel electrode 921.

[0060] Optionally, the first magnetic pole piece C1 has an opening C11 at a location corresponding to at least one of the connection via holes 2 of the first electrode T11 of the switching transistor, the connection via holes 2 of the second electrode T12 of the switching transistor, and the connection via holes 2 of the first electrode T21 of the driving transistor.

[0061] In this way, since the first magnetic pole piece C1 is not directly connected to any of the first electrode T11 and the second electrode T12 of the switching transistor and the first electrode T21 of the driving transistor, the voltages of these three electrodes T11, T12, and T21 are usually different from the voltage of the first magnetic pole piece C1, and a short circuit with the first magnetic pole piece C1 is more likely to occur. Therefore, referring to FIG. 3, it is preferable that the first magnetic pole piece C1 is provided with an opening C11 at a location corresponding to the connection via holes 2 of these three electrodes T11, T12, and T21 (of course, it is most preferable to simultaneously provide the opening C11 at the locations corresponding to the connection via holes 2 of these three electrodes T11, T12, and T21).

[0062] Optionally, as one form of the embodiment of the present disclosure, the first magnetic pole piece C1 overlaps with the connection via holes 2 of the second electrode T22 of the driving transistor in an insulating state.

[0063] Since the first magnetic pole piece C1 is electrically connected to the pixel electrode 921, it is also electrically connected to the second pole T22 of the driving transistor. The voltages of both are theoretically always the same, and the probability of a short circuit occurring between them is small. Therefore, referring to FIGS. 3 and 6, the first magnetic pole piece C1 does not have an opening at the location corresponding to the connection via hole 2 of the second pole T22 of the driving transistor, and overlaps with the connection via hole 2 of the second pole T22 of the driving transistor in an insulating state to increase the area of the first magnetic pole piece C1.

[0064] Optionally, as another form of the embodiment of the present disclosure, the first magnetic pole piece C1 has an opening C11 at the location corresponding to the connection via hole 2 of the second pole T22 of the driving transistor.

[0065] That is, although the probability of a short circuit occurring between the first magnetic pole piece C1 and the second pole T22 of the driving transistor is relatively small, in order to more thoroughly avoid a short circuit, referring to FIG. 8, the first magnetic pole piece C1 may have an opening C11 at the location corresponding to the connection via hole 2 of the second pole T22 of the driving transistor.

[0066] Optionally, the storage capacitor C further includes a second magnetic pole piece C2 electrically connected to the second pole T12 of the switching transistor. The second magnetic pole piece C2 and the first magnetic pole piece C1 overlap in an insulating state in a direction perpendicular to the display substrate to form a first sub-capacitance.

[0067] Referring to FIG. 6, in order to form a capacitance, the first magnetic pole piece C1 needs to overlap with other magnetic pole pieces. According to the above pixel circuit, the first magnetic pole piece C1 can overlap with the second magnetic pole piece C2, and the second magnetic pole piece C2 is electrically connected to the second pole T12 of the switching transistor (or the gate T23 of the driving transistor). Also, as shown in FIG. 6, the second magnetic pole piece C2 is provided in the same layer as the active layer of the pixel transistor.

[0068] Optionally, the storage capacitor C further includes a third magnetic pole piece C3 electrically connected to the first magnetic pole piece C1. The third magnetic pole piece C3 is provided in a layer different from the first magnetic pole piece C1 and is provided in the same layer as the first and second poles of the pixel transistor. The third magnetic pole piece C3 and the second magnetic pole piece C2 overlap in an insulating state to form a second sub-capacitance.

[0069] In this embodiment, a third magnetic pole piece C3 provided in a layer different from the first magnetic pole piece C1 can be added. Since the third magnetic pole piece C3 is electrically connected to the first magnetic pole piece C1, the voltage of the first magnetic pole piece C1 and the third magnetic pole piece C3 is electrically the same. At the same time, referring to FIG. 7, the third magnetic pole piece C3 and the first magnetic pole piece C1 are located on both sides of the second magnetic pole piece C2 along the direction perpendicular to the display substrate and overlap with the second magnetic pole piece C2. Therefore, the capacitance value can be increased without increasing the total area of the storage capacitor C.

[0070] Optionally, the boundary angle β of the active layer in the connection via hole 2 corresponding to the opening C11 is an acute angle.

[0071] As shown in FIG. 6, the boundary angle β of the active layer is the angle between the side wall of the active layer and the plane where the base 5 is located.

[0072] For the same reason, as shown in FIG. 6, when the angle of the boundary angle β of the active layer is relatively large, over-etching is likely to occur, and the possibility of short-circuiting between conductive layers of different layers increases. Therefore, the etching boundary angle β in the vicinity of at least the connection via hole 2 corresponding to the opening C11 of the active layer (for example, the active layer T14 of the switching transistor and the active layer T24 of the driving transistor) is an acute angle. (Of course, due to process reasons, the boundary angle β of the same active layer at each position is usually the same).

[0073] Furthermore, the inclination angle α of the connection via hole 2 corresponding to the opening C11 is an acute angle, and (α + β) / 2 > min(α, β) > 1 / 4α is satisfied. Here, the inclination angle α and the boundary angle β are corresponding angles in the same connection via hole 2 corresponding to the opening C11.

[0074] Referring to FIG. 6, in the same connection via hole 2 corresponding to the opening C11 (for example, the connection via hole 2 corresponding to the first pole T21 of the driving transistor), both the inclination angle α of the connection via hole 2 and the boundary angle β of the active layer (for example, the active layer T24 of the driving transistor) are acute angles, and satisfy the formula (α + β) / 2 > min(α, β) > 1 / 4α. Thereby, while reducing the possibility of an interlayer short circuit at the position of the connection via hole 2, the etching rate can be kept relatively high.

[0075] Of course, referring to FIGS. 5 to 7, the above-described display substrate may further include other known structures. For example, a light-emitting layer and a second electrode (not shown) of the light-emitting element L, a first insulating layer 61 that insulates the gate electrode T13 of the switching transistor and the first magnetic pole piece C1, a second insulating layer 62 that insulates the gate electrode T13 of the switching transistor and the active layer T14 (including the active layer T24 of the driving transistor), a third insulating layer 63 that insulates each active layer and each first pole / each second pole, a fourth insulating layer 64 that insulates each first pole / each second pole and the pixel electrode 921, and the like.

[0076] Of course, referring to FIGS. 5 to 7, a part of the different structures in the above-described display substrate may be provided in the same layer. For example, the gate line GATE may be provided in the same layer as the gate T13 of the switching transistor, the second magnetic pole piece C2 may be provided in the same layer as each active layer (the second magnetic pole piece C2 may be subjected to a conductor conversion process), the third magnetic pole piece C3, each first pole / each second pole, the data line DATA, the first power supply line VDD, etc. may be provided in the same layer.

[0077] Of course, in the above-described display substrate, when two structures are electrically connected, they can be realized in different ways.

[0078] The first method: Referring to FIGS. 5 to 7, if they are provided in two layers with different structures, they can be electrically connected via via holes. For example, the second pole T12 of the switching transistor can be electrically connected to the second magnetic pole piece C2 via a via hole. Referring to FIG. 3, an opening C11 may be provided in the first magnetic pole piece C1 at the via hole. For example, the third magnetic pole piece C3 can be connected to the first magnetic pole piece C1 via a via hole, and the pixel electrode 921 can be connected to the third magnetic pole piece C3 via a via hole, thereby realizing the mutual electrical connection among the first magnetic pole piece C1, the third magnetic pole piece C3, and the pixel electrode 921.

[0079] The second method: Referring to FIGS. 5 to 7, if they are provided in the same layer, they can be directly connected and integrated. For example, the second pole T12 of the switching transistor can be directly connected to the gate T23 of the driving transistor and integrated. For example, the second pole T22 of the driving transistor can be directly connected to the third magnetic pole piece C3 and integrated, and finally, the mutual electrical connection among the second pole T22 of the driving transistor, the first magnetic pole piece C1, the third magnetic pole piece C3, and the pixel electrode 921 is realized.

[0080] Of course, in the above, one specific pixel circuit (organic light-emitting diode pixel circuit) is described as an example, but it should be understood that the embodiments of the present disclosure are also applicable to other pixel circuits such as pixel circuits used in liquid crystal displays (LCDs), etc., and detailed descriptions are omitted here.

[0081] Referring to FIGS. 1 to 8, in one aspect of the present disclosure, a method for manufacturing the display substrate is further provided. Each pixel region in the display substrate includes a display region provided with a pixel electrode and a driving region provided with a pixel circuit. The pixel circuit includes at least one pixel transistor, and the first and second electrodes of the pixel transistor are respectively connected to the active layer through connection via holes. The first magnetic pole piece of the storage capacitor is located in the driving region, and the first magnetic pole piece overlaps the first and second electrodes of the pixel transistor in an insulating state in a direction perpendicular to the display substrate, and the first magnetic pole piece has an opening in at least a part of the connection via holes.

[0082] Specifically, with respect to the display substrate described with reference to FIG. 3, as shown in FIG. 9, the manufacturing method may include the following steps.

[0083] S301: Form the first magnetic pole piece C1 on the base by a patterning process. The first magnetic pole piece C1 overlaps the first and second electrodes of the pixel transistor to be formed in an insulating state in a direction perpendicular to the display substrate, and the first magnetic pole piece has an opening in at least a part of the connection via holes.

[0084] S302: Form the first insulating layer 61 on the first magnetic pole piece C1 and the exposed base by a patterning process.

[0085] S303: Form the gate T13 of the switching transistor and the gate line GATE connected to the gate T13 on the first insulating layer 61 by a patterning process.

[0086] S304: Form the second insulating layer 62 on the gate T13 of the switching transistor and the gate line GATE by a patterning process.

[0087] S305: Form the active layer T14 of the switching transistor, the active layer T24 of the driving transistor, and the second magnetic pole piece C2 on the second insulating layer 62 by a patterning process. The second magnetic pole piece C2 and the first magnetic pole piece C1 overlap in an insulating state in a direction perpendicular to the base to form a first sub-capacitance. Here, the second magnetic pole piece C2 and the active layers of the respective transistors can be formed by the same process, that is, the second magnetic pole piece C2 and the active layers of the respective transistors can be manufactured from the same material (for example, polycrystalline silicon), and the second magnetic pole piece C2 can be ion-doped alone to increase its conductivity.

[0088] S306: Form the third insulating layer 63 on the active layer T14 of the switching transistor, the active layer T24 of the driving transistor, and the second magnetic pole piece C2 by a patterning process.

[0089] S307: Form the first pole T11 of the switching transistor, the second pole T12 of the switching transistor, the first pole T21 of the driving transistor, the second pole T22 of the driving transistor, the gate T23 of the driving transistor, the data line DATA, the first power supply line VDD, and the third magnetic pole piece C3 on the third insulating layer 63 by a patterning process. Here, the third magnetic pole piece C3 is connected to the first magnetic pole piece C1 via a connection via hole and is connected to the second pole T22 of the driving transistor. The second magnetic pole piece C2 and the third magnetic pole piece C3 overlap in an insulating state in a direction perpendicular to the base to form a second sub-capacitance. The second pole T12 of the switching transistor is connected to the gate T23 of the driving transistor, the first pole T11 of the switching transistor is connected to the data line DATA, and the first pole T21 of the driving transistor is connected to the first power supply line VDD.

[0090] S308: Form a fourth insulating layer 64 on the first pole T11 of the switching transistor, the second pole T12 of the switching transistor, the first pole T21 of the driving transistor, the second pole T22 of the driving transistor, the gate T23 of the driving transistor, the data line DATA, the first power supply line VDD, the second power supply line VSS, and the third magnetic pole piece C3 by a patterning process.

[0091] S309: Form a pixel electrode 921 (first electrode) on the fourth insulating layer 64 by a patterning process. The pixel electrode 921 is connected to the third magnetic pole piece C3 via a connection via hole.

[0092] S310: Form a light-emitting layer on the pixel electrode 921 by a patterning process.

[0093] S311: Form a second electrode of the light-emitting element on the light-emitting layer by a patterning process. The second electrode is connected to the second power supply line VSS via a connection via hole.

[0094] In the above method, the case where the switching transistor is a bottom-gate type and the driving transistor is a top-gate type is taken as an example for explanation, but the present disclosure is not limited thereto.

[0095] In one aspect of the present disclosure, a display device including the above-described display substrate is provided.

[0096] Specifically, the display device may be any product or component having a display function, such as a liquid crystal display panel (LCD), an organic light-emitting diode (OLED) display panel, an electronic paper, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc.

[0097] The above embodiments are merely exemplary embodiments used to explain the principles of the present disclosure, and it should be understood that the present disclosure is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and substantial circumstances of the present disclosure, and such modifications and improvements are also regarded as falling within the scope of the claims of the present disclosure.

Claims

1. A display substrate including a plurality of pixel regions, each pixel region including a display region provided with a light-emitting element and a driving region provided with a pixel circuit, the pixel circuit including at least one pixel transistor having a first electrode and a second electrode respectively connected to an active layer through connection vias, wherein a first electrode plate of a storage capacitor is further provided in the driving region so as to overlap, in a direction perpendicular to the display substrate, the first electrode and the second electrode of the at least one pixel transistor in an insulating state, and the first electrode plate has an opening at a location corresponding to at least a part of the connection vias, Display substrate.

2. In one of the pixel regions, the first electrode plate is electrically connected to a first electrode of the light-emitting element, a second electrode of the light-emitting element is connected to a second power line, the at least one pixel transistor includes a switching transistor and a driving transistor, a gate of the switching transistor is connected to a gate line, a first electrode is connected to a data line, and a second electrode is electrically connected to a gate of the driving transistor, a first electrode of the driving transistor is connected to a first power line, and a second electrode is connected to a pixel electrode, The display substrate according to Claim 1.

3. The first electrode plate has an opening at a location corresponding to at least one of a connection via of a first electrode of the switching transistor, a connection via of a second electrode of the switching transistor, and a connection via of a first electrode of the driving transistor, The display substrate according to Claim 2.

4. The first electrode plate overlaps, in a direction perpendicular to the display substrate, a second electrode of the driving transistor in an insulating state, and the first electrode plate has an opening at a location corresponding to a connection via of a second electrode of the driving transistor, The display substrate according to Claim 3.

5. The first electrode plate overlaps, in a direction perpendicular to the display substrate, a connection via of a second electrode of the driving transistor in an insulating state, and the first electrode plate does not have an opening at a location corresponding to a connection via of a second electrode of the driving transistor, The display substrate according to Claim 3.

6. The storage capacitor further includes a second electrode plate electrically connected to a second electrode of the switching transistor, The second pole piece and the first pole piece overlap in an insulating state in a direction perpendicular to the display substrate to form a first sub-capacitance. The display substrate according to claim 2.

7. The second pole piece is provided in the same layer as the active layer of the pixel transistor. The display substrate according to claim 6.

8. The storage capacitance further includes a third pole piece electrically connected to the first pole piece. The third pole piece is provided in the same layer as the first and second poles of the pixel transistor, and overlaps with the second pole piece in an insulating state to form a second sub-capacitance. The display substrate according to claim 7.

9. The light-emitting element is an organic light-emitting diode. The display substrate according to claim 2.

10. Further comprising a base, The first and second poles of the pixel transistor are located on a side away from the base of the active layer of the pixel transistor. The first pole piece is located on a side close to the base of the active layer of the pixel transistor. The display substrate according to any one of claims 1 to 9.

11. The orthographic projection of the opening onto the base covers the orthographic projection of the corresponding connection via hole onto the base. The display substrate according to claim 10.

12. The area of the orthographic projection of the opening onto the base is equal to or larger than the area of the orthographic projection of the corresponding connection via hole onto the base. The display substrate according to claim 11.

13. The inclination angle of the connection via hole corresponding to the opening is an acute angle, and the inclination angle is the angle between the side wall of the connection via hole and the plane on which the display substrate is located. The display substrate according to any one of claims 1 to 12.

14. The inclination angle of the connection via hole corresponding to the opening is 45° to 75°. The display substrate according to claim 13.

15. The boundary angle of the active layer in the connection via hole corresponding to the opening is an acute angle, and the boundary angle is the angle between the side wall of the active layer and the plane on which the display substrate is located. The display substrate according to any one of claims 1 to 14.

16. The inclination angle of the connection via hole corresponding to the opening is an acute angle. (α+β) / 2>min(α, β)>1 / 4α α is the inclination angle of any connection via hole corresponding to the opening, β is the boundary angle of the active layer in the connection via hole, the inclination angle is the angle between the side wall of the connection via hole and the plane on which the display substrate is located, and the boundary angle is the angle between the side wall of the active layer and the plane on which the display substrate is located. The display substrate according to any one of claims 1 to 12.

17. The opening includes a recess located at an edge of the first pole piece and / or a through hole located inside the first pole piece. The display substrate according to any one of claims 1 to 16.

18. A display device including the display substrate according to any one of claims 1 to 17.

19. Providing a base; Forming a storage capacitor and at least one pixel transistor on the base, the manufacturing method of a display substrate including: The display substrate includes a plurality of pixel regions, each pixel region includes a display region provided with a pixel electrode and a driving region provided with a pixel circuit, the pixel circuit includes the at least one pixel transistor in which a first pole and a second pole are respectively connected to an active layer through a connection via hole. The first pole piece of the storage capacitor is located in the driving region, the first pole piece overlaps with the first pole and the second pole of the pixel transistor in an insulating state in a direction perpendicular to the display substrate, and the first pole piece has an opening in at least some of the connection via holes. The manufacturing method of a display substrate.

20. The step of forming a storage capacitor and at least one pixel transistor on the base includes: Forming a first pole piece of a storage capacitor on the base; Forming a first insulating layer on the first pole piece; Forming a gate and a gate line of a switching transistor on the first insulating layer; Forming a second insulating layer on the gate of the switching transistor and the gate line; Forming an active layer of the switching transistor, an active layer of a driving transistor, and a second pole piece of a storage capacitor on the second insulating layer, the second pole piece and the first pole piece overlap in an insulating state in a direction perpendicular to the base to form a first sub-capacity; Forming a third insulating layer on the active layer of the switching transistor, the active layer of the driving transistor, and the second pole piece of the storage capacitor. Form a first pole of a switching transistor, a second pole of the switching transistor, a first pole of a driving transistor, a second pole of the driving transistor, a gate of the driving transistor, a data line, a first power supply line, and a third pole piece on the third insulating layer, the third pole piece being connected to the first pole piece via a connection via hole and being connected to the second pole of the driving transistor, the second pole piece and the third pole piece overlapping in an insulating state in a direction perpendicular to the base to form a second sub-capacitance, The method according to claim 19.

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