Image forming apparatus

Abstract

To prevent a change in the shape of an image at the boundary between light-emitting element array chips.SOLUTION: An image forming apparatus has: an exposure head that includes a substrate on which a first chip in which a plurality of light-emitting elements are arranged at a predetermined interval in a first direction and a second chip in which a plurality of light-emitting elements are arranged at a predetermined interval in the first direction are arranged in order in the first direction, and the first chip and the second chip are arranged to overlap in a second direction orthogonal to the first direction, and turns on the light-emitting elements in the chips according to image data to expose a photoreceptor; and a controller that transmits signals including data signals obtained by dividing the image data for the respective chips and for controlling the exposure head. When the interval between the light-emitting elements in the first chip and the light-emitting elements in the second chip is not a predetermined interval in an area where the first chip and the second chip overlap in the second direction, the controller corrects the concentration for one light-emitting elements forming the image data in the overlapping area, by using the concentration for the other light-emitting elements forming the image data in the overlapping area.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] The present invention relates to an image forming apparatus including an exposure device that exposes a photoreceptor.

Background Art

[0002] In an electrophotographic image forming apparatus such as a printer, a method of exposing a photosensitive drum using an exposure device using LEDs, organic ELs, etc. to form a latent image is generally known. The exposure device includes a light emitting element array arranged in the rotational axis direction (longitudinal direction) of the photosensitive drum, and a rod lens array that forms an image of the light of the light emitting element array on the photosensitive drum. The LEDs and organic ELs are known to have a surface light emitting shape in which the irradiation direction of light from the light emitting surface is the same as that of the rod lens array.

[0003] In an image forming apparatus using such an exposure device, compared with a laser scanning type image forming apparatus that deflects and scans a laser beam with a polygon motor, the number of parts used is small, so the apparatus can be easily miniaturized and the cost can be reduced.

[0004] Here, the length of the light emitting element array in the longitudinal direction is determined according to the image area width of the photosensitive drum, and the interval between the light emitting elements is determined according to the resolution of the printer. For example, in the case of a printer with a resolution of 1200 dpi, since the pixel interval is 21.16 μm (omitting three decimal places), the interval between the light emitting elements is also 21.16 μm. In the case of an image forming apparatus capable of forming an image for an image area width of about 300 mm at this interval between the light emitting elements, 14,173 light emitting elements are arranged in the longitudinal direction.

[0005] When mounting the light-emitting elements of the above-mentioned number on a substrate, since the number of light-emitting elements is large, the mounting cost becomes high. Therefore, a method is used in which a plurality of light-emitting elements are formed on one light-emitting element array chip, and this light-emitting element array chip is mounted on the substrate to reduce the number of elements mounted on the substrate. For example, when 500 light-emitting elements are formed on one light-emitting element array chip, by mounting 28 of the light-emitting element array chips on the substrate, image formation can be achieved for an image area width of 296 mm. By adopting a configuration in which a plurality of light-emitting elements are formed on one light-emitting element array chip in this way, the mounting cost can be reduced.

[0006] On the other hand, when mounting a plurality of light-emitting element array chips on a substrate, an error in the mounting position of each light-emitting element array chip occurs. Then, the distance between the light-emitting elements of adjacent light-emitting element array chips in the longitudinal direction of the substrate does not necessarily become a predetermined distance, and unevenness in the pixel pitch occurs at the boundary between adjacent light-emitting element array chips. Therefore, at the boundary between adjacent light-emitting element array chips, gaps between pixels are arranged in the rotation direction of the photosensitive drum and appear as white streaks, or overlaps between pixels are arranged in the rotation direction of the photosensitive drum and appear as black streaks, resulting in a streak phenomenon.

[0007] Therefore, in Patent Documents 1 and 2, the ends of adjacent light-emitting element array chips are overlapped in the rotation direction of the photosensitive drum, and control is performed to cause both of the light-emitting elements in the overlap region to emit light. In Patent Document 1, control is performed to cause the light-emitting elements that overlap in the rotation direction of the photosensitive drum to emit light at a ratio of 1 / 2. In Patent Document 2, control is performed to cause the light-emitting ratio of the light-emitting elements that overlap in the rotation direction of the photosensitive drum to be heavier toward the center side of the light-emitting element array chip and lighter toward the end side. In this way, a method has been proposed in which, at the boundary between adjacent light-emitting element array chips, a plurality of light-emitting elements are overlapped in the rotation direction of the photosensitive drum, and exposure is shared by the plurality of light-emitting elements that overlap in the rotation direction.

Prior Art Documents

Patent Documents

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-254739 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-192675 [Summary of the Invention] [Problems to be Solved by the Invention]

[0009] However, even if exposure is shared among a plurality of light-emitting elements in the overlap region at the boundary between adjacent light-emitting element array chips, the shape of the image may appear distorted at the portion where the exposure is shared (the portion corresponding to the boundary).

[0010] Therefore, an object of the present invention is to suppress a change in the shape of an image at the boundary between light-emitting element array chips. [Means for Solving the Problems]

[0011] A typical configuration of the present invention for achieving the above object includes a photoreceptor, a first chip in which a plurality of light-emitting elements are arranged at a predetermined interval in a first direction, and a second chip in which a plurality of light-emitting elements are arranged at the predetermined interval in the first direction. The first chip and the second chip are arranged in the first direction in order, and a substrate is provided such that the first chip and the second chip overlap in a second direction orthogonal to the first direction. An exposure head that exposes the photoreceptor by emitting light from the light-emitting elements of each chip according to image data, and a controller that transmits a signal for controlling the exposure head, including a data signal obtained by dividing the image data for each chip. When the interval in the first direction between the light-emitting elements of the first chip and the light-emitting elements of the second chip in the region where the first chip and the second chip overlap in the second direction is less than the predetermined interval, the controller corrects the density for the first light-emitting elements forming the image data using the density for the second light-emitting elements forming the image data, where the light-emitting elements of the first chip forming the interval less than the predetermined interval are defined as first light-emitting elements, and the light-emitting elements of the second chip forming the interval less than the predetermined interval are defined as second light-emitting elements.and Correct the density for the second light-emitting element forming the image data using the density for the first light-emitting element forming the image data and further, the controller further corrects the density for the first light-emitting element forming the image data by using the reduced area of the pixels forming an interval less than the predetermined interval, sets the corrected density to the data signal divided for the chip on which the first light-emitting element is arranged, and further corrects the density for the second light-emitting element forming the image data by using the reduced area of the pixels forming an interval less than the predetermined interval, and sets the corrected density to the data signal divided for the chip on which the second light-emitting element is arranged characterized by doing so

Effect of the Invention

[0012] According to the present invention, it is possible to suppress a change in the shape of an image in a region where the first chip and the second chip overlap in the second direction

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Mode for Carrying Out the Invention

[0014] Hereinafter, with reference to the drawings, preferred embodiments of the present invention will be illustratively described in detail. However, the dimensions, materials, shapes, relative arrangements, etc. of the components described in the following embodiments should be appropriately changed according to the configuration of the apparatus to which the present invention is applied and various conditions, and the scope of the present invention is not intended to be limited only to those.

[0015] 〔Example 1〕 (Configuration of the entire image forming apparatus) Using FIG. 1, the electrophotographic image forming apparatus in this embodiment will be briefly described. FIG. 1 shows the configuration of the entire image forming apparatus. This image forming apparatus is composed of a scanner unit 100, an image forming unit 103, a fixing unit 104, a paper feeding / conveying unit 105, and a printer control unit (not shown) that controls these units.

[0016] The scanner unit 100 illuminates the document placed on the document table, optically reads the document image, converts the image into an electrical signal, and creates image data. In the image forming unit 103, the photosensitive drum 102 as an image carrier (photosensitive member) is rotationally driven, and the photosensitive drum 102 is charged by the charger 107. The exposure head 106 as an exposure device emits light according to the image data, and the light emitted from the chip surface of the arrayed light emitting element group is condensed onto the photosensitive drum 102 by the rod lens array to form an electrostatic latent image on the photosensitive drum 102. The developing device 108 develops the toner with respect to the electrostatic latent image formed on the photosensitive drum 102. The developed toner image is transferred onto the paper conveyed on the transfer belt 111. The image forming unit 103 has four image forming units that perform the above-described series of electrophotographic processes (charging, exposure, development, transfer), and by arranging them in the order of cyan (C), magenta (M), yellow (Y), and black (K), a full-color image is formed. The four image forming units sequentially execute the image forming operations of the magenta, yellow, and black image forming units after a predetermined time has elapsed since the start of image formation of the cyan image forming unit.

[0017] In the paper feeding / conveying unit 105, paper as a recording medium is fed from a pre-instructed paper feeding unit among the in-body paper feeding units 109a and 109b, the external paper feeding unit 109c, and the manual paper feeding unit 109d, and the fed paper is conveyed to the registration roller 110. The registration roller 110 conveys the paper onto the transfer belt 111 at the timing when the toner image formed in the above-described image forming unit 103 is transferred onto the paper. An optical sensor 113 is disposed at a position facing the transfer belt 111 to detect the position of the test chart printed on the transfer belt 111 in order to derive the color misregistration amount between the image forming units. The color misregistration amount derived here is notified to the image controller unit 415 (see FIG. 4), and the image positions of each color are corrected. By this control, a full-color toner image without color misregistration is transferred onto the paper. The fixing unit 104 is composed of a combination of rollers, incorporates a heat source such as a halogen heater, and melts and fixes the toner on the paper onto which the toner image has been transferred from the transfer belt 111 by heat and pressure. The paper on which the image has been fixed is discharged outside the image forming apparatus by the discharge roller 112.

[0018] The printer control unit (not shown) communicates with the MFP control unit that controls the entire MFP, executes control according to its instructions, and manages the states of the aforementioned scanner, image forming, fixing, paper feeding / conveying units, and gives instructions so that the whole can operate smoothly while maintaining harmony. Here, MFP is an abbreviation for Multi-Function Printer, and the entire MFP refers to the entire image forming apparatus. Here, as the image forming apparatus, a multifunction peripheral (Multi-Function Printer) having the functions of a printer, a copier, an image reader, and a FAX in one unit is exemplified.

[0019] (Configuration of the exposure head) Using FIG. 2, the exposure head 106 as an exposure device for exposing the photosensitive drum 102 will be described. FIGS. 2(a) and 2(b) show the arrangement of the exposure head 106 with respect to the photosensitive drum 102 and the state in which the light emitted from the light emitting element group 201 is condensed on the photosensitive drum 102 by the rod lens array 203.

[0020] The exposure head 106 and the photosensitive drum 102 are each attached to the image forming apparatus by attachment members (not shown). The exposure head 106 includes a light emitting element group 201, a printed circuit board 202 on which the light emitting element group 201 is mounted, a rod lens array 203, and a housing 204 that attaches the rod lens array 203 and the printed circuit board 202. In this example, the light emitting element group 201 is a group of light emitting element array chips each having a plurality of light emitting elements. In the factory, the exposure head 106 is assembled and adjusted as a single unit, and focusing adjustment and light amount adjustment are performed to adjust the spot at the focusing position to a predetermined size. Here, the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the light emitting element group 201 are arranged to be a predetermined interval, so that the emitted light (light beam) from the light emitting element group 201 is imaged on the photosensitive drum 102. Therefore, during focusing adjustment, the attachment position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting element group 201 becomes a desired value. Also, during light amount adjustment, each light emitting element is sequentially caused to emit light individually, and the drive current of each light emitting element is adjusted so that the light condensed through the rod lens array 203 becomes a predetermined light amount.

[0021] (Configuration of Printed Circuit Board) Fig. 3 shows a printed circuit board 202 on which the light emitting element group 201 is arranged. Fig. 3(a) shows the surface of the printed circuit board 202 opposite to the surface on which the light emitting element group 201 is mounted (hereinafter referred to as the non-mounting surface). Fig. 3(b) shows the surface of the printed circuit board 202 on which the light emitting element group 201 is mounted (hereinafter referred to as the mounting surface).

[0022] The arrow X shown in Fig. 3 is in the direction of the rotation axis of the photosensitive drum, which is the first direction, and is the longitudinal direction of the printed circuit board. The arrow Y is the second direction orthogonal to the first direction, which is the rotation direction of the photosensitive drum, and is the short side direction of the printed circuit board. Also, in the following description, the direction of the rotation axis of the photosensitive drum, which is the first direction, is also referred to as the main scanning direction, and the rotation direction of the photosensitive drum, which is the second direction, is also referred to as the sub-scanning direction.

[0023] The printed circuit board 202 is a board on which components can be mounted on both the non-mounted surface shown in Fig. 3(a) and the mounted surface shown in Fig. 3(b). As shown in Fig. 3(a), on the non-mounted surface of the printed circuit board 202, a driving unit 303a for driving the light-emitting element array chips 1 to 15 and a driving unit 303b for driving the light-emitting element array chips 16 to 29 are arranged on both sides of the connector 305. Signal lines for controlling the driving units 303a and 303b from an image controller unit 415 (not shown), a power supply line, and a ground line are connected to the connector 305 and then connected to the driving units 303a and 303b. Further, the connector 305 is connected to the driving unit 303a on one side in the longitudinal direction by a control signal line 304a and to the driving unit 303b on the other side in the longitudinal direction by a control signal line 304b on the non-mounted surface of the printed circuit board 202. Wiring for driving the light-emitting element array chips passes through the inner layer of the printed circuit board 202 from each of the driving units 303a and 303b and is connected to the light-emitting element array chips 1 to 15 and the light-emitting element array chips 16 to 29, respectively.

[0024] As shown in Fig. 3(b), a light-emitting element group 201 composed of a plurality of light-emitting elements is mounted on the mounted surface of the printed circuit board 202. Here, the light-emitting element group 201 has a configuration in which 29 light-emitting element array chips 1 to 29 are arranged in a staggered manner in the longitudinal direction of the printed circuit board 202. Inside each of the light-emitting element array chips 1 to 29, 516 light-emitting elements (light-emitting points) as a plurality of light-emitting elements are arranged at a resolution pitch which is a predetermined interval in the longitudinal direction (arrow X direction) of the chip. In this example, the pitch of the light-emitting elements adjacent in the longitudinal direction of the chip is a pitch of a resolution of 1200 dpi (about 21.16 μm), and the interval from end to end of the 516 light-emitting elements in the longitudinal direction within the chip is about 10.9 mm. The light-emitting element group 201 is formed by arranging 29 light-emitting element array chips 1 to 29 in the longitudinal direction (rotation axis direction) of the photosensitive drum 102, so that the number of light-emitting elements that can be exposed is 14,964 elements, and image formation corresponding to an image width of about 316 mm in the longitudinal direction becomes possible.

[0025] Here, each of the light-emitting element array chips 1 to 29 is arranged in two rows in a staggered pattern, and each row is arranged along the longitudinal direction (arrow X direction) of the printed circuit board 202. The light-emitting element array chips 1 to 29 are arranged in order in the longitudinal direction (arrow X direction) of the printed circuit board 202. Among the light-emitting element array chips arranged in order in the longitudinal direction, the odd-numbered light-emitting element array chips 1, 3, … 29 form one row, and the even-numbered light-emitting element array chips 2, 4, … 28 form the other row. Also, the light-emitting element array chip 1 and the light-emitting element array chip 2 arranged in order in the longitudinal direction are arranged so as to overlap in the short-side direction (arrow Y direction), and similarly, the light-emitting element array chip 2 and the light-emitting element array chip 3 arranged in order are arranged so as to overlap in the short-side direction. That is, the light-emitting element array chip as the first chip and the light-emitting element array chip 2 as the second chip arranged in order in the longitudinal direction are arranged so as to overlap in the short-side direction (arrow Y direction).

[0026] Fig. 3(c) shows the state of the boundary between adjacent light-emitting element array chips. Here, the boundary between the light-emitting element array chips 28 and 29 is exemplified. Wire bonding pads for inputting control signals are arranged at the ends of the chips, and the transfer section and the light-emitting elements are driven by the signals input from the wire bonding pads. The even-numbered light-emitting element array chip 28 as the first chip and the odd-numbered light-emitting element array chip 29 as the second chip, which are arranged in order in the longitudinal direction, are arranged so as to overlap in the drum rotation direction (the second direction). Even at the boundary between the chips, which is the region where the chips overlap in the drum rotation direction, the longitudinal interval (L in the figure) between the light-emitting elements is a pitch of 1200 dpi resolution (about 21.16 μm). Also, the interval (S in the figure) in the drum rotation direction between the light-emitting elements of the two rows of chips is about 84.64 μm (4 pixels at 1200 dpi, 8 pixels at 2400 dpi). Here, the interval L in the figure is a predetermined interval and is the interval between the centers (light-emitting points) of adjacent light-emitting elements in the drum rotation axis direction. Also, the interval S in the figure is the interval in the drum rotation direction between the center (light-emitting point) of the light-emitting element of the light-emitting element array chip 28 as the first chip and the center (light-emitting point) of the light-emitting element of the light-emitting element array chip 29 as the second chip. Note that the intervals S and L between the light-emitting elements are not limited to the above-described values and should be set as appropriate.

[0027] (Control block) Fig. 4 shows a block diagram of the image controller section 415 and the exposure head 106. In this example, the light-emitting element array chips 1 to 15 and the drive section 303a will be described, but it is assumed that the light-emitting element array chips 16 to 29 and the drive section 303b (not shown) perform the same operations. Also, for simplicity of explanation, monochromatic processing will be described, but it is assumed that the same processing is performed in parallel for four colors simultaneously.

[0028] The image controller unit 415 transmits signals for controlling the exposure head 106 to the exposure head 106. The signals are image data, a line synchronization signal, and a communication signal of the CPU 400, and each signal is input from the connector 416 on the image controller unit 415 side to the connector 305 on the exposure head 106 side via the cables 417, 418, and 419 that transmit the signals.

[0029] The image controller unit 415 includes a CPU 400, an image data generation unit 401, a synchronization signal generation unit 406, a chip data conversion unit 403, a chip data shift unit 404, a data transmission unit 405, and a connector 416. In the image controller unit 415, processing for image data and processing for printing timing are performed.

[0030] In the image data generation unit 401, dithering processing is performed on the image data received from the scanner unit 100 or outside the image forming apparatus at the resolution instructed by the CPU 400, and image data for print output is generated.

[0031] The synchronization signal generation unit 406 generates a periodic signal for one line (hereinafter referred to as a line synchronization signal) in the rotation direction of the photosensitive drum. The CPU 400 sets the period during which the surface of the photosensitive drum 102 moves by the pixel size based on the resolution instructed from the CPU 400 in the rotation direction as one line period with respect to the previously determined rotation speed of the photosensitive drum 102, and instructs the synchronization signal generation unit 406 of the time interval of the signal period. Regarding the speed in the rotation direction of the photosensitive drum, when there is means for detecting the printing speed (for example, speed detection using an encoder installed on the rotation shaft of the photosensitive drum), the CPU 400 calculates using the result detected in real time. On the other hand, when there is no means for detecting the printing speed, the CPU 400 calculates using the set value (fixed value) of the printing speed set in the photosensitive drum speed control means (not shown).

[0032] (Data Conversion) In FIG. 4, the chip data conversion unit 403 reads data one line at a time from the image data generation unit 401 in synchronization with the line synchronization signal and inputs it to the chip data conversion unit 403.

[0033] Here, the chip data conversion unit 403 will be described with reference to FIGS. 5 and 6. FIG. 5 shows a block diagram of the inside of the chip data conversion unit 403 and the blocks before and after the chip data conversion unit 403. FIG. 6 shows a time chart representing the data input / output timing of the chip data conversion unit 403.

[0034] The data read from the image data generation unit 401 is stored in the line memory 500. The output of the line memory 500 is input to the interpolation control unit 541 together with the data delayed by one clock by the delay element 540. The interpolation control unit 541 switches and outputs, according to the instruction of the WR control unit 532, the non-lighting data and lighting data of each memory 501 - 529, the interpolation processing data of the boundary part between the chips described above, and the data without interpolation processing outside the boundary part. Also, the WR control unit 532 instructs the writing valid period of the memories 501 - 529 and stores the output of the interpolation control unit 541 in the memories 501 - 529 corresponding to each light emitting element array chip 1 - 29.

[0035] The synchronization signal generation unit 406 inputs the line synchronization signal to the counter 530. When the line synchronization signal is input, the counter 530 resets the count value to 0 and then increments the count value in synchronization with a clock signal (not shown).

[0036] The counter 530 performs a counting operation with a number (29,928) that is twice the number of pixels per line (14,964) of the image data. Let the period from count value 1 to 14,964 be Tm1, and the period from count value 14,965 to 29,928 be Tm2.

[0037] The READ control unit 531 reads data corresponding to the count value from the full - scale data shift unit and stores the image data for one line (14,964 pixels) in the line memory 500 while the count value counts from 1 to 14,964 (Tm1).

[0038] Also, in the WR control unit 532, while the count value is in the range of 14,965 to 29,928 (Tm2), one-line data is divided and written into each of the memories 501 to 529 from the line memory 500. The one-line data in FIG. 6 refers to the data of the first line in the sub-scanning direction and the data of one line in the main-scanning direction. Also, the two-line data refers to the data of the second line in the sub-scanning direction and the data of one line in the main-scanning direction.

[0039] The memories 501 to 529 are memory areas corresponding to the respective light-emitting element array chips 1 to 29 (FIG. 3(b)) mounted on the printed circuit board 202, and store data obtained by dividing one-line image data for each chip. The memories 501 to 529 are FIFO memories (First In First Out Memories) composed of 29 memory areas, and the data for each of the light-emitting element array chips 1 to 29 (29 chips) are arranged in a predetermined transmission order in each area. In this embodiment, one-line image data is sequentially read from the line memory 500, and first, writing is performed to the memory 501 that stores the image data of the light-emitting element array chip 1. Next, writing is performed to the memory 502 that stores the image data of the light-emitting element array chip 2. Thereafter, writing is continuously performed sequentially up to the memory 529. Note that this corresponds to the data shift in the sub-scanning direction for each chip by the chip data shift unit 404. Therefore, it is assumed that the memory stores a total of 10 lines of image data, which includes two lines for position correction in the sub-scanning direction between pixels within a chip and eight lines for the interval in the sub-scanning direction due to the staggered arrangement between chips.

[0040] By the operation of the chip data conversion unit 403 described above, one-line image data is divided and stored in the memories for each light-emitting element array chip, and the data is drawn out at an appropriate timing by the chip data shift unit 404.

[0041] Returning to FIG. 4 for description. The chip data shift unit 404 controls the data read timing from the memories 501 to 529 based on the image shift information (in units of 2400 dpi) in the sub-scanning direction for each light-emitting element array chip previously instructed by the CPU 400. By controlling the data read timing from the memories 501 to 529, the chip data shift unit 404 performs an image shift (in units of 2400 dpi) in the sub-scanning direction. As described above, the memories 501 to 529 store image data for 10 lines. The chip data shift unit 404 can shift the image data in the leading edge direction of the sheet by advancing the data read timing from the memories 501 to 529. For example, by advancing the read timing by one cycle of the line synchronization signal, the image data for one line is shifted in the leading edge direction of the sheet. In this embodiment, based on the position correction information for each light-emitting element array chip instructed by the CPU 400, image data shifting is performed in units of light-emitting element array chips. Here, the position correction information instructed from the CPU 400 is calculated by adding the interval in the sub-scanning direction (8 pixels at 2400 dpi) due to the staggered arrangement (two columns) and the mounting position deviation of each light-emitting element array chip measured in advance.

[0042] In the subsequent data transmission unit 405, the image data after the above-described series of image data processing is transmitted to the exposure head 106. In the example of the time chart shown in FIG. 6, the memories 501 and 529 corresponding to the odd-numbered light-emitting element array chips 1 and 29 read the data of the first line in the sub-scanning direction during the period TL2 between the line synchronization signals after the period TL1 in which writing to each memory is performed. Also, the memory 502 corresponding to the even-numbered light-emitting element array chip 2 reads the data of the first line from the memory 502 during the period TL10 from the period TL1 in which writing to each memory is performed to nine pulses after the line synchronization signal. As described above, by controlling the read timing of the odd-numbered memories and the even-numbered memories, the printing timing is adjusted corresponding to the interval in the sub-scanning direction (eight pixels at 2400 dpi) of the chips arranged in a staggered pattern (two columns). In this embodiment, the clock frequency is determined so that the count value becomes 29,928 or more (twice the number of image data per line) within the time interval of the line synchronization signal. Thereby, data input to the line memory 500 and data input to each of the memories 501 to 529 are possible during the time between the line synchronization signals. On the other hand, for the reading of data from the memories 501 to 529, since one line of image data is output in parallel from 29 memories within one cycle period of the line synchronization signal, the reading speed may be lower than the writing speed to the memories. In this embodiment, data is read from the memories at a cycle 58 times that of the writing clock to the memories so that the time required for data input to the line memory 500 and data input to each of the memories 501 to 529 is the same as the time for reading one line of image data.

[0043] (Description of SLED Circuit) FIG. 7 is an equivalent circuit in which a part of a self-scanning type light-emitting element array chip is extracted. Ra and Rg are an anode resistor and a gate resistor, respectively, and T n is a shift thyristor, D n is a transfer diode, L n is a light-emitting thyristor. Also, G n is the corresponding shift thyristor T n and the shift thyristor Tn represents the common gate of the light-emitting thyristors connected thereto. Here, n is an integer of 2 or more. Φ1 is the transfer line of the odd-numbered shift thyristors, Φ2 is the transfer line of the even-numbered shift thyristors, and ΦW1 to ΦW4 are the lighting signal lines of the light-emitting thyristors, each with a resistor R W1 ~R W4 is provided. VGK is the gate line, and Φs is the start pulse line. As shown in FIG. 7, for one shift thyristor T n , four light-emitting thyristors L 4n-3 to L 4n are connected, and a configuration is adopted such that four light-emitting thyristors can be lit simultaneously.

[0044] (Explanation of SLED operation) Here, the operation of the circuit shown in FIG. 7 will be described. It is assumed that 5V is applied to the VGK line, and the voltages supplied to Φ1, Φ2, ΦW1 to ΦW4 are also 5V. When the shift thyristor T n is in the on state, the potential of the common gate G n of the light-emitting thyristors connected to the shift thyristor T n and the shift thyristor T n is lowered to about 0.2V. Since the gates G n and G n+1 are connected by the coupling diode D n , a potential difference approximately equal to the diffusion potential of the coupling diode D n is generated. In this embodiment, since the diffusion potential of the coupling diode is about 1.5V, the potential of the gate G n+1 is 1.7V, which is the sum of the diffusion potential of 1.5V and the potential of the gate G n of 0.2V. Similarly, the potential of the gate G n+2 is 3.2V, and the potential of the gate G n+3 is 4.7V. However, after the gate G n+4 , VGK is 5V and cannot exceed this value, so it becomes 5V. Also, regarding the part before the gate G n (the left side in FIG. 7), since the coupling diode is reverse-biased, the voltage of VGK is directly applied and is 5V.

[0045] The gate potential distribution when the shift thyristor T described above n is in the on state is shown in Fig. 8(a). The voltage required for each shift thyristor to turn on (hereinafter referred to as the threshold voltage) is approximately the same as the sum of the diffusion potential and each gate potential. When the shift thyristor T n is on, among the thyristors connected to the same line Φ1, the one with the lowest gate potential is the shift thyristor T n+2 itself. However, the potential of the gate G n+2 of the shift thyristor T n+2 is 3.2V as described above. Therefore, the threshold voltage of the shift thyristor T n+2 is 4.7V. However, since the shift thyristor T n is on, the potential of the line Φ1 is pulled to about 1.5V (diffusion potential). Since it is lower than the threshold voltage of the shift thyristor T n+2 , the shift thyristor T n+2 cannot turn on. All other shift thyristors connected to the same line Φ1 have higher thresholds than the shift thyristor T n+2 , so they cannot turn on either, and only the shift thyristor T n can maintain the on state. Regarding the shift thyristors connected to the line Φ2, the threshold of the shift thyristor T n+1 with the lowest threshold is 3.2V, and the next lowest threshold shift thyristor T n+3 is 6.2V. When 5V is supplied to the line Φ2 in this state, only the shift thyristor T n+1 can transition to the on state. In this state, the shift thyristor T n and the shift thyristor T n+1 are simultaneously on, and the gate potentials of the shift thyristors after (to the right in Fig. 7) the shift thyristor T n+1 are each lowered by the diffusion potential. However, since VGK is 5V and the gate voltage is limited by VGK, the shift thyristor T n+5The right side is 5V. The gate voltage distribution at this time is shown in Fig. 8(b). When the potential of line Φ1 is lowered to 0V in this state, the shift thyristor T n turns off, and the potential of gate G n rises to the VGK potential. The gate voltage distribution at this time is shown in Fig. 8(c). Thus, the transfer of the on state from shift thyristor T n to shift thyristor T n+1 is completed.

[0046] Next, the light emission operation of the light emitting thyristor will be described. When only the shift thyristor T n is on, the gate potentials of the four light emitting thyristors L 4n-3 to L 4n are commonly connected to the gate G n of the shift thyristor T n , so they are the same as the gate G n , which is 0.2V. Therefore, the threshold value of each light emitting thyristor is 1.7V, and it can be lit if a voltage of 1.7V or more is supplied from lines ΦW1 to ΦW4. Therefore, by supplying a lighting signal to lines ΦW1 to ΦW4 when the shift thyristor T n is on, it is possible to selectively emit light from all combinations of the light emitting thyristors L 4n-3 to L 4n . At this time, the potential of the gate G n of the shift thyristor T n+1 next to the shift thyristor T n+1 is 1.7V, and the threshold values of the four light emitting thyristors L n+1 commonly gate-connected to the gate G 4n+1 to L 4n+4 become 3.2V. Since the lighting signal supplied from lines ΦW1 to ΦW4 is 5V, the light emitting thyristors L 4n-3 to L 4n are likely to emit light in the same lighting pattern as the lighting pattern of the light emitting thyristors L 4n+1 to L 4n+4 . However, since the threshold values of the light emitting thyristors L 4n-3 to L 4n are lower, when a lighting signal is supplied, the light emitting thyristors L 4n+1 to L4n+4 turns on earlier. Once the light-emitting thyristor L 4n-3 from L 4n turns on, the connected lines ΦW1 to ΦW4 are pulled to about 1.5 V (diffusion potential), and the light-emitting thyristor L 4n+1 from L 4n+4 becomes lower than the threshold value. Therefore, the light-emitting thyristor L 4n+1 from L 4n+4 cannot turn on. By connecting a plurality of light-emitting thyristors to one shift thyristor in this way, a plurality of light-emitting thyristors can be turned on simultaneously.

[0047] (Explanation of the driving signal waveform of the SLED) Fig. 9 shows an example of the driving signal waveform. 5 V is always supplied to VGK. The clock signal Φ1 for the odd-numbered shift thyristors and the clock signal Φ2 for the even-numbered shift thyristors are applied at the same period Tc, and the start signal Φs is supplied with 5 V. However, it is dropped to 0 V to create a potential difference in the gate line shortly before Φ1 first becomes 5 V. As a result, the gate of the first shift thyristor is pulled from 5 V to 1.7 V, and the threshold value becomes 3.2 V, enabling it to be turned on by the signal from Φ1. After Φ1 is applied with 5 V and the first shift thyristor transitions to the on state, 5 V is supplied to Φs with a slight delay, and thereafter, 5 V continues to be supplied to Φs. Φ1 and Φ2 have an overlapping time Tov in their on states (here 5 V) and are configured to be in a substantially complementary relationship. The signals ΦW1 to ΦW4 for turning on the light-emitting thyristors are transmitted at a period that is half the period of Φ1 and Φ2, and the corresponding light-emitting thyristors light up when 5 V is applied while they are in the on state. For example, at time a, all four light-emitting thyristors connected to the same shift thyristor are lit, and at time b, three light-emitting thyristors are lit simultaneously. Also, at time c, all the light-emitting thyristors are in the off state, and at time d, two light-emitting thyristors are lit simultaneously. At time e, only one light-emitting thyristor is lit.

[0048] In this embodiment, the number of light-emitting thyristors connected to one shift thyristor is four, but this is not restrictive, and it may be less than or more than four depending on the application. In the circuit shown in FIG. 7, the circuit with the common cathodes of the thyristors has been described, but the anode common circuit can also be applied by appropriately inverting the polarity.

[0049] (Interpolation control) The operation of the interpolation control unit 541 in FIG. 5 will be described in detail below. FIG. 10 shows the timing of the processing of the interpolation control unit 541. Image data is read from the head of one line in the line memory 500 in order and input. The delay element 540 outputs data obtained by delaying the read data from the line memory 500 by one clock. In FIG. 10, memories N to N + 2 refer to any three adjacent memories among the memories 501 to 529. Also, the number of data in the memories is simplified to 16 for ease of viewing the figure. The selector signal for memories N to N + 2 is a signal output by the WR control unit 532 in accordance with an instruction from the CPU 400. 0 is white data, 1 selects the output of the delay element 540, and 2 is a signal that selects the output of the interpolation operation result between the read data from the line memory 500 and the output of the delay element 540. The number of white data at the appropriate boundary of the light-emitting element array chip and the position of the interpolated pixels are measured in advance at the time of factory shipment, and the CPU 400 reflects them in the image data sent to the light-emitting element array chip via the selector signal for memories N to N + 2.

[0050] In FIG. 10, two white data are arranged at both ends of memories N to N + 2, and interpolation data is arranged at the head (C0) of the image data of memories N to N + 2, but interpolation data can be arranged (output) on the rear end side (for example, P11) of the image data.

[0051] The write signal for memories N to N + 2 is a signal output by the WR control unit 532 in accordance with an instruction from the CPU 400, and is a signal for timing to write the signal output by the interpolation control unit 541 to each memory to memories N to N + 2. In this embodiment, a timing is generated in which the front and rear ends of the write signals of adjacent memories among memories N to N + 2 overlap.

[0052] Here, the correction of the image data by the image controller unit 415 of this embodiment will be described while using a comparative example.

[0053] The image controller unit 415 is a controller that transmits a signal for controlling the exposure head 106 to the exposure head 106. The image controller unit 415 transmits a data signal obtained by dividing the image data for each chip to the exposure head 106 and controls the exposure head 106.

[0054] Note that the image data is the image data stored in the line memories 501 to 529 of the chip data conversion unit 403 after being generated in the image data generation unit 401 described above. Also, the data signal obtained by dividing the image data for each chip is the data stored in the memories 501 to 529, which are memory areas corresponding to the respective light-emitting element array chips 1 to 29 mounted on the printed circuit board 202.

[0055] When mounting the plurality of light-emitting element array chips 1 to 29 on the printed circuit board 202, a shift may occur in the mounting positions of the respective light-emitting element array chips. Then, the interval between the light-emitting elements of the adjacent light-emitting element array chips in the longitudinal direction of the printed circuit board 202 does not necessarily become a predetermined interval (L in FIG. 3(c)). In this case, at the boundary between the adjacent light-emitting element array chips, the gaps between the pixels are arranged in the rotation direction of the photosensitive drum and appear as white streaks, or the overlapping of the pixels is arranged in the rotation direction of the photosensitive drum and appears as black streaks, and a streak phenomenon occurs.

[0056] Therefore, when the interval between the light-emitting elements of the chips is not the predetermined interval in the region where the adjacent light-emitting element array chips (first chip) and the light-emitting element array chip (second chip) overlap in the drum rotation direction, the image controller unit 415 corrects the image data. Here, the interval between the light-emitting element of the first chip and the light-emitting element of the second chip is calculated from the shift in the mounting position in the drum rotation axis direction of each light-emitting element array chip measured in advance.

[0057] Here, using a line screen image (see FIG. 11(c)) which is a pattern where streak phenomena are likely to be prominent, first, FIGS. 11 and 12 are used to explain a comparative example, and then FIGS. 13 and 14 are used to explain this embodiment.

[0058] FIG. 11(a) is a diagram showing a line screen image in which there is a gap between pixels at the boundary between light-emitting element array chips. FIG. 11(b) is a diagram showing a line screen image in which there is an overlap between pixels at the boundary between light-emitting element array chips. FIG. 11(c) is a diagram showing a line screen image. FIG. 12(a) is a diagram showing a comparative example in which the line screen image shown in FIG. 11(a) is corrected. FIG. 12(b) is a diagram showing a comparative example in which the line screen image shown in FIG. 11(b) is corrected. FIG. 12(c) is a diagram showing the shape of the line screen image of the comparative example shown in FIG. 12(a). FIG. 12(d) is a diagram showing the shape of the line screen image of the comparative example shown in FIG. 12(b).

[0059] For example, the case where the distance between pixel fl and pixel fr at the boundary between light-emitting element array chips is 1.5 pixels as shown in FIG. 11(a) and the case where it is 0.5 pixels as shown in FIG. 11(b) will be described. In FIGS. 11(a) and 11(b), 1 square represents 1 pixel, and the gap d between pixels and the overlap d between pixels are 0.5 pixels. Also, the black pixels, the white pixels, and the overlap of the black pixels are shown in different colors. Also, the pixel on one side (the right pixel) at the boundary is represented by fr, and the pixel on the other side (the left pixel) is represented by fl. In FIG. 11(a), the gap d between pixel fl and pixel fr at the boundary between light-emitting element array chips is arranged in the rotation direction of the photosensitive drum, and white streaks are generated. In FIG. 11(b), the overlap d between pixel fl and pixel fr at the boundary between light-emitting element array chips is arranged in the rotation direction of the photosensitive drum, and black streaks are generated.

[0060] In order to suppress such a density change at the boundary between light-emitting element array chips, the pixel values at the boundary between light-emitting element array chips are corrected in proportion to the increased or decreased area. The images of the comparative examples are shown in FIGS. 12(a) and 12(b).

[0061] In the image shown in FIG. 11(a), the area of the gap d (equivalent to 0.5 pixel) between pixel fl and pixel fr at the boundary has increased. Therefore, in the comparative example, as shown in FIG. 12(a), at the position corresponding to the gap d, the light-emitting element located in the gap exposes 50% concentration in proportion to the increased area. However, as shown in FIG. 12(c), the shape of the line screen image of the comparative example shown in FIG. 12(a) is distorted at the portion corresponding to the gap between the pixels like the shape formed by the line ff connecting the centers of the pixels, and it looks like a streak.

[0062] On the other hand, in the image shown in FIG. 11(b), the area of the overlapping portion d (equivalent to 0.5 pixel) between pixel fl and pixel fr at the boundary has decreased. Therefore, in the comparative example, as shown in FIG. 12(b), at the position corresponding to the overlapping portion d, the concentration is reduced to 50% in proportion to the decreased area by one of the light-emitting elements overlapping in the rotation direction of the photosensitive drum for exposure. However, as shown in FIG. 12(d), the shape of the line screen image of the comparative example shown in FIG. 12(b) is also distorted at the portion corresponding to the overlap of the pixels like the shape formed by the line ff connecting the centers of the image, and it looks like a streak.

[0063] That is, even if the concentration is adjusted according to the area corresponding to the gap between the pixels or the overlapping area between the pixels at the boundary between the chips as in the comparative example, there is a possibility that the shape of the image is distorted at the portion corresponding to the gap between the pixels or the overlap of the pixels and it looks like a streak.

[0064] Therefore, in this embodiment, in order to suppress the change in the shape of the image at the boundary between the light-emitting element array chips, the image data is corrected as follows. In the following description, the even-numbered light-emitting element array chip 28 is exemplified as the first chip, and the odd-numbered light-emitting element array chip 29 is exemplified as the second chip (see FIGS. 3(b) and (c)). Hereinafter, the even-numbered light-emitting element array chip 28 is also referred to as the first chip, and the odd-numbered light-emitting element array chip 29 is also referred to as the second chip.

[0065] When the distance in the X-arrow direction between the light-emitting elements of the first chip 28 and the light-emitting elements of the second chip 29 exceeds a predetermined distance L in the region where the first chip 28 and the second chip 29 overlap in the Y-arrow direction, the image controller unit 415 corrects as follows.

[0066] Here, as shown in FIG. 3(c), the light-emitting element of the first chip 28 having a distance exceeding the predetermined distance L is defined as the first light-emitting element 28a. Also, the light-emitting element of the second chip 29 having a distance exceeding the predetermined distance L is defined as the second light-emitting element 29a. Further, the light-emitting element located between the first light-emitting element 28a and the second light-emitting element 29a having a distance exceeding the predetermined distance L is defined as the intermediate light-emitting element 28b (or 29b). Note that when the predetermined pixel interval is set to 1, in the case of a distance exceeding the predetermined distance L, the pixel interval at the boundary portion exceeds 1.

[0067] The image controller unit 415 corrects the density for the intermediate light-emitting element forming the image data using the density for the first light-emitting element forming the image data and the density for the second light-emitting element forming the image data.

[0068] Furthermore, the image controller unit 415 further corrects the density for the intermediate light-emitting element forming the image data using the increased area of the pixels having a distance exceeding the predetermined distance L.

[0069] Then, the corrected density is set to the data signal divided for the chip on which the intermediate light-emitting element is arranged. That is, the corrected data signal is stored in the memory for the chip on which the intermediate light-emitting element is arranged.

[0070] Specifically, for the case where the pixel interval at the boundary portion exceeds 1, the calculation method is shown using the image shown in FIG. 11(a) as an example. Let the pixel interval at the boundary portion (1 + d) = 1.5 pixels. Therefore, the distance of the gap between the pixel fl and the pixel fr is d = 0.5 pixels. Also, assuming black is 1 and white is 0, the density Pc of the pixel of the gap of interest is expressed by the following equation 1 as the density Pr of the right pixel fr and the density Pl of the left pixel fl.

[0071] Pc = (Pr + Pl) / 2 ··· (Equation 1)

[0072] The result calculated by the above Equation 1 is shown in FIG. 13(a). In FIG. 13(a), for the pixel of the gap of interest fc, through the pixel fc of the gap, the pixel on one side (the right pixel) is represented by fr, and the pixel on the other side (the left pixel) is represented by fl. Also, the pixel fc is exposed by the intermediate light-emitting element 28b (or 29b), the right pixel fr is exposed by the second light-emitting element 29a, and the left pixel fl is exposed by the first light-emitting element 28a.

[0073] Furthermore, the concentration Pc of the pixel of the gap considering the area ratio is represented by the following Equation 2.

[0074] Pc = d×(Pr + Pl) / 2 ··· (Equation 2)

[0075] The result calculated by the above Equation 2 is shown in FIG. 13(b).

[0076] When the result shown in FIG. 13(b) is set in the memory for each chip and the pixel fc is exposed by the intermediate light-emitting element 28b, the right pixel fr is exposed by the second light-emitting element 29a, and the left pixel fl is exposed by the first light-emitting element 28a, the concentration of the pixel fc of the gap is exposed by the intermediate light-emitting element 28b within the thick frame shown in FIG. 13(c). The exposed result is shown in FIG. 13(d).

[0077] Compared with FIG. 12(a) of the comparative example where exposure is performed only with the concentration increased in proportion to the area, it can be seen that the shape of the line screen image is improved by considering the concentration of the interpolated pixel and the concentrations of the pixels on both sides thereof.

[0078] Alternatively, when the interval in the arrow X direction between the light-emitting element of the first chip 28 and the light-emitting element of the second chip 29 is less than a predetermined interval in the region where the first chip 28 and the second chip 29 overlap in the arrow Y direction, the image controller unit 415 corrects as follows.

[0079] Here, as shown in FIG. 3(c), the light-emitting element of the first chip 28 having an interval less than the predetermined interval L is defined as the first light-emitting element 28a. Further, the light-emitting element of the second chip 29 having an interval less than the predetermined interval L is defined as the second light-emitting element 29b.

[0080] The image controller unit 415 corrects the density for the first light-emitting element forming the image data using the density for the second light-emitting element forming the image data.

[0081] Furthermore, the image controller unit 415 further corrects the density for the first light-emitting element forming the image data using the reduction amount of the area of the pixel having an interval less than the predetermined interval L.

[0082] Then, the corrected density is set to the data signal divided for the chip on which the first light-emitting element is arranged. That is, the corrected data signal is stored in the memory for the chip on which the first light-emitting element is arranged.

[0083] Also, the image controller unit 415 corrects the density for the second light-emitting element forming the image data using the density for the first light-emitting element forming the image data.

[0084] Furthermore, the image controller unit 415 further corrects the density for the first light-emitting element forming the image data using the reduction amount of the area of the pixel having an interval less than the predetermined interval L.

[0085] Then, the corrected density is set to the data signal divided for the chip on which the second light-emitting element is arranged. That is, the corrected data signal is stored in the memory for the chip on which the second light-emitting element is arranged.

[0086] Specifically, the calculation method is shown for the case where the pixel interval at the boundary is less than 1. The overlapping amount between the pixel fl and the pixel fr at the boundary is set to d = 0.5 pixels. Therefore, the pixel interval (1 - d) at the boundary is 0.5 pixels. When the pixel interval at the boundary is less than 1, the densities of the pixels on both sides of the boundary are newly calculated.

[0087] Fig. 14(a) shows an image formed with no overlap between pixel fl and pixel fr at the boundary and with a predetermined pixel interval. In Fig. 14(a), each cell is regarded as a pixel, with the predetermined pixel interval being 1, and the center of each pixel column is indicated by a dotted line. Fig. 14(b) shows an image when there is an overlap between pixel fl and pixel fr at the boundary and the pixel interval becomes (1 - d). Fig. 14(b) shows that the pixel columns at the center (boundary) represented by a grid overlap, and the pixel interval between the overlapping pixel columns and the pixel columns outside them is the predetermined pixel interval 1. In Fig. 14(b), if the pixel intervals are evenly arranged including the pixel column at the boundary and the pixel columns outside it, dividing the overall pixel interval (1 + 1 + (1 - d)) = (3 - d) by 3, the ideal pixel interval is (1 - d / 3). This ideal pixel interval is indicated by a dashed-dotted line in Fig. 14(c). Let Pr be the density of one side pixel fr (the right pixel) and Pl be the density of the other side pixel fl (the left pixel) among the pixels overlapping at the boundary. And assuming that the values of the overlapping pixels fr and fl at the boundary are assigned to the position of the dashed-dotted line, the densities (pixel values) Pr' and Pl' of the pixels of the new boundary are represented by the following equations 3 and 4 respectively.

[0088] Pl' = {(1 - 2d / 3)Pl + (d / 3)Pr} / (1 - d / 3) ···(Equation 3)

[0089] Pr' = {(d / 3)Pl + (1 - 2d / 3)Pr} / (1 - d / 3) ···(Equation 4)

[0090] Also, since the area of the pixels overlapping at the boundary has decreased from 2 to 2 - d, the densities (pixel values) Pr" and Pl" of each pixel fl and fr corrected for this decreased amount are represented by the following equations 5 and 6 respectively.

[0091] Pl" = ((2 - d) / 2)Pl' ···(Equation 5)

[0092] Pr" = ((2 - d) / 2)Pr' ···(Equation 6)

[0093] The result calculated by the above formula is set in the memory for each chip, and the result of exposing the right pixel fr, which is a pixel on both sides of the boundary, to the first light-emitting element 29b and the left pixel fl to the second light-emitting element 28a is shown in Fig. 14(c).

[0094] Compared with Fig. 12(b) of the comparative example in which exposure was performed only with the density reduced in proportion to the area, it can be seen that the shape of the line screen image is improved by the amount by which the density of each pixel on both sides of the boundary is corrected in consideration of the densities of each other.

[0095] According to this embodiment, by correcting the density of the pixel targeted at the boundary between the first chip and the second chip using the density of the pixel adjacent to that pixel, it is possible to provide an image forming apparatus in which the pattern shape such as a screen does not collapse with a simple calculation and streaks between a plurality of chips are not easily visible. That is, it is possible to suppress the change in the shape of the image at the boundary between the light-emitting element array chips and to suppress the occurrence of the streak phenomenon.

[0096] [Embodiment 2] Embodiment 2 is different from Embodiment 1 in that the exposure head has a light-emitting element array chip shown in Fig. 15 and one pixel is formed by a plurality of light-emitting elements. Fig. 15 shows four light-emitting element array chips 26 to 29, which are part of the plurality of light-emitting element array chips included in the exposure head.

[0097] In FIG. 15, the light-emitting element array chips 26 to 29 arranged in order in the longitudinal direction (arrow X direction) of the printed circuit board are arranged so as to overlap at their ends in the short side direction (arrow Y direction) of the printed circuit board. Further, each of the light-emitting element array chips 26 to 29 includes a plurality of columns of light-emitting elements arranged at a constant element interval R in the main scanning direction, and a plurality of these columns are arranged in the sub-scanning direction. Here, one light-emitting element array chip has four columns of light-emitting elements arranged at a predetermined interval R in the main scanning direction arranged in the sub-scanning direction. Also, each of the light-emitting element array chips 26 to 29 arranges the columns with an offset of a constant distance R / 4 in the main scanning direction. The image controller unit transfers data that has been delay-adjusted in the sub-scanning direction so that the light-emitting element columns expose the same one line, to each light-emitting element column. Since the light-emitting element columns of each light-emitting element array chip in the exposure head of this embodiment have an offset of a distance R / 4, exposure can be performed at a resolution four times the element interval R of each light-emitting element column. In this embodiment, the resolution of the light-emitting elements is higher than the input data resolution, and one pixel is formed by two light-emitting elements.

[0098] FIGS. 16(a) and 16(b) show the state of multiple exposure of the four columns of light-emitting element columns shown in FIG. 15. One grid corresponds to the exposure of one light-emitting element, and one pixel is formed by two light-emitting elements and is shown by a thick frame. Also, in the main scanning direction (arrow X direction), the overlapping region (joint portion) in the arrow Y direction between two light-emitting element array chips is shown. Also, the lit elements and the unlit elements are shown in different colors. In FIGS. 16(a) and 16(b), the light-emitting element array chips are shifted in the sub-scanning direction, but it is assumed that the same one line is exposed by data delay adjustment in the sub-scanning direction. In FIG. 16(a), at the ends of one light-emitting element column and the other light-emitting element column in the main scanning direction, one element and two elements are made unlit respectively, and the gap between the chips is adjusted to be minimized (less than one pixel). Also, in FIG. 16(b), at the ends of one light-emitting element column and the other light-emitting element column in the main scanning direction, one element and three elements are made unlit respectively, and the gap between the chips is adjusted to be minimized (less than one pixel).

[0099] Alternatively, in FIG. 16(b), at the ends of one light-emitting element row and the other light-emitting element row in the main scanning direction, one element and one element may be turned off respectively, and an adjustment may be made to overlap the pixels between the chips to the minimum (less than one pixel). Similarly, in FIG. 16(b), at the ends of one light-emitting element row and the other light-emitting element row in the main scanning direction, one element and two elements may be turned off respectively, and an adjustment may be made to overlap the pixels between the chips to the minimum (less than one pixel).

[0100] By applying the correction of the image data described in the first embodiment to an image forming apparatus including an exposure head of a multiple exposure method in which one pixel is formed by a plurality of light-emitting elements in this way, the resolution is increased and the change in the shape of the image can be more suppressed.

[0101] In this embodiment, in the joint correction, a portion that cannot be fully corrected at the resolution of the light-emitting elements is further corrected. This will be described with reference to FIGS. 17(a) to 17(d). In FIG. 17(a), one grid corresponds to one exposure by one light-emitting element, and one pixel is formed by an exposure of 2 grids × 2 grids in the main scanning direction and the sub-scanning direction. The image shown in FIG. 17(a) shows a line screen image. In FIG. 17(b), the center in the main scanning direction indicates the boundary between the light-emitting element array chips, and shows a state where a gap that cannot be fully corrected in units of the light-emitting elements remains. The interval of the gaps at the boundary shown in FIG. 17(b) is R / 8, and the interval of the grids is R / 4. Also, in FIG. 17(b), when the density of the black part is 1 and the density of the white part is 0, the calculation result according to the above formula 1 is entered.

[0102] Also, the value corresponding to d in the above formula 2 for correcting the area ratio is calculated as (R / 8) / (R / 4) = 0.5, and the result of applying this is shown in FIG. 17(c). Also, in this embodiment, as shown in FIG. 17(d), the pixels at the boundary are exposed by the adjacent light-emitting elements at a predetermined interval within the chip in which the light-emitting elements for exposing the pixels are arranged.

[0103] According to this embodiment, even when exposure is performed at an exposure resolution higher than the input resolution, the density (exposure amount) of the joint can be corrected with higher precision. That is, the change in the shape of the image at the boundary between the light-emitting element array chips can be more suppressed, and the occurrence of streak phenomenon can be more suppressed.

[0104] 〔Other embodiments〕 In the above-described Example 1, as shown in FIG. 13(c), in order to expose the pixel fc in the gap between the pixel fl and the pixel fr at the boundary, the image controller unit 415 has been exemplified as a configuration in which exposure is performed only by the intermediate light-emitting element 28b on one side, but it is not limited thereto. The image controller unit 415 may use, as the intermediate light-emitting element, a light-emitting element closer to the light-emitting element having a higher density among the density for the first light-emitting element and the density for the second light-emitting element that form the image data. That is, as the intermediate light-emitting element, a light-emitting element closer to the light-emitting pixel having a higher density among the density Pl of the pixel fl for the first light-emitting element 28a and the density Pr of the pixel fr for the second light-emitting element 29a may be used. Specifically, the density 0.25 of the pixel fc in the second row of FIG. 18(a) is exposed by the intermediate light-emitting element 29b, which is a light-emitting element closer to the first light-emitting element 28a having a higher density. The density 0.5 of the pixel fc in the third row of FIG. 18(a) is exposed by the intermediate light-emitting element 28b, which is a light-emitting element closer to the second light-emitting element 29a having a higher density. Hereinafter, the light-emitting element having a higher density and the intermediate light-emitting element are used in the same manner. The result of exposure with the intermediate light-emitting element selected in this way is shown in FIG. 18(b). By selecting the intermediate light-emitting element in this way, as shown in FIG. 18(b), the change in the shape of the image at the boundary between the light-emitting element array chips can be more suppressed.

[0105] In the above-described Example 1, when the pixel pitch of the boundary portion exceeds a predetermined interval, the image controller unit 415 corrects the density for the intermediate light-emitting elements forming the image data by using the density for the first light-emitting elements forming the image data and the density for the second light-emitting elements forming the image data. However, the present invention is not limited to this. For example, the density for the intermediate light-emitting elements may simply copy the density of adjacent pixels, and form this pixel and the pixel overlapping therewith. That is, overlapping between pixels may be formed at the boundary, and correction may be performed when the pixel pitch of the boundary portion is less than a predetermined interval. Even in this case, the same effects as those of the above-described Example 1 can be obtained.

[0106] In the above-described example, an LED is used as the light-emitting element, but other light-emitting elements such as an organic EL may be used.

Explanation of Signs

[0107] Pc, Pl, Pr … Density fc, fl, fr … Pixel 1~29 … Light-emitting element array chip 28a, 28b, 29a, 29b … Light-emitting element 102 … Photosensitive drum 106 … Exposure head 202 … Printed circuit board 305 … Connector 400 … CPU 401 … Image data generation unit 403 … Chip data conversion unit 404 … Chip data shift unit 405 … Data transmission unit 406 … Synchronization signal generation unit 415 … Image controller unit 416 … Connector 417, 418, 419 … Cable 500 … Line memory 501~529 … Memory 530 … Counter 531 … READ control unit 532 … WR control unit 540... Delay element 541... Interpolation control unit

Claims

1. A photoreceptor, a first chip in which a plurality of light-emitting elements are arranged at a predetermined interval in a first direction, and a second chip in which a plurality of light-emitting elements are arranged at the predetermined interval in the first direction are arranged in the first direction in order, and A substrate is provided in which the first chip and the second chip are arranged so as to overlap in a second direction orthogonal to the first direction, and an exposure head that emits light from the light-emitting elements of each chip according to image data to expose the photoreceptor; a controller that transmits a signal for controlling the exposure head, the signal including a data signal obtained by dividing the image data for each chip; having, when the interval in the first direction between the light-emitting elements of the first chip and the light-emitting elements of the second chip in a region where the first chip and the second chip overlap in the second direction is less than the predetermined interval, the controller when the light-emitting elements of the first chip forming an interval less than the predetermined interval are defined as first light-emitting elements and the light-emitting elements of the second chip forming an interval less than the predetermined interval are defined as second light-emitting elements, corrects the density for the first light-emitting elements forming the image data using the density for the second light-emitting elements forming the image data, corrects the density for the second light-emitting elements forming the image data using the density for the first light-emitting elements forming the image data, further, the controller further corrects the density for the first light-emitting elements forming the image data using the reduced area of the pixels forming an interval less than the predetermined interval, and sets the corrected density in the data signal divided for the chip on which the first light-emitting elements are arranged, and further corrects the density for the second light-emitting elements forming the image data using the reduced area of the pixels forming an interval less than the predetermined interval, and sets the corrected density in the data signal divided for the chip on which the second light-emitting elements are arranged, An image forming apparatus characterized by the above.

2. A photoreceptor, a first chip in which a plurality of light-emitting elements are arranged at a predetermined interval in a first direction, and a second chip in which a plurality of light-emitting elements are arranged at the predetermined interval in the first direction are arranged in the first direction in order, and A substrate is provided in which the first chip and the second chip are arranged so as to overlap in a second direction orthogonal to the first direction, and an exposure head that emits light from the light-emitting elements of each chip according to image data to expose the photoreceptor; A controller that transmits a signal for controlling the exposure head, the signal including data signals obtained by dividing image data for each chip, to the exposure head; having; when, in a region where the first chip and the second chip overlap in the second direction, the interval in the first direction between the light-emitting elements of the first chip and the light-emitting elements of the second chip exceeds the predetermined interval, when the light-emitting element of the first chip having an interval exceeding the predetermined interval is defined as a first light-emitting element, the light-emitting element of the second chip having an interval exceeding the predetermined interval is defined as a second light-emitting element, and the light-emitting element located between the first light-emitting element and the second light-emitting element having an interval exceeding the predetermined interval is defined as an intermediate light-emitting element, correct the density for the intermediate light-emitting element forming the image data using the density for the first light-emitting element forming the image data and the density for the second light-emitting element forming the image data, and set the corrected density in the data signal divided for the chip on which the intermediate light-emitting element is arranged; An image forming apparatus characterized by the above.

3. when, in a region where the first chip and the second chip overlap in the second direction, the interval in the first direction between the light-emitting elements of the first chip and the light-emitting elements of the second chip exceeds the predetermined interval, further correct the density for the intermediate light-emitting element forming the image data using the increased area of the pixels having an interval exceeding the predetermined interval, and set the corrected density in the data signal divided for the chip on which the intermediate light-emitting element is arranged; The image forming apparatus according to claim 2, characterized by the above.

4. The controller defines the light-emitting element closer to the light-emitting element with the higher density among the density for the first light-emitting element and the density for the second light-emitting element forming the image data as the intermediate light-emitting element; The image forming apparatus according to claim 2, characterized by the above.

5. The first chip and the second chip each include a plurality of columns of the light-emitting elements arranged at the predetermined interval in the first direction, and a plurality of the columns are arranged in the second direction, and the columns are offset from each other by a certain distance in the first direction; The controller forms one pixel with a plurality of light-emitting elements; The image forming apparatus according to claim 2, characterized by the above.

Images