Redetection device, conveying device, and image reading device

Abstract

To provide a multi-feeding detection device, a conveyance apparatus, and an image reading apparatus which can increase a driving speed of a push-pull circuit outputting a driving signal to a transmission element.SOLUTION: A drive circuit outputs a driving signal to a transmission element. The drive circuit has a push-pull circuit. The push-pull circuit outputs the driving signal in which the current is amplified. The push-pull circuit includes a first N-type MOSFET and a second N-type MOSFET and is the circuit in which a source terminal of the first N-type MOSFET is connected to a drain terminal of the second N-type MOSFET. The drive circuit is the circuit in which a conversion signal in which the voltage level is inverted in comparison to a reference signal is input to a gate terminal of the first N-type MOSFET and the reference signal is input to a gate terminal of the second N-type MOSFET. The second adjustment circuit makes timing of the fall of the conversion signal input to the gate terminal of the first N-type MOSFET earlier.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a retransmission detection device, a conveyance device, and an image reading device configured to detect retransmission of a medium.

Background Art

[0002] For example, Patent Document 1 discloses an image reading device capable of reading an image of a medium, which includes a sound wave sensor composed of a transmission element and a reception element, and a drive circuit for driving the sound wave sensor. Such an image reading device can detect, for example, retransmission of a medium by the sound wave sensor. The drive circuit for driving the sound wave sensor includes a push-pull circuit using an N-type MOSFET and a P-type MOSFET to amplify current.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in such a device, among the N-type MOSFET and the P-type MOSFET used in the drive circuit, the P-type MOSFET tends to have a slower drive speed than the N-type MOSFET. For this reason, the drive speed of the push-pull circuit using the N-type MOSFET and the P-type MOSFET is slow, and it is desired to increase the drive speed of the push-pull circuit.

Means for Solving the Problems

[0005] The double-feed detection device for solving the above problems includes a transmission element capable of transmitting a signal for detecting double-feed of a medium, a reception element capable of receiving a signal for detecting double-feed of the medium, a drive circuit configured to output a drive signal to the transmission element, and a control circuit configured to detect double-feed of the medium based on the signal received by the reception element. The drive circuit includes a conversion circuit that converts a reference signal into a conversion signal, a booster circuit that boosts the conversion signal converted by the conversion circuit, a first adjustment circuit that adjusts the rise time of the conversion signal boosted by the booster circuit to be long, a push-pull circuit that outputs a drive signal obtained by amplifying the current of the conversion signal adjusted by the first adjustment circuit, and a second adjustment circuit that adjusts the conversion signal input to the push-pull circuit. The conversion signal converted by the conversion circuit is a signal whose voltage level is inverted compared to the reference signal. The push-pull circuit includes a first N-type MOSFET and a second N-type MOSFET, and is a circuit in which the source terminal of the first N-type MOSFET is connected to the drain terminal of the second N-type MOSFET. The drive circuit is a circuit in which the conversion signal adjusted by the first adjustment circuit is input to the gate terminal of the first N-type MOSFET, while the reference signal is input to the gate terminal of the second N-type MOSFET. The second adjustment circuit advances the timing of the fall of the conversion signal input to the gate terminal of the first N-type MOSFET.

[0006] The conveying device for solving the above problems includes the above double-feed detection device and a conveying unit configured to convey a medium. The image reading device for solving the above problems includes the above double-feed detection device and a reading unit configured to read an image of a medium.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0008] [First Embodiment] Hereinafter, an embodiment of an image reading apparatus as an example of a retransmission detection apparatus and a conveyance apparatus will be described. The image reading apparatus is an apparatus that reads an image from a medium.

[0009] [Configuration of Image Reading Apparatus] As shown in FIG. 1, the image reading apparatus 11 includes a main body 12. The main body 12 may have a substantially trapezoidal shape in side view. The main body 12 includes a feeding port 12A that opens at the upper part. The main body 12 includes a discharge port 12B that opens at the lower front side.

[0010] The image reading apparatus 11 may include a medium support 13. The medium support 13 can support the medium M. The medium M placed on the medium support 13 is the medium before image reading. The image reading apparatus 11 feeds the medium M placed on the medium support 13 from the feeding port 12A into the main body 12.

[0011] The main body 12 includes a main body portion 14 and a cover portion 15. The cover portion 15 may be connected so as to be rotatable about the front end portion of the main body portion 14. The main body portion 14 includes a stacker 16. The stacker 16 is provided below the discharge port 12B. The stacker 16 is slidable in the front-rear direction. The stacker 16 can place the medium M discharged from the discharge port 12B. The medium M discharged from the discharge port 12B is the medium after the image has been read. Thus, the image reading device 11 discharges the medium M on which the image has been read from the discharge port 12B to the stacker 16.

[0012] In the figure, the direction in which the medium M is conveyed is indicated as the conveyance direction Y, and the direction orthogonal to the conveyance direction Y is indicated as the width direction X. Also, the width direction X is the main scanning direction when the image reading device 11 reads the image of the medium M, and the conveyance direction Y is the sub-scanning direction.

[0013] The main body 12 includes an operation unit 17. The operation unit 17 is provided on the front surface of the cover portion 15. The operation unit 17 includes a plurality of switches operable by the user. The plurality of switches includes a power switch 17A, a start switch 17B, and a stop switch 17C.

[0014] The main body 12 includes a notification unit 18. The notification unit 18 is provided at a position adjacent to the operation unit 17. The notification unit 18 may be an indicator light such as an LED, or may be a display device such as a liquid crystal panel. The notification unit 18 notifies the user of necessary information such as the on / off of the power supply.

[0015] <Conveying path> As shown in FIG. 2, the image reading device 11 includes a conveying path 19. The conveying path 19 is provided inside the main body 12. The conveying path 19 is a path for conveying the medium M. The conveying path 19 includes a reading area SA. The reading area SA is an area for reading an image from the medium M.

[0016] The image reading device 11 includes a transport mechanism 20. The transport mechanism 20 is provided inside the main body 12. The transport mechanism 20 transports the medium M along the transport path 19. The transport mechanism 20 transports the medium M so as to pass through the reading area SA.

[0017] The transport mechanism 20 includes a feeding unit 21. The feeding unit 21 feeds a plurality of media M placed on the media support 13 one by one into the main body 12. The feeding unit 21 includes a feeding guide 22. The feeding guide 22 guides the medium M fed from the media support 13 into the main body 12. The feeding unit 21 includes one feeding roller 23. The feeding roller 23 is provided at the upstream end of the transport path 19 in the main body 12. The feeding roller 23 is a pickup roller facing the feeding guide 22. The feeding unit 21 feeds a plurality of media M stacked on the media support 13 one by one from the feeding port 12A along the feeding guide 22.

[0018] The transport mechanism 20 includes a transport unit 24. The transport unit 24 is configured to transport the medium M fed by the feeding unit 21 along the transport path 19. The transport unit 24 includes a pair of feeding rollers 25. The pair of feeding rollers 25 is provided downstream of the feeding roller 23 in the transport direction Y. The pair of feeding rollers 25 includes a feeding drive roller 25A and a feeding separation roller 25B. The outer peripheral surface of the feeding separation roller 25B has a larger friction coefficient with respect to the medium M than the feeding drive roller 25A. The feeding separation roller 25B rotates at a slightly lower rotational speed than the feeding drive roller 25A. Thereby, even if a plurality of media M are overlapped and double-fed from the feeding roller 23, the pair of feeding rollers 25 separates the bottommost one and feeds it downstream in the transport direction Y.

[0019] The conveying unit 24 includes a pair of conveying rollers 26. The pair of conveying rollers 26 is provided downstream of the pair of feeding rollers 25 in the conveying direction Y. The pair of conveying rollers 26 is provided upstream of the reading area SA in the conveying direction Y. The pair of conveying rollers 26 includes a conveying drive roller 26A and a conveying driven roller 26B. The pair of conveying rollers 26 is rotationally driven so as to convey the medium M at the same conveying speed when reading the medium M. The conveying driven roller 26B is rotated by the rotation of the conveying drive roller 26A.

[0020] The conveying mechanism 20 includes a discharging unit 27. The discharging unit 27 discharges the medium M after reading the image. The discharging unit 27 includes a pair of discharging rollers 28. The pair of discharging rollers 28 is provided downstream of the reading area SA in the conveying direction Y. The pair of discharging rollers 28 conveys the medium M during the reading together with the pair of conveying rollers 26. The pair of discharging rollers 28 includes a discharging drive roller 28A and a discharging driven roller 28B. The pair of discharging rollers 28 is rotationally driven so as to convey the medium M at the same conveying speed when reading the medium M. The discharging driven roller 28B is rotated by the rotation of the discharging drive roller 28A.

[0021] The image reading device 11 includes a feeding motor 29A and a conveying motor 29B. The feeding motor 29A is a power source for rotationally driving the feeding roller 23 and the feeding drive roller 25A. The conveying motor 29B is a power source for rotationally driving the feeding separation roller 25B, the conveying drive roller 26A, and the discharging drive roller 28A.

[0022] The image reading device 11 includes a reading unit 30. The reading unit 30 is provided inside the main body 12. The reading unit 30 is configured to read the image of the medium M conveyed along the conveying path 19. The reading unit 30 is provided between the pair of conveying rollers 26 and the pair of discharging rollers 28 in the conveying direction Y.

[0023] The reading unit 30 may include a first reading unit 30A and a second reading unit 30B. The first reading unit 30A reads the surface of the medium M. The second reading unit 30B reads the back surface of the medium M. The first reading unit 30A and the second reading unit 30B are provided on both sides sandwiching the conveyance path 19. The first reading unit 30A and the second reading unit 30B are provided at positions slightly shifted from each other in the conveyance direction Y. When only the surface of the medium M is read, the first reading unit 30A performs a reading operation, and the second reading unit 30B does not perform a reading operation. When both sides of the medium M are read, the first reading unit 30A and the second reading unit 30B perform a reading operation.

[0024] The first reading unit 30A includes a first light source 31A. The first light source 31A can irradiate light on the medium M being conveyed. The first light source 31A is constituted by, for example, an LED, a fluorescent lamp, or the like.

[0025] The first reading unit 30A includes a first image sensor 32A. The first image sensor 32A extends in the width direction X. The first image sensor 32A is, for example, a linear image sensor. The first image sensor 32A may be a contact-type image sensor in which a plurality of photoelectric conversion elements are arranged in a row along the width direction X. Specifically, the first image sensor 32A may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The first image sensor 32A receives the reflected light of the light from the first light source 31A reflected by the medium M. The first image sensor 32A converts the light received by each photoelectric conversion element into an electrical signal and outputs a pixel signal having a value corresponding to the received light amount. The image reading apparatus 11 may be capable of color scanning and monochrome scanning (gray-scale scanning).

[0026] The first reading unit 30A includes a first color reference plate 33A. The first color reference plate 33A is provided at a position facing the first image sensor 32A with the conveyance path 19 interposed therebetween. The first color reference plate 33A is for obtaining a white reference value for shading correction.

[0027] The second reading unit 30B has the same functions as the first reading unit 30A. Therefore, a detailed description of the second reading unit 30B will be omitted. The second reading unit 30B includes a second light source 31B, a second image sensor 32B, and a second color reference plate 33B. The second light source 31B has the same functions as the first light source 31A. The second image sensor 32B has the same functions as the first image sensor 32A. The second color reference plate 33B has the same functions as the first color reference plate 33A.

[0028] The image reading device 11 includes an encoder 34. The encoder 34 is provided inside the main body 12. The encoder 34 may be, for example, a rotary encoder. The encoder 34 may be able to detect the rotation of the conveyance drive roller 26A, or may be able to detect the rotation of other rollers. The encoder 34 outputs a detection signal including a number of pulses proportional to the rotation amount of the drive roller.

[0029] The image reading device 11 includes a first medium sensor 35. The first medium sensor 35 is provided slightly upstream of the feed roller 23 in the conveyance direction Y. The first medium sensor 35 detects the presence or absence of the medium M and outputs a detection signal. The first medium sensor 35 may be, for example, a contact sensor having a lever, or may be a non-contact sensor such as an optical sensor. When the medium M is placed on the medium support 13, the placed medium M presses the lever, and the first medium sensor 35 detects the presence of the medium M placed on the medium support 13.

[0030] The image reading device 11 includes a second medium sensor 36. The second medium sensor 36 is provided slightly downstream of the nip point of the conveying roller pair 26 in the conveying direction Y. The second medium sensor 36 detects the presence or absence of the medium M and outputs a detection signal. The second medium sensor 36 may be, for example, a contact sensor having a lever, or may be a non-contact sensor such as an optical sensor. When the medium M is conveyed by the conveying roller pair 26, the tip of the medium M presses the lever, and the second medium sensor 36 detects the presence of the medium M conveyed by the conveying roller pair 26. After the medium M is conveyed by the conveying roller pair 26, when the trailing edge of the medium M passes by, the lever is not pressed, and the second medium sensor 36 detects the absence of the medium M conveyed by the conveying roller pair 26.

[0031] The image reading device 11 includes a double-feed sensor 37. The double-feed sensor 37 is provided between the feeding drive roller 25A and the conveying drive roller 26A in the conveying direction Y. The double-feed sensor 37 detects double feeding of the medium M. Double feeding of the medium M means that a plurality of media M are conveyed in an overlapping state.

[0032] The double-feed sensor 37 includes a transmitting element 38 and a receiving element 39. The transmitting element 38 is an element capable of transmitting a signal for detecting double feeding of the medium M. The receiving element 39 is an element capable of receiving a signal for detecting double feeding of the medium M. The transmitting element 38 and the receiving element 39 are provided at positions facing each other with the conveying path 19 interposed therebetween. The signal for detecting double feeding of the medium M is a sound wave, and the double-feed sensor 37 may be, for example, a sound wave sensor.

[0033] <Control unit> The image reading device 11 includes a control unit 40. The control unit 40 may comprehensively control the image reading device 11 and control various operations executed by the image reading device 11. The control unit 40 may include one or more processors that execute various processes according to a computer program, one or more dedicated hardware circuits such as application-specific integrated circuits that execute at least a part of the various processes, or a combination thereof. The processor includes a CPU and memories such as a RAM and a ROM, and the memories store program codes or instructions configured to cause the CPU to execute processes. The memory, that is, the computer-readable medium, includes any readable medium accessible by a general-purpose or dedicated computer.

[0034] The control unit 40 is connected to the operation unit 17. The control unit 40 inputs an operation signal from the operation unit 17. The control unit 40 is connected to the encoder 34. The control unit 40 inputs a detection signal from the encoder 34. The control unit 40 is connected to the first medium sensor 35. The control unit 40 inputs a detection signal from the first medium sensor 35. The control unit 40 is connected to the second medium sensor 36. The control unit 40 inputs a detection signal from the second medium sensor 36. The control unit 40 is connected to the double-feed sensor 37. The control unit 40 inputs a detection signal from the double-feed sensor 37.

[0035] The control unit 40 is connected to the feeding motor 29A. The control unit 40 outputs a drive signal to the feeding motor 29A. The control unit 40 is connected to the conveying motor 29B. The control unit 40 outputs a drive signal to the conveying motor 29B.

[0036] The control unit 40 is connected to the first reading unit 30A. The control unit 40 inputs a pixel signal by driving and controlling the first reading unit 30A. The control unit 40 is connected to the second reading unit 30B. The control unit 40 inputs a pixel signal by driving and controlling the second reading unit 30B.

[0037] Specifically, when the control unit 40 identifies the input of a reading job based on an operation signal from the operation unit 17, it controls the image reading device 11 based on a reading instruction. When performing control of the reading operation, the control unit 40 controls the feeding motor 29A, the conveyance motor 29B, the first reading unit 30A, and the second reading unit 30B.

[0038] When the control unit 40 identifies the input of a reading job, it determines whether the medium M is placed on the medium support 13 based on a detection signal from the first medium sensor 35. When the control unit 40 determines that the medium M is placed on the medium support 13, it initializes the conveyance counter. The conveyance counter is allocated to the memory. The conveyance counter is a counter for identifying the position of the medium M in the conveyance direction Y. The control unit 40 updates the conveyance counter based on a detection signal input from the encoder 34 during the driving of the conveyance motor 29B. In this case, the control unit 40 identifies the position of the medium M in the conveyance direction Y based on the updated conveyance counter value.

[0039] The control unit 40 identifies that the leading end of the medium M has passed through the pair of conveyance rollers 26 based on a detection signal from the second medium sensor 36. The control unit 40 detects that the trailing end of the medium M has passed through the pair of conveyance rollers 26 based on a detection signal from the second medium sensor 36. The control unit 40 identifies the start timing of the reading operation in the first reading unit 30A and the second reading unit 30B based on the timing when the leading end of the medium M passes through the pair of conveyance rollers 26 and the timing when the trailing end of the medium M passes through the pair of conveyance rollers 26. Further, the control unit 40 identifies the end timing of the reading operation based on the timing when the leading end of the medium M passes through the pair of conveyance rollers 26 and the timing when the trailing end of the medium M passes through the pair of conveyance rollers 26.

[0040] The control unit 40 controls the reading operations of the first reading unit 30A and the second reading unit 30B based on the start timing and the end timing of the reading operation. In particular, when a reading instruction to read only the surface of the medium M is input, the control unit 40 causes the first reading unit 30A to perform the reading operation. When a reading instruction to read both sides of the medium M is input, the control unit 40 causes the first reading unit 30A and the second reading unit 30B to perform the reading operation.

[0041] <Duplex detection circuit> Here, with reference to FIG. 3, the electrical configuration for controlling the duplex sensor 37 will be described.

[0042] As shown in FIG. 3, the image reading apparatus 11 includes a duplex detection circuit 41. The duplex detection circuit 41 is connected to the control unit 40. The duplex detection circuit 41 is connected to the transmitting element 38. The duplex detection circuit 41 is connected to the receiving element 39.

[0043] The control unit 40 can output an enable signal to the duplex detection circuit 41. When the duplex detection circuit 41 receives the enable signal from the control unit 40, it outputs a drive signal to the transmitting element 38 to cause the transmitting element 38 to transmit a sound wave. The duplex detection circuit 41 outputs a detection signal to the control unit 40 based on the sound wave received by the receiving element 39. The control unit 40 can detect the duplex of the medium M based on the input of the detection signal. In this way, the control unit 40 is configured to detect the duplex of the medium M.

[0044] The duplex detection circuit 41 is supplied with a first power supply voltage V1 and a second power supply voltage V2. The first power supply voltage V1 is a voltage for overall control of the image reading apparatus 11. The second power supply voltage V2 is a drive voltage for driving the transmitting element 38. The second power supply voltage V2 is higher than the first power supply voltage V1. The first power supply voltage V1 of the present embodiment may be, for example, 3.3V. The second power supply voltage V2 of the present embodiment may be, for example, 24V. The first power supply voltage V1 is also supplied to the control unit 40. In this way, the control unit 40 is a circuit to which the first power supply voltage V1 is supplied.

[0045] The retransmission detection circuit 41 may include a transmission control circuit 42. The transmission control circuit 42 is supplied with a first power supply voltage V1. Thus, the transmission control circuit 42 is a circuit to which the first power supply voltage V1 is supplied. When the transmission control circuit 42 receives a valid signal from the control unit 40, it outputs a reference signal based on the first power supply voltage V1. The reference signal is a square wave in which the first power supply voltage V1 is at a high level and 0 V is at a low level.

[0046] The retransmission detection circuit 41 includes a drive circuit 43. The drive circuit 43 is supplied with a second power supply voltage V2. Thus, the drive circuit 43 is a circuit to which a second power supply voltage V2 higher than the first power supply voltage V1 is supplied. The drive circuit 43 is connected to the transmission control circuit 42. The drive circuit 43 is connected to the transmission element 38. The drive circuit 43 is a circuit for transmitting a sound wave from the transmission element 38. A reference signal is input to the drive circuit 43 from the transmission control circuit 42. When the drive circuit 43 receives a reference signal from the transmission control circuit 42, it generates a drive signal using the second power supply voltage V2 and outputs it to the transmission element 38. Thus, the drive circuit 43 is configured to output a drive signal to the transmission element 38.

[0047] The retransmission detection circuit 41 includes a reception amplification circuit 44. The reception amplification circuit 44 is connected to the reception element 39. The reception amplification circuit 44 amplifies and outputs the voltage of the reception signal from the reception element 39. Thus, the reception amplification circuit 44 is configured to amplify the voltage of the signal received by the reception element 39.

[0048] The retransmission detection circuit 41 includes a reception determination circuit 45. The reception determination circuit 45 is connected to the reception amplification circuit 44. The reception determination circuit 45 is connected to the control unit 40. When the reception determination circuit 45 receives the reception signal whose voltage has been amplified by the reception amplification circuit 44 from the reception amplification circuit 44, it outputs a detection signal to the control unit 40 when the reception signal satisfies the detection condition. The detection condition may be satisfied when the amplitude value of the reception signal is within a specified range. Thus, the reception determination circuit 45 is configured to determine the signal amplified by the reception amplification circuit 44.

[0049] The control unit 40 drives the retransmission sensor 37 by outputting an active signal to the transmission control circuit 42. When the detection signal from the reception determination circuit 45 is input, the control unit 40 detects the retransmission of the medium M. In this way, the control unit 40 is configured to detect the retransmission of the medium M based on the result determined by the reception determination circuit 45. That is, the control unit 40 is configured to detect the retransmission of the medium M based on the signal received by the reception element 39. In the present embodiment, the control unit 40 corresponds to an example of a control circuit.

[0050] <Drive circuit 43> Next, the drive circuit 43 will be described with reference to FIG. 4. As shown in FIG. 4, the drive circuit 43 includes a first input terminal 51. A reference signal Vin1 is input to the first input terminal 51 from the transmission control circuit 42. The reference signal Vin1 is, for example, a square wave in which 3.3V as the first power supply voltage V1 is at a high level and 0V is at a low level. The drive circuit 43 includes a second input terminal 52. A drive power supply Vin2 of the second power supply voltage V2 is supplied to the second input terminal 52. The drive power supply Vin2 is, for example, a direct current 24V as the second power supply voltage V2. The drive circuit 43 includes an output terminal 53. A drive signal Vout for driving the transmission element 38 is output from the output terminal 53. The drive signal Vout is, for example, a square wave in which 24V as the second power supply voltage V2 is at a high level and 0V is at a low level.

[0051] <Conversion circuit 54> The drive circuit 43 includes a conversion circuit 54. The conversion circuit 54 is a circuit that converts the reference signal Vin1 into a conversion signal. The reference signal Vin1 is a signal within the first voltage range. The first voltage range is a range equal to or lower than the first power supply voltage V1, such as 0 to 3.3V, for example. The conversion signal converted by the conversion circuit 54 is a voltage within the second voltage range. The second voltage range is a range equal to or lower than the second power supply voltage V2, such as 0 to 24V, for example. Also, the conversion signal becomes a low level when the reference signal Vin1 is at a high level, and becomes a high level when the reference signal Vin1 is at a low level. That is, the conversion signal is a signal whose voltage level is inverted by comparing with the reference signal Vin1.

[0052] The conversion circuit 54 may include resistors R4, R5, a third switching element M3, a third gate resistor R3, and a diode D3. The third switching element M3 may be an N-type MOSFET. One end of the resistor R4 is connected to the second input terminal 52. The other end of the resistor R4 and one end of the resistor R5 are connected. The other end of the resistor R4 and one end of the resistor R5 are the output terminals of the conversion circuit 54. The other end of the resistor R5 and the drain terminal of the third switching element M3 are connected. One end of the third gate resistor R3 is connected to the first input terminal 51. One end of the third gate resistor R3 is the input terminal of the conversion circuit 54. The other end of the third gate resistor R3 and the gate terminal of the third switching element M3 are connected. That is, the third gate resistor R3 is connected to the gate terminal of the third switching element M3. The source terminal of the third switching element M3 is grounded.

[0053] The anode terminal of the diode D3 and the source terminal of the third switching element M3 are connected. The cathode terminal of the diode D3 and the gate terminal of the third switching element M3 are connected. The diode D3 protects the absolute maximum rating between the source terminal and the gate terminal of the third switching element M3 between the source terminal and the gate terminal of the third switching element M3.

[0054] A reference signal Vin1 is input to the gate terminal of the third switching element M3 via a third gate resistor R3. When the reference signal Vin1 becomes high level, the third switching element M3 turns on, and a drain current of the third switching element M3 flows. As a result, the voltage Va at the output terminal of the conversion circuit 54 becomes a voltage lower than the second power supply voltage V2. When the reference signal Vin1 becomes low level, the third switching element M3 turns off, and no drain current of the third switching element M3 flows. As a result, the voltage Va at the output terminal of the conversion circuit 54 becomes the second power supply voltage V2.

[0055] In this way, the conversion circuit 54 is configured to convert a reference signal within the first voltage range into a conversion signal within the second voltage range. The conversion circuit 54 converts a high-level reference signal Vin1 into a low-level conversion signal and converts a low-level reference signal Vin1 into a high-level conversion signal. That is, the conversion circuit 54 is configured to convert the reference signal Vin1 into a conversion signal whose voltage level is inverted compared to the reference signal Vin1. Specifically, the conversion circuit 54 can be converted into a square-wave conversion signal whose high level is about 24V and whose low level is about 12V, for example.

[0056] <First current amplification circuit 55> The drive circuit 43 may include a first current amplification circuit 55. The first current amplification circuit 55 is a circuit that amplifies the current of the conversion signal converted by the conversion circuit 54. That is, it can be said that the first current amplification circuit 55 is a circuit that amplifies the current of the signal input to the push-pull circuit 58 described later.

[0057] The first current amplification circuit 55 may include a switching element Q1, a switching element Q2, and a resistor R6. The switching element Q1 is an npn-type bipolar transistor. The switching element Q2 is a pnp-type bipolar transistor. The first current amplification circuit 55 is a push-pull circuit using an npn-type bipolar transistor and a pnp-type bipolar transistor.

[0058] The base terminal of the switching element Q1 and the base terminal of the switching element Q2 are connected to the other end of the resistor R4 and one end of the resistor R5. The base terminal of the switching element Q1 and the base terminal of the switching element Q2 are the input terminals of the first current amplification circuit 55. That is, the output terminal of the conversion circuit 54 and the input terminal of the first current amplification circuit 55 are connected. The collector terminal of the switching element Q1 is connected to the second input terminal 52. The emitter terminal of the switching element Q1 and the emitter terminal of the switching element Q2 are connected. The emitter terminal of the switching element Q1 and the emitter terminal of the switching element Q2 are the output terminals of the first current amplification circuit 55. The collector terminal of the switching element Q2 and one end of the resistor R6 are connected. The other end of the resistor R6 is grounded.

[0059] In this way, the first current amplification circuit 55 can amplify the current Ib flowing into the input terminal of the first current amplification circuit 55 into the current Ic flowing out of the output terminal of the first current amplification circuit 55. Specifically, the first current amplification circuit 55 can amplify a current Ib of, for example, about 1.2 mA into a current Ic of about 5.2 mA as the conversion signal rises. Thereby, the capacitance of the capacitor C1 described later can be increased, and a switching element with high processing ability can also be used as the first switching element M1 described later.

[0060] <Boost circuit 56> The drive circuit 43 includes a boost circuit 56. The boost circuit 56 is a circuit that boosts the conversion signal whose current has been amplified by the first current amplification circuit 55. In other words, the boost circuit 56 is also a circuit that boosts the conversion signal converted by the conversion circuit 54.

[0061] The boost circuit 56 may include a capacitor C1 and a diode D4. One end of the capacitor C1 is connected to the emitter terminal of the switching element Q1 and the emitter terminal of the switching element Q2. One end of the capacitor C1 is the input end of the boost circuit 56. That is, the output end of the first current amplification circuit 55 and the input end of the boost circuit 56 are connected. The anode terminal of the diode D4 is connected to the second input terminal 52. The other end of the capacitor C1 and the cathode terminal of the diode D4 are connected. The other end of the capacitor C1 and the cathode terminal of the diode D4 are the output end of the boost circuit 56.

[0062] In this way, the boost circuit 56 can boost the voltage Vb at the output end of the first current amplification circuit 55 to the voltage Vc at the output end of the boost circuit 56. Specifically, the boost circuit 56 boosts the input conversion signal by, for example, about 12V. As a result, the signal boosted by the boost circuit 56 becomes a voltage higher than within the second voltage range when it is at a high level. That is, the boost circuit 56 can boost a conversion signal within the second voltage range to a voltage higher than within the second voltage range. Specifically, the boost circuit 56 can boost, for example, a square wave with a high level of about 24V and a low level of about 12V to a square wave with a high level of about 36V and a low level of about 24V.

[0063] <First adjustment circuit 57> The drive circuit 43 includes a first adjustment circuit 57. The first adjustment circuit 57 is a circuit that adjusts the conversion signal boosted by the boost circuit 56 so that its rise time becomes longer. That is, the first adjustment circuit 57 reduces the slew rate of the conversion signal boosted by the boost circuit 56 and adjusts to slow down the rise of the conversion signal boosted by the boost circuit 56.

[0064] The first adjustment circuit may include a resistor R7 as an example of a predetermined resistor. One end of the resistor R7 is connected to the other end of the capacitor C1 and the cathode terminal of the diode D4. One end of the resistor R7 is the input terminal of the first adjustment circuit 57. That is, the output terminal of the boost circuit 56 and the input terminal of the first adjustment circuit 57 are connected. The other end of the resistor R7 is the output terminal of the first adjustment circuit 57.

[0065] If the resistance value of the resistor R7 is small, the power consumption increases, and if the resistance value of the resistor R7 is large, the waveform distortion increases. Therefore, the resistor R7 has a suitable resistance value that does not increase the power consumption and does not increase the waveform distortion. Also, the resistor R7 has a suitable resistance value for the specifications of the first switching element M1 described later.

[0066] <Push-pull circuit 58> The drive circuit 43 includes a push-pull circuit 58. The push-pull circuit 58 is a circuit that amplifies the current of the conversion signal adjusted by the first adjustment circuit 57. The push-pull circuit 58 is a circuit that outputs the amplified conversion signal as a drive signal to the transmission element 38. That is, the push-pull circuit 58 is a circuit that outputs a drive signal obtained by amplifying the current of the conversion signal adjusted by the first adjustment circuit 57 to the transmission element 38.

[0067] The push-pull circuit 58 includes a first switching element M1 and a second switching element M2. The first switching element M1 is an N-type MOSFET. The second switching element M2 is an N-type MOSFET. That is, the push-pull circuit 58 is a push-pull circuit using two N-type MOSFETs. In the present embodiment, the first switching element M1 corresponds to an example of the first N-type MOSFET. In the present embodiment, the second switching element M2 corresponds to an example of the second N-type MOSFET. The push-pull circuit 58 may include a first gate resistor R1, a second gate resistor R2, and diodes D1, D2.

[0068] One end of the first gate resistor R1 is connected to the other end of the resistor R7. One end of the first gate resistor R1 is the first input terminal of the push-pull circuit 58. That is, the output terminal of the first adjustment circuit 57 and the first input terminal of the push-pull circuit 58 are connected. The other end of the first gate resistor R1 and the gate terminal of the first switching element M1 are connected. That is, the first gate resistor R1 is connected to the gate terminal of the first switching element M1. The drain terminal of the first switching element M1 is connected to the second input terminal 52. The source terminal of the first switching element M1 and the drain terminal of the second switching element M2 are connected. The source terminal of the first switching element M1 and the drain terminal of the second switching element M2 are connected to the output terminal 53. One end of the second gate resistor R2 is connected to the first input terminal 51. One end of the second gate resistor R2 is the second input terminal of the push-pull circuit 58. A reference signal Vin1 is input to one end of the second gate resistor R2. The other end of the second gate resistor R2 and the gate terminal of the second switching element M2 are connected. That is, the second gate resistor R2 is connected to the gate terminal of the second switching element M2. The drain terminal of the second switching element M2 is grounded.

[0069] The anode terminal of the diode D1 and the source terminal of the first switching element M1 are connected. The cathode terminal of the diode D1 and the gate terminal of the first switching element M1 are connected. The diode D1 protects the absolute maximum rating between the source terminal and the gate terminal of the first switching element M1 between the source terminal and the gate terminal of the first switching element M1. In the present embodiment, the diode D1 corresponds to an example of a protection circuit.

[0070] The anode terminal of diode D2 and the source terminal of the second switching element M2 are connected. The cathode terminal of diode D2 and the gate terminal of the second switching element M2 are connected. Diode D2 protects the absolute maximum rating between the source terminal and the gate terminal of the second switching element M2 between the source terminal and the gate terminal of the second switching element M2.

[0071] Thus, a converted signal adjusted by the first adjustment circuit 57 is input to the first input terminal of the push-pull circuit 58. That is, a converted signal adjusted by the first adjustment circuit 57 is input to the gate terminal of the first switching element M1 via the first gate resistor R1. A reference signal Vin1 is input to the second input terminal of the push-pull circuit 58. That is, the reference signal Vin1 is input to the gate terminal of the second switching element M2 via the second gate resistor R2. The signal adjusted by the first adjustment circuit 57 is a signal whose voltage level is inverted compared to the reference signal Vin1. Therefore, except when the first switching element M1 and the second switching element M2 are turned on and off, when the first switching element M1 is in the on state, the second switching element M2 is in the off state. Also, except when the first switching element M1 and the second switching element M2 are turned on and off, when the first switching element M1 is in the off state, the second switching element M2 is in the on state.

[0072] Thereby, the push-pull circuit 58 amplifies the current of the converted signal adjusted by the first adjustment circuit 57 using two N-type MOSFETs. The push-pull circuit 58 outputs the amplified signal as a drive signal from the output terminal 53.

[0073] <Second adjustment circuit 59> The drive circuit 43 includes a second adjustment circuit 59. The second adjustment circuit 59 is a circuit that adjusts the conversion signal input to the push-pull circuit 58. Specifically, the second adjustment circuit 59 adjusts to advance the falling timing of the conversion signal input to the gate terminal of the first switching element M1. In the present embodiment, the third switching element M3 corresponds to an example of a third N-type MOSFET.

[0074] The second adjustment circuit 59 includes a third switching element M3. The second adjustment circuit 59 may include a third gate resistor R3 and diodes D3 and D5. The third switching element M3, the third gate resistor R3, and the diode D3 may be shared by the conversion circuit 54 and the second adjustment circuit 59. The anode terminal of the diode D5 is connected to the other end of the resistor R7 and one end of the first gate resistor R1. That is, the anode terminal of the diode D5 is connected to the output terminal of the first adjustment circuit 57 and the first input terminal of the push-pull circuit 58. The cathode terminal of the diode D5 and the drain terminal of the third switching element M3 are connected. That is, the gate terminal of the first switching element M1 and the drain terminal of the third switching element M3 are connected via the first gate resistor R1 and the diode D5.

[0075] <Relationship between Switching Element and Gate Resistor> In particular, the third switching element M3 has a smaller total gate charge amount than the second switching element M2. The first switching element M1 and the second switching element M2 may have the same total gate charge amount. Also, the third gate resistor R3 has a smaller resistance value than the second gate resistor R2. The first gate resistor R1 and the third gate resistor R3 may have the same resistance value.

[0076] In this way, before the second switching element M2 changes from the off state to the on state, the third switching element M3 changes from the off state to the on state. And before the second switching element M2 changes from the off state to the on state, the first switching element M1 changes from the on state to the off state. That is, the third switching element M3 is driven so as to advance the timing of the falling edge of the conversion signal input to the gate terminal of the first switching element M1. Thereby, before the first switching element M1 changes from the on state to the off state, the second switching element M2 is prevented from changing from the off state to the on state, so that the through current from the first switching element M1 to the second switching element M2 can be prevented.

[0077] <Operation of the First Embodiment> The operation of the first embodiment will be described. As shown in FIG. 5, a square-wave reference signal Vin1 having an amplitude of the first power supply voltage V1 is input to the first input terminal 51 of the drive circuit 43. A drive power supply Vin2 of the second power supply voltage V2 is supplied to the second input terminal 52.

[0078] When the reference signal Vin1 input to the gate terminal of the third switching element M3 becomes high level, the third switching element M3 becomes on state, and the voltage Va at the output terminal of the conversion circuit 54 becomes a voltage V3 lower than the second power supply voltage V2. When the reference signal Vin1 becomes low level, the third switching element M3 becomes off state, and the voltage Va at the output terminal of the conversion circuit 54 becomes the second power supply voltage V2. That is, the reference signal Vin1 is converted into a conversion signal whose voltage level is inverted compared with the reference signal Vin1.

[0079] As shown in FIG. 6, the conversion signal output from the output terminal of the conversion circuit 54 is amplified in current by the first current amplification circuit 55. Specifically, when the voltage Va at the output terminal of the conversion circuit 54 rises, the current Ib flowing into the input terminal of the first current amplification circuit 55 is the current I1, but the current Ic flowing out of the output terminal of the first current amplification circuit 55 becomes the current I2. That is, the current Ib flowing into the input terminal of the first current amplification circuit 55 is amplified up to the current Ic flowing out of the output terminal of the first current amplification circuit 55.

[0080] As shown in FIG. 7, the conversion signal output from the output terminal of the first current amplification circuit 55 is boosted by the boost circuit 56. As a result, as the voltage Vc at the output terminal of the boost circuit 56, the high level becomes the voltage V4 and the low level becomes the second power supply voltage V2. Specifically, as the voltage Vb at the input terminal of the boost circuit 56, for example, the high level is about 24V and the low level is about 12V, but as the voltage Vc at the output terminal of the boost circuit 56, for example, the high level becomes about 36V and the low level becomes about 24V.

[0081] As shown in FIG. 8, the conversion signal output from the output terminal of the boost circuit 56 is adjusted by the first adjustment circuit 57. Specifically, the voltage Vd at the output terminal of the first adjustment circuit 57 has a waveform with a long rise time. Also, the voltage Vd at the output terminal of the first adjustment circuit 57 has a high level of voltage V5 and a low level of about 0V. Specifically, the voltage Vd at the output terminal of the first adjustment circuit 57 is, for example, about 28V at the high level.

[0082] As shown in FIG. 9, the reference signal Vin1 is input to the gate terminal of the second switching element M2 via the second gate resistor R2. The conversion signal output from the output terminal of the first adjustment circuit 57 is input to the gate terminal of the first switching element M1 via the first gate resistor R1. When the signal output from the output terminal of the first adjustment circuit 57 is at a high level, the reference signal Vin1 is at a low level. When the signal output from the output terminal of the first adjustment circuit 57 is at a low level, the reference signal Vin1 is at a high level.

[0083] When the first switching element M1 changes from the off state to the on state, the drain current Id1 of the first switching element M1 becomes a current I3 that is larger than the current I2. When the second switching element M2 changes from the off state to the on state, the drain current Id1 of the second switching element M2 becomes a current I3 that is larger than the current I2. That is, the drain current Id1 of the first switching element M1 and the drain current Id2 of the second switching element M2 are each amplified to a maximum current I3. In this way, a drive signal Vout whose current is amplified by the push-pull circuit 58 is output from the output terminal 53.

[0084] As shown in FIGS. 10 and 11, the reference signal Vin1 is also input to the gate terminal of the third switching element M3 via the third gate resistor R3. The third switching element M3 has a smaller total gate charge amount than the second switching element M2. For this reason, the voltage Vm3g of the gate terminal of the third switching element M3 becomes high level earlier than the voltage Vm2g of the gate terminal of the second switching element M2. That is, the third switching element M3 changes from the off state to the on state earlier than the second switching element M2.

[0085] The third gate resistor R3 of the third switching element M3 has a smaller resistance value than the second gate resistor R2 of the second switching element M2. For this reason, the voltage Vm3g of the gate terminal of the third switching element M3 becomes high level earlier than the voltage Vm2g of the gate terminal of the second switching element M2. That is, the third switching element M3 changes from the off state to the on state earlier than the second switching element M2.

[0086] Thus, when the third switching element M3 turns on from the off state earlier than the second switching element M2, a drain current flows through the third switching element M3. As a result, the voltage Vm1g at the gate terminal of the first switching element M1 decreases. That is, before the second switching element M2 turns on from the off state, the first switching element M1 turns off from the on state. Thereby, before the drain current Id2 of the second switching element M2 starts to flow, the drain current Id1 of the first switching element M1 stops flowing, and the through-current from the first switching element M1 to the second switching element M2 can be prevented.

[0087] <Effects of the First Embodiment> The effects of the first embodiment will be described. (1) The push-pull circuit 58 includes a first switching element M1 that is an N-type MOSFET and a second switching element M2 that is an N-type MOSFET. The push-pull circuit 58 is a circuit in which the source terminal of the first switching element M1 and the drain terminal of the second switching element M2 are connected. A conversion signal whose voltage level is inverted compared to the reference signal Vin1 is input to the gate terminal of the first switching element M1, while the reference signal Vin1 is input to the gate terminal of the second switching element M2. Therefore, the push-pull circuit 58 using an N-type MOSFET can amplify the current, and the driving speed can be increased compared to a push-pull circuit using a P-type MOSFET.

[0088] Also, the push-pull circuit 58 using an N-type MOSFET can amplify the current, and the push-pull circuit can be configured at a lower cost compared to a push-pull circuit using a P-type MOSFET.

[0089] Also, by advancing the timing of the fall of the conversion signal input to the gate terminal of the first switching element M1, the through-current from the first switching element M1 to the second switching element M2 can be suppressed.

[0090] (2) A reference signal Vin1 within a first voltage range equal to or lower than a first power supply voltage V1 can be converted into a conversion signal within a second voltage range equal to or lower than a second power supply voltage V2 higher than the first power supply voltage V1, and further boosted to a voltage higher than the second voltage range. Therefore, the reference signal Vin1 within the first voltage range can be made into a conversion signal having a voltage higher than the second voltage range, a first switching element M1 with high driving ability can be used, and the driving ability of the push-pull circuit can be enhanced.

[0091] (3) The first current amplification circuit 55 amplifies the current of the conversion signal converted by the conversion circuit 54. As a result, a first switching element M1 with high driving ability can be used, and the driving ability of the push-pull circuit 58 can be enhanced.

[0092] (4) The second adjustment circuit 59 includes a third switching element M3 which is an N-type MOSFET. The third switching element M3 has a smaller gate total charge amount than the second switching element M2. Therefore, the driving speed of the third switching element M3 is faster than that of the second switching element M2. In this way, the timing at which the driving of the first switching element M1 ends can be advanced by driving the third switching element M3. For this reason, the driving of the first switching element M1 can be ended before the second switching element M2 is driven. Therefore, the through-current from the first switching element M1 to the second switching element M2 can be suppressed.

[0093] (5) The third gate resistor R3 has a smaller resistance value than the second gate resistor R2. Therefore, the driving speed of the third switching element M3 is faster than that of the second switching element M2. In this way, the timing at which the driving of the first switching element M1 ends can be advanced by driving the third switching element M3. For this reason, the driving of the first switching element M1 can be ended before the second switching element M2 is driven. Therefore, the through-current from the first switching element M1 to the second switching element M2 can be suppressed.

[0094] (6) The push-pull circuit 58 has a diode D1 that protects the absolute maximum rating between the source terminal and the gate terminal of the first switching element M1. Therefore, when the driving of the first switching element M1 ends, the absolute maximum rating between the source terminal and the gate terminal of the first switching element M1 can be protected.

[0095] [Second Embodiment] Next, the second embodiment will be described. In the first embodiment, the drive circuit 43 includes the first current amplification circuit 55. However, in the second embodiment, a second current amplification circuit may be provided separately from the first current amplification circuit 55. In the following description, the same components and the same control content as those in the already described embodiments are denoted by the same reference numerals, and the overlapping descriptions are omitted or simplified.

[0096] <Second Adjustment Circuit 60> As shown in FIG. 12, in the second embodiment, the drive circuit 43 may include a second current amplification circuit 60. The second current amplification circuit 60 is connected in parallel with the first adjustment circuit 57 to the first input terminal of the push-pull circuit 58. The second current amplification circuit 60 is a circuit that amplifies the current of the conversion signal input to the first input terminal of the push-pull circuit 58. That is, the second current amplification circuit 60 is a circuit that amplifies the current of the conversion signal input to the gate terminal of the first switching element M1.

[0097] The second current amplification circuit 60 may include resistors R8, R9, and a switching element Q3. The switching element Q3 is a pnp bipolar transistor. One end of the resistor R8 is connected to the second input terminal 52. The other end of the resistor R8 and the base terminal of the switching element Q3 are connected. The emitter terminal of the switching element Q3 is connected to the cathode terminal of the diode D4. The collector terminal of the switching element Q3 and one end of the resistor R9 are connected. The other end of the resistor R9 is connected to the other end of the resistor R7. The other end of the resistor R9 is the output terminal of the second current amplification circuit 60.

[0098] Further, by including the second current amplification circuit 60, the drive circuit 43 can increase the resistance value of the resistor R7 of the first adjustment circuit 57. Thereby, the current consumption of the first adjustment circuit 57 can be reduced.

[0099] <Operation of the Second Embodiment> The operation of the second embodiment will be described. The second current amplification circuit 60 can amplify the current of the conversion signal input to the first input terminal of the push-pull circuit 58. Thereby, the drive circuit 43 can input a conversion signal with a large current to the first input terminal of the push-pull circuit 58. Further, even if the drive circuit 43 increases the resistor R7 of the first adjustment circuit 57, the drive circuit 43 can control the current of the conversion signal input to the first input terminal of the push-pull circuit 58 within an allowable range.

[0100] <Effect of the Second Embodiment> The effect of the second embodiment will be described. (7) The second current amplification circuit 60 amplifies the current of the conversion signal input to the push-pull circuit 58. Thereby, the first switching element M1 with high driving ability can be used, and the driving ability of the push-pull circuit 58 can be enhanced.

[0101] Also, by connecting the first adjustment circuit 57 including the resistor R7 and the second current amplification circuit 60 in parallel, the resistance value of the resistor R7 can be increased. Therefore, the current consumption in the first adjustment circuit 57 can be suppressed.

[0102] [Modification Example] This embodiment can be implemented with the following modifications. This embodiment and the following modification examples can be implemented in combination with each other within a technically non-conflicting range.

[0103] · As long as the conversion signal converted by the conversion circuit 54 is a signal whose voltage level is inverted compared with the reference signal Vin1, the high-level voltage and the low-level voltage are not limited. · The drive circuit 43 includes the second current amplification circuit 60, but may be configured not to include the first current amplification circuit 55. The drive circuit 43 may be configured not to include the first current amplification circuit 55 and the second current amplification circuit 60.

[0104] · If the gate total charge amount of the third switching element M3 is smaller than that of the second switching element M2, the resistance values of the third gate resistor R3 and the second gate resistor R2 may be the same.

[0105] · If the resistance value of the third gate resistor R3 is smaller than that of the second gate resistor R2, the gate total charge amounts of the third switching element M3 and the second switching element M2 may be the same.

[0106] · The gate total charge amount of the first switching element M1 may be smaller than that of the second switching element M2. The gate total charge amount of the first switching element M1 may be larger than that of the second switching element M2.

[0107] · The resistance value of the first gate resistor R1 may be smaller than that of the third gate resistor R3. The resistance values of the first gate resistor R1 and the second gate resistor R2 may be the same. · The cathode terminal of the diode D1 may be connected to one end of the first gate resistor R1 instead of between the gate terminal of the first switching element M1 and the other end of the first gate resistor R1. The cathode terminal of the diode D2 may be connected to one end of the second gate resistor R2 instead of between the gate terminal of the second switching element M2 and the other end of the second gate resistor R2. The cathode terminal of the diode D3 may be connected to one end of the third gate resistor R3 instead of between the gate terminal of the third switching element M3 and the other end of the third gate resistor R3.

[0108] · In the drive circuit 43, various electronic elements such as resistors, capacitors, and diodes may be appropriately added. For example, the second input terminal 52 may be grounded via a capacitor. For example, the second input terminal 52 may be connected to each circuit via a resistor.

[0109] ·The control unit 40 does not necessarily output an enable signal to the duplicate detection circuit 41. In this case, after the power is turned on, the duplicate detection circuit 41 may continuously generate the reference signal Vin1 regardless of the signal from the control unit 40.

[0110] ·The image reading device 11 does not necessarily include the transmission control circuit 42. In this case, either the drive circuit 43 or the control unit 40 may have the function of the transmission control circuit 42. For example, the drive circuit 43 may generate the reference signal Vin1 based on the input first power supply voltage V1 when the first power supply voltage V1 is input.

[0111] ·The image reading device 11 does not necessarily include the reception amplifier circuit 44. The image reading device 11 does not necessarily include the reception determination circuit 45. In this case, the control unit 40 may have the functions of the reception amplifier circuit 44 and the reception determination circuit 45.

[0112] ·The present invention may be applied to a recording device that records on the medium M. That is, the recording device may have a configuration similar to that of the drive circuit 43. Further, the recording device may include a conveyance unit that conveys the medium M. That is, the present invention may be applied to a conveyance device including the conveyance unit. This conveyance device may be the image reading device 11 or the recording device, or may be a multifunction device having a recording function, a scanner mechanism, and a copying function. Also, for example, the present invention may be applied to a device that does not include a conveyance unit. That is, the present invention may be applied to a duplicate detection device.

[0113] ·The image reading device 11 includes, but is not limited to, a drive circuit 43 for driving the double-feed sensor 37. The image reading device 11 may include, for example, a sensor for detecting the thickness of the medium M, and may have the same configuration as the drive circuit 43 for driving this sensor. As a specific example, the image reading device 11 may include a sensor for detecting paper and a card having a greater thickness than the paper as the medium M. That is, the image reading device 11 may be a double-feed detection device for detecting double-feed of the medium M, or may be a medium detection device for detecting the thickness of the medium M. Further, the medium M is not limited to paper, and may be a synthetic resin film, a laminated medium, or the like.

[0114] [Appendix] The technical idea and its operational effects grasped from the above-described embodiments and modified examples are described below.

[0115] (A) A transmitting element capable of transmitting a signal for detecting media retransmission, a receiving element capable of receiving a signal for detecting media retransmission, a driving circuit configured to output a driving signal to the transmitting element, and a control circuit configured to detect media retransmission based on the signal received by the receiving element. The driving circuit includes a conversion circuit that converts a reference signal into a conversion signal, a boosting circuit that boosts the conversion signal converted by the conversion circuit, a first adjustment circuit that adjusts the rising time of the conversion signal boosted by the boosting circuit to be longer, a push-pull circuit that outputs a driving signal obtained by amplifying the current of the conversion signal adjusted by the first adjustment circuit, and a second adjustment circuit that adjusts the conversion signal input to the push-pull circuit. The conversion signal converted by the conversion circuit is a signal whose voltage level is inverted compared to the reference signal. The push-pull circuit includes a first N-type MOSFET and a second N-type MOSFET, and is a circuit in which the source terminal of the first N-type MOSFET is connected to the drain terminal of the second N-type MOSFET. The driving circuit is a circuit in which the conversion signal adjusted by the first adjustment circuit is input to the gate terminal of the first N-type MOSFET, while the reference signal is input to the gate terminal of the second N-type MOSFET. The second adjustment circuit advances the timing of the falling edge of the conversion signal input to the gate terminal of the first N-type MOSFET.

[0116] According to this configuration, the push-pull circuit includes a first N-type MOSFET and a second N-type MOSFET, and is a circuit in which the source terminal of the first N-type MOSFET is connected to the drain terminal of the second N-type MOSFET. A conversion signal whose voltage level is inverted compared to the reference signal is input to the gate terminal of the first N-type MOSFET, while the reference signal is input to the gate terminal of the second N-type MOSFET. Therefore, the current can be amplified by the push-pull circuit using N-type MOSFETs, and the driving speed can be increased compared to the push-pull circuit using P-type MOSFETs.

[0117] In addition, a push-pull circuit using an N-type MOSFET can amplify current, and a push-pull circuit can be configured at a lower cost compared to a push-pull circuit using a P-type MOSFET.

[0118] In addition, by advancing the timing of the fall of the conversion signal input to the gate terminal of the first N-type MOSFET, the through current from the first N-type MOSFET to the second N-type MOSFET can be suppressed.

[0119] (B) The control circuit is a circuit to which a first power supply voltage is supplied, the drive circuit is a circuit to which a second power supply voltage higher than the first power supply voltage is supplied, the conversion circuit converts a reference signal within a first voltage range equal to or lower than the first power supply voltage into a conversion signal within a second voltage range equal to or lower than the second power supply voltage and having a voltage level inverted compared to the reference signal, and the boost circuit may be able to boost the conversion signal converted by the conversion circuit to a voltage higher than the second voltage range.

[0120] According to this configuration, a reference signal within a first voltage range equal to or lower than the first power supply voltage can be converted into a conversion signal within a second voltage range equal to or lower than a second power supply voltage higher than the first power supply voltage, and further boosted to a voltage higher than the second voltage range. Therefore, the reference signal within the first voltage range can be made into a conversion signal having a voltage higher than the second voltage range, an N-type MOSFET with high driving ability can be used, and the driving ability of the push-pull circuit can be enhanced.

[0121] (C) The drive circuit may include a first current amplification circuit that amplifies the current of the conversion signal converted by the conversion circuit. According to this configuration, by amplifying the current of the conversion signal converted by the conversion circuit, an N-type MOSFET with high driving ability can be used, and the driving ability of the push-pull circuit can be enhanced.

[0122] (D) The drive circuit includes a second current amplification circuit that amplifies the current of the conversion signal input to the first N-type MOSFET. The first adjustment circuit has a predetermined resistor, and the second current amplification circuit may be connected in parallel with the first adjustment circuit.

[0123] According to this configuration, by amplifying the current of the conversion signal input to the push-pull circuit, an N-type MOSFET with high driving ability can be used, and the driving ability of the push-pull circuit can be enhanced.

[0124] Also, by connecting the first adjustment circuit having a predetermined resistor and the second current amplification circuit in parallel, the resistance value of the predetermined resistor can be increased. Therefore, the current consumption in the first adjustment circuit can be suppressed.

[0125] (E) The second adjustment circuit includes a third N-type MOSFET. The drive circuit is a circuit in which a reference signal is input to the gate terminal of the third N-type MOSFET. The third N-type MOSFET is driven to advance the falling timing of the conversion signal input to the gate terminal of the first N-type MOSFET, and the third N-type MOSFET may have a smaller total gate charge amount than the second N-type MOSFET.

[0126] According to this configuration, the third N-type MOSFET has a smaller total gate charge amount than the second N-type MOSFET, and the third N-type MOSFET has a faster driving speed than the second N-type MOSFET. Thus, the timing at which the driving of the first N-type MOSFET ends can be advanced by driving the third N-type MOSFET. For this reason, the driving of the first N-type MOSFET can be terminated before the second N-type MOSFET is driven. Therefore, the through-current from the first N-type MOSFET to the second N-type MOSFET can be suppressed.

[0127] (F) The push-pull circuit has a first gate resistor connected to the gate terminal of the first N-type MOSFET and a second gate resistor connected to the gate terminal of the second N-type MOSFET. The second adjustment circuit has a third N-type MOSFET and a third gate resistor connected to the gate terminal of the third N-type MOSFET. The drive circuit has a conversion signal adjusted by the first adjustment circuit input to the gate terminal of the first N-type MOSFET via the first gate resistor, while a reference signal is input to the gate terminal of the second N-type MOSFET via the second gate resistor, and a reference signal is input to the gate terminal of the third N-type MOSFET via the third gate resistor. The third N-type MOSFET is driven to speed up the falling timing of the conversion signal input to the gate terminal of the first N-type MOSFET, and the third gate resistor may have a resistance value smaller than that of the second gate resistor.

[0128] According to this configuration, the third gate resistor has a resistance value smaller than that of the second gate resistor, and the third N-type MOSFET has a faster driving speed than the second N-type MOSFET. In this way, the driving of the first N-type MOSFET can be terminated earlier by driving the third N-type MOSFET. Therefore, the driving of the first N-type MOSFET can be terminated before the second N-type MOSFET is driven. Accordingly, the through-current from the first N-type MOSFET to the second N-type MOSFET can be suppressed.

[0129] (G) The push-pull circuit may have a protection circuit for protecting the absolute maximum rating between the source terminal and the gate terminal of the first N-type MOSFET between the source terminal and the gate terminal of the first N-type MOSFET.

[0130] According to this configuration, when the driving of the first N-type MOSFET ends, the absolute maximum rating between the source terminal and the gate terminal of the first N-type MOSFET can be protected.

[0131] It includes a duplicate detection device according to any one of (H) to (G) and a transport unit configured to transport a medium. According to this configuration, the same effects as those of (A) to (G) above can be obtained.

[0132] (I) It includes a duplicate detection device according to any one of (A) to (G) and a reading unit configured to read an image of a medium. According to this configuration, the same effects as those of (A) to (G) above can be obtained.

Explanation of Signs

[0133] C1…Capacitor, D1~D5…Diode, M…Medium, M1…First switching element, M2…Second switching element, M3…Third switching element, Q1~Q3…Switching elements, R1…First gate resistor, R2…Second gate resistor, R3…Third gate resistor, R4~R9…Resistors, SA…Reading area, Vin1…Reference signal, Vin2…Drive power supply, Vout…Drive signal, X…Width direction, Y…Conveying direction, 11…Image reading device, 12…Main body, 12A…Feeding port, 12B…Discharge port, 13…Medium support, 14…Main body part, 15…Cover part, 16…Stacker, 17…Operation part, 17A…Power switch, 17B…Start switch, 17C…Stop switch, 18…Notification part, 19…Conveying path, 20…Conveying mechanism, 21…Feeding part, 22…Feeding guide, 23…Feeding roller, 24…Conveying part, 25…Feeding roller pair, 25A…Feeding drive roller, 25B…Feeding separation roller, 26…Conveying roller pair, 26A…Conveying drive roller, 26B…Conveying driven roller, 27…Discharge part, 28…Discharge roller pair, 28A…Discharge drive roller, 28B…Discharge driven roller, 29A…Feeding motor, 29B…Conveying motor, 30…Reading part, 30A…First reading part, 30B…Second reading part, 31A…First light source, 31B…Second light source, 32A…First image sensor, 32B…Second image sensor, 33A…First color reference plate, 33B…Second color reference plate, 34…Encoder, 35…First medium sensor, 36…Second medium sensor, 37…Double-feed sensor, 38…Transmitting element, 39…Receiving element, 40…Control part, 41…Double-feed detection circuit, 42…Transmission control circuit, 43…Drive circuit, 44…Receiving amplification circuit, 45…Receiving determination circuit, 51…First input terminal, 52…Second input terminal, 53…Output terminal, 54…Conversion circuit, 55…First current amplification circuit, 56…Boost circuit, 57…First adjustment circuit, 58…Push-pull circuit, 59…Second adjustment circuit, 60…Second current amplification circuit

Claims

1. A transmitting element capable of transmitting a signal for detecting duplicate transmission of a medium, A receiving element capable of receiving a signal for detecting duplicate transmission of a medium, A drive circuit configured to output a drive signal to the transmitting element, A control circuit configured to detect duplicate transmission of a medium based on the signal received by the receiving element, Comprising: The drive circuit: A conversion circuit that converts a reference signal into a conversion signal, A boosting circuit that boosts the conversion signal converted by the conversion circuit, A first adjustment circuit that adjusts the rising time of the conversion signal boosted by the boosting circuit to be longer, A push-pull circuit that outputs a drive signal obtained by amplifying the current of the conversion signal adjusted by the first adjustment circuit, A second adjustment circuit that adjusts the conversion signal input to the push-pull circuit, Having: The conversion signal converted by the conversion circuit is a signal whose voltage level is inverted compared to the reference signal, The push-pull circuit has a first N-type MOSFET and a second N-type MOSFET, and is a circuit in which the source terminal of the first N-type MOSFET is connected to the drain terminal of the second N-type MOSFET, The drive circuit is a circuit in which the conversion signal adjusted by the first adjustment circuit is input to the gate terminal of the first N-type MOSFET, while the reference signal is input to the gate terminal of the second N-type MOSFET, The second adjustment circuit advances the timing of the fall of the conversion signal input to the gate terminal of the first N-type MOSFET, A duplicate transmission detection device characterized by the above.

2. In the duplicate transmission detection device according to Claim 1, The control circuit is a circuit to which a first power supply voltage is supplied, The drive circuit is a circuit to which a second power supply voltage higher than the first power supply voltage is supplied, The conversion circuit converts a reference signal within a first voltage range equal to or lower than the first power supply voltage into a conversion signal within a second voltage range equal to or lower than the second power supply voltage and having a voltage level inverted compared to the reference signal, The boosting circuit can boost the conversion signal converted by the conversion circuit to a voltage higher than within the second voltage range, A duplicate transmission detection device characterized by the above.

3. In the duplicate transmission detection device according to Claim 1 or Claim 2, The drive circuit has a first current amplification circuit that amplifies the current of the conversion signal converted by the conversion circuit, A duplicate transmission detection device characterized by the above.

4. In the duplicate transmission detection device according to any one of claims 1 to 3, the drive circuit includes a second current amplification circuit that amplifies the current of the conversion signal input to the first N-type MOSFET. The first adjustment circuit has a predetermined resistor. The second current amplification circuit is connected in parallel with the first adjustment circuit. A duplicate transmission detection device characterized by the above.

5. In the duplicate transmission detection device according to any one of claims 1 to 4, the second adjustment circuit includes a third N-type MOSFET. The drive circuit is a circuit to which a reference signal is input to the gate terminal of the third N-type MOSFET. The third N-type MOSFET is driven to advance the falling timing of the conversion signal input to the gate terminal of the first N-type MOSFET. The third N-type MOSFET has a smaller total gate charge amount than the second N-type MOSFET. A duplicate transmission detection device characterized by the above.

6. In the duplicate transmission detection device according to any one of claims 1 to 5, the push-pull circuit includes a first gate resistor connected to the gate terminal of the first N-type MOSFET and a second gate resistor connected to the gate terminal of the second N-type MOSFET. The second adjustment circuit includes a third N-type MOSFET and a third gate resistor connected to the gate terminal of the third N-type MOSFET. The drive circuit is a circuit in which the conversion signal adjusted by the first adjustment circuit is input to the gate terminal of the first N-type MOSFET via the first gate resistor, while a reference signal is input to the gate terminal of the second N-type MOSFET via the second gate resistor, and a reference signal is input to the gate terminal of the third N-type MOSFET via the third gate resistor. The third N-type MOSFET is driven to advance the falling timing of the conversion signal input to the gate terminal of the first N-type MOSFET. The third gate resistor has a smaller resistance value than the second gate resistor. A duplicate transmission detection device characterized by the above.

7. In the duplicate transmission detection device according to any one of claims 1 to 6, the push-pull circuit has a protection circuit between the source terminal and the gate terminal of the first N-type MOSFET to protect the absolute maximum rating between the source terminal and the gate terminal of the first N-type MOSFET. A duplicate transmission detection device characterized by the above.

8. A retransmission detection device according to any one of Claims 1 to 7, and a conveyance unit configured to convey a medium, comprising: A conveyance device characterized by the above.

9. A retransmission detection device according to any one of Claims 1 to 7, and a reading unit configured to read an image of a medium, comprising: An image reading device characterized by the above.

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