Light-emitting display device

Abstract

To provide a technology with which a highly reliable display device can be manufactured at a low cost with high yield.SOLUTION: In the present invention, a spacer is formed over a pixel electrode, thereby protecting a pixel electrode layer from a mask in formation of an electroluminescent layer. In addition, since a layer that includes an organic material having water permeability is sealed in a display device with a sealing material and the sealing material and the layer that includes the organic material are not in contact, deterioration of a light-emitting element due to a contaminant such as water can be prevented. The sealing material is formed in a portion of a driver circuit region in the display device, so that the narrower frame margin of the display device can be also achieved.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the display device.

Background Art

[0002] When an EL element is driven for a certain period, there is a problem that light emission characteristics such as light emission luminance and light emission uniformity deteriorate significantly compared to the initial stage. This low reliability is a factor limiting the practical applications.

[0003] One of the factors deteriorating the reliability is moisture, oxygen, etc. that penetrate into the EL element from the outside.

[0004] Display devices having a structure for preventing deterioration of the EL element have been developed. Also, there is a method in which a sealing material is formed on an insulator on which the EL element is formed, and a sealed space surrounded by a cover material and the sealing material is filled with a filling material made of resin or the like to block from the outside (for example, see Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] An object of the present invention is to provide a technique capable of manufacturing a display device having high reliability and excellent electrical characteristics at low cost with good yield without complicating the process and the apparatus.

Means for Solving the Problems

[0007] In the present invention, the step of the opening in the contact is covered with an insulating layer to reduce the step, The wiring is formed in contact with the insulating layer, so the wiring coverage is In addition, the layer containing the organic material having water permeability (capable of passing moisture) is formed on the display device. Since the sealing material is sealed in the inside and the sealing material and the layer containing the organic material are not in contact with each other, the water in the light-emitting element can be prevented from being affected by the water. The sealant is placed in a part of the driving circuit area of ​​the display device. Therefore, it is possible to achieve a narrower frame of the display device.

[0008] Display devices in which the present invention can be used include electroluminescent (hereinafter "EL") displays. It is also called luminescence. It contains organic matter or a mixture of organic and inorganic matter that emits light. There is a light-emitting display device in which a light-emitting element having a layer interposed between electrodes is connected to a TFT.

[0009] A display device according to the present invention has a pixel region and a connection region, and the pixel region includes an impurity region. A semiconductor layer is provided, a gate insulating layer is provided on the semiconductor layer, and a gate electrode layer is provided on the gate insulating layer. a first interlayer insulating layer on the gate electrode layer, and the gate insulating layer and the first interlayer insulating layer The layer has a first opening that reaches the impurity region, and the opening has a source electrode layer or a drain electrode layer. The source electrode layer or the drain electrode layer is a part of the gate electrode layer with a first interlayer insulating layer interposed therebetween. a second interlayer insulating layer on the source electrode layer or the drain electrode layer and the first interlayer insulating layer; The second interlayer insulating layer has a second opening that reaches the source electrode layer or the drain electrode layer. the second opening is a source electrode covering a part of the gate electrode layer through the first interlayer insulating layer. A first electrode layer is provided on the drain electrode layer and has a spacer in the second opening. and has a wiring layer provided on the first interlayer insulating layer in the connection region, and on the wiring layer, a second interlayer insulating layer having a third opening reaching the wiring layer is provided, and the upper end portion of the third opening is covered by the insulating layer, and the third opening has a second electrode layer in contact with the insulating layer. One of the display devices of the present invention has a pixel region and a connection region, and has a semiconductor layer including an impurity region in the pixel region.

[0010] On the semiconductor layer, there is a gate insulating layer, on the gate insulating layer, there is a gate electrode layer. On the gate electrode layer, there is a first interlayer insulating layer. The gate insulating layer and the first interlayer insulating layer have a first opening reaching the impurity region, and in the opening, there is a source electrode layer or a drain electrode layer. The source electrode layer or the drain electrode layer covers a part of the gate electrode layer through the first interlayer insulating layer. On the source electrode layer or the drain electrode layer and the first interlayer insulating layer, there is a second interlayer insulating layer. The second interlayer insulating layer has a second opening reaching the source electrode layer or the drain electrode layer. The second opening is provided in the source electrode layer or the drain electrode layer that covers a part of the gate electrode layer through the first interlayer insulating layer. The second opening has a first electrode layer having a spacer. In the connection region, there is a wiring layer provided on the first interlayer insulating layer. On the wiring layer, there is a second interlayer insulating layer having a third opening reaching the wiring layer. The upper end portion of the third opening is covered by the insulating layer. In the third opening, there is a second electrode layer in contact with the insulating layer. On the first interlayer insulating layer, there is a sealing material. The sealing material does not contact the insulating layer.

[0011]

[0011] In the above configuration, the spacer and the insulating layer may be separated as shown in FIG. 18, or may be continuously connected as shown in FIG. 22. The spacer may function as a pixel electrode layer. When forming an electroluminescent layer on the first electrode layer, the spacer is used as a spacer for a mask to be used. Even after the electroluminescent layer is formed and the display device is completed by sealing with a sealing substrate, It functions as a spacer to prevent the device from being damaged or deformed by external pressure or impact.

[0012] A display device according to the present invention has a pixel region and a connection region, and the pixel region includes an impurity region. A semiconductor layer is provided, a gate insulating layer is provided on the semiconductor layer, and a gate electrode layer is provided on the gate insulating layer. a first interlayer insulating layer on the gate electrode layer, and the gate insulating layer and the first interlayer insulating layer The layer has a first opening that reaches the impurity region, and the opening has a source electrode layer or a drain electrode layer. The source electrode layer or the drain electrode layer is a part of the gate electrode layer with a first interlayer insulating layer interposed therebetween. a second interlayer insulating layer on the source electrode layer or the drain electrode layer and the first interlayer insulating layer; The second interlayer insulating layer has a second opening that reaches the source electrode layer or the drain electrode layer. the second opening is a source electrode covering a part of the gate electrode layer through the first interlayer insulating layer. The second opening has a first electrode layer and the second opening has a second electrode layer. a wiring layer provided on the first interlayer insulating layer, and a third opening is provided on the wiring layer, the third opening reaching the wiring layer; The upper end of the third opening is covered with an insulating layer. A second electrode layer is provided in contact with the insulating layer in the opening of the third insulating layer, and a sealant is provided on the first interlayer insulating layer. The sealing material does not come into contact with the insulating layer.

[0013] One of the manufacturing methods of the display device of the present invention is to form a semiconductor layer having an impurity region in a pixel region. A gate insulating layer is formed on the connection region and the semiconductor layer, and a gate electrode layer and a Form a conductive layer, form a first interlayer insulating layer on the gate electrode layer and the conductive layer, and form a gate insulating layer and the first interlayer insulating layer have a first opening reaching the impurity region, and cover the first opening and a part of the gate electrode layer to form a source electrode layer or a drain electrode layer. Form a wiring layer covering the conductive layer on the first interlayer insulating layer, form a second interlayer insulating layer on the first interlayer insulating layer, the wiring layer, the source electrode layer and the drain electrode layer. Form a second opening reaching the source electrode layer or the drain electrode layer and a third opening reaching the wiring layer in the second interlayer insulating layer. Form a first electrode layer in the second opening, form an insulating layer covering the upper end of the third opening of the second interlayer insulating layer and a part of the first electrode layer, form a spacer on the first electrode layer, and form a second electrode layer in contact with the insulating layer in the third opening. One method for manufacturing the display device of the present invention is to form a semiconductor layer having an impurity region in the pixel region, form a gate insulating layer on the connection region and the semiconductor layer, form a gate electrode layer and a conductive layer on the gate insulating layer,

[0014] form a first interlayer insulating layer on the gate electrode layer and the conductive layer. The gate insulating layer and the first interlayer insulating layer have a first opening reaching the impurity region, and cover the first opening and a part of the gate electrode layer to form a source electrode layer or a drain electrode layer. Form a wiring layer covering the conductive layer on the first interlayer insulating layer, form a second interlayer insulating layer on the first interlayer insulating layer, the wiring layer, the source electrode layer and the drain electrode layer. The gate insulating layer and the first interlayer insulating layer have a first opening reaching the impurity region, and cover the first opening and a part of the gate electrode layer to form a source electrode layer or a drain electrode layer. Form a wiring layer covering the conductive layer on the first interlayer insulating layer, form a second interlayer insulating layer on the first interlayer insulating layer, the wiring layer, the source electrode layer and the drain electrode layer. Form a second opening reaching the source electrode layer or the drain electrode layer and a third opening reaching the wiring layer in the second interlayer insulating layer. Form a first electrode layer in the second opening, form an insulating layer covering the upper end of the third opening of the second interlayer insulating layer and a part of the first electrode layer, form a spacer on the first electrode layer, and form a second electrode layer in contact with the insulating layer in the third opening. covering the upper end of the third opening of the second interlayer insulating layer and a part of the first electrode layer to form an insulating layer, forming a spacer on the first electrode layer, and forming a second electrode layer in contact with the insulating layer in the third opening. to form a second electrode layer and form a sealing material on the first interlayer insulating layer without contacting the insulating layer. to do.

[0015] One of the manufacturing methods of the display device of the present invention is to form a semiconductor layer having an impurity region in a pixel region to form a gate insulating layer on the connection region and the semiconductor layer, and form a gate electrode layer and a conductive layer on the gate insulating layer, form a first interlayer insulating layer on the gate electrode layer and the conductive layer, and the gate insulating layer and the first interlayer insulating layer have a first opening reaching the impurity region, and cover the first opening and a part of the gate electrode layer to form a source electrode layer or a drain electrode layer, form a wiring layer covering the conductive layer on the first interlayer insulating layer, and form a second interlayer insulating layer on the first interlayer insulating layer, the wiring layer, the source electrode layer, and the drain electrode layer, form a second opening reaching the source electrode layer or the drain electrode layer and a third opening reaching the wiring layer in the second interlayer insulating layer, form a first electrode layer in the second opening, and cover the upper end portion of the third opening of the second interlayer insulating layer and a part of the first electrode layer to form an insulating layer, form a second electrode layer in contact with the insulating layer in the third opening, and form a sealing material on the first interlayer insulating layer without contacting the insulating layer. to do. to do. to form an insulating layer, form a second electrode layer in contact with the insulating layer in the third opening, and form a sealing material on the first interlayer insulating layer without contacting the insulating layer. to do.

[0016] In the above configuration, the spacer and the insulating layer may be formed in separate processes, or may be formed in the same process using the same material. to do.

Advantages of the Invention

[0017] When the present invention is used, a highly reliable display device can be manufactured in a simplified process. Therefore, a high-definition and high-quality display device can be manufactured with high yield at low cost. to do.

Brief Description of the Drawings

[0018]

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[0019] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made thereto. The present invention is not limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. will be used throughout and a repeated explanation will be omitted.

[0020] (Embodiment 1) A manufacturing method of a thin film transistor in this embodiment will be described in detail with reference to FIGS. explain.

[0021] FIG. 16(A) is a top view showing the structure of a display panel according to the present invention, which has an insulating surface. A pixel section 2701 in which pixels 2702 are arranged in a matrix on a substrate 2700, An input terminal 2703 and a signal line side input terminal 2704 are formed. The number of pixels varies according to various standards. Therefore, it is sufficient to set it, and for XGA it is 1024 x 768 x 3 (RGB), and for UXGA it is If it is compatible with full-spec high definition, it will be 1600 x 1200 x 3 (RGB). For example, 1920 x 1080 x 3 (RGB) should be fine.

[0022] The pixel 2702 is connected to a scanning line extending from a scanning line input terminal 2703 and a signal line input terminal The signal lines extending from the pixel 2704 intersect with each other, forming a matrix arrangement. Each of the 702 is provided with a switching element and a pixel electrode layer connected thereto. . A typical example of a switching element is a TFT, and when the gate electrode layer side of the TFT is connected to a scanning line and the source or drain side is connected to a signal line, each pixel can be independently controlled by a signal input from the outside.

[0023] The main components of a TFT include a semiconductor layer, a gate insulating layer, and a gate electrode layer. A wiring layer connected to the source and drain regions formed in the semiconductor layer is attached thereto. Structurally, a top gate type in which the semiconductor layer, the gate insulating layer, and the gate electrode layer are arranged from the substrate side, and a bottom gate type in which the gate electrode layer, the gate insulating layer, and the semiconductor layer are arranged from the substrate side are typically known. However, in the present invention, any of these structures may be used.

[0024] FIG. 16(A) shows the configuration of a display panel in which signals input to the scanning line and the signal line are controlled by an external drive circuit. However, as shown in FIG. 17(A), a driver IC 2751 may be mounted on a substrate 2700 by a COG (Chip on Glass) method. As another mounting form, a TAB (Tape Automated Bonding) method as shown in FIG. 17(B) may be used. The driver IC may be formed on a single crystal semiconductor substrate or may be a circuit formed by TFTs on a glass substrate. In FIG. 17, the driver IC 2751 is connected to an FPC (Flexible printed circuit) 2750.

[0025] Further, when the TFT provided in the pixel is formed of a crystalline semiconductor, as shown in FIG. 16(B). ) As shown in (), the scanning line side drive circuit 3702 can also be formed on the substrate 3700. FIG In 16(B), the pixel portion 3701 is controlled by an external drive circuit in the same manner as in FIG. 16( A) connected to the signal line side input terminal 3704. When the TFT provided in the pixel is formed of a highly mobile, poly crystalline (microcrystalline) semiconductor, single crystal semiconductor, etc., FIG. 16(C) shows the pixel portion 4 701, the scanning line drive circuit 4702, and the signal line drive circuit 4704 can also be integrally formed on the substrate 4700 .

[0026] As shown in FIG. 2, on the substrate 100 having an insulating surface, as an underlayer film, by sputtering method, PVD method (Physical Vapor Deposition), reduced pressure CVD method (LPCVD method), or also by CVD method (Chemical Vapor Deposition) such as plasma CVD method, a silicon oxynitride film (SiNO) is used to form the underlayer film 101a with a thickness of 10 to 200 nm (preferably 50 to 100 nm), and a silicon oxynitride film (SiON) is used to laminate the underlayer film 101b with a thickness of 50 to 200 nm (preferably 100 to 150 nm). In the present embodiment, the underlayer film 101a and the underlayer film 101b are formed by using the plasma CVD method . As the substrate 100, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a substrate having an insulating film formed on the surface of a stainless steel substrate may be used . Further, a plastic substrate having heat resistance capable of withstanding the processing temperature of the present embodiment may be used, or a flexible substrate such as a film may be used. As the plastic substrate , PET (polyethylene terephthalate), PEN (polyethylene naphthalate), P ES (polyethersulfone) substrate, and as the flexible substrate, a synthetic resin such as acrylic can be used

[0027] As the underlayer film, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. can be used and it may be a single layer or a laminated structure such as a two-layer or three-layer structure. In this specification, silicon oxynitride refers to a substance in which the composition ratio of oxygen is larger than the composition ratio of nitrogen, and can also be said to be silicon oxide containing nitrogen. Similarly, silicon nitride oxide refers to a substance in which the composition ratio of nitrogen is larger than the composition ratio of oxygen, and can also be said to be silicon nitride containing oxygen. In this embodiment, a silicon nitride oxide film with a film thickness of 50 nm is formed on the substrate using SiH4, NH3, N2O, N2 and H2 as reaction gases, and a silicon oxynitride film with a film thickness of 100 nm is formed using SiH4 and N2O as reaction gases. Further, the film thickness of the silicon nitride oxide film may be 140 nm, and the film thickness of the laminated silicon oxynitride film may be 100 nm.

[0028] Next, a semiconductor film is formed on the underlayer film. The semiconductor film has a thickness of 25 to 200 nm (preferably 30 to 150 nm) and may be formed by known means (such as sputtering method, LPCVD method, or plasma CVD method, etc.). In this embodiment, it is preferable to use an amorphous semiconductor film that is laser crystallized to form a crystalline semiconductor film.

[0029] As the material for forming the semiconductor film, an amorphous semiconductor (hereinafter also referred to as "amorphous semiconductor: AS") produced by a vapor phase growth method or a sputtering method using a semiconductor material gas typified by silane or germanium, a polycrystalline semiconductor obtained by crystallizing the amorphous semiconductor using light energy or thermal energy, or a semi-amorphous (also called microcrystalline or microcrystal. Hereinafter also referred to as "SAS") semiconductor, etc. can be used.

[0030] SAS has an intermediate structure between amorphous and crystalline structures (including single crystals and polycrystals), and free energy has a third stable state, has short-range order and lattice strain contains crystalline regions. In at least some regions of the film, crystal regions of 0.5 to 20 nm can be observed, and when silicon is the main component, the Raman spectrum is at 52 0 cm -1 shifted to lower wavenumbers than. In X-ray diffraction, diffraction peaks of (111) and (220) derived from the silicon crystal lattice are observed. To terminate unbonded hands (dangling bonds), at least 1 atomic% or more of hydrogen or halogen is included . SAS is formed by glow discharge decomposition (plasma CVD) of silicide gas. As the silicide gas , SiH4, and in addition, Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be used. Also, F2 and GeF4 may be mixed. This silicide gas may be diluted with H2, or one or more noble gas elements selected from H2, He, Ar, Kr, and Ne. The dilution ratio is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 1 33 Pa, the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 M Hz. The substrate heating temperature is preferably 300 °C or lower, and a substrate heating temperature of 100 to 200 °C is also possible. Here, as the impurity elements mainly incorporated during film formation, impurities derived from atmospheric components such as oxygen, nitrogen , and carbon are desirably 1×10 cm or less, and 20 cm -3 in particular, the oxygen concentration is 5×10 cm 19 or less, preferably 1×10 -3 cm 19 or less so that -3 . It is preferable to do so. Also, noble gas elements such as helium, argon, krypton, and neon can be included to further promote lattice strain, thereby increasing stability and obtaining good SAS. Also an SAS layer formed from a silicide gas containing hydrogen may be laminated on an SAS layer formed from a silicide gas containing fluorine as a semiconductor film.

[0031] Typical examples of amorphous semiconductors include hydrogenated amorphous silicon, and typical examples of crystalline semiconductors include polysilicon. Polysilicon (polycrystalline silicon) includes so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 °C or higher as the main material, so-called low-temperature polysilicon using polysilicon formed at a process temperature of 600 °C or lower as the main material, and polycrystalline silicon obtained by adding elements that promote crystallization and crystallizing it. Of course, as described above, semi-amorphous semiconductors or semiconductors containing a crystalline phase in a part of the semiconductor film can also be used.

[0032] When using large substrates such as 30 inches and 40 inches, using an amorphous semiconductor such as amorphous silicon results in less complex processes and good productivity.

[0033] When using a crystalline semiconductor film for the semiconductor film, the manufacturing method of the crystalline semiconductor film can be a known method (laser crystallization method, thermal crystallization method, or thermal crystallization method using elements that promote crystallization such as nickel, etc.). Also, a microcrystalline semiconductor that is SAS can be irradiated with laser light to crystallize and increase crystallinity. When elements that promote crystallization are not introduced, before irradiating the amorphous semiconductor film with laser light, it is heated at 500 °C for 1 hour in a nitrogen atmosphere. ​​​​​Therefore, the hydrogen concentration in the amorphous semiconductor film can be released to 1×10 20 atoms / cm 3 or less. This is because when a laser beam is irradiated on an amorphous semiconductor film containing a large amount of hydrogen, the amorphous semiconductor film will be damaged. The heat treatment for crystallization can use a heating furnace, laser irradiation, or irradiation with light emitted from a lamp (also called lamp annealing), etc. As heating methods, there are RTA methods such as the GRTA (Gas Rapid Thermal Anneal) method using heated gas and the LRTA (Lamp Rapid Thermal Anneal) method using light from a lamp. For the method of introducing a metal element into the amorphous semiconductor film, there is no particular limitation as long as it is a method that can cause the metal element to exist on the surface or inside of the amorphous semiconductor film. For example, sputtering method, C VD method, plasma treatment method (including plasma CVD method), adsorption method, and a method of applying a solution of a metal salt can be used. Among these, the method using a solution is simple and useful in that it is easy to adjust the concentration of the metal element. Also, at this time, in order to improve the wettability of the surface of the amorphous semiconductor film and make the aqueous solution spread over the entire surface of the amorphous semiconductor film, it is desirable to form an oxide film by irradiation with UV light in an oxygen atmosphere, thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals, etc. By using a solid-state laser capable of continuous oscillation and irradiating laser light of the second to fourth harmonics of the fundamental wave, large-grained crystals can be obtained. For example, typically, the second harmonic (532 nm) or the third harmonic (355 nm) of a Nd:YVO4

[0034] laser (fundamental wave 1064 nm) can be used.

[0035]

[0035] ​​​​​​It is desirable to use. Specifically, the laser light emitted from a continuously oscillating YVO4 laser is converted into harmonics by a nonlinear optical element to obtain laser light with an output of several W or more. Then, preferably it is shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. The energy density at this time is about 0.001 to 100 MW / cm 2 (preferably 0.1 to 10 MW / cm 2 ) is required. And the scanning speed is set to about 0.5 to 2000 cm / sec (preferably 10 to 200 cm / sec) and irradiated.

[0036] The beam shape of the laser is preferably linear. As a result, the throughput can be improved. Furthermore, the laser is preferably irradiated with an incident angle θ (0 < θ < 90 degrees) with respect to the semiconductor film. This is because laser interference can be prevented.

[0037] By relatively scanning such a laser and the semiconductor film, laser irradiation can be performed. In addition, in laser irradiation, a marker can also be formed in order to accurately overlap the beams or control the laser irradiation start position and the laser irradiation end position. The marker may be formed on the substrate simultaneously with the amorphous semiconductor film.

[0038] Note that as the laser, a gas laser, a solid laser, a copper vapor laser or a gold vapor laser that oscillates continuously or in pulses can be used. Examples of gas lasers include excimer lasers, Ar lasers, Kr lasers, He-Cd lasers, etc. Examples of solid lasers include YAG lasers , YVO4 lasers, YLF lasers, YAlO3 lasers, Y2O3 lasers, glass lasers, ruby ​​Examples include a laser, an alexandrite laser, a Ti:sapphire laser, etc.

[0039] Also, the oscillation frequency of the pulsed laser light is set to 0.5 MHz or more, and laser crystallization may be performed using a frequency band that is significantly higher than the frequency band of several tens of Hz to several hundreds of Hz that is usually used. After irradiating the semiconductor film with the pulsed laser light, the time until the semiconductor film is completely solidified is said to be several tens of nsec to several hundreds of nsec. Therefore, by using the above frequency band, before the semiconductor film solidifies after being melted by the laser light, the next pulsed laser light can be irradiated. Therefore, it is possible to continuously move the solid-liquid interface in the semiconductor film, so that a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, it is possible to form an aggregate of crystal grains having a width in the scanning direction of 10 to 30 μm and a width in a direction perpendicular to the scanning direction of about 1 to 5 μm. By forming a single crystal grain that extends long along the scanning direction, it is possible to form a semiconductor film in which there are almost no grain boundaries in at least the channel direction of the thin film transistor. Also, the laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. This can suppress roughening of the semiconductor surface due to the irradiation of the laser light, and can suppress variations in the threshold value caused by variations in the interface state density. The crystallization of the amorphous semiconductor film may be a combination of heat treatment and crystallization by laser light irradiation, or heat treatment or laser light irradiation may be performed alone or multiple times.

[0040]

[0041]

[0042] ​​​​​In this embodiment, an amorphous semiconductor film is formed on the base film 101b, and the amorphous semiconductor film is crystallized to form a crystalline semiconductor film. As the amorphous semiconductor film, amorphous silicon formed by a reaction gas of Si H4 and H2 is used. In this embodiment, the base film 101a, the base film 101b, and the amorphous semiconductor film are continuously formed while switching the reaction gas at the same temperature of 330 °C without breaking the vacuum in the same chamber (while maintaining the vacuum state).

[0043] After removing the oxide film formed on the amorphous semiconductor film, UV light irradiation in an oxygen atmosphere , a thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals, etc., are used to form an oxide film with a thickness of 1 to 5 nm. In this embodiment, Ni is used as an element that promotes crystallization . An aqueous solution containing 10 ppm of Ni acetate is applied by a spin coating method.

[0044] In this embodiment, after performing heat treatment at 650 °C for 6 minutes by the RTA method, the oxide film formed on the semiconductor film is removed, and laser light is irradiated. The amorphous semiconductor film is crystallized by the above crystallization treatment and is formed as a crystalline semiconductor film.

[0045] When crystallization using a metal element is performed, a getter ring process is performed to reduce or remove the metal element. In this embodiment, the amorphous semiconductor film is used as a getter sink to capture the metal element. First, an oxide film is formed on the crystalline semiconductor film by UV light irradiation in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals, etc. The oxide film is desirably thickened by heat treatment. In this embodiment, the oxide film formation ​After formation, heat treatment is performed at 650°C for 6 minutes by the RTA method to thicken the oxide film. Next, the plasma CVD method (conditions in this embodiment: 350 W, 35 Pa) is used to form an amorphous semiconductor film with a film thickness of 30 nm.

[0046] Thereafter, heat treatment is performed at 650°C for 6 minutes by the RTA method to reduce or remove metal elements. The heat treatment may be performed in a nitrogen atmosphere. Then, the amorphous semiconductor film that has served as a gettering sink and the oxide film formed on the amorphous semiconductor film are removed with hydrofluoric acid or the like, and a crystalline semiconductor film 102 with reduced or removed metal elements can be obtained (see Fig. 2(A)). (.). In this embodiment, the removal of the amorphous semiconductor film that has served as a gettering sink is performed using TMAH (Tetramethyl ammonium hydroxide).

[0047] For the semiconductor film thus obtained, doping with a trace amount of impurity elements (boron or phosphorus) may be performed to control the threshold voltage of the thin film transistor. This doping with impurity elements may be performed on the amorphous semiconductor film before the crystallization step. When doping impurity elements in the state of the amorphous semiconductor film, activation of the impurities can also be performed by the subsequent heat treatment for crystallization. In addition, defects and the like generated during doping can also be improved.

[0048] Next, the crystalline semiconductor film 102 is processed into a desired shape using a mask. In this embodiment, after removing the oxide film formed on the crystalline semiconductor film 102, a new oxide film is formed. Then, a photomask is fabricated, and by a processing treatment using the photolithography method, the semiconductor Layers 103, semiconductor layer 104, semiconductor layer 105, and semiconductor layer 106 are formed.

[0049] For the etching process, either plasma etching (dry etching) or wet etching may be adopted. However, plasma etching is suitable for processing large-area substrates. As the etching gas, gases containing fluorine such as CF4 and NF3, gases containing chlorine such as Cl2 and BCl3 can be used, and inert gases such as He and Ar may be appropriately added. Also, if atmospheric pressure discharge etching is applied, local discharge processing is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate. In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, etc. may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. The droplet discharge (ejection) method (depending on the method, it is also called an inkjet method.) can selectively discharge (eject) droplets of a composition prepared for a specific purpose to form a predetermined

[0050] pattern (such as a conductive layer or an insulating layer). At this time, a process for controlling the wettability and adhesion to the formation region may be performed. Also, a method by which a pattern can be transferred or drawn, for example, a printing method (methods for forming a pattern such as screen printing and offset printing), etc. can also be used. In this embodiment, as the mask used, resin materials such as epoxy resin, acrylic resin, phenolic resin, novolak resin, melamine resin, and urethane resin are used. Also, organic materials such as benzocyclobutene, parylene, flare, and permeable polyimide, siloxane In this embodiment, as the mask used, resin materials such as epoxy resin, acrylic resin, phenolic resin, novolak resin, melamine resin, and urethane resin are used. Also, organic materials such as benzocyclobutene, parylene, flare, and permeable polyimide, siloxane In this embodiment, as the mask used, resin materials such as epoxy resin, acrylic resin, phenolic resin, novolak resin, melamine resin, and urethane resin are used. Also, organic materials such as benzocyclobutene, parylene, flare, and permeable polyimide, siloxane In this embodiment, as the mask used, resin materials such as epoxy resin, acrylic resin, phenolic resin, novolak resin, melamine resin, and urethane resin are used. Also, organic materials such as benzocyclobutene, parylene, flare, and permeable polyimide, siloxane can also be used.

[0051] In this embodiment, as the mask used, resin materials such as epoxy resin, acrylic resin, phenolic resin, novolak resin, melamine resin, and urethane resin are used. Also, organic materials such as benzocyclobutene, parylene, flare, and permeable polyimide, siloxane In this embodiment, as the mask used, resin materials such as epoxy resin, acrylic resin, phenolic resin, novolak resin, melamine resin, and urethane resin are used. Also, organic materials such as benzocyclobutene, parylene, flare, and permeable polyimide, siloxane In this embodiment, as the mask used, resin materials such as epoxy resin, acrylic resin, phenolic resin, novolak resin, melamine resin, and urethane resin are used. Also, organic materials such as benzocyclobutene, parylene, flare, and permeable polyimide, siloxane Compound materials made by polymerization of olefin polymers, water-soluble homopolymers and water-soluble copolymers Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a typical positive resist is a mixture of novolac resin and a photosensitive agent, such as naphthalene. Resist containing phthalocyanine diazide compound, negative resist base resin, diphenyl A resist containing silanediol and an acid generator may be used. In this case, regardless of the material used, the surface tension and viscosity can be adjusted by adjusting the concentration of the solvent, The amount of the surfactant may be appropriately adjusted.

[0052] The oxide film on the semiconductor layer is removed, and the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, A gate insulating layer 107 is formed to cover the semiconductor layer 106. The gate insulating layer 107 is a plasma A silicon-containing insulating film is formed to a thickness of 10 to 150 nm using a CVD method or a sputtering method. The gate insulating layer 107 is formed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a nitride film, or the like. It may be formed of a known material such as a silicon oxide material, a silicon nitride material, or the like. In this embodiment mode, the gate insulating layer is a silicon nitride film, a silicon oxide film, A three-layer stack of silicon nitride films is used. In addition, a single layer or two layers of silicon oxynitride films are used. A laminated film may be used. Preferably, a silicon nitride film having a dense film quality is used. Furthermore, a semiconductor Between the gate insulating layer and the gate insulating layer, a thickness of 1 to 100 nm is preferably 1 to 10 nm, and more preferably A thin silicon oxide film having a thickness of about 2 to 5 nm may be formed. The method is to oxidize the surface of the semiconductor region using the GRTA method, LRTA method, etc., to form a thermal oxide film. By forming the silicon oxide film at a low temperature, a thin silicon oxide film can be formed. To form a dense insulating film with low leakage current, it is advisable to include a noble gas element such as argon in the reaction gas and incorporate it into the formed insulating film. Next, a first conductive film 108 with a thickness of 20 to 100 nm and a second conductive film 109 with a thickness of 100 to 400 nm, which are used as the gate electrode layer, are laminated on the gate insulating layer 107.

[0053] (See Fig. 2(B).) The first conductive film 108 and the second conductive film 109 can be formed by known methods such as sputtering, evaporation, and CVD. The first conductive film 108 and the second conductive film 109 may be formed of an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd), or an alloy material or compound material mainly composed of the above elements. Further, as the first conductive film 108 and the second conductive film 109, a semiconductor film typified by a polycrystalline silicon film doped with impurity elements such as phosphorus, or an AgPdCu alloy may be used. Moreover, it is not limited to a two-layer structure. For example, a three-layer structure in which a tungsten film with a thickness of 50 nm is sequentially laminated as the first conductive film, an alloy of aluminum and silicon (Al-Si) film with a thickness of 500 nm is used as the second conductive film, and a titanium nitride film with a thickness of 30 nm is used as the third conductive film may be employed. When a three-layer structure is adopted, tungsten nitride may be used instead of tungsten for the first conductive film, an alloy film of aluminum and titanium (Al-Ti) may be used instead of the alloy of aluminum and silicon (Al-Si) film for the second conductive film, and a titanium film may be used instead of the titanium nitride film for the third conductive film. Also, a single-layer structure may be used. ​​​​​​​​​​In the embodiment, tantalum nitride (TaN) is formed as the first conductive film 106 with a film thickness of 30 nm. Then, tungsten (W) is formed as the second conductive film 107 with a film thickness of 370 nm.

[0054] Next, masks 110a, 110b, 110c, 110d, and 110f made of resist are formed using photolithography, and the first conductive film 108 and the second conductive film 109 are processed into a desired shape to form the first gate electrode layer 121, the first gate electrode layer 122, the conductive layer 123, the first gate electrode layer 124, the first gate electrode layer 125, and the first gate electrode layer 126, as well as the conductive layers 111, 112, 113, 114, 115, and 116 (see Fig. 2(C)). Using the ICP (Inductively Coupled Plasma) etching method, by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode layer, the amount of power applied to the electrode layer on the substrate side, the electrode temperature on the substrate side, etc.), the first gate electrode layer 121, the first gate electrode layer 122, the conductive layer 123, the first gate electrode layer 124, the first gate electrode layer 125, and the first gate electrode layer 126, as well as the conductive layers 111, 112, 113, 114, 115, and 116 can be etched to have a desired tapered shape. Also, the tapered shape can be controlled in terms of angle, etc. according to the shapes of the masks 110a, 110b, 110c, 110d, and 110f. Note that as the etching gas, chlorine-based gases represented by Cl2, BCl3, SiCl4, or CCl4, or fluorine-based gases represented by CF4, SF6, or NF3, etc. Appropriate fluorine-based gas or O2 can be used. In this embodiment, etching gas composed of CF4, Cl2, O2 is used to etch the second conductive film 109, and then etching gas composed of CF4 and Cl2 is used to etch the first conductive film 108 continuously. .

[0055] Next, using mask 110a, mask 110b, mask 110c, mask 110d, and mask 110f, conductive layers 111, 112, 113, 114, conductive layers 115, and conductive layer 116 are processed into a desired shape. At this time, etching is performed on the conductive layers under high etching conditions with a high selectivity ratio between the second conductive film 109 forming the conductive layer and the first conductive film 108 forming the first gate electrode layer. By this etching, conductive layers 111, 112, 113, 114, 115, and 116 are etched, and the second gate electrode layers 131, 132, conductive layer 133, second gate electrode layer 134, second gate electrode layer 135, and second gate electrode layer 136 are formed. In this embodiment, the third conductive layer also has a tapered shape, but its taper angle is larger than the taper angles of the first gate electrode layers 121, 122, conductive layer 123, first gate electrode layer 124, first gate electrode layer 125, and first gate electrode layer 126. Note that the taper angle is the angle of the side surface with respect to the surface of the first gate electrode layer, the second gate electrode layer, and the conductive layer. Therefore, by increasing the taper angle, when it is 90 degrees, the conductive layer has a vertical side surface and no longer has a tapered shape. In this embodiment, Cl2, SF6, and O2 are used as the etching gas for forming the second gate electrode layer. ​​​​​​​

[0056] In this embodiment, the first gate electrode layer, the conductive layer, and the second gate electrode layer are formed to have a tapered - shape, so both of the two-layer gate electrode layers have a tapered shape. However, the present invention is not limited thereto, and only one of the gate electrode layers may have a tapered shape, and the other may have a vertical side surface by anisotropic etching. As in this embodiment, the taper angle may be different or the same between the stacked gate electrode layers. By having a tapered shape, the covering property of the film laminated thereon is improved, and defects are reduced so that the reliability is improved.

[0057] Through the above steps, in the peripheral drive circuit region 204, the gate electrode layer 117 composed of the first gate electrode layer 121 and the second gate electrode layer 131, the gate electrode layer 118 composed of the first gate electrode layer 122 and the second gate electrode layer 132, in the pixel region 206, the gate electrode layer 127 composed of the first gate electrode layer 124 and the second gate electrode layer 134, the gate electrode layer 128 composed of the first gate electrode layer 125 and the second gate electrode layer 135, the gate electrode layer 129 composed of the first gate electrode layer 126 and the second gate electrode layer 136, and in the connection region 205, the conductive layer 130 composed of the conductive layer 123 and the conductive layer 133 can be formed (see Fig. 2(D ).). In this embodiment, the gate electrode layer is formed by dry etching, but wet etching may also be used.

[0058] By the etching process when forming the gate electrode layer, the gate insulating layer 107 may be slightly etched and its film thickness may decrease (the film thickness becomes thinner, so-called film thinning).

[0059] When forming the gate electrode layer, the width of the gate electrode layer is narrowed to achieve high speed operation. The gate electrode layer is thinned in the channel direction to form a thin film transistor. Two methods for forming the junction are shown below.

[0060] In the first method, a mask for the gate electrode layer is formed, and then the mask is etched in the width direction. The mask is then thinned by cutting or other methods to form a thinner mask. By using the formed mask, the gate electrode layer can also be formed to have a narrow width. Cut.

[0061] Then, the second method forms a mask and uses the mask to form a gate electrode layer. Next, the gate electrode layer is thinned further in the width direction by side etching. By going through the above steps, a gate electrode layer having a narrow width can be formed. It is possible to form thin-film transistors with short channel lengths in a single layer, enabling high-speed operation. It is possible to fabricate thin film transistors.

[0062] Next, the gate electrode layer 117, the gate electrode layer 118, the gate electrode layer 127, and the gate electrode layer 128, a gate electrode layer 129, and a conductive layer 130 are used as a mask to form an n-type impurity element. 151 is added to form the first n-type impurity region 140a, the first n-type impurity region 140b, and the first The first n-type impurity region 141a, the first n-type impurity region 141b, and the first n-type impurity region 14 2a, the first n-type impurity region 142b, the first n-type impurity region 142c, the first n-type impurity In this embodiment, a first n-type impurity region 143a and a second n-type impurity region 143b are formed (see FIG. 3(A)). In the embodiment, phosphine (PH3) (doping gas) containing an impurity element is used. The group V gas dilutes PH3 with hydrogen (H2), and the ratio of PH3 in the gas is 5%). Using this, the gas flow rate is 80 sccm, the beam current is 54 μA / cm, the acceleration voltage is 50 kV, and the dose amount to be added is 7.0×10 13 ions / cm 2 doping is performed under these conditions. Here, the first n-type impurity regions 140a, the first n-type impurity region 140b, the first n-type impurity region 141a, the first n-type impurity region 141b, the first n-type impurity region 142a, the first n-type impurity region 14 2b, the first n-type impurity region 142c, the first n-type impurity region 143a, the first n-type impurity regions 143b are doped with an impurity element that imparts an n-type with a concentration of 1×10 17 to 5×10 18 / cm 3 or so. In this embodiment, phosphorus (P) is used as the impurity element that imparts an n-type.

[0063] In this embodiment, the region where the impurity region overlaps the gate electrode layer via the gate insulating layer is denoted as the L ov region, and the region where the impurity region does not overlap the gate electrode layer via the gate insulating layer is denoted as the L off region. In FIG. 3, the impurity region is shown by hatching and white areas, but this does not indicate that no impurity element is added to the white area. Instead, it is to make it intuitively understandable that the concentration distribution of the impurity element in this region reflects the mask and doping conditions. Note that this is the same for other drawings in this specification.

[0064] Next, masks 153a , mask 153b, mask 153c, and mask 153d that cover the semiconductor layer 103, a part of the semiconductor layer 105, and the semiconductor layer 106 are formed. Masks 153a, A mask 153b, a mask 153c, a mask 153d, and a mask for the second gate electrode layer 132 are formed. An impurity element 152 that imparts n-type conductivity is added to form a second n-type impurity region 144 a and a second The first n-type impurity region 144b, the second n-type impurity region 145a, and the third n-type impurity region 14 5b, the second n-type impurity region 147a, the second n-type impurity region 147b, the second n-type impurity The third n-type impurity region 147c, the third n-type impurity region 148a, the third n-type impurity region 148b, the third In this embodiment, a first n-type impurity region 148c and a third n-type impurity region 148d are formed. The doping gas containing impurity elements is PH3 (doping gas is PH3 hydrogen (H 2) was used, and the ratio of PH3 in the gas was 5%. The gas flow rate was 80 sccm, and the beam Current 540μA / cm, acceleration voltage 70kV, dose 5.0×10 15 ions / cm 2 Here, the doping is performed under the condition of the second n-type impurity region 144a, the second The impurity element that imparts n-type to the n-type impurity region 144b is 5×10 19 ~5×10 20 / cm 3 The third impurity region 145a is doped so as to have a concentration of about 45b includes the third n-type impurity region 148a, the third n-type impurity region 148b, and the third n-type The impurity region 148c has a concentration similar to or slightly higher than that of the third n-type impurity region 148d. The semiconductor layer 104 is formed to include an impurity element that imparts n-type conductivity. The channel formation region 146, the channel formation region 149a and the channel formation region 14 9b is formed.

[0065] The second n-type impurity region 144a, the second n-type impurity region 144b, the second n-type impurity The first n-type impurity region 147a, the second n-type impurity region 147b, and the second n-type impurity region 147c are high-concentration n-type impurity regions and function as sources and drains. On the other hand, the third n-type impurity regions 145a, the third n-type impurity region 145b, the third n-type impurity region 148a, the third n-type impurity regions 148b, the third n-type impurity region 148c, and the third n-type impurity region 148d are low-concentration impurity regions and serve as LDD (Lightly Doped Drain) regions. The n-type impurity regions 145a and 145b are Lov regions because they are covered by the first gate electrode layer 122 via the gate insulating layer 107, relax the electric field near the drain, and can suppress the degradation of the on-current due to hot carriers. As a result, a thin-film transistor capable of high-speed operation can be formed. On the other hand, the third n-type impurity regions 148a, the third n-type impurity region 148b, the third n-type impurity region 148c, and the third n-type impurity regions 148d are formed in the Loff region not covered by the gate electrode layer 127 and the gate electrode layer 128, so they relax the electric field near the drain to prevent degradation due to hot carrier injection and have the effect of reducing the off-current. As a result, it is possible to fabricate a highly reliable semiconductor device with low power consumption.

[0066] Next, the masks 153a, 153b, 153c, and 153d are removed and masks 155a and 155b that cover the semiconductor layers 103 and 105 are formed. An impurity element 154 that imparts p-type is added using the masks 155a, 155b, the gate electrode layer 117, and the gate electrode layer 129 as masks, and the first p-type impurity region 160a, the first The p-type impurity regions 160b of 1, the first p-type impurity regions 163a, the first p-type impurity regions 1 63b, the second p-type impurity regions 161a, the second p-type impurity regions 161b, the second p-type impurity regions 164a, and the second p-type impurity regions 164b are formed. In this embodiment, since boron (B) is used as the impurity element, diborane (B2H6) (the doping gas is B2H6 diluted with hydrogen (H2), and the ratio of B2H6 in the gas is 15%) is used as the doping gas containing the impurity element. Doping is performed with a gas flow rate of 70 sccm, a beam current of 180 μA / cm, an acceleration voltage of 80 kV, and a dose amount to be added of 2.0×10 15 ions / cm 2 . Here, the impurity element that imparts a p-type to the first p-type impurity regions 160a, the first p-type impurity regions 160b, the first p-type impurity regions 163a, the first p-type impurity regions 163b, the second p-type impurity regions 161a, the second p-type impurity regions 161b, the second p-type impurity regions 164a, and the second p-type impurity regions 164b is added so as to be contained at a concentration 20 of about 1×10 21 to 5×10 3 / cm . In this embodiment, the second p-type impurity regions 161a, the second p-type impurity regions 161b, the second p-type impurity regions 164a, and the second p-type impurity regions 164b reflect the shapes of the gate electrode layers 117 and 129 and are self-alignedly formed to have a lower concentration than the first p-type impurity regions 160a, the first p-type impurity regions 160b, the first p-type impurity regions 163a, and the first p-type impurity regions 163b. Further, a channel formation region 162 is formed in the semiconductor layer 103, and a channel formation region 165 is formed in the

[0067] The second n-type impurity regions 144a, the second n-type impurity regions 144b, and the second n-type impurity regions 147a, the second n-type impurity regions 147b, and the second n-type impurity regions 147c are high-concentration n-type impurity regions and function as sources and drains. On the other hand, the second p-type impurity regions 161a, the second p-type impurity regions 161b, the second p-type impurity regions 164a, and the second p-type impurity regions 164b are low-concentration impurity regions and become LDD (Lightly Doped D rain) regions. The second p-type impurity regions 161a, the second p-type impurity regions 161b , the second p-type impurity regions 164a, and the second p-type impurity regions 164b are covered by the gate insulating layer 10 7 and the first gate electrode layers 121 and 126, so they are Lov regions, which relax the electric field near the drain and suppress the deterioration of the on-current due to hot carriers and are capable of doing so.

[0068] The masks 155a and 155b are removed by O2 ashing or resist stripper, and the oxide film is also removed. Then, an insulating film, so-called side wall, may be formed to cover the side surfaces of the gate electrode layers. The side wall can be formed of an insulating film containing silicon by using the plasma CVD method or the low-pressure CVD (LPC VD) method.

[0069] Heat treatment, irradiation with intense light, or irradiation with laser light may be performed to activate the impurity elements . At the same time as activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

[0070] Next, an interlayer insulating layer covering the gate electrode layer and the gate insulating layer is formed. In this embodiment It is formed into a laminated structure of an insulating film 167 and an insulating film 168 (see Fig. 4(A)). Insulating film 16 7 is formed as a silicon oxynitride film with a thickness of 200 nm, and insulating film 168 is formed as a silicon nitride oxide film with a thickness of 800 nm to form a laminated structure. Also, covering the gate electrode layer and the gate insulating layer, a silicon oxynitride film is formed with a thickness of 30 nm, a silicon nitride oxynitride film is formed with a thickness of 140 nm, and a silicon oxynitride film is formed with a thickness of 800 nm to form a three-layer laminated structure. In this embodiment, insulating films 167 and 168 are continuously formed using the plasma CVD method in the same manner as the base film. Insulating film 108 is not limited to a silicon nitride film, and may be a silicon nitride oxide film, a silicon oxynitride film, or a silicon oxide film using sputtering or plasma CVD, or other silicon-containing insulating films may be used in a single-layer or three-layer or more laminated structure.

[0071] Furthermore, a heat treatment is performed at 300 to 550 °C for 1 to 12 hours in a nitrogen atmosphere to hydrogenate the semiconductor layer. Preferably, it is performed at 400 to 500 °C. This process is a process of terminating the dangling bonds of the semiconductor layer by hydrogen contained in insulating film 167, which is an interlayer insulating layer. In this embodiment, heat treatment is performed at 410 °C (°C).

[0072] As insulating films 167 and 168, other materials such as aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide (AlNO) in which the nitrogen content is more than the oxygen content, or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon film (CN), polysilazane, and other substances containing inorganic insulating materials can be selected. Also, a siloxane resin may be used. Note that the siloxane resin is formed from a material selected from the group consisting of and may be used. , which corresponds to a resin containing Si-O-Si bonds. Siloxane has a skeletal structure formed by the bonds between silicon (Si) and oxygen ( O). As substituents, organic groups containing at least hydrogen (e.g., alkyl groups, aromatic hydrocarbons) are used. A fluoro group may also be used as a substituent. Or, as substituents, an organic group containing at least hydrogen and a fluoro group may be used. Also, an organic insulating material may be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, or benzocyclobutene can be used. . A coating film formed by a coating method with good flatness may also be used.

[0073] Next, using a mask made of resist, contact holes (openings) reaching the semiconductor layer are formed in the insulating film 167, the insulating film 168, and the gate insulating layer 107. The etching may be performed once or multiple times depending on the selectivity of the material used. In this embodiment, under the condition that a selectivity can be achieved between the insulating film 168 which is a silicon oxynitride film and the insulating film 167 which is a silicon nitride oxide film and the gate insulating layer 107, the first etching is performed to remove the insulating film 168. Next, by the second etching, the insulating film 167 and the gate insulating layer 107 are removed, and openings (also referred to as opening portions) reaching the first p-type impurity regions 160a, 160b, 163a, 163b which are source regions or drain regions, the second n-type impurity regions 144a, 144b, 147a, 147b are formed. In this embodiment, the first etching is performed by wet etching, and the second etching is performed by dry etching. layer 107. The etching may be performed once or multiple times depending on the selectivity of the material used. In this embodiment, under the condition that a selectivity can be achieved between the insulating film 168 which is a silicon oxynitride film and the insulating film 167 which is a silicon nitride oxide film and the gate insulating layer 107, the first etching is performed to remove the insulating film 168. Next, by the second etching, the insulating film 167 and the gate insulating layer 107 are removed, and openings (also referred to as opening portions) reaching the first p-type impurity regions 160a, 160b, 163a, 163b which are source regions or drain regions, the second n-type impurity regions 144a, 144b, 147a, 147b are formed. In this embodiment, the first etching is performed by wet etching, and the second etching is performed by dry etching. The etching may be performed once or multiple times depending on the selectivity of the material used. In this embodiment, under the condition that a selectivity can be achieved between the insulating film 168 which is a silicon oxynitride film and the insulating film 167 which is a silicon nitride oxide film and the gate insulating layer 107, the first etching is performed to remove the insulating film 168. Next, by the second etching, the insulating film 167 and the gate insulating layer 107 are removed, and openings (also referred to as opening portions) reaching the first p-type impurity regions 160a, 160b, 163a, 163b which are source regions or drain regions, the second n-type impurity regions 144a, 144b, 147a, 147b are formed. In this embodiment, the first etching is performed by wet etching, and the second etching is performed by dry etching. The insulating film 168 which is a silicon oxynitride film, the insulating film 167 which is a silicon nitride oxide film, and the gate insulating layer 107 are removed, and openings (also referred to as opening portions) reaching the first p-type impurity regions 160a, 160b, 163a, 163b which are source regions or drain regions, the second n-type impurity regions 144a, 144b, 147a, 147b are formed. In this embodiment, the first etching is performed by wet etching, and the second etching is performed by dry etching. 107, the first etching is performed to remove the insulating film 168. Next, by the second etching, the insulating film 167 and the gate insulating layer 107 are removed, and openings (also referred to as opening portions) reaching the first p-type impurity regions 160a, 160b, 163a, 163b which are source regions or drain regions, the second n-type impurity regions 144a, 144b, 147a, 147b are formed. In this embodiment, the first etching is performed by wet etching, and the second etching is performed by dry etching. Next, by the second etching, the insulating film 167 and the gate insulating layer 107 are removed, and openings (also referred to as opening portions) reaching the first p-type impurity regions 160a, 160b, 163a, 163b which are source regions or drain regions, the second n-type impurity regions 144a, 144b, 147a, 147b are formed. In this embodiment, the first etching is performed by wet etching, and the second etching is performed by dry etching. region or drain region, the first p-type impurity regions 160a, 160 b, the first p-type impurity regions 163a, 163b, the second n-type impurity regions 144a, 144b, the second n-type impurity regions 147a, the second n-type impurity regions 147b are formed. In this embodiment, , the first etching is performed by wet etching, and the second etching is performed by dry etching. The etchant for wet etching is ammonium hydrogen fluoride and A hydrofluoric acid-based solution such as a mixture containing ammonium fluoride and fluorine may be used. The gases used are chlorine-containing gases such as Cl2, BCl3, SiCl4, or CCl4. Gas containing fluorine, such as CF4, SF6 or NF3, or O2, as appropriate An inert gas may be added to the etching gas. The inert elements are one or more selected from He, Ne, Ar, Kr, and Xe. The following elements can be used:

[0074] A conductive film is formed so as to cover the openings, and the conductive film is etched to form each source region or drain region. a source or drain electrode layer 169a electrically connected to a part of the in-region; A source or drain electrode layer 169b, a source or drain electrode layer 170a, A source or drain electrode layer 170b, a source or drain electrode layer 171a, A source or drain electrode layer 171b, a source or drain electrode layer 172a, The source or drain electrode layer 172b and the wiring 156 are formed. The rain electrode layer is formed by forming a conductive film using a PVD method, CVD method, vapor deposition method, etc., and then cutting it into the desired shape. In addition, the method can be performed by a droplet discharge method, a printing method, an electrolytic plating method, etc. By this method, a conductive layer can be selectively formed at a desired location. The source electrode layer or the drain electrode layer may be made of Ag, Au, Cu, or N. i, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, It is formed using metals such as Ge, Zr, Ba, or their alloys, or their metal nitrides. Alternatively, it may be a laminated structure of materials selected from these. In this embodiment, titanium (Ti ) is formed to a thickness of 100 nm, an alloy of aluminum and silicon (Al-Si) is formed to a thickness of 700 nm, titanium (Ti) is formed to a thickness of 200 nm, and then processed into a desired shape.

[0075] In the above process, a p-channel thin film transistor 173 having a p-type impurity region in the Lov region, an n-channel thin film transistor 174 having an n-channel impurity region in the Lov region, a conductive layer 177 in the connection region, and a multi-channel n-channel thin film transistor 17 5 having an n-type impurity region in the Loff region and a p-channel thin film transistor 176 having a p-type impurity region in the Lov region are formed in the peripheral drive circuit region 204, thereby fabricating an active matrix substrate (see FIG. 4(B)).

[0076] The active matrix substrate can be used in a light-emitting device having a self-luminous element, a liquid crystal display device having a liquid crystal element, and other display devices. Further, it can be used in semiconductor devices such as cards equipped with various processors typified by a CPU (Central Processing Unit Device) and ID chips.

[0077] The thin film transistor is not limited to this embodiment, and may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Further, the thin film transistors in the peripheral drive circuit region may also have a single gate structure, a double gate structure, or a triple gate structure.

[0078] ​​​​​​​​​Note that the method for manufacturing the thin film transistor shown in this embodiment is not limited to the top gate type (planar type), bottom gate type (reverse stagger type), or dual gate type having two gate electrode layers disposed via a gate insulating film above and below the channel region, or other structures can also be applied. Next, an insulating film 180 and an insulating film 181 are formed as a second interlayer insulating film (see Fig. 5(A)

[0079] ). Fig. 5 shows the manufacturing process of the display device, and includes a separation region 201 for scribing separation, an external terminal connection region 202 which is an attachment portion of the FPC, a wiring region 203 which is a peripheral routing wiring region, a peripheral drive circuit region 204, a connection region 205, and a pixel region 206. Wiring 179a and wiring 179b are provided in the wiring region 203, and a terminal electrode layer 178 connected to an external terminal is provided in the external terminal connection region 202.

[0080] As the insulating film 180 and the insulating film 181, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide (AlNO) having a nitrogen content higher than the oxygen content, or aluminum oxide, diamond like carbon (DLC), carbon nitride film (CN), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), alumina film, polysilazane, or other substances containing inorganic insulating materials can be formed. Also, a siloxane resin may be used An organic insulating material may also be used. As the organic material, either a photosensitive or non - photosensitive material may be used, such as polyimide, acrylic, polyamide, polyimide amide, resist, or benz Cyclobutene and a Low k material with a low dielectric constant can be used.

[0081] In this embodiment, a silicon oxynitride film is formed with a thickness of 20 0 nm as the insulating film 180 using the CVD method. As the interlayer insulating layer provided for planarization, since those with high heat resistance and insulation properties and a high planarization rate are required, it is preferable to use a coating method typified by the spin

[0082] coating method as the method for forming the insulating film 181. In this embodiment, as the material of the insulating film 181, a coating film using a siloxane resin material is used. The film after firing can be called a silicon oxide film (SiOx) containing an alkyl group (x, y = 1, 2 ···). This silicon oxide film containing an alkyl group can withstand heat treatment at 300 °C or higher.

[0083] The insulating film 180 and the insulating film 181 can be formed by adopting dip coating, spray coating, doctor knife coating, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, etc. The insulating film 180 and the insulating film 181 may be formed by the droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Also, methods in which patterns can be transferred or drawn, such as the droplet discharge method, for example, printing methods (such as screen printing and offset printing where patterns are formed), etc. can also be used.

[0084] Next, as shown in FIG. 5(B), openings are formed in the insulating film 180 and the insulating film 1 81, which are the second interlayer insulating layers. The insulating film 180 and the insulating film 181 are etched over a wide area in the connection region 205, wiring region 203, external terminal connection region 202, separation region 201, etc. However, the opening area of ​​the pixel region 206 is smaller than the opening area of ​​the connection region 205, etc. Therefore, the photoresist for forming the opening in the pixel area is very small and fine compared to the photoresist for forming the opening in the pixel area. Providing a lithography process and a photolithography process for forming an opening in a connection region. This allows for a wider margin in etching conditions, resulting in improved yield. In addition, the margin of etching conditions is expanded, so that the pixel area can be The contact holes can be formed with high precision.

[0085] Specifically, the connection area 205, the wiring area 203, the external terminal connection area 202, the separation area The insulating film 180 and the insulating film 181 are provided in a part of the region 201 and the peripheral driving circuit region 204. Therefore, a large opening is formed in the pixel region 206, a part of the connection region 205, and A mask is formed so as to cover a part of the insulating film 180 and the insulating film 181 in the peripheral driving circuit region 204. Etching can be performed using a parallel plate RIE device or an ICP etching device. The etching time is set to such an extent that the wiring layer and the first interlayer insulating layer are overetched. If the etching is set to such an extent that the film thickness in the substrate is In this way, the variation in the connection and the variation in the etching rate can be reduced. An opening 182 is formed in the region 205, and an opening 183 is formed in the external terminal connection region 202. It is done.

[0086] 5B, the insulating film 180 and the insulating film 181 in the pixel region 206 are A fine opening, i.e. a contact hole, is formed (see FIG. 5(C)). The pixel region 206, a part of the connection region 205, the peripheral driving circuit region 204, and the pixel region 206 are Form a mask so as to cover. The mask is a mask for forming an opening in the pixel region 206 and is provided with fine openings at predetermined locations. As such a mask, for example, a reticle mask can be used.

[0087] Then, using a parallel plate RIE apparatus, etch the insulating film 180 and the insulating film 181. Note that the etching time may be set such that the wiring layer and the first interlayer insulating layer are over-etched. By setting it to be over-etched in this way, the film thickness variation within the substrate and the variation in the etching rate can be reduced.

[0088] Alternatively, an ICP apparatus may be used for the etching apparatus. In the above steps, an opening 184 reaching the source electrode or the drain electrode 172a is formed in the pixel region 206. In the present invention, the source electrode or the drain electrode 172a covers the gate electrode layer 126, which is a location where a large amount of thin film is laminated and the total film thickness is large in the thin film transistor 176, via the insulating film 167 and the insulating film 168. Therefore, since it is not necessary to open the opening 184 deeply in terms of film thickness, the opening process can be shortened and the controllability is also improved. Also, the electrode layer formed in the opening does not need to widely cover the opening with a large angle, so it can be formed with good coverage and the reliability is also improved.

[0089] In the present embodiment, a case will be described in which the insulating film 180 and the insulating film 181 are etched using a mask that covers a part of the connection region 205, the wiring region 203, the external terminal connection region 202, the separation region 201, and the peripheral drive circuit region 204, and has a predetermined opening part provided in the pixel region 206. ​​​​​However, the present invention is not limited to this. For example, the opening of the connection region 204 has a large area, so the amount of etching is large. Such a large-area opening may be etched multiple times. Also, when forming a deep opening compared to other openings, it may be etched multiple times as well. Therefore, only the wiring region 203, the external terminal connection region 202, the separation region 2 01, a part of the insulating films 180 and 181 in the peripheral drive circuit region 204 are covered, and a mask provided with predetermined openings in the connection region 205 and the pixel region 206 may be used to etch the insulating films 18 0 and 181. When etching using such a mask, in the connection region 205, the insulating films 180 and 181 are etched so that the depth increases until the insulating film 168 is exposed.

[0090] Also, in this embodiment, the formation of the openings in the insulating films 180 and 181 is performed in multiple steps as shown in FIGS. 5( B), (C), but it may be formed in a single etching process. In this case, using an ICP apparatus, with an ICP power of 7000 W, a bias power of 1 000 W, a pressure of 0.8 Pascal (Pa), and CF4 as the etching gas at 240 sccm and O2 at 160 sccm for etching. The bias power is preferably 1000 - 4000 W . Since the opening can be formed in a single etching process, there is an advantage of simplifying the process.

[0091] Next, a first electrode layer 18 5 (also referred to as a pixel electrode layer) is formed so as to be in contact with the source electrode layer or the drain electrode layer 172a. The first electrode layer functions as an anode or a cathode, and is an element selected from Ti, Ni, W, Cr, Pt, Zn, Sn, In, or Mo, Ti ​ N, TiSi X N Y , WSi X , WN X , WSi X N Y , NbN, or a film mainly composed of an alloy material or a compound material containing the above elements, or a laminated film thereof may be used in the range of a total film thickness of 100 nm to 800 nm. In this embodiment, a light-emitting element is used as the display element, and since the light from the light-emitting element is extracted from the first electrode layer 185 side, the first electrode layer 185 has translucency. As the first electrode layer 185, a transparent conductive film is formed and etched into a desired shape to form the first electrode layer 185. As the first electrode layer 185 used in the present invention, indium tin oxide containing silicon oxide (also referred to as indium tin silicate oxide, hereinafter referred to as "ITSO").

[0092] In this embodiment, a light-emitting element is used as the display element, and since the light from the light-emitting element is extracted from the first electrode layer 185 side, the first electrode layer 185 has translucency. For the structure of extracting light from the first electrode layer 185 side, the first electrode layer 185 has translucency. As the first electrode layer 185, a transparent conductive film is formed and etched into a desired shape to form the first electrode layer 185. As the first electrode layer 185, a transparent conductive film is formed and etched into a desired shape to form the first electrode layer 185. 185. As the first electrode layer 185 used in the present invention, indium tin oxide containing silicon oxide (also referred to as indium tin silicate oxide, hereinafter referred to as "ITSO"). Indium tin oxide (also referred to as indium tin silicate oxide containing silicon oxide, hereinafter referred to as "ITSO"). ), zinc oxide, tin oxide, indium oxide, etc. may be used. In addition, a transparent conductive film such as an indium zinc oxide alloy in which 2 to 20 atomic% of zinc oxide (ZnO) is mixed with indium oxide. In addition to the above transparent conductive film, a titanium nitride film or a titanium film may be used as the first electrode layer 185. In this case, after forming the transparent conductive film, a titanium nitride film or a titanium film is formed to a film thickness (preferably about 5 nm to 30 nm) that allows light to pass through. In this embodiment, as the first electrode layer 185, ITSO using indium tin oxide and silicon oxide is used. In this embodiment, for the ITSO film, a target in which 1 to 10 [wt%] of silicon oxide (SiO2) is mixed with indium tin oxide is used, and the Ar gas flow rate is 120 sccm, the O2 gas flow rate is 5 sccm, the pressure is 0.25 Pa, and the power is 3 r gas flow rate is 120 sccm, O2 gas flow rate is 5 sccm, pressure is 0.25 Pa, power 3 ​​​​​The first electrode layer 185 is formed to a thickness of 185 nm by sputtering under the condition of 0.2 kW. The surface is planarized by the CMP method, wiping with a polyvinyl alcohol-based porous material, etc. After polishing using the CMP method, the surface of the first electrode layer 185 may be irradiated with ultraviolet light. X-ray irradiation, oxygen plasma treatment, etc. may be performed.

[0093] After the first electrode layer 185 is formed, heat treatment may be performed. The moisture contained in the first electrode layer 185 is released. Therefore, the first electrode layer 185 is degassed. Therefore, even if a light-emitting material that is easily deteriorated by moisture is formed on the first electrode layer, The light-emitting material does not deteriorate, and a highly reliable display device can be manufactured. Since the first electrode layer 185 is made of ITO, the ITO (indium oxide) does not change even after baking. It does not crystallize like tin oxide (I-tin alloy), but remains in an amorphous state. TSO has a higher flatness than ITO, and even if the layer containing the organic compound is thin, it does not short with the cathode. is less likely to occur.

[0094] Next, an insulator ( An insulating layer 186 (called a partition or a barrier) is formed (see FIG. 6(B)). Insulators 187a and 187b are formed in the external terminal connection region 202 during the process.

[0095] In order to achieve full color display, when forming an electroluminescent layer on the first electrode layer, RGB emission is performed. Therefore, it is necessary to make separate electroluminescent layers for each color. When the pixel electrode layer (first electrode layer) is formed, the pixel electrode layer (first electrode layer) is covered with a mask. A film-like form made of a metal material or the like can be used. At this time, the mask serves as a partition wall and is provided and supported on the insulator 186, but due to bending or twisting, etc., it may come into contact with the pixel electrode layer and damage the pixel electrode layer. If shape defects occur in the pixel electrode layer due to scratches or the like it will cause light emission defects, display defects, etc., leading to a deterioration in image quality. Therefore, both reliability and performance will decline.

[0096] In the present invention, a spacer 199 having the same film thickness as the insulator 186 is formed on the first electrode layer 185 which is the pixel electrode layer. Since the mask is supported by this spacer 199, it will not come into contact with the first electrode layer. Therefore, shape defects of the first electrode layer caused by the mask are prevented and the first electrode layer can be a highly reliable and high-image-quality display device without causing light emission defects or display defects. The spacer not only serves as a spacer for the mask when forming the electroluminescent layer on the first electrode layer that functions as the pixel electrode layer, but also functions as a spacer to prevent the electroluminescent layer from being damaged or deformed due to external pressure or impact after forming the electroluminescent layer and sealing it with a sealing substrate to complete the display device.

[0097] In this embodiment, the spacer 199 is formed of the same material and in the same process as the insulator 186 which is a partition wall, but it may also be formed in a separate process. The shape and size of the spacer are not limited and may be set in consideration of the size of the pixel region, the aperture ratio, etc. In this embodiment, as shown in FIG. 6(B), it has a columnar shape with a rounded top like a hemisphere, and the size is 1 μm to 2 μm (preferably 1.5 μm or more and 2 μm or less).

[0098] An example of the shape of the spacer will be described with reference to FIG. 22. FIGS. 22(A1), (B1), (C1 ) are top views of the pixel region, and FIGS. 22(A2), (B2), (C2) are cross-sectional views of the lines X1-Y1, X2-Y2, X3-Y3 in FIGS. 22(A1), (B1), (C1). In FIGS. 22(A1) and (A2), on a substrate 600, an underlying film 601a, an underlying film 601b, a gate insulating layer 602, an insulating film 603, an insulating film 604, an insulating film 605, an insulating film 606, a pixel electrode layer, i.e., a first electrode layer 607, is formed. An insulator 608, which is a partition wall, is formed so as to cover the end of the first electrode layer 607, and a spacer 609 is formed of the same material and in the same process as the insulator 608. The spacer may be formed connected to the insulating layer serving as the partition wall as shown in FIG. 22.

[0099] In FIGS. 22(A1) and (A2), the spacer 609 is formed so as to be in contact with the insulator 608 and is continuously formed across the first electrode layer diagonally on the first electrode layer 609. By continuously forming the spacer 609 in this way, the mask is always supported by the spacer 609 even during movement, so that it contacts the first electrode layer 607 and can prevent the occurrence of shape defects in the first electrode layer 6 07.

[0100] In FIGS. 22(B1) and (B2), on a substrate 610, an underlying film 611a, an underlying film 611 b, a gate insulating layer 612, an insulating film 613, an insulating film 614, an insulating film 615, an insulating film 616, a pixel electrode layer, i.e., a first electrode layer 617, is formed. An insulator 618, which is a partition wall, is formed so as to cover the end of the first electrode layer 617, and a s pacer 619 is formed of the same material and in the same process as the insulator 608.

[0101] In FIGS. 22(B1) and (B2), the spacer 619 is formed to be in contact with the insulator 618, and is formed continuously on the first electrode layer so as to cross the short side direction of the first electrode layer 619 at two locations. When the spacer 619 is formed continuously at a plurality of locations in this way, the mask is always supported by the spacer 619 during movement, so it is in contact with the first electrode layer 617 and can prevent the occurrence of shape defects in the first electrode layer 617. In FIGS. 22(C1) and (C2), on the substrate 620, the underlying film 621a, the underlying film 621b, the gate insulating layer 622, the insulating film 623, the insulating film 624, the insulating film 625, the insulating film 626, the first electrode layer 627 which is a pixel electrode layer is formed. An insulator 628 which is a partition is formed so as to cover the end portion of the first electrode layer 627, and a spacer 629 is formed of the same material and in the same process as the insulator 628. In FIGS. 22(C1) and (C2), the spacer 629 is formed to be in contact with the insulator 628, and is formed continuously on the first electrode layer so as to cross the long side direction and the short side direction of the first electrode layer 629 in a lattice shape. When the spacer 629 is formed continuously in a lattice shape in this way, the mask is always supported by the spacer 629 during movement, so it is in contact with the first electrode layer 627 and can prevent the occurrence of shape defects in the first electrode layer 627. As shown in FIG. 22(C2), the spacer 629 has a tapered shape. In this way, the spacer may be substantially a rectangular parallelepiped as shown in FIG. 22(A2), and various shapes such as a cylinder, a prism, and one having a tapered shape can be used.

[0102] In FIGS. 22(C1) and (C2), on the substrate 620, the underlying film 621a, the underlying film 621b, the gate insulating layer 622, the insulating film 623, the insulating film 624, the insulating film 625, the insulating film 626, the first electrode layer 627 which is a pixel electrode layer is formed. An insulator 628 which is a partition is formed so as to cover the end portion of the first electrode layer 627, and a spacer 629 is formed of the same material and in the same process as the insulator 628.

[0103] In FIGS. 22(C1) and (C2), the spacer 629 is formed to be in contact with the insulator 628, and is formed continuously on the first electrode layer so as to cross the long side direction and the short side direction of the first electrode layer 629 in a lattice shape. When the spacer 629 is formed continuously in a lattice shape in this way, the mask is always supported by the spacer 629 during movement, so it is in contact with the first electrode layer 627 and can prevent the occurrence of shape defects in the first electrode layer 627. As shown in FIG. 22(C2), the spacer 629 has a tapered shape.

[0104] In FIG. 22, the spacer is formed in contact with an insulator serving as a partition wall, but it may be formed separately without contact. It may be formed separately and at a distance.

[0105] The spacer can be formed using silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, other inorganic insulating materials, or acrylic acid, methacrylic acid, and their derivatives, or heat-resistant polymers such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane resin. In this embodiment, acrylic is used for the spacer 199. In this embodiment, acrylic is used for the insulator 186. Also, if the same material as that of the insulating film 181 is used for the insulator 186 and they are formed in the same process, the manufacturing cost can be reduced. Further,

[0106] cost reduction can be achieved by sharing devices such as coating film-forming devices and etching devices. The insulator 186 can be formed using silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, other inorganic insulating materials, or acrylic acid, methacrylic acid, and

[0107] their derivatives, or heat-resistant polymers such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane resin. It may be formed using photosensitive or non-photosensitive materials such as acrylic and polyimide. The insulator 186 preferably has a shape in which the radius of curvature changes continuously, and the coverage of the upper electric field emitting layer 188 and the second electrode layer 189 is improved. It can be formed using heat-resistant polymers such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane resin. It may be formed using photosensitive or non-photosensitive materials such as acrylic and polyimide. The insulator 186 preferably has a shape in which the radius of curvature changes continuously, and the coverage of the upper electric field emitting layer 188 and the second electrode layer 189 is improved. emitting layer 188 and the second electrode layer 189 is improved.

[0108] In the connection region 205, the insulator 186 is formed so as to cover the insulating films 180 and the ends of the insulating film 181. Due to the step formed by the etching process, the ends of the insulating film 180 and the insulating film 181 processed in such a way have poor coverage of the second electrode layer 189 laminated thereon because of their sharp step. Therefore, as in the present invention, by covering the step around the opening with the insulator 186 and making the step gentle, the coverage of the second electrode layer to be laminated can be improved. In the connection region 205, the wiring layer formed in the same process and of the same material as the second electrode layer is electrically connected to the wiring layer 156. In this embodiment, the second electrode layer 189 is in direct contact with and electrically connected to the wiring layer 156, but it may be electrically connected via other wirings.

[0109] Also, in order to further improve the reliability, it is preferable to perform vacuum heating for degassing before forming the electroluminescent layer (layer containing an organic compound) 188. For example, before depositing the organic compound material, in order to remove the gas contained in the substrate, heat treatment is performed at 200 to 4 00 °C, preferably 250 to 350 °C in a reduced pressure atmosphere or an inert atmosphere. Also, it is preferable to form the electroluminescent layer 188 by vacuum evaporation or droplet discharge method under reduced pressure without exposing it to the atmosphere directly. This heat treatment can release the moisture contained and adhered to the conductive film and insulating layer (partition wall) that become the first electrode layer. This heat treatment can be combined with the previous heating process as long as the substrate can be transported within the vacuum chamber without breaking the vacuum, and the previous heating process can be performed once after forming the insulating layer (partition wall). Here, if the interlayer insulating film and the insulator (partition wall) are formed of a material having high heat resistance, the heat treatment process for improving the reliability can be sufficiently performed. (partition wall). ​

[0110] An electroluminescent layer 188 is formed on the first electrode layer 185. Note that in FIG. 1, only one pixel is illustrated, but in the present embodiment, different electroluminescent electrode layers are prepared for each of the colors R (red), G (green), and B (blue). In the present embodiment, as the electroluminescent layer 188, materials that exhibit emission of red (R), green (G), and blue (B) are selectively formed by a deposition method using a deposition mask or the like. The state of selective formation is shown in FIG. 23.

[0111] In FIG. 23, thin film transistors 651a, 651b, and 651c are connected to first electrode layers 652a, 652b, and 652c, respectively, which are pixel electrode layers. The ends of the first electrode layers are each covered with insulators 653a, 653b, 654c, and 653d that function as partition walls, and spacers 654a, 654b, and 654c are formed on the first electrode layer. The mask 656 forms an electroluminescent layer on the first electrode layers 652a, 652b, and 652c and then moves in the direction of arrow 655 to form an electroluminescent layer on each first electrode layer. Since the mask 656 is supported by the spacers 654a, 654b, and 654c on the first electrode layers 652a, 652b, and 652c, there is no problem of contacting the first electrode layer and causing shape defects in the first electrode layer due to bending or twisting. Therefore, a highly reliable high-quality display device can be manufactured without causing light emission defects or display defects in the first electrode layer.

[0112] The materials that exhibit emission of red (R), green (G), and blue (B) are formed by a droplet discharge method.​​​​​​​​​​​ It can also be (such as low-molecular or high-molecular materials).

[0113] Next, a second electrode layer 189 made of a conductive film is provided on the electroluminescent layer 188. The As the second electrode layer 189, a material with a small work function (Al, Ag, Li, Ca, or alloys or compounds thereof, MgAg, MgIn, AlLi, CaF2, or calcium nitride ) may be used. Thus, a light-emitting element 190 composed of the first electrode layer 185, the electroluminescent layer 188, and the second electrode layer 189 is formed.

[0114] In the display device of the present embodiment shown in FIG. 1, the light emitted from the light-emitting element 190 is transmitted and emitted in the direction of the arrow in FIG. 1 from the side of the first electrode layer 185.

[0115] It is effective to provide a passivation film 191 so as to cover the second electrode layer 189. As the passivation film 191, silicon nitride, silicon oxide, silicon oxynitride (Si ON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride aluminum (AlON), aluminum nitride oxide (AlNO) having a nitrogen content higher than the oxygen content or aluminum oxide, diamond-like carbon (DLC), an insulating film containing a nitrogen-containing carbon film (C N) can be used, and a single layer or a laminate of the insulating films combined can be used. In addition, a material in which a skeletal structure is formed by the bond between silicon (Si) and oxygen (O) and at least hydrogen is contained in the substituent, or a material having at least one of fluorine, an alkyl group, or an aromatic hydrocarbon in the substituent may be used.

[0116] At this time, it is preferable to use a film with good coverage as the passivation film, and carbon It is effective to use a bare film, especially a DLC film. DLC films can be formed at temperatures from room temperature to 100°C or less. Since the film can be formed in the range, it can be easily formed above the electroluminescent layer 188, which has low heat resistance. DLC films can be formed by plasma CVD (typically RF plasma CVD, Microwave CVD method, Electron Cyclotron Resonance (ECR) CVD method, Hot Filament CVD method etc.), combustion flame method, sputtering method, ion beam deposition method, laser deposition method, etc. The reactive gas used for film formation is hydrogen gas and a hydrocarbon gas (e.g., CH4, C2 H2, C6H6, etc.) are used, ionized by glow discharge, and a negative self-bias is applied. The CN film is formed by accelerating ions and colliding them with a cathode. The DLC film has a high blocking effect against oxygen. Therefore, the oxidation of the electroluminescent layer 188 can be suppressed. This can prevent problems such as oxidation of the electroluminescent layer 188 during the process.

[0117] A top view of a pixel region of a display device manufactured in this embodiment mode is shown in FIG. The pixel 2702 includes a thin film transistor 501, a thin film transistor 502, a capacitor 504, Light emitting element 190, gate wiring layer 506, source and drain wiring layer 505, power line 507 In FIG. 18, a plurality of spacers 199 are provided on the first electrode layer. The spacer may be singular or plural, and if plural, they do not need to be of the same shape. Also, the spacer 199 is not connected to the insulating layer 186 (shown by the dotted line in FIG. 18). They may be formed separately and not in contact with each other.

[0118] The substrate 100 on which the light-emitting element 190 is formed and the sealing substrate 195 are fixed with a sealing material 192 to seal the light-emitting element (see FIG. 1). In the display device of the present invention is formed so that the sealing material 192 and the insulator 186 are separated from each other without contact. When the sealing material and the insulator 186 are formed separately in this way, even if an insulating material having a highly hygroscopic organic material is used for the insulator 186 moisture is difficult to penetrate, deterioration of the light-emitting element can be prevented, and the reliability of the display device is improved. As the sealing material 192, it is typically preferable to use a visible light curable, ultraviolet light curable or thermosetting resin. For example, bisphenol A type liquid resin, bis phenol A type solid resin, bromine-containing epoxy resin, bisphenol F type resin, bisphenol AD type resin, phenol type resin, cresol type resin, novolac type resin, cycloaliphatic epoxy resin, epibis type epoxy resin, glycidyl ester resin, glycidylamine-based resin, heterocyclic epoxy resin, modified epoxy resin and other epoxy resins can be used . Note that the region surrounded by the sealing material may be filled with a filler 193, and nitrogen or the like may be enclosed by sealing under a nitrogen atmosphere. Since this embodiment is a bottom emission type, the filler 193 does not necessarily need to have translucency, but in the case of a structure in which light is extracted through the filler 193 it needs to have translucency. Typically, a visible light curable, ultraviolet light curable or thermosetting epoxy resin may be used. In the above steps, the display device having the display function using the light-emitting element in this embodiment is completed. The filler can also be dropped in a liquid state and filled into the display device.

[0119] The drop injection method employing the dispenser method will be described with reference to FIG. 19. The drop injection in FIG. 19 The filling method includes a control device 40, an imaging means 42, a head 43, a filler 33, a marker 35, and a marker -45, which consists of a barrier layer 34, a sealing material 32, a TFT substrate 30, and a counter substrate 20. The sealing material 32 forms a closed loop, and the filler 33 is dropped once or multiple times from the head 43 into it. When the viscosity of the filler material is high, it is continuously discharged and adheres to the formation area while remaining connected. On the other hand, when the viscosity of the filler material is low, as shown in Fig. 19, it is intermittently discharged and the filler is dropped. At this time, a barrier layer 34 may be provided to prevent the reaction between the sealing material 32 and the filler 33. Subsequently, the substrates are bonded together in a vacuum, and then ultraviolet curing is performed to obtain a state where the filler is filled. When a substance containing hygroscopicity such as a desiccant is used as this filler, a further water absorption effect can be obtained, and the deterioration of the element can be prevented. In the EL display panel, a desiccant is installed to prevent the deterioration of the element due to moisture. In this embodiment, the desiccant is installed in a recess formed in the sealing substrate so as to surround the pixel region,

[0120] and is configured not to interfere with thinning. Also, a desiccant is formed in the region corresponding to the gate wiring layer, and since the water absorption area is large, the water absorption effect is high. Also, since the desiccant is formed on the gate wiring layer that does not emit light directly, the light extraction efficiency is not reduced.

[0121] Note that in this embodiment, the case where the light-emitting element is sealed with a glass substrate is shown, but the sealing treatment is a treatment for protecting the light-emitting element from moisture, and any of the following methods can be used: mechanically enclosing it with a cover material, enclosing it with a thermosetting resin or an ultraviolet curable resin, or enclosing it with a thin film having high barrier ability such as a metal oxide or nitride. As the cover material, glass, ceramics, etc. can be used. treatment is a treatment for protecting the light-emitting element from moisture, and any of the following methods can be used: mechanically enclosing it with a cover material, enclosing it with a thermosetting resin or an ultraviolet curable resin, or enclosing it with a thin film having high barrier ability such as a metal oxide or nitride. As the cover material, glass, ceramics, etc. can be used. Lumix, plastic or metal can be used, but the cover material side must emit light If it is to be emitted, it must be translucent. Also, the cover material and the base on which the light-emitting element is formed The plate is bonded using a sealing material such as a thermosetting resin or an ultraviolet curable resin, and heat treatment Or an ultraviolet irradiation treatment is used to cure the resin to form a sealed space. Inside this sealed space It is also effective to provide a moisture absorbent typified by barium oxide. This moisture absorbent can be provided in contact with the sealing material It may be provided, or it may be provided on or around the partition wall so as not to interfere with the light from the light-emitting element Furthermore, the space between the cover material and the substrate on which the light-emitting element is formed can also be filled with a thermosetting resin or An ultraviolet curable resin. In this case, it is effective to add a moisture absorbent typified by barium oxide to the thermosetting resin or ultraviolet curable resin .

[0122] In this embodiment, in the external terminal connection region 202, the FPC 194 is connected to the terminal electrode layer 178 by the anisotropic conductive Layer 196 to form a structure for electrically connecting to the outside. Also, as shown in FIG. 1(A), which is a top view of the display device Shown, the display device manufactured in this embodiment has, in addition to the peripheral drive circuit region 204 having a signal line drive circuit, a Peripheral drive circuit region 207a having a scan line drive circuit and a peripheral drive circuit region 207b are provided.

[0123] In this embodiment, it is formed by the above circuit, but the present invention is not limited to this, and the peripheral drive circuit is an IC chip mounted by the COG method or the TAB method described above It may also be used. Also, the gate line drive circuit and the source line drive circuit may be plural or singular Yes.

[0124] ​​​ In the display device of the present invention, the method for driving the screen display is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method may be used, and a time-division gradation driving method or an area gradation driving method may be appropriately used. Further, the video signal input to the source line of the display device may be an analog signal or a digital signal, and the driving circuit or the like may be designed appropriately according to the video signal.

[0125] Furthermore, in a display device where the video signal is digital, the video signal input to the pixel may be one with a constant voltage (CV) or one with a constant current (CC). For a video signal with a constant voltage ( CV), there are those with a constant voltage applied to the light-emitting element (CVCV) and those with a constant current applied to the light-emitting element (CVCC). Also, for a video signal with a constant current (CC) there are those with a constant voltage applied to the light-emitting element (CCCV) and those with a constant current applied to the light-emitting element (CCCC).

[0126] By using the present invention, a highly reliable display device can be manufactured in a simplified process. Therefore, a high-definition and high-quality display device can be manufactured with low cost and high yield.

[0127] (Embodiment 2) Embodiments of the present invention will be described with reference to FIGS. 7 to 9. This embodiment shows an example in which the second interlayer insulating layer is not formed in the display device manufactured in Embodiment 1. Therefore, the description of the same part or the repetition of the part having the same function will be omitted.

[0128] As shown in Embodiment 1, a thin film transistor 173 and a thin film transistor are formed on a substrate 100. Form the resistor 174, thin film transistor 175, thin film transistor 176, and conductive layer 177 and form the insulating films 168, 168. Each thin film transistor has a source electrode layer or a drain electrode layer connected to the source region or the drain region of the semiconductor layer formed. A first electrode layer 395 is formed in contact with the source electrode layer or the drain electrode layer 172b in the thin film transistor 176 provided in the pixel region 206 (see Fig. 7(A)). The first electrode layer 395 functions as a pixel electrode and may be formed of the same material and by the same process as the first electrode layer 185 in Embodiment 1. Also in this embodiment, in the same manner as in Embodiment 1, in order to extract light through the first electrode layer, ITSO, which is a transparent conductive film, is used for the first electrode layer 395 and processed into a desired shape and formed

[0129] 395 and formed. An insulator 186 is formed so as to cover the end portion of the first electrode layer 395 and the thin film transistor (see Fig. 7(B)). In this embodiment, acrylic is used for the insulator 186. An electroluminescent layer 188 is formed on the first electrode layer, and a second electrode layer 189 is laminated to form a light-emitting element 190 The second electrode layer 189 is electrically connected to the wiring layer 156 in the connection region 205, and in the external terminal connection region 202, the FPC 194 is adhered to the terminal electrode layer 178 via the anisotropic conductive layer 196. A passivation film 191 is formed so as to cover the second electrode layer 189. The substrate 100 is bonded to the sealing substrate 195 by the sealing material 192, and the filling material 193 is filled in the display device (see Fig. 8). In the display device of the present invention the sealing material 192 and the insulator 186 are formed so as not to be in contact with each other in this way

[0130] The second electrode layer 189 is electrically connected to the wiring layer 156 in the connection region 205, and in the external terminal connection region 202, the FPC 194 is adhered to the terminal electrode layer 178 via the anisotropic conductive layer 196. A passivation film 191 is formed so as to cover the second electrode layer 189. The substrate 100 is bonded to the sealing substrate 195 by the sealing material 192, and the filling material 193 is filled in the display device (see Fig. 8). In the display device of the present invention the sealing material 192 and the insulator 186 are formed so as not to be in contact with each other in this way the sealing material 192 and the insulator 186 are formed so as not to be in contact with each other in this way in this way in this way in this way In the display device of the present invention, the sealing material 192 and the insulator 186 are formed so as not to be in contact with each other When the sea urchin sealing material and the insulator 186 are separated and formed, even if an insulating material using an organic material with high hygroscopicity is used for the insulator 186, moisture is less likely to penetrate, deterioration of the light-emitting element can be prevented, and the reliability of the display device is improved. Also, in the display device in FIG. 9, the first electrode layer 395 can be selectively formed on the insulating film 168 before the formation of the source electrode layer or drain electrode layer 172b that is subsequent to the thin film transistor 176. In this case, in this embodiment, the connection structure between the source electrode layer or drain electrode layer 172b and the first electrode layer 395 is a structure in which the source electrode layer or drain electrode layer 172b is laminated on the first electrode layer 395.

[0131] When the first electrode layer 395 is formed prior to the source electrode layer or drain electrode layer 172b, it can be formed in a flat formation region, so there are advantages that the coating property is good and polishing treatment such as CMP can be sufficiently performed, and thus it can be formed with good flatness.

[0132]

[0133]

[0134]

[0135] (Embodiment 3) An embodiment of the present invention will be described with reference to FIG. 10. This embodiment shows an example in which the structure of the gate electrode layer of the thin film transistor is different in the display device manufactured in Embodiment 1. Therefore, repeated descriptions of the same part or parts having similar functions are omitted.

[0134] FIGS. 10(A) to (C) are display devices in the manufacturing process, and correspond to the display device in FIG. 4(B) shown in Embodiment 1.

[0135] ​​ In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape. In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape. In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape. In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape. In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape. In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape. In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape. In FIG. 10(A), thin film transistors 273 and 274 are provided in the peripheral drive circuit region 214, a conductive layer 277 is provided in the connection region 215, and thin film transistors 275 and 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(A) is composed of a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. Thus, the gate electrode layer may have a tapered shape, or may have a shape with an angle on the side close to vertical, that is, a shape that does not have a so-called tapered shape.

[0136] In FIG. 10(B), thin film transistors 373 and 374 are provided in the peripheral drive circuit region 214, a conductive layer 377 is provided in the connection region 215, and thin film transistors 375 and 376 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(B) is also composed of a stack of two conductive films, but the upper gate electrode layer and the lower gate electrode layer have a continuous tapered shape. In FIG. 10(B), thin film transistors 373 and 374 are provided in the peripheral drive circuit region 214, a conductive layer 377 is provided in the connection region 215, and thin film transistors 375 and 376 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(B) is also composed of a stack of two conductive films, but the upper gate electrode layer and the lower gate electrode layer have a continuous tapered shape. In FIG. 10(B), thin film transistors 373 and 374 are provided in the peripheral drive circuit region 214, a conductive layer 377 is provided in the connection region 215, and thin film transistors 375 and 376 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(B) is also composed of a stack of two conductive films, but the upper gate electrode layer and the lower gate electrode layer have a continuous tapered shape. In FIG. 10(B), thin film transistors 373 and 374 are provided in the peripheral drive circuit region 214, a conductive layer 377 is provided in the connection region 215, and thin film transistors 375 and 376 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(B) is also composed of a stack of two conductive films, but the upper gate electrode layer and the lower gate electrode layer have a continuous tapered shape. In FIG. 10(B), thin film transistors 373 and 374 are provided in the peripheral drive circuit region 214, a conductive layer 377 is provided in the connection region 215, and thin film transistors 375 and 376 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(B) is also composed of a stack of two conductive films, but the upper gate electrode layer and the lower gate electrode layer have a continuous tapered shape.

[0137] In FIG. 10(C), thin film transistors 473 and 474 are provided in the peripheral drive circuit region 214, a conductive layer 477 is provided in the connection region 215, and thin film transistors 475 and 476 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(C) has a single-layer structure and has a tapered shape. Thus, the gate electrode layer may have a single-layer structure. In FIG. 10(C), thin film transistors 473 and 474 are provided in the peripheral drive circuit region 214, a conductive layer 477 is provided in the connection region 215, and thin film transistors 475 and 476 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(C) has a single-layer structure and has a tapered shape. Thus, the gate electrode layer may have a single-layer structure. In FIG. 10(C), thin film transistors 473 and 474 are provided in the peripheral drive circuit region 214, a conductive layer 477 is provided in the connection region 215, and thin film transistors 475 and 476 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(C) has a single-layer structure and has a tapered shape. Thus, the gate electrode layer may have a single-layer structure. In FIG. 10(C), thin film transistors 473 and 474 are provided in the peripheral drive circuit region 214, a conductive layer 477 is provided in the connection region 215, and thin film transistors 475 and 476 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(C) has a single-layer structure and has a tapered shape. Thus, the gate electrode layer may have a single-layer structure. In FIG. 10(C), thin film transistors 473 and 474 are provided in the peripheral drive circuit region 214, a conductive layer 477 is provided in the connection region 215, and thin film transistors 475 and 476 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10(C) has a single-layer structure and has a tapered shape. Thus, the gate electrode layer may have a single-layer structure.

[0138] As described above, the gate electrode layer can have various structures depending on its configuration and shape. Therefore, the display devices fabricated thereby also exhibit various structures. When the impurity region in the semiconductor layer is self-alignedly formed using the gate electrode layer as a mask, the structure and concentration distribution of the impurity region change depending on the structure of the gate electrode layer. Considering the above, a thin-film transistor having a desired function can be fabricated through design.

[0139] This embodiment can be used in combination with Embodiments 1 and 2, respectively.

[0140] (Embodiment 4) Although a display device having a light-emitting element can be formed by applying the present invention, the light emitted from the light-emitting element is either bottom emission, top emission, or both emissions. In this embodiment, examples of both emission type and top emission type will be described with reference to FIGS. 11 and 12.

[0141] The display device shown in FIG. 12 includes an element substrate 1300, thin-film transistors 1355, 1365, and 1375, a first electrode layer 1317, an electroluminescent layer 13 19, a second electrode layer 1320, a transparent conductive film 1321, a filling material 1322, a sealing material 1325, a gate insulating layer 1310, insulating films 1311, 1312, 1313, 13 09, an insulator 1314, a sealing substrate 1323, a wiring layer 1308, a terminal electrode layer 1381, an anisotropic conductive layer 1382, an FPC 1383, spacers 1330, and a light-emitting element 1305. The display device has a separation region 221, an external terminal connection region 222, a wiring region 2 23, a peripheral drive circuit region 224, and a pixel region 226. The filling material 1322 is shown in FIG. 1 It can be formed by the dropping method with a liquid composition like the dropping method of 9. Dropping The element substrate 1300 on which the filler is formed by the dropping method and the sealing substrate 1323 are bonded together to emit light Seal the display device.

[0142] The display device in FIG. 12 is a double-sided emission type, and has a structure that emits light from both the element substrate 1300 side and the sealing substrate 1323 side in the direction of the arrow. In this embodiment, a transparent conductive film is formed and etched into a desired shape to form the first electrode layer 1317. A transparent conductive film can be used as the first electrode layer 1317. In addition to the above-mentioned transparent conductive film, a titanium nitride film or a titanium film may be used as the first electrode layer 1317. In this case, after forming the transparent conductive film, a titanium nitride film or a titanium film is formed to a film thickness (preferably about 5 nm to 30 nm) that allows light to pass through. In this embodiment, ITSO is used as the first electrode layer 1317 .

[0143] Next, a second electrode layer 1320 made of a conductive film is provided on the electroluminescent layer 1319 . As the second electrode layer 1320, a material with a small work function (Al, Ag, Li, Ca, or their alloys and compounds, MgAg, MgIn, AlLi, CaF2, or calcium nitride lucium) can be used. In the display device of FIG. 6, in order for light to pass through, a metal thin film (MgAg: film thickness 10 nm) with a thin film thickness is used as the second electrode layer 1320, and a laminate with ITSO having a film thickness of 100 nm is used as the transparent conductive film 13 21. The same material as the above-mentioned first electrode layer 1317 can be used as the transparent conductive film 1321 .

[0144] The display device in FIG. 11 is a single-sided emission type and has a structure that emits upward in the direction of the arrow. FIG​​ The display device shown in Fig. 11 includes an element substrate 1600, thin film transistors 1655, thin film transistors 1665, thin film transistors 1675, a reflective metal layer 1624, a first electrode layer 1617, an electroluminescent layer 1619, a second electrode layer 1620, a transparent conductive film 1621, a filler 1 622, a sealing material 1625, a gate insulating layer 1610, insulating films 1611, insulating films 1612, insulating films 1613, insulating film 1609, an insulator 1614, a sealing substrate 1623, a wiring layer 1608 , a terminal electrode layer 1681, an anisotropic conductive layer 1682, an FPC 1683, spacers 1630, and a light emitting element 1605. In the display device shown in Fig. 11, the insulating layer laminated on the terminal electrode layer 1681 has been removed by etching. In this way, the reliability is considered to be improved by having a structure in which a water-permeable (capable of permeating moisture) insulating layer is not provided around the terminal electrode layer. Further, the display device has a separation region 231, an external terminal connection region 232, a wiring region 233, a peripheral drive circuit region 234, and a pixel region 236. In this case, in both injection-type display devices shown in Fig. 12 described above, a metal layer 1624 having reflectivity is formed under the first electrode layer 1317. A first electrode layer 1617, which is a transparent conductive film functioning as an anode, is formed on the reflective metal layer 1624 having reflectivity. As the metal layer 1624, any material having reflectivity may be used, such as Ta, W, Ti, Mo, Al, Cu, etc. Preferably, a material having high reflectivity in the visible light region is used. In this embodiment, a TiN film is used.

[0145] A second electrode layer 1620 made of a conductive film is provided on the electroluminescent layer 1619. As the second electrode layer 1620, a material having a small work function (Al, Ag, Li, Ca, or alloys or compounds thereof, MgAg, MgIn, AlLi, Ca F2, or calcium nitride) may be used. In this embodiment, in order for light emission to be transmitted a metal thin film with a reduced thickness (MgAg: film thickness 10 nm) is used as the second electrode layer 1620, and a stack of ITSO with a film thickness of 110 nm is used as the transparent conductive film 1621.

[0146] The form of the light-emitting element applicable in this embodiment is shown in FIG. 13. The light-emitting element has a configuration in which an electroluminescent layer 860 is sandwiched between a first electrode layer 870 and a second electrode layer 850. The first electrode layer and the second electrode layer need to select materials in consideration of the work function, and both the first electrode layer and the second electrode layer can be either an anode or a cathode depending on the pixel configuration. In this embodiment, when the polarity of the driving TFT is p-channel type, the first electrode layer is preferably an anode and the second electrode layer is preferably a cathode. Also, since the polarity of the driving TFT is N-channel type it is preferable that the first electrode layer is a cathode and the second electrode layer is an anode.

[0147] FIGS. 13(A) and (B) show the case where the first electrode layer 870 is an anode and the second electrode layer 850 is a cathode. The electroluminescent layer 860 is preferably laminated in the order of HIL (hole injection layer), HTL (hole transport layer) 804, EML (emitting layer) 803, ETL (electron transport layer), EIL (electron injection layer) 802, and the second electrode layer 850 from the side of the first electrode layer 870. FIG. 13(A) shows a configuration in which light is emitted from the first electrode layer 870. The first electrode layer 870 is composed of an electrode layer 805 made of a transparent oxide conductive material. The second electrode layer is an electrode containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the side of the electroluminescent layer 860. It is composed of a layer 801 and an electrode layer 800 formed of a metal material such as aluminum. FIG 13(B) has a configuration in which light is emitted from the second electrode layer 850. The first electrode layer is made of aluminum a metal such as nickel or titanium, or a metal material containing nitrogen at a concentration below the stoichiometric composition ratio with the metal It is composed of an electrode layer 807 formed of a material and a second electrode layer 806 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. The second electrode layer is from the side of the electroluminescent layer 860, an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum. However, by setting the thickness of any layer to 100 nm or less so that light can be transmitted, it is possible to emit light from the second electrode layer 850. FIGS. 13(C) and (D) show a case where the first electrode layer 870 is a cathode and the second electrode layer 850 is an anode. The electroluminescent layer 860 is preferably laminated in the order of an EIL (electron injection layer) ETL

[0148] (electron transport layer) 802, an EML (emitting layer) 803, an HTL (hole transport layer) HIL (hole injection layer) 804, and the second electrode layer 850 which is an anode from the cathode side. FIG. 13 (C) has a configuration in which light is emitted from the first electrode layer 870. The first electrode layer 870 is an electroluminescent layer 860 side, an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum. However, by setting the thickness of any layer to 100 nm or less so that light can be transmitted, it is possible to emit light from the first electrode layer 870. The second electrode layer is from the side of the electroluminescent layer 860 or By making the thickness of any layer 100 nm or less so that light can be transmitted, it is possible to emit light from the first electrode layer 870. The second electrode layer is on the side of the electroluminescent layer 860 The second electrode layer 8 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic %. 06, It is composed of an electrode layer 807 formed of a metal such as aluminum or titanium, or a metal material containing nitrogen at a concentration below the stoichiometric composition ratio of the metal. FIG. 13(D) shows a configuration in which light is emitted from the second electrode layer 850. The first electrode layer 870 is composed of an electrode layer 801 containing an alkali metal or an alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum. The film thickness is formed thick enough to reflect the light emitted from the electroluminescent layer 8 60. The second electrode layer 850 is composed of an electrode layer 805 made of a translucent oxide conductive material. The electroluminescent layer can have a single-layer structure, a mixed structure, or other than a laminated structure. from the electroluminescent layer 860 side. The first electrode layer 870 is composed of an electrode layer 801 containing an alkali metal or an alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum. The film thickness is formed thick enough to reflect the light emitted from the electroluminescent layer 8 60. The second electrode layer 850 is composed of an electrode layer 805 made of a translucent oxide conductive material. The electroluminescent layer can have a single-layer structure, a mixed structure, or other than a laminated structure. The second electrode layer 850 is composed of an electrode layer 805 made of a translucent oxide conductive material. The electroluminescent layer can have a single-layer structure, a mixed structure, or other than a laminated structure. The second electrode layer 850 is composed of an electrode layer 805 made of a translucent oxide conductive material. The electroluminescent layer can have a single-layer structure, a mixed structure, or other than a laminated structure. In addition to the laminated structure, the electroluminescent layer can have a single-layer structure or a mixed structure.

[0149] In addition, as the electroluminescent layer, materials that exhibit red (R), green (G), and blue (B) light emission are selectively formed by a vapor deposition method using a vapor deposition mask or the like. Materials that exhibit red (R), green ( G), and blue (B) light emission can also be formed by a droplet discharge method (such as low molecular weight or high molecular weight materials). In this case, it is preferable because RGB painting can be performed without using a mask. G), and blue (B) light emission can also be formed by a droplet discharge method (such as low molecular weight or high molecular weight materials). In this case, it is preferable because RGB painting can be performed without using a mask. G), and blue (B) light emission can also be formed by a droplet discharge method (such as low molecular weight or high molecular weight materials). In this case, it is preferable because RGB painting can be performed without using a mask.

[0150] In the case of the top emission type, when using ITO or ITSO having translucency for the second electrode layer BzOs-Li obtained by adding Li to a benzoxazole derivative (BzOs) can be used. For example, as the EML, Alq3 doped with dopants corresponding to the respective emission colors of R, G, and B (such as DCM for R and DMQD for G) can be used. BzOs-Li obtained by adding Li to a benzoxazole derivative (BzOs) can be used. For example, as the EML, Alq3 doped with dopants corresponding to the respective emission colors of R, G, and B (such as DCM for R and DMQD for G) can be used. BzOs-Li obtained by adding Li to a benzoxazole derivative (BzOs) can be used. For example, as the EML, Alq3 doped with dopants corresponding to the respective emission colors of R, G, and B (such as DCM for R and DMQD for G) can be used. That's it.

[0151] Note that the electroluminescent layer is not limited to the above materials. For example, instead of CuPc or PEDOT, oxides such as molybdenum oxide (MoOx: x = 2 to 3) and α-NPD or rubrene can be co-evaporated to form and improve the hole injection property. Also, the material of the electroluminescent layer can be used as an organic material (including low molecular weight or high molecular weight) or a composite material of an organic material and an inorganic material. The materials for forming the light-emitting element will be described in detail below.

[0152] Among the charge injection and transport materials, particularly high electron-transporting materials include, for example, tris(8- quinolinolato)aluminum (abbreviation: Alq3), tris(5-methyl-8-quinolinolato)aluminum (abbreviation: Almq3), bis(10-hydroxybenzo[h]-quinolinato)beryllium (abbreviation: BeBq2), bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and metal complexes having a quinoline skeleton or a benzoquinoline skeleton. Also, high hole-transporting materials include, for example, 4,4'-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (abbreviation: α-NPD), 4,4'-bis[N-(3-methylphenyl)-N-phenyl-amino]-biphenyl (abbreviation: TPD), 4,4',4''-tris(N,N-diphenyl-amino)-triphenylamine (abbreviation: TDATA), 4,4',4''-tris[N-(3- methylphenyl)-N-phenyl-amino]-triphenylamine (abbreviation: MTDATA ), etc., aromatic amine-based (i.e., having a benzene ring-nitrogen bond) compounds. For example, 4,4'-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (abbreviation: α-NPD), 4,4'-bis[N-(3-methylphenyl)-N-phenyl-amino]-biphenyl (abbreviation: TPD), 4,4',4''-tris(N,N-diphenyl-amino)-triphenylamine (abbreviation: TDATA), 4,4',4''-tris[N-(3- methylphenyl)-N-phenyl-amino]-triphenylamine (abbreviation: MTDATA ), etc., aromatic amine-based (i.e., having a benzene ring-nitrogen bond) compounds. are mentioned.

[0153] Among the charge injection and transport materials, particularly as materials with high electron injection properties, there are compounds of alkali metals or alkaline earth metals such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF2), etc. Also, in addition to these, a mixture of a material with high electron transport properties such as Alq3 and an alkaline earth metal such as magnesium (Mg) may be used. Among the charge injection and transport materials, as materials with high hole injection properties, for example, there are metal oxides such as molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), tungsten oxide (WOx), manganese oxide (MnOx), etc. Also, in addition to these, there are phthalocyanine-based compounds such as phthalocyanine (abbreviation: H2Pc) and copper phthalocyanine (CuPc). The light-emitting layer may be configured to form light-emitting layers with different emission wavelength bands for each pixel to perform color display. Typically, light-emitting layers corresponding to each color of R (red), G (green), and B (blue) are formed. Also, in this case, by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel, it is possible to improve color purity and prevent mirroring (reflection) of the pixel portion. By providing the filter, it becomes possible to omit a circular polarizing plate or the like that has been conventionally considered necessary, and to eliminate the loss of light emitted from the light-emitting layer. Furthermore, it is possible to reduce the change in color tone that occurs when viewing the pixel portion (display screen) from an oblique direction. There are various materials for the light-emitting material. Among the low-molecular organic light-emitting materials, 4-dicyanomethylene-

[0154]

[0155]

[0156] 2-Methyl-6-[2-(1,1,7,7-tetramethyl-9-julolidinyl)ethenyl]- 4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6-[2- (1,1,7,7-tetramethyldecylyl-9-yl)ethenyl]-4H-pyran (abbreviation: DCJTB), periflanthene, 2,5-dicyano-1,4-bis[2-(10-methoxy -1,1,7,7-tetramethyldecylyl-9-yl)ethenyl]benzene, N,N’- dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris(8 -quinolinolato)aluminum (abbreviation: Alq3), 9,9’-bianthryl, 9,10-di phenylanthracene (abbreviation: DPA), 9,10-bis(2-naphthyl)anthracene ( abbreviation: DNA), etc. can be used. Other substances may also be used.

[0157] On the other hand, polymer-based organic light-emitting materials have higher physical strength than low-molecular-weight materials, and the durability of the device is high. Also, since it is possible to form a film by coating, the fabrication of the device is relatively easy. The structure of a light-emitting device using a polymer-based organic light-emitting material is basically the same as that when using a low-molecular-weight organic light-emitting material, and consists of a cathode, an organic light-emitting layer, and an anode in that order. However, when forming a light-emitting layer using a polymer-based organic light-emitting material, it is difficult to form a laminated structure as in the case of using a low-molecular-weight organic light-emitting material, and in many cases, it has a two-layer structure. Specifically, it has a laminated structure of a cathode, a light-emitting layer, a hole transport layer, and an anode in that order. Since the emission color is determined by the material forming the light-emitting layer, a light-emitting device showing a desired emission can be formed by selecting these. Polymer-based materials that can be used for forming the light-emitting layer are as follows.

[0158] Since the emission color is determined by the material forming the light-emitting layer, a light-emitting device showing a desired emission can be formed by selecting these. Polymer-based materials that can be used for forming the light-emitting layer are as follows. Electroluminescent materials include poly(p-phenylene vinylene)-based, poly(p-phenylene)-based, polythiophene-based, and polyfluorene-based materials. Examples of poly(p-phenylene vinylene)-based materials include derivatives of poly(p-phenylene vinylene) [PPV], poly(2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV],

[0159] poly(2-(2'-ethyl-hexyloxy)-5-methoxy-1,4-phenylene vinylene) [MEH-PPV], poly(2-(dialkoxyphenyl)-1,4-phenylene vinylene) [ROPh-PPV], and the like. Examples of poly(p-phenylene)-based materials include derivatives of poly(p-phenylene) [PPP], poly(2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly(2,5-dihexyloxy-1,4-phenylene), and the like. Examples of polythiophene-based materials include derivatives of polythiophene [PT], poly(3-alkylthiophene) [PAT], poly(3-hexylthiophene) [PHT], poly(3-cyclohexylthiophene) [PCHT], poly(3-cyclohexyl-4-methylthiophene) [PCHMT], poly(3,4-dicyclohexylthiophene) [PDCHT], poly[3-(4-octylphenyl)-thiophene] [POPT], poly[3-(4-octylphenyl)-2,2-bithiophene] [PTOPT], and the like. Examples of polyfluorene-based materials include derivatives of polyfluorene [PF], poly(9,9-dialkylfluorene) [PDAF], poly(9,9-dioctylfluorene) [PDOF], and the like. In addition, a hole-transporting polymer-based organic light-emitting material is used between the anode and the light-emitting polymer-based organic light-emitting material.

[0160] ​​​​​​​​When formed by sandwiching, the hole injection property from the anode can be improved. Generally, a solution dissolved in water together with the acceptor material is applied by a spin coating method or the like. Also, since it is insoluble in organic solvents, it can be laminated with the above-described light-emitting organic light-emitting material. Examples of the hole transporting polymer-based organic light-emitting material include a mixture of PEDOT and camphorsulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. A solution dissolved in water together with the acceptor material is applied by a spin coating method or the like. Also, since it is insoluble in organic solvents, it can be laminated with the above-described light-emitting organic light-emitting material. Since it is insoluble in organic solvents, it can be laminated with the above-described light-emitting organic light-emitting material. Examples of the hole transporting polymer-based organic light-emitting material include a mixture of PEDOT and camphorsulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. Examples of the hole transporting polymer-based organic light-emitting material include a mixture of PEDOT and camphorsulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. Examples of the hole transporting polymer-based organic light-emitting material include a mixture of PEDOT and camphorsulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. Examples of the hole transporting polymer-based organic light-emitting material include a mixture of PEDOT and camphorsulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like.

[0161] Also, the light-emitting layer can be configured to exhibit single-color or white light emission. When a white light-emitting material is used, color display can be enabled by providing a filter (colored layer) that transmits light of a specific wavelength on the light-emitting side of the pixel. When a white light-emitting material is used, color display can be enabled by providing a filter (colored layer) that transmits light of a specific wavelength on the light-emitting side of the pixel. When a white light-emitting material is used, color display can be enabled by providing a filter (colored layer) that transmits light of a specific wavelength on the light-emitting side of the pixel.

[0162] To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly To form a light-emitting layer that emits white light, for example, white can be obtained by sequentially laminating Alq3, Alq3 doped with Nile Red which is partially a red light-emitting dye, Alq3, p-EtTAZ, and TPD (aromatic diamine) by a vapor deposition method. Also, when forming EL by a coating method using spin coating, it is preferable to bake it by vacuum heating after coating. For example, an aqueous solution of poly(ethylenedioxythiophene) / poly(styrene sulfonic acid) (PEDOT / PSS) that acts as a hole injection layer is applied over the entire surface and baked, and then, a light-emitting center dye (1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile Red, Coumarin 6, etc.) doped poly The vinyl carbazole (PVK) solution may be applied to the entire surface and fired.

[0163] The light-emitting layer can also be formed as a single layer, or an electron-transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in a hole-transporting polyvinyl carbazole (PV K). In addition, white light emission can be obtained by dispersing 30 wt% of PBD as an electron transport agent and an appropriate amount of four types of dyes (TPB, coumarin 6, DCM1, Nile Red). In addition to the light-emitting device that exhibits white light emission shown here, by appropriately selecting the material of the light-emitting layer, a light-emitting device that exhibits red light emission, green light emission, or blue light emission can be fabricated.

[0164] Furthermore, in addition to the singlet excitation light-emitting material, the light-emitting layer may use a triplet excitation material such as a metal complex. For example, among the red light-emitting pixel, green light-emitting pixel, and blue light-emitting pixel, the red light-emitting pixel with a relatively short luminance half-life is formed of a triplet excitation light-emitting material and the others are formed of a singlet excitation light-emitting material. Since the triplet excitation light-emitting material has good luminous efficiency, it has the characteristic that less power consumption is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light-emitting device can be reduced, so that the reliability can be improved. As a measure for reducing power consumption, the red light-emitting pixel and the green light-emitting pixel may be formed of a triplet excitation light-emitting material and the blue light-emitting pixel may be formed of a singlet excitation light-emitting material. By forming the green light-emitting device with high human visual sensitivity also of a triplet excitation light-emitting material, further power consumption reduction can be achieved.

[0165] As an example of the triplet excitation light-emitting material, there is one using a metal complex as a dopant. , metal complexes having platinum, which is a third transition series element, as a central metal, and iridium as a central metal Metal complexes and the like are known. The triplet excimer luminescent materials are not limited to these compounds It is also possible to use a compound having the above structure and having an element belonging to Groups 8 to 10 of the periodic table as the central metal.

[0166] The substances forming the light-emitting layer described above are merely examples, and a light-emitting element can be formed by appropriately laminating functional layers such as a hole injection / transport layer, a hole transport layer, an electron injection / transport layer, an electron transport layer, a light-emitting layer, an electron blocking layer, and a hole blocking layer. Further, a mixed layer or a mixed junction may be formed by combining these layers. The layer structure of the light-emitting layer can be changed. Instead of having a specific electron injection region or light-emitting region, modifications such as having only an electrode layer for this purpose or having a light-emitting material dispersed therein are allowed within the scope not departing from the gist of the present invention.

[0167] The light-emitting element formed of the above-described material emits light when biased in the forward direction. The pixel of the display device formed using the light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias in a specific timing, but is in a non-light-emitting state for a certain period. By applying a reverse bias during this non-light-emitting time, the reliability of the light-emitting element can be improved. In the light-emitting element, there are deterioration modes in which the light-emitting intensity decreases under certain driving conditions and the non-light-emitting region expands within the pixel, resulting in a decrease in apparent luminance. However, by performing an alternating drive in which forward and reverse biases are applied, the progress of deterioration can be slowed down. ​ (k) can improve the reliability of the light-emitting device. Also, it can be applied to either digital driving or analog driving.

[0168] Therefore, a color filter (coloring layer) may be formed on the encapsulation substrate. The color filter ( coloring layer) can be formed by a vapor deposition method or a droplet discharge method. When using the color filter (coloring layer ), high-definition display can also be performed. The color filter (coloring layer) can correct the broad peak in the emission spectrum of each RGB to a sharp peak. This is because of this.

[0169] Above, the case of forming materials showing the emission of each RGB has been described. However, by forming a material showing single-color emission and combining it with a color filter or a color conversion layer, full-color display can be performed. The color filter (coloring layer) and the color conversion layer can be formed on, for example, the second substrate (encapsulation substrate) and then bonded to the substrate.

[0170] Of course, single-color emission display may also be performed. For example, an area color type display device may be formed using single-color emission. The area color type is suitable for a passive matrix type display section and can mainly display characters and symbols.

[0171] In the above configuration, as the cathode, a material with a small work function can be used. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. The electroluminescent layer may be of any of a single-layer type, a laminated type, or a mixed type without layer interfaces. Also, a singlet material, a triplet material, or a material combining them, or a charge injection containing an organic compound or an inorganic compound Formed of a transport material and a light-emitting material, and including one or more layers selected from low-molecular organic compounds, medium-molecular organic compounds (referring to organic compounds that do not have sublimability and have a molecular number of 20 or less, or a chain molecular length of 10 μm or less), and high-molecular organic compounds, and may be combined with an inorganic compound having electron injection / transport properties or hole injection / transport properties. The first electrode layer is formed using a transparent conductive film that transmits light. For example, in addition to ITO and ITSO, a transparent conductive film in which indium oxide is mixed with 2 to 20 atomic% of zinc oxide (ZnO) is used. Note that, before forming the first electrode layer, plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere may be performed. The partition (also referred to as a bank) is formed using a material containing silicon, an organic material, and a compound material. Also, a porous film may be used. However, when formed using a photosensitive or non-photosensitive material such as acrylic or polyimide, the side surface thereof has a shape in which the radius of curvature continuously changes, and the upper thin film is preferably formed without steps (without breaking). The form of this embodiment can be freely combined with the above-described embodiments. (It does not have sublimability and has a molecular number of 20 or less, or refers to an organic compound having a chain molecular length of 10 μm or less.) Including one or more layers selected from the above, and may be combined with an inorganic compound having electron injection / transport properties or hole injection / transport properties. The first electrode layer is formed using a transparent conductive film that transmits light. For example, in addition to ITO and ITSO, a transparent conductive film in which indium oxide is mixed with 2 to 20 atomic% of zinc oxide (ZnO) is used. Note that, before forming the first electrode layer, plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere may be performed. The partition (also referred to as a bank) is formed using a material containing silicon, an organic material, and a compound material. Also, a porous film may be used. However, when formed using a photosensitive or non-photosensitive material such as acrylic or polyimide, the side surface thereof has a shape in which the radius of curvature continuously changes, and the upper thin film is preferably formed without steps (without breaking). The form of this embodiment can be freely combined with the above-described embodiments. When the present invention is used, a highly reliable display device can be manufactured with a simplified process. Therefore, a high-definition and high-quality display device can be manufactured with a low cost and a high yield. This embodiment can be used in combination with Embodiments 1 to 3, respectively.

[0172]

[0173] This embodiment can be used in combination with Embodiments 1 to 3, respectively.

[0174] (Embodiment 5) Regarding one aspect in which protection diodes are provided at the scanning line side input terminal portion and the signal line side input terminal portion. A description will be given with reference to FIG. 15. In FIG. 15, a TFT 501, a TFT 502, a capacitive element 504, and a light-emitting element 503 are provided in the pixel 2702. This TFT has the same configuration as that in Embodiment 1.

[0175] A protection diode 561 and a protection diode 562 are provided at the signal line side input terminal portion. This protection diode is fabricated in the same process as the TFT 501 or the TFT 502, and is operated as a diode by connecting one of the gate and the drain or the source. The equivalent circuit diagram of the top view shown in FIG. 15 is shown in FIG. 14. The protection diode 561 is composed of a gate electrode layer, a semiconductor layer, and a wiring layer. The protection

[0176] diode 562 has the same structure. The common potential lines 554 and 555 connected to this protection diode are formed in the same layer as the gate electrode layer. Therefore, in order to be electrically continuous with the wiring layer, it is necessary to form contact holes in the insulating layer. The contact holes to the insulating layer may be formed by forming a mask layer and performing etching. In this case, if atmospheric pressure discharge etching is applied, local discharge processing is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate. The signal wiring layer is formed in the same layer as the source and drain wiring layers 505 in the TFT 501, and has a structure in which the signal wiring layer connected thereto is connected to the source or the drain side.

[0177] The input terminal portion on the scanning signal line side has the same configuration. The protection diode 563 is a gate electrode... The input terminal portion on the scanning signal line side has the same configuration. The protection diode 563 is a gate

[0178] The signal wiring layer is formed in the same layer as the source and drain wiring layers 505 in the TFT 501, and has a structure in which the signal wiring layer connected thereto is connected to the source or the drain side. The input terminal portion on the scanning signal line side has the same configuration. The protection diode 563 is a gate electrode...

[0179] The input terminal portion on the scanning signal line side has the same configuration. The protection diode 563 is a gate It consists of a polar layer, a semiconductor layer, and a wiring layer. The protection diode 564 has a similar structure. The common potential lines 556 and 557 connected to this protection diode are formed in the same layer as the source and drain wiring layers. It is possible to simultaneously form the protection diodes provided in the input stage. Note that the position where the protection diode is inserted is not limited to only this embodiment, and it can also be provided between the drive circuit and the pixel.

[0180] (Embodiment 6) A television device can be completed by the display device formed according to the present invention. On the display panel, only the pixel portion is formed as shown in FIG. 16(A). There are cases where the scanning line side drive circuit and the signal line side drive circuit are mounted by the TAB method as shown in FIG. 17(B), cases where they are mounted by the COG method as shown in FIG. 17(A), cases where TFTs are formed by SAS as shown in FIG. 16(B), the pixel portion and the scanning line side drive circuit are integrally formed on the substrate, and the signal line side drive circuit is separately mounted as a driver IC, and cases where the pixel portion, the signal line side drive circuit, and the scanning line side drive circuit are integrally formed on the substrate as shown in FIG. 16(C), etc., but any form is acceptable.

[0181] As for the configuration of other external circuits, on the input side of the video signal, among the signals received by the tuner, there are a video signal amplification circuit that amplifies the video signal, a video signal processing circuit that converts the signal output therefrom into color signals corresponding to each of the red, green, and blue colors, and a control circuit for converting the video signal into the input specification of the driver IC, etc. The control circuit outputs signals to the scanning line side and the signal line side respectively. When digitally driving, signals are output to the signal line side. It is also possible to provide a signal splitting circuit and configure it to split the input digital signal into m signals for supply.

[0182] Of the signals received by the tuner, the audio signal is sent to the audio signal amplification circuit, and the output thereof is supplied to the speaker via the audio signal processing circuit. The control circuit receives control information on the receiving station (receiving frequency) and the volume from the input section and sends signals to the tuner and the audio signal processing circuit.

[0183] As shown in FIGS. 20(A) and 20(B), the display module can be incorporated into the housing to complete the television receiver. The display panel as shown in FIG. 1 that is attached up to the FPC is generally also referred to as an EL display module. Therefore, by using the EL display module as shown in FIG. 1, an EL television receiver can be completed. The display module forms the main screen 2003, and other accessories such as a speaker unit 2009 and an operation switch are provided. In this way, the television receiver can be completed according to the present invention.

[0184] Also, a retardation plate or a polarizing plate may be used to block the reflected light of the light incident from the outside. Further, in the case of a top emission type display device, the insulating layer serving as a partition may be colored and used as a black matrix. This partition can also be formed by a droplet discharge method or the like, and carbon black or the like may be mixed into a pigment-based black resin or a resin material such as polyimide, or a laminate thereof may be used. Different materials may be discharged a plurality of times into the same region by the droplet discharge method to form a partition. As the retardation plate, a λ / 4 plate or a λ / 2 plate may be used, and it may be designed so that light can be controlled. The configuration is, in order, a TFT element substrate, a light emitting element, and a sealing substrate ( ​​​​​​​It becomes a sealing material, a retardation plate, a retardation plate (λ / 4 plate, λ / 2 plate), and a polarizing plate, and the light emitted from the light-emitting element passes through these and is radiated to the outside from the polarizing plate side. These retardation plates and polarizing plates may be installed on the side where the light is radiated, and in the case of a double-sided radiation type display device that radiates light on both sides, they can be installed on both sides. Also, an antireflection film may be provided outside the polarizing plate. Thus, a finer and more precise image can be displayed. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. Also, an antireflection film may be provided outside the polarizing plate. Thus, a finer and more precise image can be displayed. Also, an antireflection film may be provided outside the polarizing plate. Thus, a finer and more precise image can be displayed.

[0185] As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided. As shown in FIG. 20(A), a display panel 2002 using a display element is incorporated in a housing 2001, and a receiver 2005 receives general television broadcasts and is connected to a communication network by wire or wirelessly via a modem 2004, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers) information communication. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote control unit 2006, and a display unit 2007 for displaying the information output to this remote control device may be provided.

[0186] In addition, in the television device, in addition to the main screen 2003, a sub-screen 2008 may be formed on a second display panel to display channels, volume, etc. In this configuration, the main screen 2003 may be formed of an EL display panel with excellent viewing angles, and the sub-screen may be formed of a liquid crystal display panel capable of displaying with low power consumption. Also, in order to prioritize low power consumption, the main screen 2003 may be formed of a liquid crystal display panel, the sub-screen may be formed of an EL display panel, and the sub-screen may be configured to be blinkable. Using the present invention, In addition, in the television device, in addition to the main screen 2003, a sub-screen 2008 may be formed on a second display panel to display channels, volume, etc. In this configuration, the main screen 2003 may be formed of an EL display panel with excellent viewing angles, and the sub-screen may be formed of a liquid crystal display panel capable of displaying with low power consumption. Also, in order to prioritize low power consumption, the main screen 2003 may be formed of a liquid crystal display panel, the sub-screen may be formed of an EL display panel, and the sub-screen may be configured to be blinkable. Using the present invention, In addition, in the television device, in addition to the main screen 2003, a sub-screen 2008 may be formed on a second display panel to display channels, volume, etc. In this configuration, the main screen 2003 may be formed of an EL display panel with excellent viewing angles, and the sub-screen may be formed of a liquid crystal display panel capable of displaying with low power consumption. Also, in order to prioritize low power consumption, the main screen 2003 may be formed of a liquid crystal display panel, the sub-screen may be formed of an EL display panel, and the sub-screen may be configured to be blinkable. Using the present invention, In addition, in the television device, in addition to the main screen 2003, a sub-screen 2008 may be formed on a second display panel to display channels, volume, etc. In this configuration, the main screen 2003 may be formed of an EL display panel with excellent viewing angles, and the sub-screen may be formed of a liquid crystal display panel capable of displaying with low power consumption. Also, in order to prioritize low power consumption, the main screen 2003 may be formed of a liquid crystal display panel, the sub-screen may be formed of an EL display panel, and the sub-screen may be configured to be blinkable. Using the present invention, In addition, in the television device, in addition to the main screen 2003, a sub-screen 2008 may be formed on a second display panel to display channels, volume, etc. In this configuration, the main screen 2003 may be formed of an EL display panel with excellent viewing angles, and the sub-screen may be formed of a liquid crystal display panel capable of displaying with low power consumption. Also, in order to prioritize low power consumption, the main screen 2003 may be formed of a liquid crystal display panel, the sub-screen may be formed of an EL display panel, and the sub-screen may be configured to be blinkable. Using the present invention, In addition, in the television device, in addition to the main screen 2003, a sub-screen 2008 may be formed on a second display panel to display channels, volume, etc. In this configuration, the main screen 2003 may be formed of an EL display panel with excellent viewing angles, and the sub-screen may be formed of a liquid crystal display panel capable of displaying with low power consumption. Also, in order to prioritize low power consumption, the main screen 2003 may be formed of a liquid crystal display panel, the sub-screen may be formed of an EL display panel, and the sub-screen may be configured to be blinkable. Using the present invention, Even when using a large substrate and a large number of TFTs and electronic components, a highly reliable display device can be achieved. This is possible.

[0187] FIG. 20(B) shows a television device having a large display unit of, for example, 20 to 80 inches. It includes a housing 2010, a keyboard unit 2012 which is an operation unit, a display unit 2011, a speaker unit 2013, etc. The present invention is applied to the production of the display unit 2011. The display unit in FIG. 20(B) uses a bendable material, so it is a television device in which the display unit is bent. Since the shape of the display unit can be freely designed in this way, a television device with a desired shape can be manufactured.

[0188] According to the present invention, since a display device can be formed in a simple process, cost reduction can also be achieved. Therefore, in a television device using the present invention, even if it has a large-screen display unit, it can be formed at a low cost. Therefore, a high-performance and highly reliable television device can be manufactured with a high yield. This is possible.

[0189] Of course, the present invention is not limited to television devices, and can be applied to various uses as a large-area display medium such as a monitor of a personal computer, an information display board at a railway station or an airport, and an advertisement display board on the street. Starting with a monitor of a personal computer, an information display board at a railway station or an airport, and an advertisement display board on the street, etc. It can be applied to various uses.

[0190] (Embodiment 7) By applying the present invention, various display devices can be manufactured. That is, the present invention can be applied to various electronic devices incorporating those display devices in the display unit. This is possible.

[0191] Such electronic devices include cameras such as video cameras and digital cameras, projectors Terminal, head-mounted display (goggle-type display), car navigation, car stereo, personal computer, game device, portable information terminal (mobile computer, mobile phone or e-book, etc.), image playback device equipped with a recording medium (specifically, a device capable of playing a recording medium such as a Digital Versatile Disc (DVD) and displaying the image on a display equipped therewith), etc. Examples thereof are shown in Fig. 21.

[0192] Fig. 21(A) is a computer, including a main body 2101, a housing 2102, a display unit 210 3, a keyboard 2104, an external connection port 2105, a pointing mouse 2106, etc. When using the present invention, even if miniaturized and the pixels are miniaturized, a computer capable of displaying highly reliable and high-quality images can be completed.

[0193] Fig. 21(B) is an image playback device equipped with a recording medium (specifically, a DVD playback device), including a main body 2201, a housing 2202, a display unit A2203, a display unit B2204, a recording medium (DV D, etc.) reading unit 2205, operation keys 2206, a speaker unit 2207, etc. The display unit A2203 mainly displays image information, and the display unit B2204 mainly displays character information. When using the present invention, even if miniaturized and the pixels are miniaturized, an image playback device capable of displaying highly reliable and high-quality images can be completed.

[0194] Fig. 21(C) is a mobile phone, including a main body 2301, a voice output unit 2302, a voice input unit 2 303, a display unit 2304, an operation switch 2305, an antenna 2306, etc. When using the present invention, even if miniaturized and the pixels are miniaturized, a mobile phone capable of displaying highly reliable and high-quality images The telephone can be completed.

[0195] FIG. 21(D) is a video camera, including a main body 2401, a display unit 2402, a housing 2403 , an external connection port 2404, a remote control receiving unit 2405, an imaging unit 2406, a battery 24 07, an audio input unit 2408, an eyepiece 2409, operation keys 2410, etc. When the present invention is used , a video camera that can be miniaturized, has high reliability even when pixels are miniaturized, and can display high-quality images can be completed. This embodiment can be freely combined with the above-described embodiments. It can be.

Claims

1. A light-emitting display device capable of color display, a first electrode layer electrically connected to the transistor; an insulating layer having an area over the first electrode layer; an electroluminescent layer having a region over the first electrode layer and a region over the insulating layer; the electroluminescent layer emits white light; the insulating layer has a portion covering an end of the first electrode layer and a portion provided on the first electrode layer so as to divide a light emitting region; The light emitted from the electroluminescent layer is extracted through a color filter.

2. A light-emitting display device capable of color display, A transistor; a first electrode layer on the transistor; an insulating layer having an area over the first electrode layer; an electroluminescent layer having a region over the first electrode layer and a region over the insulating layer; the electroluminescent layer emits white light; the first electrode layer is electrically connected to the transistor; the insulating layer has a portion covering an end of the first electrode layer and a portion provided on the first electrode layer so as to divide a light emitting region; The light emitted from the electroluminescent layer is extracted through a color filter.

3. A light-emitting display device having a first pixel and a second pixel and capable of color display, a color taken from the first pixel is different from a color taken from the second pixel; The first pixel includes: a first electrode layer electrically connected to the transistor; an insulating layer having an area over the first electrode layer; an electroluminescent layer having a region over the first electrode layer and a region over the insulating layer; the electroluminescent layer emits white light; the insulating layer has a portion covering an end of the first electrode layer and a portion provided on the first electrode layer so as to divide a light emitting region; The light emitted from the electroluminescent layer is extracted through a color filter.

4. A light-emitting display device having a first pixel and a second pixel and capable of color display, a color taken from the first pixel is different from a color taken from the second pixel; The first pixel includes: A transistor; a first electrode layer on the transistor; an insulating layer having an area over the first electrode layer; an electroluminescent layer having a region over the first electrode layer and a region over the insulating layer; the electroluminescent layer emits white light; the first electrode layer is electrically connected to the transistor; the insulating layer has a portion covering an end of the first electrode layer and a portion provided on the first electrode layer so as to divide a light emitting region; The light emitted from the electroluminescent layer is extracted through a color filter.

5. In claim 3 or claim 4, the electroluminescent layer has an area overlapping with a light-emitting area of ​​the second pixel.

6. In any one of claims 1 to 5, The electroluminescent layer has a plurality of light-emitting regions on the first electrode layer.

7. In any one of claims 1 to 6, a second electrode layer having an area over the electroluminescent layer; The light emitting display device, wherein light emitted from the electroluminescent layer is extracted from the second electrode layer side.

Images