Arc Flash Reduction Device

The arc flash mitigation device addresses the long response time of current protection systems by using an electromechanical switching device and a solid-state bypass power switch to quickly interrupt fault currents, effectively mitigating arc flash events.

JP7699653B2Active Publication Date: 2025-06-27EATON INTELLIGENT POWER LTD
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Patent Information

Application Number
JP2023519997
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2020-10-14
Filing Date
2021-10-07
Publication Date
2025-06-27
Estimated Expiration
2041-10-07

AI Technical Summary

Technical Problem

Current protection systems have a relatively long response time to interrupt dangerous currents associated with short circuit faults and eliminate arc flash events, especially in cases of faults caused by low-level overcurrents.

Method used

The implementation of an arc flash mitigation device that includes an electromechanical switching device, a bypass power switch device with a solid-state circuit breaker, and a current sensor, which detects fault currents and triggers the actuator to open the electromechanical switching device, allowing the bypass power switch device to interrupt the fault current.

Benefits of technology

This solution achieves a significantly shorter response time to interrupt fault currents, effectively mitigating arc flash events and protecting maintenance personnel and equipment.

✦ Generated by Eureka AI based on patent content.

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Abstract

The device includes an electromechanical switching device having an open-circuit state and a closed-circuit state, and a path of least resistance having a path input and a path output, the switching device being between the input and the output. The device includes a bypass power switch device comprising a solid-state circuit breaker and configured to conduct current between the input and the output in response to an open-circuit state of the switch device. The device includes a current sensor connected to the output and configured to detect a fault current event. The device includes an actuator coupled to the switching device, and a controller configured to generate a trigger signal to activate the actuator to place the switching device in an open-circuit state and interrupt the fault current event with the power switch device based on the detected fault current event.
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Description

Technical Field

[0001] This document describes devices, systems, and methods for power protection devices, systems, and methods, and more particularly, for arc flash mitigation devices for protecting maintenance personnel and power equipment.

[0002] Arc flash events can not only cause significant damage to distribution systems such as switchgear and switchboards, but also potentially cause injury to workers. Circuit breakers and fuses can be used in switchgear to provide protection in the event of a short circuit fault. However, current protection systems have a relatively long response time to interrupt the propagation of dangerous currents associated with short circuit faults and eliminate arc flash events, especially in the case of faults caused by low-level overcurrents.

[0003] To provide additional protection in the event of an arc flash event, it is desirable to have an arc flash mitigation device with an even shorter response time.

Summary of the Invention

[0004] In some embodiments, the device includes an electromechanical switching device having an open circuit state and a closed circuit state, and a minimum resistance path having a path input and a path output, the electromechanical switching device being between the path input and the path output. The device may also include a bypass power switch device including a solid-state circuit breaker configured to conduct current between the path input and the path output in response to the open circuit state of the electromechanical switching device. In this device, a current sensor is connected to the path output and configured to detect a fault current event. The device may include an actuator coupled to the electromechanical switching device and a controller. Based on the detected fault current event, the controller operates the actuator to place the electromechanical switching device in the open circuit state and generates a trigger signal for interrupting the fault current event by the bypass power switch device.

[0005] In various embodiments, the current sensor may have an output connected to the sensor input of the controller. The current sensor may be configured to communicate a signal representative of the detection of a fault current event to the sensor input of the controller.

[0006] In various embodiments, the device may further include an external control panel connected to the control panel input of the controller. The external control panel may be configured to provide a user interface for controlling the operation of the controller.

[0007] In various embodiments, the controller may also be configured to close the electromechanical switching device in the minimum resistance path in response to receiving a deactivation control signal at the control panel input. The controller may also be configured to open the electromechanical switching device in the minimum resistance path in response to receiving an activation control signal at the control panel input.

[0008] In various embodiments, the solid-state circuit breaker may include at least one transient-voltage suppression (TVS) diode having a first end connected to the path input and a second end connected to the minimum resistance path between the electromechanical switching device and the path output. The solid-state circuit breaker may also include a bidirectional transistor switch having a first connection connected to the first end and the path input and a second connection connected to the second end and the path output.

[0009] In various embodiments, the at least one TVS diode includes parallel TVS diodes.

[0010] In various embodiments, the device may further include an enclosure for housing an electromechanical switching device, a path of least resistance, a bypass power switch device, and a controller. The enclosure may include a molded case circuit breaker or an air circuit breaker.

[0011] In various embodiments, the electromechanical switching device may include a vacuum circuit breaker. Additionally, the actuator may include a Thompson coil or a piezoelectric actuator connected to the vacuum circuit breaker.

[0012] In various embodiments, the bypass power switch device may include a cooling device.

[0013] In various embodiments, the detected fault current event may include a current associated with an arc flash event.

[0014] In various embodiments, the method may include controlling in a path of least resistance that includes a path input and a path output, and an electromechanical switching device between the path input and the path output. The method may include detecting, by a current sensor, a fault current event at the path output, and generating, by a controller, a trigger signal for actuating an actuator coupled to the electromechanical switching device. In response to the actuation of the actuator, the method may include opening the electromechanical switching device in the path of least resistance. In response to the open circuit state, the method may include interrupting the detected fault current event by a bypass power switch device including a solid state circuit breaker connected to the path input and the path output.

[0015] In various embodiments, the method may include controlling the operation of the controller by an external control panel connected to an input of a control panel of the controller.

[0016] In various embodiments, the control by the controller may include closing the electromechanical switching device from the path input to the path output in response to an operating state deactivation control signal received at the control panel input of the controller. Also, the control by the controller may include opening the electromechanical switching device in response to an operating state activation control signal received at the control panel input of the controller.

[0017] In various embodiments, blocking by the bypass power switch device may include passing a fault current event to at least one transient voltage suppression (TVS) diode of a solid-state circuit breaker connected to the path of minimum resistance between the electromechanical switching device and the path output to suppress transient voltage.

[0018] In various embodiments, the bypass power switch device may include a cooling device. The method may further include cooling the bypass power switch device by the cooling device.

[0019] In various embodiments, the bypass power switch device has a response time of 100 microseconds to 0.5 milliseconds until it blocks a detected fault current event.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4A

Figure 4B

Figure 4C

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Figure 6A

Figure 6B

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Figure 8

DETAILED DESCRIPTION OF THE INVENTION

[0021] Next, specific exemplary embodiments of the subject matter of the present invention will be described with reference to the accompanying drawings. However, the subject matter of the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter of the present invention to those skilled in the art. In the drawings, like numbers refer to like elements. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that it can be directly connected or coupled to the other element, or intervening elements may be present. For example, if there is an electrical conduction path between devices, the devices are "electrically connected" even if the path includes one or more intermediate components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the subject matter of the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "includes", "comprises", "including", and / or "comprising", when used herein, specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise specified, all terms (including technical and scientific terms) used in this specification shall have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present invention belongs. Furthermore, terms defined as in commonly used dictionaries shall be interpreted to have a meaning consistent with their meaning in the context of this specification and the related art, and it should be understood that they shall not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this specification.

[0024] FIG. 1 shows a block diagram of a system 10 using a hybrid arc flash mitigation device (AFMD) 100. The arc flash mitigation device 100 may include a housing 110 having a control panel 120. The control panel 120 may include a display panel 125 and an indicator 130. The indicator 130 may include an optical indicator including a light emitting diode (LED), another type of light, or some other type of indicator device. As a non-limiting example, by operating the arc flash mitigation device 100, the optical indicator 130 can be lit. The optical indicator 130 can enable an operator 20 to determine that the arc flash mitigation device 100 is in an active or “ON” state.

[0025] The display panel 125 may include a liquid crystal display (LCD) or an LED display. The display panel 125 may include a touch sensor type user interface for receiving user input. The control panel 120 may include control buttons 132 and 134 for respectively activating, deactivating and / or resetting the arc flash mitigation device 100. One or more components of the arc flash mitigation device 100 may include a solid state design. Details of the arc flash mitigation device 100 will be described in more detail in connection with FIGS. 2A-2B and FIG. 3.

[0026] The housing 110 houses the protection electronic circuit 105 of the arc flash mitigation device 100 shown as a dashed box in FIG. 1. The protection electronic circuit 105 may include a minimum resistance path 107. In FIG. 1, the minimum resistance path 107 includes the electromechanical switch SW1, which will be described in more detail in connection with FIGS. 2A-2B. In FIG. 1, the switch SW1 is "open" to form an open circuit state within the protection electronic circuit 105 along the minimum resistance path 107 when the arc flash mitigation device 100 is activated or in an active state.

[0027] The system 10 may include an electrical circuit 35 that sometimes requires maintenance by the operator 20. The electrical circuit 35 may be a sub-component of an electric machine or an element of a power distribution device. For example, the machine or device may include a switching device, a switchboard or a distribution board. The electrical circuit 35 may include a power circuit. The operator 20 may need to electrically connect an electrical circuit 25, such as an electrical tester or other device, to the electrical circuit 35 to perform tests or other maintenance operations. The electrical circuit 25 can generate a current representing a test signal. The electrical circuit 25 may expect a response or return signal from the electrical circuit 35. As will be described in more detail below, the arc flash mitigation device 100 is configured to protect the operator 20 when activated.

[0028] In various embodiments, system 10 may include an arc flash sensor system (AFSS) 30 configured to sense an arc flash event, such as a current representing a flash 15 or an arc flash, downstream of the arc flash mitigation device 100. The arc flash sensor system 30 may include a vision system having one or more optical sensors, such as a camera or other image capture device, capable of detecting the flash 15. However, for purposes of illustration, the arc flash sensor system 30 is separate from the arc flash mitigation device 100 and may be used to protect other equipment including the electrical circuit 35. The arc flash sensor system 30 may include a current sensor of the Arcflash Reduction Maintenance System (trademark) (ARMS) by Eaton (registered trademark) Corporation, or other suitable current sensors.

[0029] The housing 110 may include a form factor that is substantially similar to the form factor of a circuit breaker, as described later in connection with FIGS. 4A - 4C. The housing 110 may have a molded case. Packaging for the arc flash mitigation device 100 within such a housing can find particularly advantageous applications in providing arc fault mitigation in an electrical distribution panel or other equipment in a location suitable for the installation of a standard form factor breaker. However, it should be understood that the embodiments are not limited to such form factors.

[0030] Figure 2A shows a schematic diagram of the arc flash mitigation device 100 in a first operating mode according to some embodiments. The first mode corresponds to an operating state disabling mode or a normal mode of operation of the protection electronic circuit 105 in which the electromechanical switch SW1 is in the "closed" or closed circuit state. The switch SW1 is configured to have a lower on-resistance along the path of least resistance 107. Figure 2B shows a schematic diagram of the arc flash mitigation device 100 in a second operating mode according to some embodiments. The second mode corresponds to an operating state enabling mode or an arc flash mitigation maintenance mode of the protection electronic circuit 105 in which the electromechanical switch SW1 is in the "open" or open circuit state, so an open circuit is formed along the path of least resistance 107 and an alternative bi-directional bypass path to the vacuum interrupter 310 of the electromechanical switching device 210 is formed through the electronic bi-directional bypass power switch device 201. The electromechanical switching device 210 will be described in more detail in connection with Figure 3. The path of least resistance 107 when the switch SW1 is "closed" may be bi-directional.

[0031] Figures 2A and 2B show the same arc flash mitigation device 100 in different operating modes, and thus the same reference numbers are used in these figures.

[0032] The bidirectional bypass power switch device 201 may include a solid-state circuit breaker for interrupting the fault current of a fault event. The fault event can be one of the currents representing a high current event or an arc flash event. In particular, the bypass power switch device 201 is electrically connected to a controller 250. The controller 250 can transmit a trigger signal on a trigger conductor 255 to activate an ultra-high speed actuator 240 connected to an electromechanical switching device 210 in response to an arc flash event or a high current, so as to turn the switch SW1 "open". The ultra-high speed actuator 240 is ultra-high speed in that it can operate faster than the branch breaker and / or the main breaker of the system. For example, the switch SW1 can be forced to separate (open) to a distance of at least 1 millimeter (mm) within several hundred microseconds (μs) driven by the ultra-high speed actuator 240, as will be described in more detail in connection with FIG. 3, and may include contacts 313 and 323 (FIG. 3) of the electromechanical switching device 210.

[0033] The controller 250 can respond to a fault signal (i.e., high current) from a current sensor 270 in-line with the path 107 of minimum resistance between the switch SW1 and the output node N30. The current sensor 270 senses, for example, the current on the line L25 flowing into the node N30. As used herein, the term "node" may refer to a connection or a connection point.

[0034] In response to detecting a current level indicative of the occurrence of a fault event, such as a current associated with a high current event or an arc flash event, controller 250 generates a trigger signal on trigger conductor 255 to trigger ultra-high speed actuator 240. The arc flash event corresponds to the presence of arc flash light 15. Current sensor 270 detects the current along the path of least resistance 107 or upstream of arc flash mitigation system 100 and can be triggered by a current level exceeding a threshold corresponding to a high risk to maintenance personnel or equipment. Using the signals from current sensor 270 and the optical sensor, it may take about 2 ms to detect and confirm an arc flash event and transmit a trigger signal to electromechanical switching device 210 via arc flash sensor system 30 and controller 250. The fault current of the fault event can be interrupted by arc flash mitigation device 100 within about 2.5 ms.

[0035] A circuit breaker, sometimes referred to as a circuit breaker, includes electrical contacts that are connected to each other to conduct current from a power source to a load. The contacts may be separated by a force to interrupt the supply of current in response to a command or to protect the electrical system from electrical fault conditions such as current overloads, short circuits, and high or low voltage states. In some embodiments, electromechanical switching device 210 may be coupled to ultra-high speed actuator 240 that generates a force to separate contacts 313 and 323, as described in connection with FIG. 3. Ultra-high speed actuator 240 (FIG. 3) is configured to open switch SW1 and achieve a contact gap of at least 1 millimeter (mm) between contacts 313 and 323 within a response time of about 0.5 ms. Electromechanical switching device 210 will be described in more detail in connection with FIG. 3.

[0036] Assume that, as a reference point, the node N01 on the path 107 of minimum resistance is an input node configured to receive current, for example, from the external electrical circuit 25. The path 107 of minimum resistance may start from the node N01. Thus, the node N01 may also be referred to as an "input" or a "path input". The current at the node N01 can propagate along the line L02 to the electromechanical switching device 210 having the switch SW1. When the current propagates through the switch SW1, the current propagates, for example, along the line L04 to the node N20. The switch SW1 includes the output terminal T01. In the closed circuit state, the representative switching arm A1 of the switch SW1 is oriented such that the current flowing on the line L02 flows through the switch SW1 and also flows to the line L04 which is a part of the path 107 of minimum resistance. The switch arm A1 is for illustrative purposes only and does not limit the configuration or operation of the switch SW1 in any way. The path 107 of minimum resistance continues from the node N20 to the output at the node N30. The node N20 can provide a bypass path from the node N01 on the input side of the switch SW1 to the output side of the switch SW1 corresponding to the node N20 in the path of the output terminal T01. The output side of the switch SW1 corresponds to the output terminal T01 disposed in-line with the path 107 of minimum resistance.

[0037] The electronic bidirectional bypass power switch device 201 is shown within the dashed box disposed under the path 107 of minimum resistance and is configured to interrupt the fault current of a fault event, such as an arc flash event. When the switch SW1 is "open", for example, current can propagate from node N01, in the direction of arrow 109A, to the bidirectional bypass power switch device 201, along line L12 to node N03. Alternatively, the current on line L12 can propagate in the direction of arrow 109B to the switch 203 of the bidirectional bypass power switch device 201. The switch 203 may include a transistor such as a Metal Oxide Field Effect Transistor (MOSFET). The drain side of the switch 203 may be connected to node N03. The source side of the switch 203 may be connected to node N13, and the first side of the diode 207 is connected to node N13 or the source side of the switch 203. The drain side of the switch 203 may be connected to the second side of the diode 207 via node N05. In the figure, the drain side of the switch 203 is connected to the cathode of the diode 207, and the source side of the switch 203 is connected to the anode of the diode 207. Although the description in this specification uses MOSFET devices, other semiconductor transistor switch configurations may be used.

[0038] The source side of switch 203 may be electrically connected to the source side of switch 205 via node N16 in series with node N13. Switch 205 may include a transistor such as a metal oxide semiconductor field effect transistor (MOSFET). The drain side of switch 205 may be electrically connected to node N26 that propagates a signal in the direction of arrow 109C to node N20 on the path 107 of minimum resistance. MOSFET (transistor) switches 203 and 205 can form a bidirectional switch. The source side of switch 205 may be electrically connected to node N16, and the first side of diode 209 is electrically connected to node N16 or the source side of switch 205. The drain side of switch 205 may be electrically connected to the second side of diode 209 via node N18. In the figure, the drain side of switch 205 is electrically connected to the cathode of diode 209, and the source side of switch 205 is electrically connected to the anode of diode 209. Since the bypass power switch device 201 is bidirectional, current can flow in the reverse direction, such as from node N20 through arrows 109C, 109B, and 109A to node N01 when switch SW1 is "open".

[0039] The bidirectional bypass power switch device 201 may include a first transient voltage suppression (TVS) diode 213 with one side connected to node N07 and the second side connected to node N17. Node N17 is electrically connected to node N18. The bidirectional bypass power switch device 201 may similarly include a second transient voltage suppression (TVS) diode 215 with one side connected to node N07 and the second side connected to node N17. Diodes 213 and 215 may be in parallel.

[0040] The current sensor 270 is downstream of the switch SW1, proximate to a node N30, sometimes called an "output" or "path output". The current sensor 270 is configured to sense the amount of current on line L25. The current sensor 270 is in electronic communication with or electrically connected to the controller 250 and can send a sensed current signal representative of the measured current on line L25 over line 275. In other variations, the sensed current signal may generate a fault detection signal communicated to the controller 250 when the sensed signal is at a predetermined current threshold that could cause injury to the operator 20.

[0041] Figure 3 shows a block diagram of the controller 250 of the arc flash mitigation device 100 of FIGS. 2A - 2B interfaced with the components of the device. The controller 250 is in electrical communication with or connected to the control panel 120 to receive a first control signal on line 303. For example, the operator 20 may place the arc flash mitigation device 100 in a normal operating mode in response to a first control signal generated by the control panel 120. The normal operating mode corresponds to the arc flash reduction maintenance mode which is "OFF", and thus the controller 250 sets the switch SW1 to a closed circuit state. The controller 250 can respond to control buttons 132 and 134 to respectively enable and disable the operating state of the arc flash mitigation device 100. When the arc flash mitigation device 100 is enabled in the operating state, the arc flash reduction maintenance mode becomes "ON" such that the switch SW1 is set to an open circuit state.

[0042] The control panel 120 may generate a first control signal on line 303 to cause the controller 250 to control the operating mode of the device 100. Line 303 may be connected to a control panel input or port of the controller 250. The signal received at the control panel input or port of the controller 250 controls the operation of the controller (arm process or disarm process). Thus, the control panel can generate a deactivation control signal for deactivating the device 100 and an activation control signal for enabling the arc flash mitigation device 100. The controller 250 may be powered even though the device 100 is deactivated, as the deactivation mode generally changes the state of the switch SW1.

[0043] Specifically, in the normal operating mode, the controller 250 can transition the switch SW1 to a closed circuit state as shown in FIG. 2A, represented as switch arm A1 connected to output terminal T01. Thus, the path 107 of minimum resistance extends from node N01 to node N30 without an open circuit condition. The controller 250 can, in some embodiments, transmit a control signal on control line 309 to the control bypass power switch device 201 to switch it to "OFF". Further, the controller 250 can control the active cooling device 345 if it is present in the bypass power switch device 201. The control panel 120 may generate a second control signal on line 303 to cause the controller 250 to control the operating mode of the device 100, causing the switch SW1 to be "open" and the device 100 to be activated, as best seen in FIG. 2B. In other words, the switch SW1 has an open circuit state represented as the switch arm A1 being lifted in a direction away from the terminal T01.

[0044] The controller 250 may include at least one processor 355. Details of the hardware of the controller 250 will be described in more detail in connection with FIG. 8. The controller 250 may also include hardware, software, and / or firmware for performing the operating state activation process 360 and the operating state deactivation process 365. The operating state deactivation process 365 configures the arc flash mitigation device 100 to operate according to the normal operation mode as shown and described above with respect to FIG. 2A. For example, the operating state deactivation process 365 may cause the controller 250 to control the switch SW1 to be "closed" or to transition to a closed circuit state in response to a control signal on line 303.

[0045] The operating state deactivation process can switch the arc flash reduction maintenance mode to "OFF". Additionally, the switch SW1 may be set to be in the "closed" position, and the bypass power switch device 201 may be either in the "OFF" state or the "ON" state. In various embodiments, the bypass power switch device 201 may remain in the "ON" state when the arc flash reduction maintenance mode is "OFF".

[0046] The activation process 360 can cause the controller 250 to control the switch SW1 to "open" in response to the second control signal on line 303, or to transition to an open circuit state with respect to the minimum resistance path 107. The switch SW1 is represented as a switch arm A1 lifted away from the output terminal T01 when "open" with respect to the minimum resistance path 107. The switch SW1 has a low on-resistance. The activation process 360 may also set or reset the ultra-high speed actuator 240 in the controller 250 and turn on the arc flash reduction maintenance mode. In some embodiments, the activation process 360 may engage the switch SW1, which may be part of the vacuum circuit breaker 310. In some embodiments, it separates the contacts 313 and 323 from each other or opens the switch SW1. The vacuum circuit breaker 310 can include a vacuum chamber 315, such as within a ceramic bottle, and an arc is drawn by separating the contacts 313 and 323 while current is propagating. When the actuator 240 is reset, the link mechanism 330 and the actuator 240 are configured to keep the contacts 313 and 323 in an electrically open state. The device 100 can also be reused under the control of the controller 250 after an arc flash event is detected and cleared.

[0047] When the electromechanical switching device 210 is "open", the fault current of the fault event can be diverted to the bypass power switch device 201 within the current path of the downstream electrical circuit 35. The diversion of the current can be achieved by using a high-frequency electronic oscillation circuit (not shown) or by the arc voltage across the contact gap between contacts 313 and 323 when contacts 313 and 323 separate while the current is flowing. The fault event or fault current is completely diverted to the power electronic circuit current path through the bypass power switch device 201 within several tens of microseconds. Contacts 313 and 323 are forced to reach the minimum contact gap to withstand the transient recovery voltage (TRV). Therefore, the fault current is interrupted by the bypass power switch device 201, stopping or eliminating the arc flash event or fault current event. All of these (e.g., opening the switch SW1 by the bypass power switch device 201 and interrupting the fault current of the fault event) are configured to occur within about 0.5 ms. That is, the response time is about 0.5 ms or less.

[0048] The controller 250 may also include a trigger generator 370 and a comparator 375 that may include hardware, software, and / or firmware. While the arc flash mitigation device 100 is in the active operating state, the comparator 375 can compare the signals received from the sensor 270. The signal on line 275 may be connected to the sensor input or port of the controller 250. Depending on the result of the comparison, the trigger generator 370 may generate a trigger signal that propagates along the trigger conductor 255 to the electromechanical switching device 210. Specifically, the trigger signal can be communicated to the ultra-high-speed actuator 240 to activate the actuator and force the electrical contacts 313 and 323 to open by the link mechanism 330 by opening the vacuum circuit breaker 310. In FIG. 3, contacts 313 and 323 are shown as "open".

[0049] In various embodiments, for example, when switch SW1 is "closed" and bypass power switch device 201 is in the "ON" state, although the arc flash reduction maintenance mode is deactivated, the controller 250 is still operable to trigger actuator 240 to open switch SW1 in response to a fault event detected by fault detector (comparator) 375. Thus, when switch SW1 is opened, the current of the fault event is diverted to bypass power switch device 201, so the fault event can be interrupted by bypass power switch device 201.

[0050] In some scenarios, the signal received by controller 250 from sensor 270 may be a fault signal representing an arc flash event. Sensor 270 may transmit a measurement signal representing an arc flash event or a high current event. The high current event is associated with a high current that may be smaller than the current associated with the arc flash event. The fault signal and the measurement signal may be configured to represent an overcurrent or overvoltage condition resulting from one of the arc flash event and / or the high current event detected by sensor 270. In some embodiments, comparator 375 of controller 250 can detect the occurrence of an arc flash event by comparing the measurement signal with a threshold. In any scenario, comparator 375 may provide a control signal to trigger generator 370 to generate a trigger signal.

[0051] In some embodiments, the ultra-high speed actuator 240 may include a Thompson coil actuator connected to the link mechanism 330. Actuator 240 may be a piezoelectric actuator or other ultra-high speed actuator. During operation, ultra-high speed actuator 240 may receive a control (trigger) signal from controller 250 to operate actuator 240. When actuated, actuator 240 generates a high-speed acting force applied to link mechanism 330, and then separates contacts 313 and 323 (i.e., switch SW1) within vacuum circuit breaker 310.

[0052] The bypass power switch device 201 may have a cooling device 345 configured to perform passive or active cooling. In embodiments where the cooling device 345 performs active cooling, a fan may be used for cooling. For passive cooling, the cooling device 345 may include a heat sink. When a fan is used and the arc flash mitigation device 100 is in an active operating state, or when the bypass power switch device 201 is set to "ON", the active cooling device is likewise set to "ON". The controller 250 may provide additional control signals to the electromechanical switching device 210 and the bypass power switch device 201.

[0053] When implemented in software, the functions of the controller 250 may be stored as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. The computer-readable medium corresponds to a tangible medium such as a data storage medium (e.g., RAM, ROM, EEPROM, flash memory, or any other medium that can be used to store the desired program code in the form of instructions or data structures and is accessible by a computer).

[0054] The instructions may be executed by one or more processors 355 such as, for example, one or more digital signal processors (DSPs), general-purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor" as used herein may refer to any of the foregoing structures or any other physical structure suitable for implementation of the techniques described. Additionally, the techniques may be implemented entirely in one or more circuits or logic elements.

[0055] Specifically, the path of least resistance 107 has a first resistance. The switch SW1 has a low on-resistance and the switch SW1 has a closed position with respect to the output terminal T01. The path of least resistance 107 has an input (i.e., node N01) and an output (i.e., node N30), and the switch SW1 is between the input (i.e., node N01) and the output (i.e., node N30). The electromechanical switching device 210 has an open-circuit state when the switch SW1 is in the open position. The bidirectional bypass power switch device 201 is electrically connected to the path of least resistance 107 at a first position associated with the input (i.e., node N01) and at a second position between the switch SW1 and the output (i.e., node N30).

[0056] When the bidirectional bypass power switch device 201 is "ON" and the switch SW1 is "open", the power switch device 201 is configured to propagate the current generated at the node N01 or the input to the node N30 or the output. The bidirectional bypass power switch device 201 is also configured to conduct the current generated from the node N30 or the output to the node N01 or the input. In a scenario where a fault event occurs when the arc flash reduction maintenance mode is "ON", the bidirectional bypass power switch device 201 protects maintenance personnel by interrupting the fault current of the fault event. In particular, the parallel transient voltage suppression (TVS) diodes 213 and 215 may be configured to limit the transient overvoltage level. Alternatively, any current from the line L25 to the node N20 may be propagated through the bidirectional bypass power switch device 201.

[0057] When the bidirectional bypass power switch device 201 is "ON" and the switch SW1 is "closed", the controller 250 generates a trigger signal to the actuator 240 in response to receiving a signal representing a fault event, and is configured to cut off the fault current of an arc flash event or a high current fault event by opening the switch SW1. Therefore, the fault current of the fault event bypasses part of the path of the minimum resistance and is cut off by flowing the fault current at node N20 to the bidirectional bypass power switch device 201. Here too, any current from line L25 to node N20 can be propagated through the bidirectional bypass power switch device 201 and cut off to stop the fault event.

[0058] For example, when the arc flash reduction maintenance mode in which the switch SW1 is already "open" is turned on, when the fault current reaches 2X or 2.5X of the rated current, the bidirectional power electronic switch 201 cuts off the fault current within 100 μs. The arc flash energy is associated with the arc flash event and can be described as the product of the arc voltage and the fault current.

[0059] The solid-state design can be packaged in the same form factor as a molded case circuit breaker (MCCB) or an air circuit breaker (ACB) so as to be incorporated into an existing switchgear, switchboard, or distribution board, as described in connection with FIGS. 4A-4C, FIGS. 6A-6B, and FIG. 7.

[0060] FIG. 4A illustrates a front perspective view of an arc flash mitigation device 400 with a housing having an MCCB form factor. The arc flash mitigation device 400 is the same as the arc flash mitigation device 100 except that details of the form factor of the housing 410 are described. The housing 410 may include an upper connector 405 and a lower connector 407 for attaching cables or busbars for conducting current from the line side to load side electrical equipment, e.g., or other electrical machinery. The front panel or cover 402 of the housing 410 may have a display panel 125, indicators 130, and control buttons 132 and 134 for easy access by an operator 20 (FIG. 1). However, it should be understood that the control panel 120 may include other control buttons not described. FIG. 4B shows an end perspective view and a side perspective view of the arc flash mitigation device 400 of FIG. 4A with a portion of the housing removed. FIG. 4C shows a side view of the arc flash mitigation device 400 of FIG. 4A with a portion of the housing removed. The back panel 412 may be fitted and attached to the inner panel of the opening / closing device 500 (FIG. 5). The housing 410 may dispose a bidirectional bypass power switch device 201 of the protection electronic circuit 105 adjacent to the back panel 412 of the housing 410. The electromechanical switching device 210 may include a vacuum interrupter 310. The ultra-high speed actuator 240 is mechanically coupled to the vacuum interrupter 310 via a link mechanism 330. The electromechanical switching device 210 may have one end coupled to the upper end of the housing 410. The arc flash mitigation device 400 may include a plurality of electromechanical switching devices 210 arranged in parallel for different poles. Each electromechanical switching device 210 is connected to its own actuator 240 via a link mechanism 330.

[0061] FIG. 5 shows an exemplary electrical switching device 500 in which an arc reduction device can be installed, according to some embodiments. The switching device 500 can be configured to receive a standard circuit breaker. The switching device 500 includes a housing 510 for accommodating a busbar backplane assembly 520 attached to the housing 510. The busbar backplane assembly 520 can be configured to receive a circuit breaker, and the circuit breaker can be electrically connected to a bus of the busbar backplane assembly 520 and an arc flash reduction device 100 housed in a housing having a compatible form factor, and includes a control panel 120.

[0062] The housing 510 may include a notch sized to expose the front of a circuit breaker 550 installed within the busbar backplane assembly 520. As shown, according to some embodiments, an arc reduction device 100 having substantially the same form factor as the circuit breaker 550 may be installed in the switching device 500 in place of the circuit breaker. The switching device 500 is shown with cutouts of various sizes for accommodating other electronic devices.

[0063] FIG. 6A shows a front perspective view of an arc flash mitigation device 600 having a housing with an air circuit breaker (ACB) form factor. The arc flash mitigation device 600 is the same as the arc flash mitigation device 100, except that details of the form factor of the housing 610 are described. The front panel or cover 602 of the housing 610 may carry a display panel 125, indicators 130, and control buttons 132 and 134 of the control panel 120 so that an operator 20 (FIG. 1) can easily access them. The housing 610 may include a rear housing section 612 configured to fit and attach to the front panel or cover 602. The rear housing section 612 may carry, for example, on its rear surface, an upper rear connector 605 and a lower rear connector 607 for attaching the housing 610 to a bus bar connector for passing current from its line side to its load side to a downstream electrical device (FIG. 5), or other electrical machinery. FIG. 6B shows a front perspective view of the arc flash mitigation device 600 of FIG. 6A with a portion of the housing removed. The housing 610 can have a bi-directional bypass power switch device 201 of the protection electronic circuit 105 disposed adjacent to the front panel 602 of the housing 610. The electromechanical switching device 210 may include a vacuum circuit breaker 310 mechanically connected to a lower-mounted ultra-high speed actuator 240 via a link mechanism 330.

[0064] FIG. 7 illustrates a front perspective view of an arc flash mitigation device 700 with a housing having a cassette form factor. The arc flash mitigation device 700 is the same as the arc flash mitigation device 100, except that details of the form factor of the housing 710 are described. The front panel or cover 702 of the housing 710 may have a mounted display panel 125, indicators 130, and control buttons 132 and 134 of the control panel 120 for easy access by an operator 20 (FIG. 1). The housing 710 may include a rear housing section 712 configured to fit and attach to the front panel or cover 702.

[0065] FIG. 8 shows an example of internal hardware that may be included in any of the electronic components of a system, such as a controller, sensor, and computing device. Electrical bus 800 functions as an information highway interconnecting the other illustrated components of the hardware. Processor 805 is the central processing device of the system configured to perform the calculations and logical operations necessary to execute programming instructions. As used in this document and the claims, the terms "processor" and "processing device" may refer to a single processor, such as a central processing unit (CPU), a remote server, or a combination thereof, or any number of processors within a set of processors that collectively perform a set of operations. Read only memory (ROM), random access memory (RAM), flash memory, hard drives, and other devices capable of storing electronic data constitute examples of memory device 825. Memory device 825 may include a single device or a collection of devices in which data and / or instructions are stored. Various embodiments of the present invention may include a computer-readable medium including programming instructions configured to perform the functions described in the context of the previous figures on one or more processors, printing devices, and / or scanning devices.

[0066] Any display interface 830 can enable information from bus 800 to be displayed on a display device 835 (i.e., a control panel) in visual, graphic, or alphanumeric form. An audio interface and audio output (such as speakers) can also be provided. Communication with external devices can be performed using various communication devices 840 such as wireless antennas, radio frequency identification (RFID) tags, and / or short-range or near-field communication transceivers, each of which can optionally be communicatively connected to other components of the device via one or more communication systems. The communication device(s) 840 may be configured to be communicatively connected to a communication network such as the Internet, a local area network, or a cellular phone data network.

[0067] The hardware may also include a user interface sensor 845 that enables reception of data from input devices 850 such as a keyboard or keypad, a joystick, a touch screen, a touch pad, a remote control, control buttons, a pointing device, and / or a microphone. The above features and functions, as well as alternatives, may be combined in many other different systems or applications. The various components can be implemented in hardware or software or embedded software. Various currently unforeseen or unanticipated alternatives, modifications, variations, or improvements may be made by those skilled in the art, each of which is also intended to be encompassed by the disclosed embodiments.

[0068] The terms related to the above disclosure include the following.

[0069] The terms "memory" and "computer-readable medium" each refer to a non-transitory device in which computer-readable data, programming instructions, or both are stored. Unless otherwise specified, the terms "memory" and "computer-readable medium" are intended to include embodiments of a single device, embodiments in which multiple memory devices store a set of data or instructions together or collectively, and individual sectors within such devices.

[0070] The terms "processor" and "processing device" each refer to a hardware component of an electronic device configured to execute programming instructions. Unless otherwise specified, the term "memory" or "computer-readable medium" is intended to include both embodiments of a single processing device and embodiments in which multiple processing devices perform a process together or collectively.

[0071] In this document, the term "communication line" means a wired or wireless path by which a first device transmits communication signals to and / or receives communication signals from one or more other devices. A device is "communicatively connected" if it can transmit and / or receive data via a communication link. "Electronic communication" refers to the transmission of data via one or more signals between two or more electronic devices, either directly or indirectly via one or more intermediate devices, whether through a wired network or a wireless network.

[0072] In this document, when such terms as "first" and "second" are used to modify a noun, such use is intended merely to distinguish one item from another and does not require a sequential order unless specifically described.

[0073] In addition, terms of relative position such as "vertical" and "horizontal", or "front" and "back", when used, are intended to be relative to each other and need not be absolute, and refer only to one possible position of the device associated with those terms depending on the orientation of the device. Further, the terms "front" and "back" are not necessarily limited to the region facing forward or the region facing backward, but also include, respectively, a side region closer to the front than the back, or vice versa.

Claims

1. An electromechanical switching device having an open-circuit state and a closed-circuit state, A path input, a path output, and a minimum-resistance path having the electromechanical switching device between the path input and the path output, A bypass power switch device comprising a solid-state circuit breaker and configured to conduct current between the path input and the path output only in response to the open-circuit state of the electromechanical switching device, wherein the solid-state circuit breaker includes a first MOSFET and a second MOSFET, A current sensor connected to the path output and configured to detect a fault current event, An actuator coupled to the electromechanical switching device, A controller configured to generate a trigger signal for actuating the actuator to place the electromechanical switching device in the open-circuit state and interrupting the fault current event by the bypass power switch device based on the detected fault current event, The bypass power switch device is connected to the minimum-resistance path at a first node and a second node, the first node is at the path input, and the second node is disposed between the electromechanical switching device and the path output, The drain terminal of the first MOSFET is electrically connected to the first node, The drain terminal of the second MOSFET is electrically connected to the second node, The source terminal of the first MOSFET is electrically connected to the source terminal of the second MOSFET at a common node, and the common node is disposed between the first node and the second node, The bypass power switch device is configured to allow current to flow from the path input through the bypass power switch device to bypass a portion of the minimum-resistance path so that the bypass power switch device can complete interruption of the fault current event, The bypass power switch device is configured to allow the current flowing from the path output to the second node to bypass a part of the minimum resistance path in order to flow current through the bypass power switch device so that the bypass power switch device can complete the interruption of the fault current event. The solid-state circuit breaker has a first end connected to the path input and a second end connected to the minimum resistance path between the electromechanical switching device and the path output, and includes two transient voltage suppression (TVS) diodes connected in parallel with each other. **Claim 2** The current sensor has an output connected to the sensor input of the controller. The current sensor is configured to communicate a signal representing the detection of the fault current event to the sensor input of the controller. The device according to claim 1. **Claim 3** The device further comprises an external control panel connected to the control panel input of the controller. The external control panel is configured to provide a user interface for controlling the operation of the controller. The device according to claim 1. **Claim 4** The controller is also configured to close the electromechanical switching device in the minimum resistance path in response to receiving a deactivation control signal at the control panel input. The device according to claim 3, further configured to open the electromechanical switching device in the minimum resistance path in response to receiving an activation control signal at the control panel input. **Claim 5** The device further comprises a housing for accommodating the electromechanical switching device, the minimum resistance path, the bypass power switch device, and the controller. The housing comprises a molded case circuit breaker or an air circuit breaker. The device according to claim 1. **Claim 6** The electromechanical switching device comprises a vacuum circuit breaker. The actuator includes a Thompson coil or a piezoelectric actuator connected to the vacuum circuit breaker. The device according to claim 1. **Claim 7** The bypass power switch device also comprises a cooling device. The device according to claim 1. **Claim 8** The device according to claim 7, wherein the detected fault current event includes a current related to an arc flash event.

9. Controlling an electromechanical switching device between the path input and the path output in a path of minimum resistance including the path input and the path output; Detecting a fault current event at the path output by a current sensor; Generating, by a controller, a trigger signal for actuating an actuator coupled to the electromechanical switching device; Opening the electromechanical switching device in the path of minimum resistance in response to the actuation of the actuator; Interrupting the detected fault current event by a bypass power switch device including a solid-state circuit breaker connected to the path input and the path output, wherein the bypass power switch device is configured to conduct current between the path input and the path output only in response to the open-circuit state, and the solid-state circuit breaker includes a first MOSFET and a second MOSFET; comprising The bypass power switch device is connected to the path of minimum resistance at a first node and a second node, the first node is at the path input, and the second node is disposed between the electromechanical switching device and the path output; A drain terminal of the first MOSFET is electrically connected to the first node; A drain terminal of the second MOSFET is electrically connected to the second node; A source terminal of the first MOSFET is electrically connected to a source terminal of the second MOSFET at a common node, and the common node is disposed between the first node and the second node; The bypass power switch device is configured to allow current to flow from the path input through the bypass power switch device to bypass a part of the path of minimum resistance so that the bypass power switch device can complete interruption of the fault current event. The bypass power switch device is configured to allow the current flowing from the path output to the second node to bypass a part of the path of the minimum resistance in order to flow a current through the bypass power switch device so that the bypass power switch device can complete the interruption of the fault current event. The interruption is achieved by the bypass power switch device. A method including passing the fault current event to two transient voltage suppression (TVS) diodes connected in parallel to each other of the solid-state circuit breaker connected to the path of the minimum resistance between the electromechanical switching device and the path output to suppress transient voltage. **Claim 10** The method according to claim 9, wherein the fault current event includes an arc flash event occurring downstream of the path output. **Claim 11** The method according to claim 9, further comprising controlling the operation of the controller by an external control panel connected to the control panel input of the controller. **Claim 12** The controlling includes: Closing the electromechanical switching device from the path input to the path output in response to an operation state disabling control signal received at the control panel input of the controller; and Opening the electromechanical switching device in response to an operation state enabling control signal received at the control panel input of the controller. The method according to claim 11. **Claim 13** The electromechanical switching device includes a vacuum circuit breaker having a vacuum chamber and an electromechanical switching device within the vacuum chamber. The actuator includes a Thompson coil or a piezoelectric actuator connected to the vacuum circuit breaker. The method according to claim 9. **Claim 14** The bypass power switch device includes a cooling device. The method further includes cooling the bypass power switch device by the cooling device. The method according to claim 13. **Claim 15** The method according to claim 9, wherein the detected fault current event is an arc flash event. **Claim 16** The method according to claim 15, wherein the bypass power switch device has a response time of 100 microseconds to 0.5 milliseconds until the detected fault current event is interrupted.

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