Charge pump circuit

Abstract

To provide a charge pump circuit capable of adjusting an output voltage easily and rapidly.SOLUTION: A boosting circuit 11 included in a charge pump circuit 1 of an embodiment includes a first capacitor C11 which accepts a first drive signal OSC1 or its inverted signal OSC_inv as a first input signal I1 with an end C1a, a switching element Q11 for switching the conduction state between a first node N11 to which the other end C1b of the first capacitor C11 is connected and a second node N12 of an output end Vout side according to the voltage of a third node N13, and a second capacitor C12 for transmitting level change of a second input signal I2 to the third node N13, and the second input signal I2 can be switched between a second drive signal OSC2 for causing the switching element Q11 to the conduction state during a period in which the first drive signal OSC1 is at low level and a third drive signal OSC3 for causing the switching element Q11 to the conduction state during a period in which the first drive signal OSC1 is at high level.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a charge pump circuit.

Background Art

[0002] Conventionally, charge pumps have been used as power supplies for various electrical devices. A charge pump superimposes a voltage charged in a capacitor on an input voltage by moving charges, and generates a desired output voltage boosted from the input voltage by repeating this superposition in multiple stages. As such a charge pump, Patent Document 1 discloses a charge pump circuit composed of a unit charge pump shown in FIG. 9.

[0003] The unit charge pump in FIG. 9 includes a capacitor C101 connected to node N101, a capacitor C102 connected to node N102, a transistor T102 diode-connected between node N101 and node N102, and a transistor T101 having its drain and gate connected to node N101 and node N102 respectively and outputting an output voltage Vo from its source. A transistor T103 is connected between node N101 and the power supply voltage Vcc in a diode-connected form. A signal S101 that oscillates between GND and Vcc at a constant period is input to the capacitor C101. A signal S102 having the same period and level as the signal S101 but a smaller pulse width is input to the capacitor C102.

[0004] When the power supply voltage Vcc is applied, a voltage of Vcc - (threshold voltage of transistor T103) is set at node N101. The voltage of node N101 is transmitted to node N102 via transistor T102, and a voltage of Vcc - (2 × threshold voltage) is set at node N102. Note that the threshold voltages of transistor T102 and transistor T103 are the same and are simply denoted as "threshold voltage". When signal S101 transitions from the GND level to Vcc in this state, the voltages of node N101 and node N102 transition to 2Vcc - (threshold voltage) and 2Vcc - (2 × threshold voltage), respectively. Then, when signal S102 rises from the GND level to Vcc, the voltage of node N102 becomes 3Vcc - (2 × threshold voltage), and due to the potential difference between node N102 and node N101, transistor T101 turns on, and the voltage of node N101, which is boosted by Vcc - (threshold voltage) compared to the power supply voltage Vcc, i.e., 2Vcc - (threshold voltage), is transmitted to the source of transistor T101 and output as output voltage Vo. Unit charge pumps are appropriately connected in series according to the required output voltage, and boosting is performed in multiple stages.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a charge pump circuit, the input voltage, input signal, and / or the number of boosting stages may be adjusted so as to obtain an output voltage required by the device in which the charge pump circuit is used. For example, the output of a charge pump circuit used in a MEMS microphone is applied between parallel plates within the MEMS microphone, and the voltage value affects the sensitivity of the MEMS microphone. Other factors that affect the sensitivity of the MEMS microphone may vary from individual MEMS microphones due to manufacturing variations of the MEMS microphone. Therefore, in a charge pump circuit used in a MEMS microphone, adjustment of the output voltage may be required in combination with the MEMS microphone so as to obtain a desired sensitivity.

[0007] In such adjustment of the output voltage, adjustment in the direction of increasing the output voltage may be necessary, or adjustment in the direction of decreasing the output voltage may be necessary. In the charge pump circuit shown in FIG. 9, for example, it is relatively easy to increase the output voltage Vo by increasing the high-level voltage of the signal S101 or increasing the power supply voltage Vcc. However, the charge pump circuit shown in FIG. 9 does not have a mechanism for discharging the charge from the capacitor C101. Therefore, in the adjustment for decreasing the output voltage, it may take time because it is necessary to wait for the capacitor C101 to be discharged by the leakage current of each transistor or the like. If a discharge path is simply newly provided to shorten that time, the efficiency of the essential function of boosting may decrease.

[0008] In order to prevent such a decrease in efficiency, it is possible to provide a discharge path including a switching element such as a transistor so that the discharge path can be connected as needed. However, for example, when the voltage after boosting in multiple stages reaches a high voltage, the transistor connected to discharge the capacitor holding a voltage close to the output voltage requires high breakdown voltage characteristics.

[0009] In view of such problems, an object of the present invention is to provide a charge pump circuit capable of easily and promptly adjusting an output voltage without requiring a high breakdown voltage element regardless of the adjustment direction.

Means for Solving the Problem

[0010] One embodiment of the charge pump circuit of the present invention is a charge pump circuit including one or more boost circuits connected in series between an input terminal and an output terminal, wherein each of the one or more boost circuits includes: a first capacitor that receives, at one end, a first drive signal that periodically changes in level or an inverted signal obtained by inverting the first drive signal as a first input signal; a first node to which the other end of the first capacitor is connected; a switching element that switches between conduction and non-conduction between the first node and a second node on the output terminal side of the first node according to the potential of a third node connected via a rectifying element; and a second capacitor that receives a second input signal and transmits a change in the level of the second input signal to the third node. The second input signal is configured to be switchable between a second drive signal having a level that causes the switching element to be in a conductive state during a period when the first drive signal is at a low level and a third drive signal having a level that causes the switching element to be in a conductive state during a period when the first drive signal is at a high level.

Advantages of the Invention

[0011] According to the charge pump circuit of the present invention, regardless of the adjustment direction, the output voltage can be easily and quickly adjusted over a wide range without requiring high-breakdown-voltage elements.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0013] Embodiments of the charge pump circuit of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiments described below.

[0014] <Configuration of the Charge Pump Circuit> FIG. 1 shows a charge pump circuit 1 which is an example of the charge pump circuit according to an embodiment. Further, FIG. 2 shows an example of a timing chart for the first to third drive signals OSC1, OSC2, OSC3 input to the charge pump circuit 1, and the inverted signal OSC_inv of the first drive signal OSC1.

[0015] As shown in FIG. 1, the charge pump circuit 1 includes a plurality of boost circuits (boost circuits 11 to 13) connected in series between the input terminal Vin and the output terminal Vout. An input circuit 10 is connected between the input terminal Vin and the boost circuit 11, which is the boost circuit closest to the input terminal Vin among the three boost circuits 11 to 13. In the example of FIG. 1, the input terminal Vin is connected to GND. A capacitor C3 (third capacitor) is connected between the output terminal Vout and GND. The charge pump circuit 1 in FIG. 1 further includes an inverter 2. A first drive signal OSC1 is input to the input of the inverter 2. The first drive signal OSC1 is a signal that periodically changes its level between a high level and a low level, as illustrated in FIG. 2. The inverter 2 generates an inverted signal OSC_inv, which is a signal obtained by inverting the high level and the low level of the first drive signal OSC1.

[0016] The boost circuit 11 includes a capacitor C11 (first capacitor of the boost circuit 11) and a capacitor C12 (second capacitor of the boost circuit 11), a switching element Q11, and a rectifying element Q12. The capacitor C11 has one end C1a and the opposite other end C1b, and the other end C1b is connected to a node N11 (first node of the boost circuit 11). A first input signal I1 is applied to one end C1a of the capacitor C11. The capacitor C11 receives the first drive signal OSC1 or its inverted signal OSC_inv as the first input signal I1 at one end C1a and is charged or discharged according to the level of the first input signal I1. In the example of FIG. 1, the first drive signal OSC1 or its inverted signal OSC_inv is input to the capacitor C11 via a switching element S5.

[0017] The switching element Q11 is connected between the node N11 and the node N12 (the second node of the boost circuit 11). In the example of FIG. 1, the switching element Q11 is an N-type metal oxide semiconductor field effect transistor (MOSFET). The node N12 is located on the output terminal Vout side with respect to the node N11 regarding the switching element Q11. The node N11 is located on the input terminal Vin side with respect to the node N12 regarding the switching element Q11. One of the controlled terminals (drain and source) of the switching element Q11 is connected to the node N11 and the other is connected to the node N12. The control terminal (gate) of the switching element Q11 is connected to the node N13 (the third node of the boost circuit 11). The switching element Q11 switches between conduction and non-conduction between the node N11 and the node N12 according to the potential of the node N13. Note that the switching element Q11 does not have to be composed of a MOSFET as in the example of FIG. 1. The switching element Q11 can be any element that can switch between conduction and non-conduction of the two controlled terminals according to the voltage of the control terminal.

[0018] The node N13 is connected to the node N11 via the rectifying element Q12. That is, the rectifying element Q12 is connected between the node N11 and the node N13. The rectifying element Q12 in FIG. 1 is composed of a MOSFET (for example, an N-type MOSFET) with its drain and gate connected (diode connection). The rectifying element Q12 allows current to flow from the node N11 to the node N13, while blocking the energization from the node N13 to the node N11. When the potential of the node N11 is higher than the potential of the node N13, current flows from the node N11 to the node N13. Therefore, with a voltage drop corresponding to the forward voltage of the rectifying element Q12 (the threshold voltage of the MOSFET constituting the rectifying element Q12 in the case of FIG. 1), the potential of the node N11 is transmitted to the node N13. On the other hand, when the potential of the node N13 is higher than the potential of the node N11, the potential of the node N13 is not transmitted to the node N11.

[0019] Capacitor C12 has one end C2a and the opposite other end C2b, and one end C2a is connected to node N13. A second input signal I2 is applied to the other end C2b. Capacitor C12 receives the second input signal I2 and transmits the change in the level of the second input signal I2 to node N13.

[0020] The boost circuit 11 in the example of FIG. 1 further includes a rectifying element Q13. The rectifying element Q13 is connected between node N13 and node N12. The rectifying element Q13 is connected so as to be in the forward direction from node N13 to node N12. The rectifying element Q13 in FIG. 1 is composed of a diode-connected MOSFET (for example, an N-type MOSFET). The rectifying element Q13 allows current to flow from node N13 to node N12 and blocks the flow of current from node N12 to node N13. Therefore, when the potential of node N13 is higher than the potential of node N12, current flows from node N13 to node N12. That is, the gate capacitance of the MOSFET constituting the switching element Q11 and the capacitor C12 are discharged. Note that the rectifying elements Q12 and Q13 do not have to be composed of transistors as in the example of FIG. 1, and may be composed of any diodes.

[0021] The boost circuits 12 and 13 are configured with the same circuit as the boost circuit 11. That is, the boost circuit 12 includes capacitors C21 and C22 (the first and second capacitors of the boost circuit 12, respectively), a switching element Q21, rectifying elements Q22 and Q23, and nodes N21, N22, and N23 (the first, second, and third nodes of the boost circuit 12, respectively), which respectively correspond to the capacitors C11 and C12, the switching element Q11, the rectifying elements Q12 and Q13, and the nodes N11, N12, and N13 of the boost circuit 11. Similarly, the boost circuit 13 includes capacitors C31 and C32 (the first and second capacitors of the boost circuit 13, respectively), a switching element Q31, rectifying elements Q32 and Q33, and nodes N31, N32, and N33 (the first, second, and third nodes of the boost circuit 13, respectively), which respectively correspond to the capacitors C11 and C12, the switching element Q11, the rectifying elements Q12 and Q13, and the nodes N11, N12, and N13 of the boost circuit 11. In each of the boost circuits 12 and 13, these circuit elements and nodes are connected to each other in the same manner as the respective circuit elements and nodes in the boost circuit 11. In the example of FIG. 1, the node N32 of the boost circuit 13 is connected to the output terminal Vout of the charge pump circuit 1.

[0022] The input circuit 10 is configured as the same circuit as the boost circuit 11, except that it does not include a capacitor corresponding to the capacitor C11 of the boost circuit 11. That is, the input circuit 10 includes a capacitor C2 (the second capacitor of the input circuit 10), switching elements Q1, rectifying elements Q2 and Q3, and nodes N1, N2, and N3 (the first, second, and third nodes of the input circuit 10), which respectively correspond to the capacitor C12, switching element Q11, rectifying elements Q12 and Q13, and nodes N11, N12, and N13 of the boost circuit 11. In the input circuit 10, these circuit elements and nodes are connected to each other in the same manner as each circuit element and each node in the boost circuit 11. And the node N1 of the input circuit 10 is connected to the input terminal Vin of the charge pump circuit 1. The input circuit 10 transmits the initial potential set at the input terminal Vin (GND potential in the example of FIG. 1) to the node N11 of the boost circuit 11 by turning on the switching element Q1. Also, the input circuit 10 provides a discharge path from the boost circuit 11 to the input terminal Vin during the discharge operation described later.

[0023] In the charge pump circuit 1 of FIG. 1, the node N2 of the input circuit 10 is connected to the node N11 of the boost circuit 11, the node N12 of the boost circuit 11 is connected to the node N21 of the boost circuit 12, and further, the node N22 of the boost circuit 12 is connected to the node N31 of the boost circuit 13.

[0024] And in the charge pump circuit 1 of the present embodiment, the second input signal I2 input to the second capacitors (capacitors C12, C22, C32, and C2) included in the boost circuits 11 to 13 and the input circuit 10 is configured to be switched between the second drive signal OSC2 and the third drive signal OSC3.

[0025] As means for making the second input signal I2 switchable, the charge pump circuit 1 illustrated in FIG. 1 further includes switching elements S1 to S4 (second switching elements). The switching elements S1 to S4 switch the second input signal I2 input to the second capacitors (capacitors C2, C12, C22, and C32) of the input circuit 10 and each boosting circuit between the second drive signal OSC2 and the third drive signal OSC3.

[0026] For example, the common contact Sa of the switching element S2 is connected to the other end C2b of the capacitor C12, and the two fixed contacts Sb and Sc of the switching element S2 are connected to the transmission lines 31 and 32 of the second drive signal OSC2 and the third drive signal OSC3, respectively. For example, when the common contact Sa and the fixed contact Sb are connected in the switching element S2, the second drive signal OSC2 is input to the capacitor C12 as the second input signal I2. The switching elements S1, S3, and S4 are also connected between the capacitors C2, C22, and C32 and the transmission lines 31 and 32, respectively, in the same manner as the switching element S2.

[0027] In the charge pump circuit 1 of the example in FIG. 1, the first input signal I1 input to the capacitors C11, C21, and C31 (first capacitors) is further configured to be switched between the first drive signal OSC1 and its inverted signal OSC_inv.

[0028] As means for making the first input signal I1 switchable, the charge pump circuit 1 illustrated in FIG. 1 further includes switching elements S5 to S7 (third switching elements). The switching elements S5 to S7 switch the first input signal I1 input to the first capacitors (capacitors C11, C21, and C31) of each boosting circuit between the first drive signal OSC1 and its inverted signal OSC_inv.

[0029] For example, the common contact Sa of the switching element S5 is connected to one end C1a of the capacitor C11, and the two fixed contacts Sb and Sc of the switching element S5 are connected to the transmission lines 33 and 34 of the first drive signal OSC1 and the inverted signal OSC_inv, respectively. For example, when the common contact Sa and the fixed contact Sb are connected in the switching element S5, the first drive signal OSC1 is input to the capacitor C11 as the first input signal I1. The switching elements S6 and S7 are also connected between the capacitors C21 and C31 and the transmission lines 33 and 34, respectively, in the same manner as the switching element S5.

[0030] The charge pump circuit 1 can be constituted by, for example, transistors, capacitors formed on a semiconductor substrate, and a metal wiring layer made of aluminum or the like. In that case, each capacitor constituting the boost circuits 11 to 13 and the input circuit 10 can be a so-called MOS capacitor constituted by, for example, a metal layer, a semiconductor layer, and an oxide film sandwiched therebetween. Also, in that case, the switching elements S1 to S7 can be so-called MOS switches made of MOSFETs formed on a semiconductor substrate. Alternatively, the charge pump circuit 1 may be constituted by discrete transistors, diodes, capacitors, and mechanical switches or electromagnetic relays as the switching elements S1 to S7, which are individually formed and connected to each other by wiring so as to constitute the circuit as shown in FIG. 1. Each circuit element constituting the charge pump circuit 1 is not limited to the elements exemplified herein and can be composed of elements of any form and / or structure.

[0031] When the switching elements S1 to S7 are elements that switch between a conductive state and a non-conductive state in response to a control signal input to a control terminal, such as MOSFETs or electromagnetic relays, the control signal can be formed by, for example, a logic circuit (not shown) that generates part or all of the first to third drive signals OSC1 to OSC3. However, the control signal for the switching elements S1 to S7 can be formed by any signal generation circuit (not shown) that can generate a signal capable of switching the conductive state of the switching elements S1 to S7. Further, when the switching elements S1 to S7 are mechanical switches, for example, the conductive state of the switching elements may be switched by the manufacturer of the charge pump circuit 1 or by a manual operation of the user.

[0032] As shown in FIG. 2, both the second drive signal OSC2 and the third drive signal OSC3 are signals that transition between a high level and a low level at substantially the same period as the first drive signal OSC1. The second drive signal OSC2 is a signal that becomes a level that causes the switching elements Q1, Q11, Q21, and Q31 of the input circuit 10 and each boosting circuit 11 to 13 to be in a conductive state during the period when the first drive signal OSC1 is at a low level. On the other hand, the third drive signal OSC3 is a signal that becomes a level that causes the switching elements Q1, Q11, Q21, and Q31 to be in a conductive state during the period when the first drive signal OSC1 is at a high level. In the example of FIG. 1, the switching elements Q1, Q11, Q21, and Q31 are composed of N-type MOSFETs. Therefore, FIG. 2 illustrates the second drive signal OSC2 that becomes a high level during the period when the first drive signal OSC1 is at a low level, and the third drive signal OSC3 that becomes a high level during the period when the first drive signal OSC1 is at a high level.

[0033] In the example of FIG. 2, the period during which the second drive signal OSC2 is at a high level is shorter than the period during which the first drive signal OSC1 is at a low level, and the period during which the third drive signal OSC3 is at a high level is shorter than the period during which the first drive signal OSC1 is at a high level. That is, the second drive signal OSC2 rises after the fall of the first drive signal OSC1 and falls before the rise of the first drive signal OSC1. The third drive signal OSC3 rises after the rise of the first drive signal OSC1 and also falls before the fall of the first drive signal OSC1. However, the period during which the second drive signal OSC2 is at a high level may be the same as the period during which the first drive signal OSC1 is at a low level, and the period during which the third drive signal OSC3 is at a high level may be the same as the period during which the first drive signal OSC1 is at a high level. That is, the second drive signal OSC2 may rise substantially simultaneously with the fall of the first drive signal OSC1 and fall substantially simultaneously with the rise of the first drive signal OSC1. The third drive signal OSC3 may rise substantially simultaneously with the rise of the first drive signal OSC1 and fall substantially simultaneously with the fall of the first drive signal OSC1.

[0034] In the example of FIG. 2, the first drive signal OSC1 and the inverted signal OSC_inv periodically change levels between a high level VH1 and a low level VL1. The second drive signal OSC2 periodically changes levels between a high level VH2 and a low level VL2, and the third drive signal OSC3 periodically changes levels between a high level VH3 and a low level VL3. The low levels VL1 to VL3 can be arbitrary values and may be, for example, the GND level. The high level VH1 can also take an arbitrary value. Only the magnitude of the differential voltage between the high level VH1 and the low level VL1 is used to boost the voltage input from the input terminal Vin side in each boost circuit. The high levels VH2 and VH3 can take arbitrary values as long as they can turn on the switching elements Q1, Q11, Q21, and Q31 by the transitions from the low levels VL2 and VL3, respectively. The high levels VH1, VH2, and VH3 may be the same level as each other or may be different from each other.

[0035] In this embodiment, as described above, the second input signal I2 input to each boosting circuit and the input circuit 10 is configured to be switchable between the second driving signal OSC2 and the third driving signal OSC3. Therefore, according to the first to third driving signals OSC1 to OSC3, a discharge path of the capacitor C3 (see FIG. 1) connected to the output terminal Vout can be formed. Therefore, in the charge pump circuit 1 of this embodiment, adjustment for lowering the output voltage can be quickly performed. With continued reference to FIGS. 1 and 2 and with reference to FIG. 3, the boosting operation and the discharging operation of the capacitor C3 when the first to third driving signals OSC1 to OSC3 of the example of FIG. 2 are input to the charge pump circuit 1 of FIG. 1 will be described. For ease of understanding of the operation, it is described that the low level of each driving signal is 0V.

[0036] <Boosting operation> In the setting of the switching elements S1 to S7 in the charge pump circuit 1 of FIG. 1, the second driving signal OSC2 is input to the input circuit 10 and the boosting circuit 12, and the third driving signal OSC3 is input to the boosting circuits 11 and 13. Then, the first driving signal OSC1 is input to the boosting circuits 11 and 13, and the inverted signal OSC_inv is input to the boosting circuit 12. When the driving signals OSC1 to OSC3 shown in FIG. 2 are input to the charge pump circuit 1 with the nodes N11, N21, and N31 of the boosting circuits 11 to 13 in a state of, for example, 0V, at time t1, since the first driving signal OSC1 becomes the high level VH1, the potentials of the nodes N11 and N31 rise to VH1. At this time, the potentials of the nodes N12 and N32 are set to a potential lower than the potentials of the nodes N11 and N31 by the threshold voltages of the MOSFETs constituting the rectifying elements Q12, Q13 and Q32, Q33, respectively, because the rectifying elements Q12, Q13 and Q32, Q33 are in the conducting state with respect to the potentials of the nodes N11 and N31.

[0037] When the third driving signal OSC3 rises to the high level VH3 at time point t2, the change in its level is transmitted to nodes N13 and N33 respectively, and the switching elements Q11 and Q31 enter the conducting state. The charge stored in the capacitor C11 moves to the capacitor C21 so that the potentials of nodes N11 and N21 become equal, charging the capacitor C21 and raising the potential of node N21 (the potential of node N11 drops according to the amount of charge movement). Similarly, the charge stored in the capacitor C31 moves to the capacitor C3 so that the potentials of nodes N31 and the output terminal Vout become equal, charging the capacitor C3 and raising the potential of the output terminal Vout (the potential of node N31 drops according to the amount of charge movement). Note that since the second driving signal OSC2 is at the low level, the switching elements Q1 and Q21 are in the non-conducting state, so the charges of the capacitors C11 and C31 do not move to the input terminal Vin side, and the charge of the capacitor C21 does not move to the output terminal Vout side.

[0038] When the third driving signal OSC3 drops to the low level VL3 at time point t3, the switching elements Q11 and Q31 enter the non-conducting state, and the potentials of nodes N11, N21, N31, and the output terminal Vout are maintained.

[0039] At time point t4, the first driving signal OSC1 becomes the low level VL1, while its inverted signal OSC_inv rises to the high level VH1, so the potential of node N21 rises. The charge of the capacitor C21 moves to the capacitor C31 so that the potential of node N22 becomes lower than the potential of node N21 by the threshold voltages of the MOSFETs forming the rectifying elements Q22 and Q23.

[0040] As described above, the potential of node N11 at time t2 decreases according to the amount of charge transferred to node 21, and the charge between both ends of capacitor C11 is held until time t4. When the first driving signal OSC1 becomes the low level VL1 at time t4, node N11 becomes a negative voltage due to the charge held in capacitor C11. Then, when the second driving signal OSC2 rises to the high level VH2 at time t5, the change in its level is transmitted to node N3, and the switching element Q1 becomes conductive. Capacitor C11 is charged so that the potential of the input terminal Vin becomes equal to that of node N11. Also, when the second driving signal OSC2 rises to the high level VH2 at time t5, the change in its level is transmitted to node N23, and the switching element Q21 becomes conductive. The charge stored in capacitor C21 moves to capacitor C31 so that the potentials of node N21 and node N31 become equal, and capacitor C31 is charged. At the same time, the potential of node N31 rises according to the amount of charge transferred (the potential of node N21 decreases according to the amount of charge transferred). On the other hand, since the third driving signal OSC3 is at the low level, the switching elements Q11 and Q31 are non-conductive. Therefore, the charge of capacitor C21 does not move to the input terminal Vin side, and the charge of capacitor C31 does not move to the output terminal Vout side.

[0041] Next, when the second driving signal OSC2 drops to the low level VL2 at time t6, the switching elements Q1 and Q21 become non-conductive, and the potentials of node N11, node N21, and node N31 are maintained. When the first driving signal OSC1 becomes the high level VH1 again at time t7 and the inversion signal OSC_inv drops to the low level VL1, similar to time t1, there is also charge transfer through the paths of the rectifying elements Q12, Q13, and Q32, Q33. However, the potentials of node N11 and node N31 rise according to the amount of charge held in capacitor C11 and capacitor C31. On the other hand, the potential of node N21 decreases according to the amount of charge held in capacitor C21.

[0042] Then, at time t8, the third drive signal OSC3 rises to the high level VH3 again. Thus, similar to time t2, the switching elements Q11 and Q31 are turned on. The capacitor C21 is charged and the potential of the node N21 rises. Also, the capacitor C3 is further charged and the potential of the output terminal Vout rises further.

[0043] Thereafter, every time a level transition occurs in each drive signal, the potential of the output terminal Vout rises. Also at the node N31, although there is a potential drop at time t2 and the like, since the charge from the input terminal Vin side moves to the output terminal Vout side every time a level transition occurs, the charging of the capacitor C31 progresses and the potential of the node N31 rises. Similarly, the potentials of the nodes N21 and N11 also rise with the repetition of the level transitions of each drive signal. Then, each of the capacitors C11, C21, and C31 is charged until the potential difference across both ends thereof reaches VH1, and the movement of charge between the capacitors ends. Thereafter, the node N11 repeats level transitions between 0V and VH1, the node N21 repeats level transitions between VH1 and 2×VH1, and the node N31 repeats level transitions between 2×VH1 and 3×VH1. A charge corresponding to a voltage of 3×VH1 is accumulated in the capacitor C3, and at the output terminal Vout, an output voltage of 3×VH1 is obtained between it and GND.

[0044] The charge pump circuit 1 in the example of FIG. 1 includes a plurality of boost circuits (boost circuits 11 to 13), but the charge pump circuit of the present embodiment may include a boost circuit such as one or more arbitrary numbers of boost circuits 11. Even with a single boost circuit, the voltage of the input terminal Vin can be boosted by the amplitude of the first drive signal OSC1, and the more boost circuits are included, the higher the voltage of the input terminal Vin can be boosted. Also, the input terminal Vin does not have to be connected to GND as in the example of FIG. 1, and an arbitrary voltage can be applied to the input terminal Vin. In the charge pump circuit of the embodiment, an output voltage approximated by (the number N of boost circuits connected in series × the amplitude of the first drive signal OSC1) + (the voltage of the input terminal Vin) is obtained.

[0045] Note that the rectifying elements Q3, Q13, Q23, and Q33 of the boost circuits 11 to 13 and the input circuit 10 function as protection elements for the switching elements Q1, Q11, Q21, and Q31 when signals such as the first drive signal OSC1 stop. For example, when the input of a drive signal such as the first drive signal OSC1 stops after the boost operation, the potentials of nodes N11, N21, and N31 and the output terminal Vout gradually decrease due to the leakage current of the switching elements Q1, Q11, Q21, and Q31. On the other hand, when the rectifying elements Q3, Q13, Q23, and Q33 are not provided, there is no discharge path for the gates of the switching elements Q1, Q11, Q21, and Q31, so the potential of this gate will eventually become higher than the potentials of the drain and source, and the switching elements Q1, Q11, Q21, and Q31 may be damaged.

[0046] In particular, when the charge pump circuit 1 is used for the MEMS microphone as described above, a protection circuit (not shown) may be connected to the output terminal Vout side as an ESD countermeasure, and such a protection circuit may have a large leakage current characteristic. In that case, the decrease in the potentials of the output terminal Vout and nodes N11, N21, and N31 is accelerated, and the potential of the gate of the switching element Q31 or the like becomes relatively easier to rise higher than the potentials of the drain and source. That is, the switching element Q31 or the like is likely to be damaged. However, in the example of FIG. 1, a discharge path for the gate of the switching element Q31 or the like is provided by the rectifying elements Q3, Q13, Q23, and Q33. Therefore, damage to the switching elements Q1, Q11, Q21, and Q31 can be prevented.

[0047] <Discharge operation> Since the charge pump circuit 1 of the present embodiment is configured to be able to switch the second input signal I2 between the second drive signal OSC2 and the third drive signal OSC3, when the discharge of the capacitor C3 is necessary, the second input signal I2 is switched from the boosting operation. For example, as shown in FIG. 3, the switching elements S1 to S4 are switched so that their common contacts are connected to the fixed contacts opposite to those connected in the example of FIG. 1. That is, the second drive signal OSC2 is input to the boosting circuit 11 and the boosting circuit 13, and the third drive signal OSC3 is input to the input circuit 10 and the boosting circuit 12.

[0048] When each drive signal in the example of FIG. 2 is input to the charge pump circuit 1 in which each switching element is set and the capacitor C3 is charged as in the example of FIG. 3, the first drive signal OSC1 becomes the high level VH1 at time t1, so the potentials of the node N11 and the node N31 rise by VH1. On the other hand, since the inverted signal OSC_inv becomes the low level VL1, the potential of the node N21 drops by VH1.

[0049] When the third drive signal OSC3 rises to the high level VH3 at time t2, the switching elements Q1 and Q21 are turned on instead of the switching elements Q11 and Q31. The charge stored in the capacitor C31 moves to the capacitor C21, the capacitor C31 is discharged, and the potential of the node N31 drops (the potential of the node N21 rises). Similarly, the charge stored in the capacitor C11 flows into the GND via the input terminal Vin, the capacitor C11 is discharged, and the potential of the node N11 drops. Since the second drive signal OSC2 is at the low level, the switching elements Q11 and Q31 are in the non-conducting state, so the charges of the capacitors C11 and C31 do not move to the output terminal Vout side.

[0050] When the third drive signal OSC3 drops to the low level VL3 at time point t3, the switching elements Q1 and Q21 become non-conductive, and the potentials of node N11, node N21, node N31, and the output terminal Vout are maintained. Next, at time point t4, the first drive signal OSC1 becomes the low level VL1, while its inverted signal OSC_inv rises to the high level VH1. Therefore, although there is also a movement of charge through the paths of the rectifying elements Q2, Q3 and Q22, Q23, the potential of node N21 rises according to the amount of charge held by the capacitor C21, and the potentials of node N11 and node N31 respectively drop according to the amount of charge held by the capacitors C11 and C31.

[0051] When the second drive signal OSC2 rises to the high level VH2 at time point t5, the switching elements Q11 and Q31 become conductive. The charge stored in the capacitor C3 moves to the capacitor C31 and the capacitor C3 is discharged, and at the same time, the potential of the output terminal Vout drops (the potential of node N31 rises). Similarly, the charge stored in the capacitor C21 moves to the capacitor C11 and the capacitor C21 is discharged, and at the same time, the potential of node N21 drops (the potential of node N11 rises). On the other hand, since the third drive signal OSC3 is at the low level, the switching elements Q1 and Q21 are in the non-conductive state, and therefore the charges of the capacitors C11 and C31 do not move to the input terminal Vin side.

[0052] Next, at time point t6, the second drive signal OSC2 drops to the low level VL2 and the switching elements Q1 and Q31 become non-conductive, and the potentials of node N11, node N21, and node N31 are maintained. At time point t7, the first drive signal OSC1 becomes the high level VH1 again and the inverted signal OSC_inv drops to the low level VL1. Similar to time point t1, the potentials of node N11 and node N31 rise only by VH1. On the other hand, the potential of node N21 drops only by VH1.

[0053] At time t8, the third driving signal OSC3 rises to the high level VH3 again. Thus, similar to time t2, the switching elements Q1 and Q21 enter the conducting state. The capacitors C11 and C31 are discharged, and the potentials of nodes N11 and N31 decrease. Thereafter, at time t9, the potentials of the respective nodes are maintained as in time t3, and at time t10, the potentials of the respective nodes increase or decrease as in time t4.

[0054] Then, when the second driving signal OSC2 rises to the high level VH2 again at time t11, similar to time t5, the switching elements Q11 and Q31 enter the conducting state, the capacitor C21 is discharged, and the potential of node N21 decreases. Similarly, the capacitor C3 is further discharged, and the potential of the output terminal Vout further decreases.

[0055] Thereafter, each time a level transition occurs in each driving signal, the capacitor C3 is discharged and the potential of the output terminal Vout decreases. Also at node N31, although the potential rises at times such as t5, the discharge of the capacitor C31 progresses with the conduction of Q21 at time t8, and the potential of node N31 decreases. Similarly, the potentials of nodes N21 and N11 also decrease with the repetition of the level transitions of each driving signal. If the input of each driving signal continues, the capacitors C3, C11, C21, and C31 are each completely discharged. Then, the potential of the output terminal Vout decreases to the potential of the input terminal Vin (GND in the example of FIG. 3).

[0056] Thus, in this embodiment, since the second input signal I2 can be switched between the second drive signal OSC2 and the third drive signal OSC3, not only the boosting operation but also a discharge path for the capacitance at the output terminal (mainly the capacitor C3 in FIG. 3) can be intentionally formed. Therefore, the potential of the output terminal Vout can be rapidly decreased. In other words, during the period when the high level of the first input signal I1 is input to each boosting circuit, by inputting the second input signal I2, which is at a level that causes the switching element of each boosting circuit to be in a conductive state, to each boosting circuit, the charge in each boosting circuit can be moved to the output terminal Vout side, and the boosting operation can be performed. On the other hand, during the period when the low level of the first input signal I1 is input to each boosting circuit, by inputting the second input signal I2, which is at a level that causes the switching element of each boosting circuit to be in a conductive state, to each boosting circuit, the charge in each boosting circuit and the charge in the capacitance of the output terminal Vout can be moved to the input terminal Vin side, and the potential of the output terminal Vout can be rapidly decreased.

[0057] In the example of FIG. 3, for discharging the capacitor C3 at the output terminal Vout, the connection states of all the switching elements S1 to S4 are switched from the settings for the boosting operation shown in FIG. 1. That is, in each of the boosting circuits 11 to 13 and the input circuit 10, the second input signal I2 is simultaneously switched from the second drive signal OSC2 to the third drive signal OSC3, or from the third drive signal OSC3 to the second drive signal OSC2. Thus, in this embodiment, the switching of the second input signal I2 in each of the plurality of boosting circuits 11 to 13 and the input circuit 10 may be possible simultaneously in all of the plurality of boosting circuits 11 to 13 and the input circuit 10.

[0058] When the connection states of the switching elements S1 to S4 are set as in the example of FIG. 3, as described above, the capacitors of each boosting circuit such as the capacitor C31 are sequentially discharged for each level transition of each drive signal. Therefore, even immediately after the start of discharge, an excessive voltage based on the boosted high voltage is unlikely to be applied to the switching elements of each boosting circuit such as the switching element Q31. For example, even if there are variations in the on-resistance characteristics among the MOSFETs constituting the switching elements Q1, Q11, Q21, and Q31, since all of the switching elements Q1, Q11, Q21, and Q31 do not simultaneously enter the conductive state, the high voltage after boosting is not distributed to each switching element according to the characteristics of each switching element. Therefore, an excessive voltage is unlikely to be applied to a specific switching element. These switching elements theoretically only need to have a breakdown voltage of twice or more the amplitude of the first drive signal OSC1. Therefore, compared to the case of only performing the boosting operation, a particularly large breakdown voltage is not required for the switching element Q31 or the like, and a high degree of freedom is obtained in the selection of the switching element Q31 or the like. However, the setting of the switching elements S1 to S4 for lowering the potential of the output terminal Vout is not limited to the example of FIG. 3.

[0059] <Another example of the setting of the switching elements S1 to S4 for discharge> FIG. 4 shows another example of the setting of the switching elements S1 to S4 that lower the potential of the output terminal Vout, that is, discharge the capacitor C3. In the example of FIG. 4, only the connection states of the switching elements S1 and S3 are switched from the setting for the boosting operation shown in FIG. 1. As a result, the third drive signal OSC3 is input as the second input signal I2 to all of the boosting circuits 11 to 13 and the input circuit 10. Therefore, for example, when the third drive signal OSC3 rises to the high level VH3 at time t2, time t8, etc. in each drive signal in the example of FIG. 2, the switching elements Q1, Q11, Q21, and Q31 are simultaneously turned on. Then, the charges in the capacitor C3 and the charges in the capacitors C11, C21, and C31 in each boosting circuit move to the input terminal Vin side simultaneously, and all of these capacitors are discharged simultaneously. Therefore, the capacitor C3 can be discharged more quickly, and the voltage of the output terminal Vout can be decreased more quickly. Also, when discharging the capacitor C3 with the setting of the switching elements S1 to S4 as in the example of FIG. 4, the logic circuit that generates the control signals of the switching elements S1 to S4 may be realized with a simpler configuration compared to the case of discharging with the setting as in the example of FIG. 3.

[0060] Note that in the example of FIG. 4, the switching elements S1 to S4 are set such that the third drive signal OSC3 is input as the second input signal I2 to all of the boosting circuits 11 to 13 and the input circuit 10, but the switching elements S1 to S4 may be set such that the second drive signal OSC2 is input as the second input signal I2 to all of the boosting circuits 11 to 13 and the input circuit 10. Also in this case, for example, when the second drive signal OSC2 rises to the high level VH2 at time t5, time t11, etc. in each drive signal in the example of FIG. 2, the switching elements Q1, Q11, Q21, and Q31 are simultaneously turned on, and the voltage of the output terminal Vout can be decreased more quickly than in the example of FIG. 3.

[0061] Thus, in this embodiment, the switching of the second input signal I2 may be possible such that the second input signal I2 becomes the second drive signal OSC2 or the third drive signal OSC3 in all of the plurality of boost circuits 11 to 13 and the input circuit 10.

[0062] Also, in this embodiment, the switching of the second input signal I2, such as the switching from the setting for the boost operation shown in FIG. 1 to the setting shown in FIG. 4 for the switching elements S1 to S4, may be individually switchable in each of the plurality of boost circuits 11 to 13 and the input circuit 10. That is, the second input signal I2 may be configured to be switchable between the second drive signal OSC2 and the third drive signal OSC3 independently of each other among the plurality of boost circuits 11 to 13 and the input circuit 10.

[0063] <Switching of Boost Stages> In an n-stage charge pump circuit in which n unit charge pumps as in the above-described Patent Document 1 are connected in series, adjustment to an output voltage obtained by boosting by (n - x) stages (x is an integer smaller than n) may be required. In that case, for example, by shorting the output of any one of the n unit charge pumps to GND, a voltage that does not include the boosting for the number of stages from the first stage to that unit charge pump can be obtained as the output voltage of the n-stage charge pump circuit. However, in this case, a switching element such as a transistor is required to short the output of any one of the unit charge pumps to GND. And the switching element is required to have a breakdown voltage corresponding to the boosting for the number of stages to be reduced. When only a switching element that does not have a sufficient breakdown voltage can be selected due to constraints in the manufacturing process or the like, the adjustment range of the output voltage (boosting stage number) of the charge pump circuit will be limited.

[0064] In contrast, as described above, in the charge pump circuit 1 shown in FIGS. 1 to 4, in addition to the second input signal I2 being switchable, the first input signal I1 (see FIG. 1) is configured to be switched between the first drive signal OSC1 and its inverted signal OSC_inv. Therefore, even if the charge pump circuit 1 is configured to perform step-up conversion in three steps using three step-up circuits 11 to 13 as in the example of FIG. 1, the number of step-up stages can be switched from three steps, that is, the number of step-up stages can be adjusted between one step and three steps. FIG. 5 shows an example of the settings of the switching elements S1 to S7 when the number of step-up stages of the charge pump circuit 1 of the present embodiment is switched.

[0065] In the example of FIG. 5, the switching element S1 and the switching element S5 are switched so that their common contacts are connected to fixed contacts opposite to the fixed contacts connected in the example of FIG. 1. That is, the inverted signal OSC_inv of the first drive signal OSC1 is input as the first input signal I1 to both the step-up circuit 11 and the step-up circuit 12, and the third drive signal OSC3 is input as the second input signal I2 to both the input circuit 10 and the step-up circuit 11. In the charge pump circuit 1 in which the first input signal I1 and the second input signal I2 are switched as in the example of FIG. 5, step-up conversion is not performed in the step-up circuit 11, and two-step step-up conversion is performed by the step-up circuit 12 and the step-up circuit 13.

[0066] That is, in the period from time point t4 to time point t7 when the inverted signal OSC_inv illustrated in FIG. 2 becomes high level VH1 and the potential of node N11 rises, since the third drive signal OSC3 is at low level, the charge of capacitor C11 does not move to the output terminal Vout side. When the inverted signal OSC_inv drops to low level VL1 at time point t7, the potential of node N11 returns to the potential before time point t4. Therefore, even if the third drive signal OSC3 rises to high level VH3 at time point t8 and the switching element Q1 becomes conductive, no charge moves from the input terminal Vin side to the capacitor C11. Therefore, step-up conversion is not performed in the step-up circuit 11, and two-step step-up conversion is performed only by the step-up circuit 12 and the step-up circuit 13.

[0067] Note that even if the settings of all the switching elements S1 to S7 in FIG. 5 are switched so that each common contact is connected to a fixed contact opposite to the fixed contact to which it is connected in the example of FIG. 5, a two-stage boosting operation can be obtained only by the boosting circuits 12 and 13. Further, by switching the settings of the switching elements S3, S4, and S7 in FIG. 5 so that each common contact is connected to a fixed contact opposite to the fixed contact to which it is connected in the example of FIG. 5, a one-stage boosting operation can be obtained only by the boosting circuit 13. Furthermore, even if all the settings of the switching elements S1 to S7 are switched in the reverse direction from that setting, a one-stage boosting operation can be obtained only by the boosting circuit 13.

[0068] Thus, in the present embodiment, from the settings of the switching elements S1 to S7 illustrated in FIG. 1, the same signal (the first drive signal OSC1 or its inverted signal OSC_inv) may be input as the first input signal I1 to both of the adjacent boosting circuits, and the same signal (the second drive signal OSC2 or the third drive signal OSC3) may be input as the second input signal I2. That is, in the present embodiment, the first input signal I1 may be switchable so that the first input signals I1 between adjacent boosting circuits among the plurality of boosting circuits 11 to 13 become the same. Also, the second input signal I2 may be switchable so that the second input signals I2 between adjacent boosting circuits among the plurality of boosting circuits 11 to 13 become the same. Further, the second input signal I2 may be switchable so that the second input signals I2 become the same between the input circuit 10 and the boosting circuit 11 adjacent to the input circuit 10, such as the switching from the setting illustrated in FIG. 1 to the setting illustrated in FIG. 5.

[0069] Furthermore, in the present embodiment, the first input signal I1 may be switchable between the first drive signal OSC1 and its inverted signal OSC_inv independently of each other among the plurality of boost circuits 11 to 13. Also, in each boost circuit, regardless of whether the first input signal I1 is the first drive signal OSC1 or the inverted signal OSC_inv, the second input signal I2 may be switchable to either the second drive signal OSC2 or the third drive signal OSC3. Similarly, in each boost circuit, regardless of whether the second input signal I2 is the second drive signal OSC2 or the third drive signal OSC3, the first input signal I1 may be switchable to either the first drive signal OSC1 or the inverted signal OSC_inv.

[0070] FIG. 6 shows an example of the change in the voltage (output voltage Vo) at the output terminal Vout when switching from the three-stage boost according to the setting of the example in FIG. 1 to the two-stage boost according to the setting of the example in FIG. 5 after the three-stage boost. In the example of FIG. 6, the three-stage boost starts from time point ta according to the setting illustrated in FIG. 1. The output voltage Vo gradually rises and substantially completes the boost at time point tb. Thereafter, in order to obtain the output voltage Vo of the two-stage boost, the setting of any of the switching elements S1 to S7 (see FIG. 1) is switched at time point tc.

[0071] At this time, if directly switched from the setting of FIG. 1 to the setting of FIG. 5, it takes time for the capacitance (such as the capacitor C3 in FIG. 1) at the output terminal Vout to discharge, and the output voltage Vo does not easily decrease as indicated by the two-dot chain line L in FIG. 6. Therefore, the switching elements S1 to S4 are once switched to the setting illustrated in FIG. 3, for example, and the capacitor C3 or the like is discharged. Along with the discharge of the capacitor C3 or the like, the output voltage Vo rapidly decreases from time point tc and decreases to approximately 0V at time point td.

[0072] Thereafter, at time point te, the switching elements S2 to S5 are switched to the settings illustrated in FIG. 5. Boosting in two steps is started from time point te, and substantially two-step boosting is completed at time point tf. When the output voltage Vo is to be decreased, regardless of whether or not the switching of the number of steps (reduction of the number of steps) is included, by intentionally discharging the capacitor C3 or the like once in this way, the desired output voltage Vo after the decrease can be obtained promptly.

[0073] <Another example of the charge pump circuit of this embodiment> FIGS. 7 and 8 show charge pump circuits 1a and 1b, which are other examples of the charge pump circuit of this embodiment. The charge pump circuit 1a in FIG. 7 does not include the switching elements S5 to S7 provided in the example of FIG. 1. That is, the capacitor C11 of the boosting circuit 11 and the capacitor C31 of the boosting circuit 13 are directly connected to the transmission line 33 of the first drive signal OSC1, and the capacitor C21 of the boosting circuit 12 is directly connected to the transmission line 34 of the inverted signal OSC_inv. The charge pump circuit of this embodiment, like the charge pump circuit 1a in FIG. 7, does not necessarily have to be able to switch the first input signal I1. Even in that case, as described with reference to FIGS. 1 and 3 in which the settings of each of the switching elements S5 to S7 are the same, the potential of the output terminal Vout can be promptly decreased by intentionally discharging the capacitor C3.

[0074] The charge pump circuit 1b in Fig. 8 does not include all of the switching elements S1 to S7 provided in the example of Fig. 1. The capacitors C11, C21, and C31 of the boost circuits 11 to 13 respectively, and the capacitors C2, C12, C22, and C32 of the input circuit 10 and the boost circuits 11 to 13 respectively are connected to the signal generation circuit 4. The signal generation circuit 4 generates and outputs, as the first input signals In11, In12, In13 of the boost circuits 11, 12, 13 respectively, the first drive signal OSC1 or the inverted signal OSC_inv according to the required number of boost stages to each of the boost circuits 11, 12, 13. Further, the signal generation circuit 4 generates and outputs, as the second input signals In20, In21, In22, In23 of the input circuit 10 and the boost circuits 11, 12, 13 respectively, the second drive signal OSC2 or the third drive signal OSC3 according to the operation (boost operation or discharge operation) and / or the number of boost stages required in the charge pump circuit 1b to the input circuit 10 and each of the boost circuits 11 to 13.

[0075] That is, the first input signals In11 to In13 of each boost circuit are switched between the first drive signal OSC1 and the inverted signal OSC_inv by the signal generation circuit 4, rather than by the switching elements S5 to S7 in the example of Fig. 1. Also, the second input signals In20 to In23 of the input circuit 10 and each boost circuit are switched between the second drive signal OSC2 and the third drive signal OSC3 by the signal generation circuit 4, rather than by the switching elements S1 to S4 in the example of Fig. 1. Note that the signal generation circuit 4 can be configured, for example, by a combination of an oscillation circuit and an appropriate logic circuit. Thus, in this embodiment, as a switching means for the first input signal and the second input signal, it is not necessary to provide a switching means for connecting signal lines such as the switching elements S1 to S7. A signal generation means such as the signal generation circuit 4 may be provided, and the first input signal and the second input signal may be switched by switching the generated signal by the signal generation means. Note that in this embodiment, the switching means for the first input signal and the second input signal is not limited to the examples of Figs. 1 and 8, and any switching means may be used.

[0076] The charge pump circuit of this embodiment is not particularly limited in its application and is used in various electrical devices that require boosting. Therefore, its output terminal (for example, the output terminal Vout of the charge pump circuit 1 in FIG. 1) can output a voltage applied to any electrical device. In particular, the charge pump circuit of this embodiment, which can rapidly decrease the voltage at the output terminal, may be suitable as a voltage source for a MEMS microphone that requires adjustment of the output voltage. Therefore, the output terminal of the charge pump circuit of this embodiment may output a voltage applied to the MEMS microphone.

Explanation of Signs

[0077] 1, 1a, 1b Charge pump circuit 10 Input circuit 11 - 13 Boosting circuit (unit charge pump) C11, C21, C31 Capacitor (first capacitor) C1a One end C1b The other end C2, C12, C22, C32 Capacitor (second capacitor) I1 First input signal I2 Second input signal N1, N11, N21, N31 Node (first node) N2, N12, N22, N32 Node (second node) N3, N13, N23, N33 Node (third node) OSC1 First drive signal OSC_inv Inverted signal OSC2 Second drive signal OSC3 Third drive signal Q1, Q11, Q21, Q31 Switching element Q2, Q12, Q22, Q32 Rectifying element Q3, Q13, Q23, Q33 Rectifying element S1 - S4 Switching element (second switching element) S5 - S7 Switching element (third switching element) Vin Input terminal Vout Output terminal

Claims

1. A charge pump circuit including one or more boost circuits connected in series between an input terminal and an output terminal, wherein each of the one or more boost circuits includes: a first capacitor that receives, at one end, a first driving signal that periodically changes in level or an inverted signal obtained by inverting the first driving signal as a first input signal; a switching element that switches between conduction and non-conduction between the first node and a second node on the output terminal side of the first node in accordance with the potential of a third node connected to the other end of the first capacitor via a rectifying element; a second capacitor that receives a second input signal and transmits a change in the level of the second input signal to the third node; and the second input signal is configured to be switchable between a second driving signal having a level that causes the switching element to be in a conductive state during a period in which the first driving signal is at a low level and a third driving signal having a level that causes the switching element to be in a conductive state during a period in which the first driving signal is at a high level. A charge pump circuit.

2. The charge pump circuit according to claim 1, further including a second switching element that switches the second input signal between the second driving signal and the third driving signal.

3. The charge pump circuit according to claim 1 or 2, wherein each of the one or more boost circuits further includes a rectifying element connected so as to be in a forward direction from the third node toward the second node.

4. The charge pump circuit according to any one of claims 1 to 3, wherein the first input signal is configured to be switchable between the first driving signal and the inverted signal.

5. The charge pump circuit according to claim 4, further including a third switching element that switches the first input signal between the first driving signal and the inverted signal.

6. The one or more boost circuits include a plurality of boost circuits, The charge pump circuit according to claim 4 or 5, wherein the first input signals can be switched so as to be the same between adjacent boost circuits among the plurality of boost circuits.

7. The one or more boost circuits include a plurality of boost circuits, The charge pump circuit according to any one of claims 1 to 6, wherein the second input signals can be switched so as to be the same between adjacent boost circuits among the plurality of boost circuits.

8. The above-described boosting circuit(s) with a count of 1 or more includes a plurality of boosting circuits, The charge pump circuit according to any one of claims 1 to 7, wherein switching of the second input signal in each of the plurality of boosting circuits can be performed simultaneously for all of the plurality of boosting circuits.

9. The above-described boosting circuit(s) with a count of 1 or more includes a plurality of boosting circuits, The charge pump circuit according to any one of claims 1 to 8, wherein the second input signal can be switched so that the second input signal becomes the second drive signal or the third drive signal in all of the plurality of boosting circuits.

10. The charge pump circuit according to any one of claims 1 to 9, wherein the output terminal outputs a voltage applied to a MEMS microphone.

Images