Error Rate Measuring Apparatus and Error Rate Measuring Method

Abstract

To simultaneously measure not only a bit error but also a Flit error.SOLUTION: An operation part 2 sets: one cycle of a Flit pattern including EIEOS and SKP OS according to a lane number defined by a high speed bus standard; a Flit length according to the lane number; a threshold value for determining Flit errors; the insertion cycle of the EIEOS; and the pattern head of the Flit pattern. The error detection part 44 of an error detection device 4 detects and counts the errors of a Flit corresponding part of a PAM4 signal received by return from an object to be measured W when transmitting the PAM4 signal based on the bit string data of the Flit pattern from a pattern generator 3 to the object to be measured W in a loopback state; and a Flit error detection part 45 detects and counts the FEC symbol errors of the Flit corresponding part for every ECC Group to determine the number of the FEC symbol errors beyond the threshold value as the Flit errors.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an error rate measurement device and an error rate measurement method for performing error measurement of a PAM4 signal based on bit string data of a Flit pattern that is transmitted back from a device under measurement that transitions to a loopback state in link training.

Background Art

[0002] An error rate measurement device is conventionally known as a device that transmits a test signal of a known pattern including fixed data to a device under measurement, and compares, on a bit-by-bit basis, a received signal received back from the device under measurement with a reference signal as a reference to measure a bit error rate (BER).

[0003] Also, as disclosed in Patent Document 1 below, an error rate measurement device having an RS-FEC measurement function compliant with the IEEE 802.3 standard is known. In this error rate measurement device, the number of FEC symbol errors for each codeword length in a region delimited by the codeword length is totaled, and each error count number and error rate are acquired and displayed.

[0004] By the way, the physical layer evaluation of PCI Express 5.0 was performed by performing link training with the LTSSM (Link Training and Status State Machine) of the device under measurement to put the device under measurement in the Loopback state (signal feedback state) and using the MCP (Modified Compliance Pattern). The performance index at this time was BER < 10 -12 is.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] FEC was introduced in PCI Express 6.0. However, although MCP is defined in PCI Express 6.0, it is not subject to FEC guard. Therefore, when attempting to perform Gen6 physical layer evaluation with a Flit pattern protected by FEC, since the Flit pattern does not include EIEOS (Electrical Idle Exit Ordered Set) required for 1b / 1b synchronization, the PCIe Gen6 physical layer alone cannot be synchronized.

[0007] To further explain, the Gen6 Flit of PCI Express 6.0 is 1b / 1b encoded. In 1b / 1b encoding, EIEOS is used for 1b / 1b synchronization. And if only the pattern flowing in the L0 state is sent from the error rate measuring device to the object under measurement, as shown in Fig. 5(b), the pattern in L0 only includes Flit, SDS, and SKP OS (SKP Ordered Sets). Therefore, the error rate measuring device cannot receive EIEOS from the object under measurement, and the PCIe Gen6.0 physical layer cannot achieve 1b / 1b synchronization, resulting in the problem that error measurement cannot be performed.

[0008] The L0 state where normal Flits are transmitted and received is a state that arrives after the synchronization of 1b / 1b symbols by EIEOS, and EIEOS is not transmitted. In the L0 state, if EIEOS flows, a transition to the Recovery state will occur.

[0009] Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide an error rate measuring device and an error rate measuring method that simultaneously measure not only bit errors but also Flit errors.

Means for Solving the Problems

[0010] To achieve the above object, the error rate measurement device according to claim 1 of the present invention includes an operation unit 2 that performs settings for one cycle of a Flit pattern including EIEOS and SKP OS according to the number of lanes defined by the high-speed bus standard, a Flit length according to the number of lanes, a threshold for discriminating Flit errors, an insertion period of the EIEOS, and a pattern start of the Flit pattern. A pattern generator 3 that generates a PAM4 signal based on the bit string data of the Flit pattern and transmits it to the object under measurement W in a loopback state. An error detector 4 that receives a PAM4 signal based on the bit string data of the Flit pattern transmitted back from the object under measurement in the loopback state, detects and counts errors in the portion corresponding to the Flit by excluding the portions corresponding to the EIEOS and the SKP OS of the received PAM4 signal, detects and counts the number of FEC symbol errors for each ECC Group in the portion corresponding to the Flit, and determines as a Flit error those in which the number of FEC symbol errors exceeds the threshold, and a synchronization state management unit 46 that instructs reacquisition of the pattern start of the Flit pattern when the amount of errors in the portion corresponding to the Flit detected by the error detector exceeds a synchronization condition threshold. It is characterized by comprising the above.

[0011] The error rate measurement device according to claim 2 of the present invention is the error rate measurement device according to claim 1, When excluding the portion corresponding to the SKP OS from the measurement target, the operation unit is characterized in that it selectively sets whether to mask bit errors in the corresponding portion or filter and remove the SKP OS itself.

[0012] The error rate measurement device according to claim 3 of the present invention is the error rate measurement device according to claim 1, Regarding the portion corresponding to the Flit, whether there is no High-speed bus standard decoding or whether there is High-speed bus standard decoding of SelectIt is characterized in that it is selectively set in the selection part.

[0013] The error rate measurement device according to claim 4 of the present invention is the error rate measurement device according to any one of claims 1 to 3, characterized in that link training is performed with the object to be measured, and the LTSSM of the object to be measured is transitioned to a loopback state.

[0014] The error rate measurement device according to claim 5 of the present invention includes an operation unit 2 that performs one cycle of a Flit pattern including EIEOS and SKP OS according to the number of lanes defined by the high-speed bus standard, a Flit length according to the number of lanes, a threshold value for discriminating Flit errors, an insertion period of the EIEOS, and setting of the pattern start of the Flit pattern, a pattern generator 3 that generates a PAM4 signal based on the bit string data of the Flit pattern and transmits it to the object to be measured W in the loopback state, an error detector 4 that receives a PAM4 signal based on the bit string data of the Flit pattern transmitted back from the object to be measured in the loopback state, detects and counts errors in the part corresponding to Flit by excluding the parts corresponding to the EIEOS and the SKP OS of the received PAM4 signal, a Flit error detector 45 that detects and counts the number of FEC symbol errors for each ECC Group in the part corresponding to Flit and determines as a Flit error those with the number of FEC symbol errors exceeding the threshold value, and a synchronization state management unit 46 that instructs reacquisition of the pattern start of the Flit pattern when the amount of errors in the part corresponding to Flit detected by the error detector exceeds a synchronization condition threshold value, and is provided with when the part corresponding to the SKP OS is excluded from the measurement target, the operation unit selectively sets whether to mask the bit error in the corresponding part or filter and remove the SKP OS itself, Regarding the part corresponding to the Flit, High-speed bus standard without decoding of High-speed bus standard or with decoding ofSelect Select and set at the selection part, perform link training with the object to be measured, and transition the LTSSM of the object to be measured to a loopback state.

[0015] The error rate measurement method according to claim 6 of the present invention includes one cycle of a Flit pattern including EIEOS and SKP OS corresponding to the number of lanes defined by the high-speed bus standard, a Flit length corresponding to the number of lanes, a threshold value for discriminating a Flit error, an insertion period of the EIEOS, and a step of performing, at the operation unit 2, setting of the pattern start of the Flit pattern; a step of generating, by a pattern generator 3, a PAM4 signal based on the bit string data of the Flit pattern and transmitting the generated PAM4 signal to the object to be measured W in a loopback state; a step of receiving, by an error detection unit 44 of an error detector 4, a PAM4 signal based on the bit string data of the Flit pattern transmitted back from the object to be measured in the loopback state, and detecting and counting an error in a portion corresponding to a Flit, excluding portions corresponding to the EIEOS and the SKP OS of the received PAM4 signal; a step of detecting, by a Flit error detection unit 45 of the error detector, an FEC symbol error for each ECC Group in a portion corresponding to the Flit, counting the number of FEC symbol errors, and determining, as a Flit error, those in which the number of FEC symbol errors exceeds the threshold value; and a step of instructing, by a synchronization state management unit 46 of the error detector, reacquisition of the pattern start of the Flit pattern when the amount of error in a portion corresponding to the Flit detected by the error detection unit exceeds a synchronization condition threshold value.

[0016] The error rate measurement method according to claim 7 of the present invention is the error rate measurement method according to claim 6, including a step of selecting and setting, at the operation unit, whether to mask a bit error in a corresponding portion or filter and remove the SKP OS itself when the portion corresponding to the SKP OS is excluded from the measurement target.

[0017] The error rate measurement method according to claim 8 of the present invention is the error rate measurement method according to claim 6, wherein For the part corresponding to the Flit, whether there is no decoding of the High-speed bus standard or there is decoding of the High-speed bus standard is selected and set in the selection part. Select It is characterized by including a step of

[0018] The error rate measurement method according to claim 9 of the present invention is the error rate measurement method according to any one of claims 6 to 8, wherein Link training is performed with the object to be measured, and the LTSSM of the object to be measured is transitioned to a loopback state.

[0019] The error rate measurement method according to claim 10 of the present invention includes one cycle of a Flit pattern including EIEOS and SKP OS corresponding to the number of lanes defined by the high-speed bus standard, a Flit length corresponding to the number of lanes, a threshold value for discriminating a Flit error, an insertion period of the EIEOS, and setting the pattern start of the Flit pattern at the operation unit 2, generating a PAM4 signal based on the bit string data of the Flit pattern by a pattern generator 3 and transmitting it to the object to be measured W in a loopback state, receiving, by an error detection unit 44 of an error detector 4, a PAM4 signal based on the bit string data of the Flit pattern transmitted back from the object to be measured in the loopback state, and detecting and counting an error in the part corresponding to the Flit by excluding the parts corresponding to the EIEOS and the SKP OS of the received PAM4 signal from the measurement target, detecting and counting the number of FEC symbol errors for each ECC Group in the part corresponding to the Flit by a Flit error detection unit 45 of the error detector, and determining that a Flit error occurs when the number of FEC symbol errors exceeds the threshold value, When the amount of errors in the portion corresponding to the Flit detected by the error detector exceeds the synchronization condition threshold by the synchronization state management unit 46 of the error detector, a step of instructing reacquisition of the pattern start of the Flit pattern; When the portion corresponding to the SKP OS is excluded from the measurement target, a step of selecting and setting by the operation unit whether to mask the bit error of the corresponding portion or filter and remove the SKP OS itself; Regarding the portion corresponding to the Flit, High-speed bus standard Whether there is no decoding release of High-speed bus standard or there is decoding release of Select is selected and set by the selection unit; performing link training with the object to be measured and transitioning the LTSSM of the object to be measured to the loopback state, characterized by including.

Advantages of the Invention

[0020] According to the present invention, without setting the object to be measured to the L0 state, the same Flit pattern as in the L0 state can be used, and the relationship between bit errors and Flit errors can be correctly grasped. Also, it is possible to identify the pattern guarded by FEC and determine whether it becomes uncorrectable even in an environment where patterns guarded by FEC and patterns not guarded by FEC are mixed.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0022] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

[0023] As shown in FIG. 1, the error rate measurement device 1 of the present embodiment uses a device that transitions to a loopback state in link training as a device under test (DUT), and in the error measurement of the physical layer of the PCI Express 6.0 (hereinafter referred to as PCIe Gen6) standard as a high-speed bus standard, it has a function of simultaneously measuring not only bit errors but also Flit errors (whether the FEC of Flit becomes uncorrectable) using the Flit pattern, and is schematically configured with an operation unit 2, a pattern generator 3, and an error detector 4.

[0024] Note that in the PCIe Gen6 standard targeted by this embodiment, the signals to be handled are PAM4 signals. Also, although the concept of Flit was defined starting from PCIe Gen6, the present invention can also be applied to future PCI Express standards using a similar concept of Flit. Furthermore, in this embodiment, PCIe Gen6 is exemplified for explanation, but the present invention can also be applied when measuring Flit errors in other high-speed bus standards such as USB, for example.

[0025] [Regarding Flit] First, the Flit defined in the PCIe Gen6 standard handled by the error rate measurement device 1 of this embodiment will be described with reference to FIGS. 3 and 4. Flit is a data format transmitted when the state of the LTSSM (Link Training and Status State Machine) is L0 in the PCIe Gen6 standard, and has an error correction function by FEC.

[0026] As shown in FIG. 3, 1 Flit is interleaved by three ECC Groups (ECC Group0, ECC Group1, ECC Group2). One ECC Group is delimited by 1 FEC symbol (4 PAM4 symbols = 8 bits).

[0027] Summarizing the conditions for a Flit to become Uncorrectable, it becomes Uncorrectable when FEC symbol errors occur twice in the same ECC Group within 1 Flit.

[0028] A further description will be given with reference to FIG. 4. FIG. 4 shows an example of the number of Flits for each ECC Group of Flits, the number of uncorrectable Flits (2 or more), and the number of FEC symbol errors (0 to 7, 8 or more) in a Flit. In FIG. 4, the portion indicated by the downward diagonal lines represents the portion that becomes uncorrectable, and the portion indicated by the upward diagonal lines represents the portion that may or may not become uncorrectable.

[0029] For example, taking the case where the FEC symbol error threshold: n ≥ 2 as an example, an explanation will be given with reference to FIG. 4. In A (number of Flits: 3) surrounded by the dotted line in FIG. 4, 2 FEC symbol errors have occurred in the Flit, but since the number of errors in each ECC Group (in this case, ECC Group0 and ECC Group1) is 1 each, it does not become uncorrectable.

[0030] On the other hand, in B (number of Flits: 5) surrounded by the dotted line in FIG. 4, not only 4 FEC symbol errors have occurred in the Flit, but also when looking at the number of errors for each ECC Group, the number of errors in one of the ECC Groups (in this case, ECC Group0) is 2, so it becomes uncorrectable.

[0031] Also, in C (number of Flits: 9) surrounded by the dotted line in FIG. 4, 2 FEC symbol errors have occurred in the Flit, and the number of errors in the same ECC Group (in this case, ECC Group0) is 2, so it becomes uncorrectable.

[0032] Thus, in PCIe Gen6, a new Flit mode has been introduced. The Flit has a 256 FEC symbol length (1 FEC symbol = 8 bits) and has an error correction function by FEC. Also, since the Flit in Gen6 is 1b / 1b encoded, 1 FEC symbol is also 1b / 1b symbol. The FEC of the Flit is 3-way interleaved ECC, and each ECC Group can correct single-bit errors (errors in 1 FEC symbol).

[0033] And in 1 Flit, errors up to 3 FEC symbols can be corrected. If the error cannot be corrected, it becomes a Flit error (ECC is Uncorrectable). However, even with 3 FEC symbol errors, depending on the occurrence situation of the error position, it may become uncorrectable. For example, if the symbol 0 of ECC Group0, the symbol 1 of ECC Group1, and the symbol 2 of ECC Group2 are in error, it can be corrected, but if the symbol 0, 3, 6 of the same ECC Group0 are in error, it becomes uncorrectable. This means that even with the same bit error rate, the number of Flit errors varies depending on the occurrence position of the bit error.

[0034] [Regarding the Summary of the Invention] As shown in FIG. 5(a), the error rate measuring device 1 uses a Flit pattern with EIEOS inserted periodically as a pattern to be transmitted after setting the object under measurement W in a loopback state by link training, and measures errors (bit errors, PAM4 symbol errors, FEC symbol errors) and Flit errors simultaneously. At this time, the pattern at the SKP OS (SKP Ordered Sets, hereinafter abbreviated as SKP: illustrated as "SKP" in the drawing) position is masked, and further, the pattern at the EIEOS position is masked so as not to be a measurement target, and errors (bit errors, PAM4 symbol errors, FEC symbol errors) only in the Flit part are counted. Also, for the Flit part, the FEC symbol errors for each ECC Group are counted, and those with the number of FEC symbol errors exceeding the FEC symbol error threshold are determined as Flit errors.

[0035] When performing the above error measurement, the operation unit 2 can select two methods for excluding the part corresponding to SKP from the measurement target: a method of masking the bit errors in the corresponding part and a method of filtering and removing SKP itself. Also, for the part corresponding to Flit, the operation unit 2 can select whether to perform uncoding of PCIe Gen6 or not, and it is possible to confirm the occurrence condition of errors depending on whether uncoding is performed or not.

[0036] Note that the influence of inserting EIEOS can be almost ignored by making the lengths of the Flit and SKP parts sufficiently longer than the EIEOS length. The method of determining the EIEOS insertion period, that is, the pattern length L [bit], is as follows.

[0037] The SKP insertion interval t [Flit] is defined by the PCIe Gen6 standard. Also, since the Flit is scrambled by LFSR: G(X) = X^23 + X^21 + X^16 + X^8 + X^5 + X^2 + 1, the EIEOS period is ensured to be LFSR_L = 2^23 - 1 = 8,388,607 [bit] or longer. If it is less than this, values that do not appear in the scrambled value will appear.

[0038] Therefore, the least common multiple LCM_LFSR_Flit of the scramble length LFSR_L [bit] and the flit length Flit_L [bit] is obtained (Equation (1) below).

[0039] LCM(LFSR_L, Flit_L) = LCM_LFSR_Flit... Equation (1)

[0040] From this, the number of flits LCM_Flit [flit] reaching the LCM is expressed as in Equation (2) below.

[0041] LCM_Flit = LCM_LFSR_Flit / Flit_L... Equation (2)

[0042] Next, the number of SKPs LCM_skp_t (rounded up to an integer) that is equal to or greater than the LFSR is expressed as in Equation (3) below. Here, ceil() represents the number obtained by rounding up the decimal part of a positive number.

[0043] LCM_skp_t = ceil(LCM_Flit / t)... Equation (3)

[0044] Also, the number of flits Flit_1fsr_t [flit] that makes one or more rounds of the LFSR can be obtained by Equation (4) below.

[0045] Flit_1fsr_t = t × LCM_skp_t... Equation (4)

[0046] Here, since it is necessary to insert SKPs periodically, if one pair of flit and SKP has a flit period length Flit_size [bit], it is expressed as in Equation (5) below.

[0047] Flit_size [bit] = SKP_L + t × Flit_L... Equation (5)

[0048] Note that SKP_L is the pattern length [bit] of the SKP.

[0049] Therefore, the pattern length L [bit] can be obtained by the following formula (6).

[0050] L [bit] = EIEOS length [bit] + (LCM_skp_t × Flit_size) × n [bit] (n is an integer of 1 or more) … Formula (6)

[0051] The number of Flits included in this pattern length L [bit] is given by Formula (4) × n.

[0052] The EIEOS length is 128 bits, and if n is made large, the EIEOS in the pattern length L [bit] can be almost ignored.

[0053] In the PCIe Gen6 standard, even if the physical layer meets the bit error performance index, Flit errors may occur under stress conditions. In contrast, by simultaneously measuring bit errors and Flit errors, the correlation between bit errors and Flit errors can be clarified, and it is possible to know whether a Flit error will occur.

[0054] Also, a Flit carries user data in the Transaction Layer. When a Flit error occurs, it is recovered by retransmitting the user data. However, if this occurs frequently, communication cannot be performed at the original bandwidth of PCIe Gen6. In contrast, by simultaneously performing bit error measurement and Flit error measurement, it becomes possible to accurately grasp the throughput performance when using user data, that is, whether the original bandwidth of PCIe Gen6 is being used.

[0055] [Regarding the configuration of each part of the error rate measurement device] The operation unit 2 also functions as a setting means and a display means, and is composed of a user interface such as, for example, an operation knob, various keys, switches, buttons provided in the main body of the error rate measurement device 1 in FIG. 1, and soft keys on the display screen of the display means. It performs various settings, instructions, and displays of measurement results according to the user's operations.

[0056] The setting contents set in the operation unit 2 include one cycle of the Flit pattern (including EIEOS and SKP) according to the number of lanes, the Flit length according to the number of lanes, the mask pattern length for masking the part corresponding to SKP, the mask pattern period corresponding to the repetition period of SKP, the threshold value for discriminating Flit errors, the mask pattern length for masking the part corresponding to EIEOS, the insertion period of EIEOS, and the setting of the pattern start of the Flit pattern. In addition, in the operation unit 2, as a method of excluding SKP from the measurement target, either a method of masking the bit error of the corresponding part or a method of filtering and removing SKP itself can be selected, and for the Flit part, either without decoding of PCIe Gen6 coding or with decoding of PCIe Gen6 coding can be selected.

[0057] The pattern generator 3 generates a Flit error measurement pattern according to an instruction from the operation unit 2. As shown in FIG. 1, it includes a first selection unit 11, a first sequence generation unit 12, a second sequence generation unit 13, a measurement pattern generation unit 14, a first encoder 15, a second encoder 16, a second selection unit 17, a bit splitting unit 18, and a PAM4 encoder 19.

[0058] The first selection unit 11 selects any one of the transmission completion signals from the first sequence generation unit 12, the second sequence generation unit 13, and the measurement pattern generation unit 14 according to the Link Speed and outputs it to the LTSSM36.

[0059] The first sequence generation unit 12 selectively generates training sequences (TSx OS) such as TS1, TS2, EIEOS, and SKP used in PCIe Gen1-2, and training sequences (TSx OS) such as TS1, TS2, EIEOS, and SKP used in PCIe Gen3-5.

[0060] The second sequence generation unit 13 generates training sequences (TSx OS) such as TS0, TS1, TS2, EIEOS, and SKP used in PCIe Gen6.

[0061] The measurement pattern generation unit 14 generates a Flit pattern (pattern (including EIEOS, SKP) calculated by Expression (6)) corresponding to the number of lanes set by the operation unit 2 as a pattern that serves as the basis for the Flit error measurement pattern to be transmitted to the object under measurement W.

[0062] The first encoder 15 is composed of an 8b / 10b encoder and a 128b / 130b encoder. The 8b / 10b encoder performs 8b / 10b encoding used in PCIe Gen1-2 on the training sequence generated by the first sequence generation unit 12. The 128b / 130b encoder performs 128b / 130b encoding used in PCIe Gen3-5 on the training sequence generated by the first sequence generation unit 12.

[0063] The second encoder 16 performs 1b / 1b encoding used in PCIe Gen6 on the training sequence generated by the second sequence generation unit 13.

[0064] The second selection unit 17 selects output data from any one of the measurement pattern generation unit 14, the first encoder 15, and the second encoder 16 according to the LTSSM state and Link Speed from the LTSSM 36.

[0065] The bit splitting unit 18 distributes the input signal into the most significant bit string data (hereinafter referred to as MSB data) and the least significant bit string data (hereinafter referred to as LSB data) according to the Link Speed instructed by the LTSSM 36. In PCIe Gen1-5, the same signal is output to the MSB data and the LSB data so as to be NRZ, and in PCIe Gen6, the input signal is bit-interleaved so as to be a PAM4 signal and output to the MSB data and the LSB data.

[0066] The PAM4 encoder 19 PAM4-encodes the MSB data and the LSB data split by the bit splitting unit 18, and outputs the PAM4-encoded PAM4 signal as a Flit error measurement pattern.

[0067] When the Flit error measurement pattern (PAM4 signal) is transmitted from the pattern generator 3 to the object under test W, the error detector 4 receives the Flit error measurement pattern (PAM4 signal) folded back from the object under test W that has transitioned to the loopback state by link training and detects an error. As shown in FIG. 2, it includes a PAM4 decoder 21, a bit synthesis unit 22, a first synchronization unit 23, a first SKP filter unit 24, a processing circuit 25, a first scrambling analysis unit 26, a second synchronization unit 27, a second SKP filter unit 28, a Precoding decoder 29, a first delay unit 30, a first selection unit 31, a Graycoding decoder 32, a second delay unit 33, a second selection unit 34, a second scrambling analysis unit 35, an LTSSM 36, a third selection unit 37, a bit splitting unit 38, a synchronization pattern detection unit 39, a reference pattern generation unit 40, a symbol mask generation unit 41, a third delay unit 42, a fourth delay unit 43, an error detection unit 44, a Flit error detection unit 45, and a synchronization state management unit 46.

[0068] The PAM4 decoder 21 decodes and separates the PAM4 symbols of the Flit error measurement pattern (PAM4 signal) received from the object under test W into MSB data and LSB data.

[0069] The bit synthesis unit 22 synthesizes the MSB data and LSB data decoded by the PAM4 decoder 21 using a bit MUX and outputs them to the first synchronization unit 23 and the second synchronization unit 27.

[0070] The first synchronization unit 23, the first SKP filter unit 24, the processing circuit 25, and the first scrambling analysis unit 26 are circuits corresponding to PCIe Gen1-5.

[0071] The first synchronization unit 23 is composed of an 8b / 10b synchronization unit and a 128b / 130b synchronization unit. The 8b / 10b synchronization unit finds the comma pattern of PCIe Gen1-2 from the data synthesized by the bit synthesis unit 22, performs symbol synchronization at 10-bit intervals, aligns the input data at the symbol boundary, and outputs it. Here, the comma pattern is composed of 7 bits of Comma+(0011111) or Comma-(1100000), which is a single pattern when looking at 7 consecutive bits in the pattern after 8b / 10b encoding. Since this pattern does not appear beyond the 10-bit boundary without bit errors, it is used to find the 10-bit interval. Also, the 128b / 130b synchronization unit finds the EIEOS pattern of PCIe Gen3-5 from the data synthesized by the bit synthesis unit 22, performs symbol synchronization at 130-bit intervals, aligns the input data at the symbol boundary, and outputs it.

[0072] The first SKP filter unit 24 identifies the SKP of PCIe Gen1-5 from the input bit sequence from the first synchronization unit 23 and removes the SKP from the input bit sequence.

[0073] The processing circuit 25 is configured to include an 8b / 10b decoder, a 128b / 130b decoder, a Precoding decoder, a delay circuit, and a selection circuit. The 8b / 10b decoder is a decoder that performs 8b / 10b code conversion used in PCIe Gen1-2, and converts the input bit sequence of the 10-bit symbol from which SKP has been removed by the first SKP filter section 24 into an 8-bit symbol. The 128b / 130b decoder is a decoder that performs 128b / 130b code conversion used in PCIe Gen3-5, and converts the input bit sequence of the 130-bit symbol from which SKP has been removed by the first SKP filter section 24 into a 128-bit symbol. The Precoding decoder is a decoder for canceling the Precoding of PCIe Gen5 in the data decoded by the 128b / 130b decoder. The delay circuit has the same delay amount as the processing time of the Precoding decoder, and outputs the data from the 128b / 130b decoder in the same phase as the Precoding decoder. The selection circuit selects the output of either the Precoding decoder or the delay circuit according to the instruction of the LTSSM 36.

[0074] The first descrambling analysis section 26 is composed of a descrambler for canceling the scrambling applied in PCIe Gen1-2 and a descrambler for canceling the scrambling applied in PCIe Gen3-5 for the data from the processing circuit 25.

[0075] When the second synchronization section 27 finds the EIEOS pattern of PCIe Gen6 from the data synthesized by the bit synthesis section 22, it takes 1b / 1b symbol synchronization at 8-bit intervals, aligns the input data at the symbol boundary, and outputs it.

[0076] The second SKP filter section 28 identifies the SKP of PCIe Gen6 from the input bit sequence from the second synchronization section 27, and removes the SKP from the input bit sequence.

[0077] The Precoding decoder 29 is a decoder for canceling the Precoding of PCIe Gen6 for the input bit sequence from which the SKP has been removed by the second SKP filter section 28.

[0078] The first delay section 30 has the same delay amount as the processing time of the Precoding decoder 29, and outputs the data from the second SKP filter section 28 in the same phase as the Precoding decoder 29.

[0079] The first selection section 31 selects the output of either the Precoding decoder 29 or the first delay section 30 according to the instruction of the LTSSM 36.

[0080] The Graycoding decoder 32 is a decoder for canceling the Graycoding of PCIe Gen6 for the input bit sequence selected by the first selection section 31.

[0081] The second delay section 33 has the same delay amount as the processing time of the Graycoding decoder 32, and outputs the input bit sequence selected by the first selection section 31 in the same phase as the Graycoding decoder 32.

[0082] The second selection section 34 selects the output of either the Graycoding decoder 32 or the second delay section 33 according to the instruction of the LTSSM 36.

[0083] The second descrambling analysis section 35 is a descrambler for canceling the scrambling applied in PCIe Gen6 for the data selected by the second selection section 34.

[0084] The LTSSM36 is a state machine that analyzes the TS0 (output only from the second scrambling analysis unit 35), the TS1 and TS2 training sequences, the idle symbol, and the idle Flit from the first scrambling analysis unit 26 and the second scrambling analysis unit 35, and advances the LTSSM value (internal state value) and the Link Speed. Further, the LTSSM36 generates a transmission REQ to the pattern generator and manages the transmission pattern by receiving a transmission ACK from the pattern generator.

[0085] The third selection unit 37 is a selector that selects any one of the input raw data from the second synchronization unit 27, the data after SKP removal from the second SKP filter unit 28, and the data after decoding the code after SKP removal from the second scrambling analysis unit 35, that is, the data after Precoding, Graycoding, and scrambling removal, and is selected according to an instruction from the operation unit 2.

[0086] The bit splitting unit 38 splits the data selected and output by the third selection unit 37 into MSB data and LSB data by a bit DMUX and outputs them to the third delay unit 42.

[0087] The synchronization pattern detection unit 39 searches for the same pattern as the pattern start of the Flit pattern set by the operation unit 2 from the data selected and output by the third selection unit 37 and outputs a pattern start signal.

[0088] The reference pattern generation unit 40 generates an MSB reference pattern and an LSB reference pattern based on the Flit pattern (pattern (including EIEOS, SKP) calculated by Equation (6)) corresponding to the number of lanes set by the operation unit 2, using the pattern start signal from the synchronization pattern detection unit 39 as a trigger.

[0089] The symbol mask generation unit 41 generates a mask pattern in units of 1b / 1b symbols for whether to distinguish the input patterns of MSB data and LSB data from the Flit region or to distinguish them from the SKP region and the EIEOS region, based on the mask pattern length and mask pattern period set by the operation unit 2, using the pattern start signal from the synchronization pattern detection unit 39 as a trigger. Further, the symbol mask generation unit 41 outputs the mask pattern start signal to the error detection unit 44.

[0090] Note that the Flit pattern of PCIe Gen6 is 1 FEC symbol = 8 bits, and since 1 FEC symbol has bits interleaved between MSB data and LSB data, it becomes a mask in units of 4PAM4 symbols. In this embodiment, 0 represents the Flit region, 1 represents the EIEOS region, and the SKP region. The mask pattern corresponding to FIG. 5(a) is calculated in advance by the setting operation of the operation unit 2 and set in the internal memory of the symbol mask generation unit 41. Note that when the data after SKP removal from the second SKP filter unit 28 or the data with SKP removed from the second scrambling analysis unit 35 and the PCIe Gen6 code released is selected by the third selection unit 37, the data input to the error detection unit 44 has SKP removed, so a pattern without a mask for the SKP region is set (a mask pattern for distinguishing the EIEOS region is set).

[0091] The third delay unit 42 delays the MSB data and LSB data by a predetermined time so that the MSB data, LSB data, pattern start signal, MSB reference pattern, LSB reference pattern, mask pattern, and mask pattern start signal input to the error detection unit 44 are in the same phase, and inputs them to the error detection unit 44.

[0092] The fourth delay unit 43 delays the pattern start signal by a predetermined time so that the MSB data, LSB data, pattern start signal, MSB reference pattern, LSB reference pattern, mask pattern, and mask pattern start signal input to the error detection unit 44 are in the same phase, and inputs them to the error detection unit 44.

[0093] The error detection unit 44 uses the MSB data and LSB data according to the Flit pattern, the pattern start signal, the MSB reference pattern, the LSB reference pattern, the mask pattern, and the mask pattern start signal to detect and count bit errors (MSB bit errors, LSB bit errors), detect and count PAM4 symbol errors, detect and count FEC symbol errors, and outputs the count results to the operation unit 2.

[0094] Here, FIG. 6 shows an example of a timing chart of various error detections by the error detection unit 44 of the error rate measurement device 1. FIG. 6 is an example of a timing chart when a PAM4 signal based on the bit string data of the Flit pattern is transmitted to the object under measurement W.

[0095] Taking the case where attention is paid to the CLK positions 1 to 36 after the input of the mask pattern start signal in FIG. 6 as an example, in this case, each bit of the MSB (corresponding to the MSB data according to the Flit pattern) of the input Flit pattern is compared with the corresponding bit of the MSB (corresponding to the MSB reference pattern) of the reference Flit pattern, and each bit of the LSB (corresponding to the LSB data according to the Flit pattern) of the input Flit pattern is compared with the corresponding bit of the LSB (corresponding to the LSB reference pattern) of the reference Flit pattern.

[0096] As a result, the error results in the Flit region (mask signal is 0) are that the MSB bit error is "0", "1", "0", "1", "1", "0", "1", "1", "0", "0", "0", "0", "1", "1", "0", "1", "1", "1", "1", "1", the LSB bit error is "1", "0", "0", "0", "1", "0", "1", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", the PAM4 symbol error is "1", "1", "0", "1", "1", "0", "1", "1", "0", "0", "0", "0", "1", "1", "0", "1", "1", "1", "1", "1", and the FEC symbol error is "1", "1", "0", "1", "1".

[0097] In contrast, the error results in the EIEOS and SKP regions (mask signal is 1) are that the MSB bit error is "0", "1", "0", "1", "0", "1", "0", "1", "0", "0", "0", "0", "1", "1", "0", "0", the LSB bit error is "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", the PAM4 symbol error is "1", "1", "1", "1", "0", "1", "0", "1", "0", "0", "0", "0", "1", "1", "0", "0", and the FEC symbol error is "1", "1", "0", "1".

[0098] Note that the error detection unit 44 aligns the mask pattern and the mask pattern start signal input from the symbol mask generation unit 41 with the error detection result and phase in units of FEC symbols, and outputs them to the Flit error detection unit 45 together with the error detection result in units of FEC symbols. Here, instead of the mask pattern start from the symbol mask generation unit 41, the pattern start signal from the fourth delay unit 43 may be used.

[0099] The Flit error detection unit 45 uses a mask pattern to detect and count FEC symbol errors by separating the Flit area (where the mask signal is 0) and the EIEOS and SKP areas (where the mask signal is 1).

[0100] Also, the Flit error detection unit 45 detects and counts whether the number of FEC symbol errors within any ECC Group exceeds the FEC symbol error threshold set by the operation unit 2 in one Flit length, and outputs the count result to the operation unit 2.

[0101] Note that capture etc. can also be performed using the detection result of the Flit error detection unit 45.

[0102] The synchronization state management unit 46 notifies the operation unit 2 of synchronization establishment when the amount of errors in the part corresponding to Flit is below the synchronization condition threshold based on the error number information based on the error detection result of the error detection unit 44. Also, the synchronization state management unit 46 notifies the operation unit 2 of non - synchronization establishment when the amount of errors in the part corresponding to Flit exceeds the synchronization condition threshold based on the error number information based on the error detection result of the error detection unit 44, and instructs the Flit pattern detection unit 39 to reacquire (re - search for the pattern start) the start of the Flit pattern. Note that the notification destination of synchronization establishment or non - synchronization establishment is not limited to the operation unit 2. For example, it may be an external terminal device, and the user can also be notified by message display or voice etc.

[0103] Next, the internal configuration of the Flit error detection unit 45 in FIG. 2 will be described with reference to FIG. 7.

[0104] As shown in FIG. 7, the Flit error detection unit 45 includes a Flit length timing counter 45a, an ECC Group timing counter 45b, a first ECC Group error detection unit 45c, a second ECC Group error detection unit 45d, a third ECC Group error detection unit 45e, a first ECC Group error count unit 45f, a second ECC Group error count unit 45g, a third ECC Group error count unit 45h, a comparison unit 45i, and a Flit error count unit 45j.

[0105] The Flit length timing counter 45a counts the Flit length set by the operation unit 2 with the mask pattern start signal as a trigger. The counter counts up when the mask pattern is in the Flit area (mask signal is 0), and when it reaches the Flit length, it repeats counting from 0.

[0106] The ECC Group timing counter 45b is a counter used to distinguish ECC Groups, and is a counter that outputs the remainder obtained by dividing the Flit length timing counter value by 3.

[0107] The first ECC Group error detection unit 45c detects an FEC symbol error when the counter value of the ECC Group timing counter 45b is 0 and the mask pattern is in the Flit area (mask signal is 0).

[0108] The first ECC Group error count unit 45f counts the number of FEC symbol errors in a 1 Flit length interval detected by the first ECC Group error detection unit 45c for each Flit length interval.

[0109] The second ECC Group error detection unit 45d detects an FEC symbol error when the counter value of the ECC Group timing counter 45b is 1 and the mask pattern is in the Flit area (mask signal is 0).

[0110] The second ECC Group error count unit 45g counts the number of FEC symbol errors in a 1-Flit length interval detected by the second ECC Group error detection unit 45d for each Flit length interval.

[0111] The third ECC Group error detection unit 45e detects FEC symbol errors where the counter value of the ECC Group timing counter 45b is 2 and the mask pattern is in the Flit area (mask signal is 0).

[0112] The third ECC Group error count unit 45h counts the number of FEC symbol errors in a 1-Flit length interval detected by the third ECC Group error detection unit 45e for each Flit length interval.

[0113] The comparison unit 45i compares the number of FEC symbol errors in a 1-Flit length interval with the FEC symbol error threshold value: n set by the operation unit 2, and when there is an ECC Group where the number of FEC symbol errors in a 1-Flit length interval exceeds the FEC symbol error threshold value: n, it outputs a Flit error detection signal to the Flit error count unit 45j.

[0114] The Flit error count unit 45j counts the Flit error detection signal from the comparison unit 45i and outputs the count result (Flit error count value) to the operation unit 2.

[0115] Here, FIG. 8 shows an example of a timing chart of FEC symbol error detection for each ECC Group by the Flit error detection unit 45 of the error rate measurement device 1. In this example, it is assumed that the Flit length is 8 symbols and the FEC symbol error threshold value n is set to 3 symbols.

[0116] Focusing on the Flit regions at CLK positions 0 to 15 in Fig. 8, the FEC symbol errors "1", "1", "1", "1", "0", "0", "0", "0", "1", "1", "1", "1", "0", "0", "1", "0" are input. The number of FEC symbol errors in ECC Group0 for every 4PAM4 symbols = 8 bits within the Flit region is "2", "3", the number of FEC symbol errors in ECC Group1 is "1", "1", and the number of FEC symbol errors in ECC Group2 is "1", "1". And the number of FEC symbol errors in ECC Group0 in the Flit region at CLK positions 8 to 15 is "3", and since the FEC symbol error threshold: n = "3" or more, Flit error 1 is output as the error result.

[0117] Note that the CLK positions 16 to 20 and 37 to 41 in the SKP region of Fig. 8 are masked by the mask pattern, so error detection and counting are not performed.

[0118] Next, the processing operation during error measurement of the PCIe Gen6 physical layer by the error rate measurement device 1 with the above configuration will be described with reference to the flowchart in Fig. 9. When performing error measurement of the PCIe Gen6 physical layer, it is assumed that the error rate measurement device 1 operates normally up to PCIe Gen1 - 5, and the object under measurement W has transitioned to the Gen6 loopback state through link training.

[0119] First, a PAM4 signal based on the bit - string data of the Flit is generated from the pattern generator 3 and transmitted to the object under measurement W in the Gen6 loopback state (ST1).

[0120] Then, the error detector 4 receives the PAM4 signal folded back from the object under measurement W along with the transmission of the PAM4 signal from the pattern generator 3 to the object under measurement W, and divides the received PAM4 signal into MSB data and LSB data by the PAM4 decoder 21 (ST2). The MSB data and LSB data divided by this PAM4 decoder 21 are bit - multiplexed by the bit synthesis unit 22 and output to the second synchronization unit 27.

[0121] Then, when the second synchronization unit 27 finds the PCIe Gen6 EIEOS pattern from the data synthesized by the bit synthesis unit 22, it takes 1b / 1b symbol synchronization at 8-bit intervals, aligns the input data at symbol boundaries, and outputs it to the second SKP filter unit 28 and the third selection unit 37 (ST3).

[0122] Subsequently, the synchronization pattern detection unit 39 searches for the same pattern as the pattern start of the Flit pattern set by the operation unit 2 from the data selected by the third selection unit 37 (any of the data from the second synchronization unit 27, the data from the second SKP filter unit 28, and the data from the second descrambling analysis unit 35) and outputs a pattern start signal (ST4).

[0123] Here, when selecting data in the above-mentioned third selection unit 37, the following processing is executed. First, the second SKP filter unit 28 removes SKP from the input bit string from the second synchronization unit 27 and outputs it to the Precoding decoder 29, the first delay unit 30, and the third selection unit 37. Then, the Precoding decoder 29 releases the PCIe Gen6 Precoding from the input bit string from which SKP has been removed and outputs it to the first selection unit 31. Also, the first delay unit 30 outputs the input bit string from the second SKP filter unit 28 to the first selection unit 31 in the same phase as the Precoding decoder 29. Then, in the first selection unit 31, according to the instruction of the LTSSM 36, the output of either the Precoding decoder 29 or the first delay unit 30 is selected and input to the Graycoding decoder 32 and the second delay unit 33.

[0124] Subsequently, the Gray coding decoder 32 decodes the Gray coding of PCIe Gen6 for the input bit string selected by the first selection unit 31 and outputs it to the second selection unit 34. Further, the second delay unit 33 outputs the input bit string from the first selection unit 31 to the second selection unit 34 in the same phase as the Gray coding decoder 32. Then, in the second selection unit 34, according to the instruction of the LTSSM 36, the output of either the Gray coding decoder 32 or the second delay unit 33 is selected and input to the second descrambling analysis unit 35. Furthermore, the second descrambling analysis unit 35 descrambles the scrambling applied by PCIe Gen6 from the data selected by the second selection unit 34 and outputs it to the LTSSM 36 and the third selection unit 37.

[0125] Then, the reference pattern generation unit 40 generates an MSB reference pattern and an LSB reference pattern based on the pattern obtained by Expression (6) using the pattern start signal from the synchronization pattern detection unit 39 as a trigger (ST5).

[0126] Also, the symbol mask generation unit 41 generates a symbol mask pattern based on the mask pattern length and mask pattern period set by the operation unit 2 using the pattern start signal from the synchronization pattern detection unit 39 as a trigger (ST6).

[0127] Then, the error detection unit 44 uses the MSB data and LSB data according to the Flit pattern, the pattern start signal, the MSB reference pattern, the LSB reference pattern, the mask pattern, and the mask pattern start signal to detect and count bit errors, detect and count PAM4 symbol errors, and detect and count FEC symbol errors (ST7). The count result at this time is output to the operation unit 2. At this time, when the amount of error in the portion corresponding to the Flit detected by the error detection unit 44 is below the synchronization condition threshold, the synchronization state management unit 46 notifies the operation unit 2 of the establishment of synchronization. On the contrary, when the amount of error in the portion corresponding to the Flit detected by the error detection unit 44 exceeds the synchronization condition threshold, the synchronization state management unit 46 notifies the operation unit 2 of the non-establishment of synchronization, and instructs the synchronization pattern detection unit 39 to reacquire (re-search for the pattern start) the pattern start of the Flit pattern.

[0128] Also, the Flit error detection unit 45 detects and counts whether the number of FEC symbol errors in any ECC Group exceeds the FEC symbol error threshold set by the operation unit 2 within one Flit length (ST8). The count result at this time is output to the operation unit 2.

[0129] As described above, according to the present embodiment, it is possible to use the same Flit pattern as in the L0 state without setting the object to be measured to the L0 state, and correctly grasp the relationship between bit errors and Flit errors. Moreover, since error correction is not performed, the circuit scale can be reduced.

[0130] In addition, it is possible to identify a pattern guarded by FEC and determine whether it becomes uncorrectable even in an environment where patterns guarded by FEC and patterns not guarded by FEC are mixed.

[0131] Furthermore, since the data for error measurement can be selected from the raw input data, the data after SKP removal, and the data after SKP removal and PCIe Gen6 code release, it becomes possible to accurately grasp the occurrence conditions of bit errors and Flit errors due to PCIe Gen6 coding.

[0132] Also, even when the error rate is high and SKP removal is difficult, by enabling the selection of a method to mask the bit errors in the SKP part, it becomes possible to exclude SKP from the measurement target.

[0133] As described above, the best mode of the error rate measurement device and the error rate measurement method according to the present invention has been described, but the present invention is not limited by the description and drawings in this mode. That is, of course, all other modes, examples, operation techniques, etc. made by those skilled in the art based on this mode are included in the scope of the present invention.

Explanation of Signs

[0134] 1 Error rate measurement device 2 Operation unit 3 Pattern generator 4 Error detector 11 First selection unit 12 First sequence generation unit 13 Second sequence generation unit 14 Measurement pattern generation unit 15 First encoder 16 Second encoder 17 Second selection unit 18 Bit division unit 19 PAM4 encoder 21 PAM4 decoder 22 Bit synthesis unit 23 First synchronization unit 24 First SKP filter unit 25 Processing circuit 26 First scrambling analysis unit 27 Second synchronization unit 28 Second SKP filter unit 29 Precoding Decoder 30 First Delay Unit 31 First Selection Unit 32 Graycoding Decoder 33 Second Delay Unit 34 Second Selection Unit 35 Second Scrambling Analysis Unit 36 LTSSM 37 Third Selection Unit 38 Bit Splitting Unit 39 Synchronization Pattern Detection Unit 40 Reference Pattern Generation Unit 41 Symbol Mask Generation Unit 42 Third Delay Unit 43 Fourth Delay Unit 44 Error Detection Unit 45 Flit Error Detection Unit 45a Flit Length Timing Counter 45b ECC Group Timing Counter 45c First ECC Group Error Detection Unit 45d Second ECC Group Error Detection Unit 45e Third ECC Group Error Detection Unit 45f First ECC Group Error Counting Unit 45g Second ECC Group Error Counting Unit 45h Third ECC Group Error Counting Unit 45i Comparison Unit 45j Flit Error Counting Unit 46 Synchronization State Management Unit W Object Under Test

Claims

1. An operation unit (2) that performs operations for setting one cycle of a Flit pattern including an EIEOS and a SKP OS according to the number of lanes defined by a high-speed bus standard, a Flit length according to the number of lanes, a threshold for determining a Flit error, an insertion period of the EIEOS, and a pattern start of the Flit pattern; A pattern generator (3) that generates a PAM4 signal based on the bit string data of the Flit pattern and transmits it to a device under test (W) in a loopback state; An error detector (4) that receives a PAM4 signal based on the bit string data of the Flit pattern transmitted back from the device under test in the loopback state, detects and counts an error in a portion corresponding to the Flit by excluding portions corresponding to the EIEOS and the SKP OS of the received PAM4 signal, a Flit error detector (45) that detects an FEC symbol error for each ECC Group in the portion corresponding to the Flit and counts the number of FEC symbol errors, and determines an FEC symbol error whose number exceeds the threshold as a Flit error, and a synchronization state management unit (46) that instructs reacquisition of the pattern start of the Flit pattern when the amount of error in the portion corresponding to the Flit detected by the error detector exceeds a synchronization condition threshold; An error rate measuring device, characterized by comprising the above.

2. The error rate measuring device according to claim 1, wherein when a portion corresponding to the SKP OS is excluded from measurement targets, the operation unit selectively sets whether to mask a bit error in the corresponding portion or filter and remove the SKP OS itself.

3. The error rate measuring device according to claim 1, wherein for a portion corresponding to the Flit, a selection unit selectively sets whether there is no decoding release of the high-speed bus standard or there is decoding release of the high-speed bus standard.

4. The error rate measuring device according to any one of claims 1 to 3, characterized in that link training is performed with the device under test, and the LTSSM of the device under test is transitioned to a loopback state.

5. One cycle of a Flit pattern including an EIEOS and an SKP OS according to the number of lanes defined by the high-speed bus standard, a Flit length according to the number of lanes, a threshold value for determining a Flit error, an insertion period of the EIEOS, and an operation unit (2) for setting the pattern start of the Flit pattern A pattern generator (3) that generates a PAM4 signal based on the bit string data of the Flit pattern and transmits it to the object under measurement (W) in a loopback state An error detector (4) that receives a PAM4 signal based on the bit string data of the Flit pattern transmitted back from the object under measurement in the loopback state, detects and counts errors in the portion corresponding to the Flit, excluding the portions corresponding to the EIEOS and the SKP OS of the received PAM4 signal; a Flit error detector (45) that detects an FEC symbol error for each ECC Group in the portion corresponding to the Flit and counts the number of FEC symbol errors, and determines a Flit error when the number of FEC symbol errors exceeds the threshold value; and a synchronization state management unit (46) that instructs reacquisition of the pattern start of the Flit pattern when the amount of error in the portion corresponding to the Flit detected by the error detector exceeds a synchronization condition threshold value Comprising When setting the portion corresponding to the SKP OS as out of the measurement target, the operation unit selectively sets whether to mask the bit error in the corresponding portion or filter and remove the SKP OS itself For the portion corresponding to the Flit, a selection unit selectively sets whether there is no decoding of the high-speed bus standard or there is decoding of the high-speed bus standard An error rate measurement device, characterized by performing link training with the object under measurement and transitioning the LTSSM of the object under measurement to a loopback state

6. A step of performing, by an operation unit (2), setting of one cycle of a Flit pattern including an EIEOS and an SKP OS according to the number of lanes defined by the high-speed bus standard, a Flit length according to the number of lanes, a threshold value for determining a Flit error, an insertion period of the EIEOS, and a pattern start of the Flit pattern A step of generating, by a pattern generator (3), a PAM4 signal based on the bit string data of the Flit pattern and transmitting it to the object under measurement (W) in a loopback state The error detection unit (44) of the error detector (4) receives a PAM4 signal based on the bit sequence data of the Flit pattern that is transmitted back from the object under measurement in the loopback state, and detects and counts errors in the portion corresponding to Flit, excluding the portions corresponding to the EIEOS and the SKP OS of the received PAM4 signal. The Flit error detection unit (45) of the error detector detects FEC symbol errors for each ECC Group in the portion corresponding to Flit, counts the number of FEC symbol errors, and determines those with the number of FEC symbol errors exceeding the threshold as Flit errors. When the amount of errors in the portion corresponding to Flit detected by the error detection unit exceeds the synchronization condition threshold by the synchronization state management unit (46) of the error detector, the method includes instructing re-acquisition of the pattern start of the Flit pattern. A method for measuring error rate, characterized by including this.

7. When setting the portion corresponding to the SKP OS as not being a measurement target, the method includes a step of the operation unit selectively setting whether to mask bit errors in the corresponding portion or filter and remove the SKP OS itself. The error rate measurement method according to claim 6, characterized by including this.

8. Regarding the portion corresponding to Flit, the method includes a step of the selection unit selectively setting whether there is no decoding of the high-speed bus standard or there is decoding of the high-speed bus standard. The error rate measurement method according to claim 6, characterized by including this.

9. The method for measuring error rate according to any one of claims 6 to 8 includes performing link training with the object under measurement and transitioning the LTSSM of the object under measurement to the loopback state.

10. Performing, by the operation unit (2), setting of one cycle of the Flit pattern including the EIEOS and the SKP OS corresponding to the number of lanes defined by the high-speed bus standard, the Flit length corresponding to the number of lanes, the threshold for discriminating Flit errors, the insertion period of the EIEOS, and the setting of the pattern start of the Flit pattern. Generating, by the pattern generator (3), a PAM4 signal based on the bit sequence data of the Flit pattern and transmitting it to the object under measurement (W) in the loopback state. The error detector (4) receives a PAM4 signal based on the bit string data of the Flit pattern that is transmitted back from the object under measurement in the loopback state by the error detection unit (44) of the error detector (4), and measures the error of the portion corresponding to Flit by excluding the portions corresponding to the EIEOS and the SKP OS of the received PAM4 signal from the measurement target and counting the error; The Flit error detection unit (45) of the error detector detects the FEC symbol error for each ECC Group of the portion corresponding to Flit, counts the number of FEC symbol errors, and determines that the number of FEC symbol errors exceeding the threshold is a Flit error; When the amount of error of the portion corresponding to Flit detected by the error detection unit exceeds the synchronization condition threshold by the synchronization state management unit (46) of the error detector, the synchronization state management unit instructs to reacquire the pattern start of the Flit pattern; When excluding the portion corresponding to the SKP OS from the measurement target, the operation unit selects and sets whether to mask the bit error of the corresponding portion or filter and remove the SKP OS itself; For the portion corresponding to Flit, the selection unit selects and sets whether there is no decoding of the high-speed bus standard or there is decoding of the high-speed bus standard; A method for measuring an error rate, comprising performing link training with the object under measurement and transitioning the LTSSM of the object under measurement to the loopback state.

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