Touch Sensing Display Device

Abstract

To provide a touch sensing display apparatus improving a touch performance by ensuring a sufficient scan output time for touch sensing.SOLUTION: A touch sensing display apparatus includes a display panel 10 where display driving and touch sensing driving are alternately implemented in cycles of a frame time, a data driving circuit including at least one source driver IC (SDIC), and a gate driving circuit 13 that drives a gate line in the display panel by using a plurality of stages. The gate driving circuit generates a scan signal corresponding to display driving, external compensation driving, and touch sensing driving on the basis of a gate control signal, and supplies the scan signal to a gate line 15. The scan signals include a display scan signal for display driving, a sensing scan signal for external compensation driving, and a touch scan signal for touch sensing driving.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This specification relates to a touch-sensing display device.

Background Art

[0002] Touch sensors are simple, have few malfunctions, and are applied to various display devices for user convenience. A touch-sensing display device can sense touch input while an image is being displayed on the screen by alternately driving a display frame and a touch frame in a time-division manner. Such a touch-sensing display device has a problem in that, since it uses an existing gate driving circuit as it is for time-division driving, the scan output time for touch sensing is insufficient, making it difficult to improve touch performance.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Therefore, the present embodiment is for solving the above-described problems, and provides a touch-sensing display device capable of sufficiently securing a scan output time for touch sensing and improving touch performance.

Means for Solving the Problems

[0004] The touch-sensing display device according to this embodiment includes the display panel in which display driving and touch-sensing driving are alternately implemented at a predetermined cycle; and a gate driving circuit that drives the gate lines of the display panel by using a plurality of stages whose operations are sequentially activated. The plurality of stages are sequentially activated based on a display carrier clock that swings between a gate-on voltage and a gate-off voltage in a display frame, outputs a display scan signal to the display panel, and are sequentially activated based on a touch carrier clock that swings between the gate-on voltage and the gate-off voltage in a touch frame, outputs a touch scan signal to the display panel, and the on-pulse width of the touch carrier clock is narrower than the on-pulse width of the display carrier clock.

[0005] This embodiment can minimize the additional configuration for touch sensing and improve touch sensing performance.

[0006] This embodiment can shorten the transmission time of the carrier signal within the touch frame by designing the on-pulse width of the carrier clock to be even narrower during touch-sensing driving than during display driving. This embodiment can improve touch performance by ensuring a longer time is allocated to the output of the touch scan signal within the touch frame for the amount by which the transmission time of the carrier signal is shortened. The effects according to this specification are not limited by the content exemplified above, and more diverse effects are included in this specification.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals mean substantially the same components.

[0009] In the following description, when it is determined that specific descriptions of known functions and configurations related to the present invention may unnecessarily obscure the gist of the present invention, the detailed descriptions thereof will be omitted.

[0010] The scan signal (or gate signal) applied to the pixel swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. In the case of an N-channel transistor, the gate-on voltage can be a gate high voltage (VGH), and the gate-off voltage can be a gate low voltage (VGL). In the case of a P-channel transistor, the gate-on voltage can be a gate low voltage Vgl, and the gate-off voltage can be a gate high voltage Vgh.

[0011] FIG. 1 is a block diagram showing a touch-sensing display device according to this embodiment. FIG. 2 is a diagram showing a connection configuration of a pixel array and a source driver integrated circuit.

[0012] Referring to FIGS. 1 and 2, the touch-sensing display device according to this embodiment can include a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a sensing circuit SU. The sensing circuit SU can be built in the data driving circuit 12, but is not limited thereto.

[0013] On the screen where the input video is represented by the display panel 10, a first signal line 14 extending in the column (or vertical) direction and a second signal line 15 extending in the row (or horizontal) direction intersect, and pixels P are arranged in a matrix form for each intersection region to form a pixel array. The first signal line 14 can include a data line 14A to which a data voltage is supplied and a reference voltage line 14B to which a reference voltage is supplied. The reference voltage line 14B connects the pixel P and the sensing circuit SU and can also be called a sensing line. The second signal line 15 can be a gate line to which a scan signal is supplied.

[0014] The pixel array includes a number of pixel set lines PL. Here, the pixel set line PL does not mean a physical signal line, but can be defined as a pixel aggregate of one-line component or a pixel block of one-line component arranged adjacent to each other in the horizontal direction. A plurality of pixels P can be grouped to represent various colors. When defining a pixel group for color representation as a unit pixel UPXL, one unit pixel UPXL can also include R (red), G (green), B (blue), and W (white) pixels. The pixels constituting one unit pixel UPXL are arranged adjacent to each other in the horizontal direction and are designed to share the same reference voltage line 14B, so that the pixel array can be simplified.

[0015] Based on the presence or absence of touch input, user mode selection information, and distance information between the display device and the user, etc., the timing controller 11 can switch the driving mode between the touch driving mode and the non-touch driving mode, or vice versa, in the non-touch driving mode. The non-touch driving mode is a driving mode for performing display operation and external compensation operation. The touch driving mode is a driving mode for further performing touch sensing operation in addition to display operation and external compensation operation.

[0016] In the non-touch driving mode, all frames become display frames for display driving. In contrast, in the touch driving mode, display frames for display driving and touch frames for touch sensing driving can be alternately performed at regular time intervals.

[0017] Here, the regular time may be one frame time. In this case, one display frame may be arranged between adjacent touch frames. However, the technical idea of the present invention is not limited thereto. The regular time may be several frame times. In this case, a plurality of display frames may be arranged between adjacent touch frames.

[0018] One frame includes a vertical active section in which new video data DATA is scanned (refreshed or updated) on the display panel 10, and a vertical blank section in which the scanning of the video data DATA is not performed. The display driving is performed in the vertical active section of the display frame, and the touch sensing driving can be performed in the vertical active section of the touch frame. The external compensation driving can be performed in the vertical blank section of each of the display frame and the touch frame. The external compensation driving is for sensing the element characteristic values (threshold voltage and electron mobility of the driving transistor, threshold voltage of the light emitting element, etc.) of the pixel P.

[0019] The timing controller 11 corrects the digital video data input from the host system with a compensation value based on the pixel sensing value by the external compensation driving, and then supplies the corrected video data DATA to the data driving circuit 12. The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data in enable signal DE, and a dot clock DCL from the host system, and can generate a gate timing control signal GDC for controlling the operation timing of the gate driving circuit 13 and a data driving circuit operation timing control signal DDC for the data driving circuit 12.

[0020] The timing controller 11 can compare the touch sensing value obtained by the touch sensing operation with a predetermined reference value to obtain the coordinate information of the touch input position and transmit it to the host system. Then, the host system can execute a touch application corresponding to the coordinate information.

[0021] The data driving circuit 12 includes at least one or more source driver ICs (Integrated Circuits) SDIC. This source driver IC can be provided with a latch array, a number of digital-to-analog converters DAC connected to each data line 14A, a plurality of sensing circuits SU connected to the sensing line 14B, a multiplex switch SS that selectively connects the sensing circuit SU to an analog-to-digital converter ADC, and a shift register SR that sequentially turns on the multiplex switch SS.

[0022] The latch array latches the corrected video data DATA input from the timing controller 11 based on the data control signal DDC and supplies it to the DAC. The DAC can convert the latched video data DATA into a display data voltage and supply it to the data line 14A. The DAC can generate a predetermined external sensing data voltage and supply it to the data line 14A during external compensation driving. The DAC can generate a predetermined touch driving data voltage and supply it to the data line 14A during touch sensing driving.

[0023] The sensing circuit SU is commonly used during both external compensation driving and touch sensing driving, so that a separate touch sensing circuit for touch sensing can be removed. Since touch sensing is possible without a separate touch sensing circuit, the source driver IC is simplified, and power consumption and manufacturing costs can be reduced.

[0024] The sensing circuit SU can supply the reference voltage Vpre to the sensing line 14B based on the data control signal DDC, or sample the element characteristic value sensing value or touch sensing value input through the sensing line 14B and supply it to the ADC.

[0025] The ADC can convert the element characteristic value sensing value or touch sensing value input by the sensing circuit SU into a digital sensing signal SLV and transmit it to the timing controller 11.

[0026] The gate driving circuit 13 generates a scan signal (Figure 3, SCAN) suitable for display driving, external compensation driving, and touch sensing driving based on the gate control signal GDC, and then supplies it to the gate line 15. The scan signal includes a display scan signal for display driving, an external sensing scan signal for external compensation driving, and a touch scan signal for touch sensing driving. The on interval of the display scan signal corresponds to the supply timing of the display data voltage. The on interval of the external sensing scan signal corresponds to the supply timing of the external sensing data voltage. The on interval of the touch scan signal corresponds to the supply timing of the touch driving data voltage.

[0027] The gate control signal GDC includes a plurality of scan clocks and a plurality of carry clocks. The on pulse width of the carry clock is designed to be narrower during touch sensing driving than during display driving, so that the transmission time of the carry signal within the touch frame can be shortened. The shorter the transmission time of the carry signal, the longer the time that can be allocated to the output of the touch scan signal within the touch frame, so that the touch performance can be improved.

[0028] Figure 3 is a diagram showing the connection configuration of one pixel P and the sensing circuit SU.

[0029] Referring to FIG. 3, one pixel P can be implemented with a structure capable of performing an external compensation operation and a touch sensing operation. The pixel P can include a light emitting element OLED, a driving transistor DT, a storage capacitor Cst, a first switch transistor ST1, and a second switch transistor ST2.

[0030] The transistors DT, ST1, and ST2 can be implemented with TFTs (Thin Film Transistors). The TFT can be implemented as a P-type, an N-type, or a hybrid type in which P-type and N-type are mixed. Also, the semiconductor layer of the TFT can include amorphous silicon, polysilicon, or an oxide.

[0031] The light emitting element OLED includes an anode electrode connected to the source node DTS, a cathode electrode connected to the input terminal of the low potential driving voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The organic compound layer can include a hole injection layer (Hole Injection layer, HIL), a hole transport layer (Hole transport layer, HTL), an emission layer (Emission layer, EML), and an electron injection layer (Electron Injection layer, EIL).

[0032] The driving transistor DT controls the magnitude of the drain-source current (hereinafter referred to as Ids) of the driving transistor DT input to the light emitting element OLED by the gate-source voltage (hereinafter referred to as Vgs). The driving transistor DT includes a gate electrode connected to the gate node DTG, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the source node DTS.

[0033] The storage capacitor Cst is connected between the gate node DTG and the source node DTS to maintain the voltage between the gate and source of the driving transistor DT for a predetermined period.

[0034] The first switch transistor ST1 electrically connects the data line 14A and the gate node DTG by a scan signal SCAN from the gate line 15 so that the data voltage Vdata is charged to the gate node DTG. The first switch transistor ST1 includes a gate electrode connected to the gate line 15, a drain electrode connected to the data line 14A, and a source electrode connected to the gate node DTG.

[0035] The second switch transistor ST2 electrically connects the source node DTS and the sensing line 14B by the scan signal SCAN so that the reference voltage Vpre is charged to the source node DTS.

[0036] Then, the second switch transistor ST2 causes the source node voltage corresponding to the Ids of the drive transistor DT to be charged to the line capacitor LCa of the sensing line 14B. The second switch transistor ST2 includes a gate electrode connected to the gate line 15, a drain electrode connected to the sensing line 14B, and a source electrode connected to the source node DTS.

[0037] Referring to FIG. 3, the sensing circuit SU can be realized in a voltage sensing type.

[0038] The sensing circuit SU is for sensing the voltage charged in the line capacitor LCa of the sensing line 14B, and can include a reference voltage control switch SW1, a sampling switch SW2, and a sample and hold section S / H. The reference voltage control switch SW1 is turned on by a reference voltage control signal SPRE to electrically connect the input terminal of the reference voltage Vpre and the sensing line 14B. The sampling switch SW2 is turned on according to a sampling control signal SAM to electrically connect the sensing line 14B and the sample and hold section S / H.

[0039] If the drive transistor DT deteriorates or there is a touch input, the Vgs of the drive transistor DT changes, and thereby the Ids of the drive transistor DT changes. The voltage of the source node DTS of the drive transistor DT changes according to the magnitude of the Ids of the drive transistor DT. While the second switch transistor ST2 is on, the voltage of the source node DTS of the drive transistor DT is charged to the line capacitor LCa of the sensing line 14B. The sample and hold section S / H samples and holds the voltage of the source node DTS of the drive transistor DT charged to the line capacitor LCa of the sensing line 14B while the sampling switch SW2 is on, and then transmits it to the ADC.

[0040] Figures 4 and 5 are diagrams showing the concept for sensing the change in the source node voltage of a pixel due to a touch input.

[0041] The principle of sensing a touch input in the touch sensing display device of this embodiment will be described with reference to FIGS. 4 and 5 as follows.

[0042] When the Vgs of the driving transistor is set to the differential voltage between the touch driving data voltage and the reference voltage, if a touch input object such as a finger touches the screen of the display panel, the Vgs of the driving transistor decreases due to the touch capacitor Ctouch between the touch input object and the driving transistor. The touch capacitor Ctouch is a capacitive capacitor between the gate node DTG of the driving transistor and the touch input object. If the Vgs of the driving transistor decreases, the Ids of the driving transistor also decreases. Therefore, it is possible to determine whether a touch input is possible by changing the source node voltage Vs of the driving transistor between the pixel touched by the touch input object and the pixels that are not. According to the TFT current formula, Ids is proportional to the square of Vgs. Therefore, even if the amount of change in Vgs due to the touch input is small, Ids is amplified and the source node voltage Vs changes rapidly, so the touch sensing performance can be improved. On the other hand, in FIG. 5, "Vg" is the gate node voltage of the driving transistor.

[0043] FIG. 6 is a diagram showing a cross-sectional structure of a representative pixel capable of touch sensing.

[0044] Since the area touched by the touch input object is much larger than the area occupied by one pixel, the touch sensing device of this embodiment can shorten the touch sensing cycle and improve the touch report rate by sensing the touch input only for some pixels (hereinafter, representative pixels) of the display panel.

[0045] Referring to FIG. 6, the representative pixel P includes a light emitting portion EP where an image is displayed and a circuit portion CP where an image is not displayed. The light emitting portion EP of the representative pixel P includes the light emitting element OLED of FIG. 3. The circuit portion CP of the representative pixel P includes the driving transistor DT, the storage capacitor Cst, the first switch transistor ST1, and the second switch transistor ST2 of FIG. 3.

[0046] The circuit portion CP of the representative pixel P can be composed of conductive patterns M1, M2, PXL and insulating layers BUF, GI, OC laminated on the substrate GLS as shown in FIG. 6. The greater the change in Vgs of the driving transistor during touch input, the higher the touch sensing performance. For this purpose, it is desirable that the gate node connected to the gate electrode of the driving transistor is located closer to the substrate GLS than the source node connected to the source electrode of the driving transistor. This improves the responsiveness to touch input. On the other hand, since the source node of the driving transistor is connected to the internal capacitor of the light emitting element, when the source node is located closer to the substrate GLS than the gate node, the change in Vgs corresponding to the touch input (i.e., the responsiveness to the touch input) is very small and not suitable for touch sensing. The internal capacitor of the light emitting element is a capacitor existing between the anode electrode PXL and the cathode electrode.

[0047] Referring to FIG. 6, the array configuration of the representative pixel P will be specifically described as follows.

[0048] The voltage of the source node DTS of the representative pixel P is the object of touch sensing. The representative pixel P has a gate node DTG electrically separated from the source node DTS. The gate node DTG can have a first conductive pattern M1 that faces the source node DTS with at least one or more insulating layers GI, BUF in between and serves as one side electrode of the storage capacitor Cst, and a second conductive pattern M2 connected to the first conductive pattern M1 through a first contact hole CH1 that penetrates the insulating layers GI, BUF. And the source node DTS can be located on the insulating layers GI, BUF and have a third conductive pattern M3 that serves as the other side electrode of the storage capacitor Cst. At this time, among the first conductive pattern M1, the second conductive pattern M2, and the third conductive pattern M3, the first conductive pattern M1 is located closest to the substrate GLS.

[0049] That is, the first conductive pattern M1 formed closest to the substrate GLS functions as a touch electrode and can also function as a light-shielding pattern. The first conductive pattern M1 can block external light incident on the semiconductor layer ACT of the driving transistor and prevent the characteristic values of the driving transistor from deteriorating due to the external light.

[0050] The first conductive pattern M1 is covered by the buffer insulating film BUF and the gate insulating film GI, and is electrically connected through the second conductive pattern M2 and the first contact hole CH1 on the gate insulating film GI. The second conductive pattern M2 constitutes the gate electrode of the driving transistor.

[0051] The third conductive pattern M3 serving as the other electrode of the storage capacitor Cst is located on the first conductive pattern M1 with the buffer insulating film BUF and the gate insulating film GI interposed therebetween. The third conductive pattern M3 can be formed of the same material as the second conductive pattern M2 and can constitute the same layer as the second conductive pattern M2. The source electrode of the driving transistor can be formed by making the semiconductor layer ACT conductive or by laminating a conductive layer on the semiconductor layer ACT, and can be electrically connected to the third conductive pattern M3 through a contact hole.

[0052] The second conductive pattern M2 and the third conductive pattern M3 are covered by the planarization film OC, and the anode electrode PXL of the light-emitting element is formed on the planarization film OC. Although not shown, the source node DTS of the driving transistor and the anode electrode PXL of the light-emitting element can be electrically connected to each other through a contact hole process penetrating the planarization film OC.

[0053] FIG. 7 is a diagram showing voltage changes of the gate node and the source node of the driving transistor during touch input.

[0054] Referring to FIG. 7, the touch input to the representative pixel is sensed within the on-pulse section of the touch scan signal T-SCAN. In response to the touch scan signal T-SCAN, a touch driving data voltage is applied to the gate node DTG of the driving transistor, and a reference voltage Vpre is applied to the source node DTS of the driving transistor, turning on the driving transistor and causing Ids to flow through the driving transistor.

[0055] When a touch input is made at the first timing t1 of the on-pulse section, Ids1 corresponding to Vgs1 flows through the driving transistor. Such Ids1 of the driving transistor is even smaller than Ids2 when there is no touch input. In other words, Ids1 of the first representative pixel corresponding to the position with touch input is smaller than Ids2 of the second representative pixel corresponding to the position without touch input.

[0056] When touch sensing is performed at the second timing t2 of the on-pulse section, the source node DTS voltage of the driving transistor becomes Vsen due to Ids1. Such Vsen of the driving transistor is even smaller than Vsen' due to Ids2 when there is no touch input. In other words, Vsen for the first representative pixel at the position with touch input is smaller than Vsen' for the second representative pixel at the position without touch input.

[0057] Therefore, it becomes possible to determine whether there is a touch input to the representative pixel based on the difference between Vsen and Vsen', which are the source node DTS voltages of the driving transistor.

[0058] FIGS. 8 and 9 are diagrams showing an example in which display driving and touch sensing driving are implemented in a time division manner.

[0059] Referring to FIG. 8, a display frame D-Frame for display driving and a touch frame T-Frame for touch sensing driving can be alternately performed. The touch frame T-Frame can be positioned between two adjacent display frames D-Frame.

[0060] The display driving is for writing video data into all pixels P of the display panel to update the video, and can be performed during the vertical active section of the display frame D-Frame. The touch sensing driving is performed during the vertical active section of the touch frame T-Frame, but only targets the representative pixels P of the display panel, so a longer time can be ensured for touch sensing. Since the time allocated for touch sensing is long, the touch sensing cycle is shortened and the touch report rate can be improved.

[0061] On the other hand, external compensation driving can be performed in the respective vertical blank sections of the display frame D-Frame and the touch frame T-Frame.

[0062] Referring to FIG. 9, the screen of the display panel is divided into a plurality of touch screen blocks TBLK, and touch input can be sensed in units of the touch screen blocks TBLK. Each touch block TBLK includes a plurality of pixel set lines PL1~PLn, and any one of the pixel set lines PL1~PLn can be composed of representative pixels in each touch block TBLK.

[0063] The gate drive circuit authorizes the display scan signal D-SCAN to all pixels in the display frame D-Frame, and authorizes the touch scan signal T-SCAN to the representative pixels in the touch frame T-Frame. The on-pulse width PW1 of the touch scan signal T-SCAN is wider than the on-pulse width PW2 of the display scan signal D-SCAN. Since the on-pulse width PW1 of the touch scan signal T-SCAN is wide, the touch sensing performance for the touch screen block TBLK can be improved.

[0064] FIGS. 10 and 11 are diagrams schematically showing the stage configuration of the gate drive circuit 13.

[0065] Referring to FIGS. 10 and 11, the gate drive circuit 13 includes first to k-th stage circuits STG(1) to STG(k), a gate drive voltage line 131, and a clock signal line 132. Further, the gate drive circuit 13 can further include a dummy stage circuit DST1 disposed at the front end of the first stage circuit STG(1).

[0066] The gate drive voltage line 131 supplies the high potential voltage GVDD and the low potential voltage GVSS supplied from a power supply circuit (not shown) to the first to k-th stage circuits STG(1) to STG(k) and the dummy stage circuit DST1. In this embodiment, the gate drive voltage line 131 can include two high potential voltage lines that supply the first high potential voltage GVDD1 and the second high potential voltage GVDD1 having different voltage levels, respectively, and three low potential voltage lines that supply the first low potential voltage GVSS1, the second low potential voltage GVSS2, and the third low potential voltage GVSS3 having different voltage levels, respectively. However, this is only an example, and the number of voltage lines included in the gate drive voltage line 131 can be changed.

[0067] The clock signal line 132 supplies a number of clock signals, such as a carry clock signal CRCLK and a scan clock signal SCCLK, which are supplied from the timing controller 11, to the first to k-th stage circuits STG(1) to STG(k) and the dummy stage circuit DST1.

[0068] The carry clock signal CRCLK can be embodied by, but is not limited to, first to third carry clocks CRCLK1, CRCLK2, and CRCLK3 having different phases from each other. The first to third carry clocks CRCLK1, CRCLK2, and CRCLK3 are shifted in phase while swinging between a gate-on voltage and a gate-off voltage. The first to third carry clocks CRCLK1, CRCLK2, and CRCLK3 can be supplied to the first to k-th stage circuits STG(1) to STG(k) through first to third carry clock lines 131-1, 131-2, and 131-3, respectively. Each of the first to k-th stage circuits STG(1) to STG(k) receives any one of the first to third carry clocks CRCLK1, CRCLK2, and CRCLK3 in a phase-sequential manner and outputs carry signals C(1) to C(K) corresponding to the input carry clock. Each of the first to k-th stage circuits STG(1) to STG(k) has its stage operation activated according to a front-end carry signal.

[0069] The scan clock signal SCCLK can be implemented by the first to twelfth scan clocks SCLK1 to SCLK12 with different phases, but is not limited thereto. The first to twelfth scan clocks SCLK1 to SCLK12 have their phases shifted while swinging between the gate-on voltage and the gate-off voltage. The first to twelfth scan clocks SCLK1 to SCLK12 can be supplied to the first to k-stage circuits STG(1) to STG(k) through the first to twelfth scan clock lines 232-1 to 232-12, respectively. Each of the first to k-stage circuits STG(1) to STG(k) receives an input of any one of the first to twelfth scan clocks SCLK1 to SCLK12 according to the phase sequential method, and outputs scan signals SCOUT(1) to SCOUT(n) corresponding to the input scan clock.

[0070] In this embodiment, each stage circuit can output four gate signals SCOUT and one carry signal C. For example, the first stage circuit STG(1) outputs the first to fourth gate signals SCOUT(1) to SCOUT(4) and the first carry signal CS(1), and the second stage circuit STG(2) can output the fifth to eighth gate signals SCOUT(5) to SCOUT(8) and the second carry signal CS(2).

[0071] The number of gate signals output from the first to k-stage circuits STG(1) to STG(k) matches the number of gate lines in the display panel. In this embodiment, the number (k) of stage circuits is 1 / 4 of the number (n) of gate lines. That is, k = n / 4.

[0072] In this way, if the number (k) of stage circuits is designed to be 1 / 4 of the number (n) of gate lines, there is an advantage that the mounting area of the gate driving circuit 13 can be reduced and the bezel size of the display panel can be reduced.

[0073] FIG. 12 is a diagram showing the configuration of the k-stage circuit STG(k) included in the gate driving circuit 13.

[0074] Referring to FIG. 12, the k-th stage circuit STG(k) includes a Q node, a QH node, and a QB node. The k-th stage circuit STG(k) includes a Q / QH node control unit BK1, a QB node control unit BK2, a carry output unit BK3, and a scan output unit BK4.

[0075] In response to the input of the front-end carry signal C(k - 2), the Q / QH node control unit BK1 charges the Q node to the first high potential voltage GVDD1 level, and in response to the input of the rear-end carry signal C(k + 2), discharges the Q node to the third low potential voltage GVSS3 level. For this purpose, the Q / QH node control unit BK1 includes first to eighth transistors T21 to T28.

[0076] The first transistor T21 and the second transistor T22 are connected between the first high potential voltage line for transmitting the first high potential voltage GVDD1 and the Q node. The first transistor T21 and the second transistor T22 are connected in series with each other. The first transistor T21 and the second transistor T22 charge the Q node to the first high potential voltage GVDD1 level in response to the input of the front-end carry signal C(k - 2). The first transistor T21 is turned on by the input of the front-end carry signal C(k - 2) and supplies the first high potential voltage GVDD1 to the connection node NC2. The second transistor T22 is turned on by the input of the front-end carry signal C(k - 2) and electrically connects the connection node NC2 and the Q node. Therefore, when the first transistor T21 and the second transistor T22 are turned on simultaneously, the first high potential voltage GVDD1 is supplied to the Q node.

[0077] The fifth transistor T25 and the sixth transistor T26 are connected to a third high potential voltage line that transmits the third high potential voltage GVDD3. The fifth transistor T25 and the sixth transistor T26 supply the third high potential voltage GVDD3 to the connection node NC2 in response to the third high potential voltage GVDD3. The fifth transistor T25 and the sixth transistor T26 are turned on simultaneously by the third high potential voltage GVDD3 to constantly supply the third high potential voltage GVDD3 to the connection node NC2, thereby increasing the voltage difference between the gate voltage of the first transistor T21 and the connection node NC2. Therefore, when an off-level front-end carry signal C(k-2) is input to the gate of the first transistor T21 and the first transistor T21 is turned off, the first transistor T21 can be completely maintained in the off state due to the voltage difference between the gate voltage of the first transistor T21 and the connection node NC2. Thereby, current leakage of the first transistor T21 and the voltage drop of the Q node due thereto can be prevented, and the voltage of the Q node can be stably maintained. For this purpose, the third high potential voltage GVDD3 can be set to a voltage level lower than the first high potential voltage GVDD1.

[0078] The third transistor T23 and the fourth transistor T24 are connected between the Q node and a third low potential voltage line that transmits the third low potential voltage GVSS3. The third transistor T23 and the fourth transistor T24 are connected in series with each other. The third transistor T23 and the fourth transistor T24 discharge the Q node and the QH node to the third low potential voltage GVSS3 level in response to the input of the back-end carry signal C(k+2). The fourth transistor T24 is turned on by the input of the back-end carry signal C(k+2) and discharges the QH node to the second low potential voltage GVSS2 level. The third transistor T23 is turned on by the input of the back-end carry signal C(k+2) and electrically connects the Q node and the QH node. Therefore, when the third transistor T23 and the fourth transistor T24 are turned on simultaneously, the Q node and the QH node are discharged to the third low potential voltage GVSS3 level, respectively.

[0079] The seventh transistor T27 and the eighth transistor T28 are connected between a first high potential voltage line that transmits the first high potential voltage GVDD1 and the Q node, and between the first high potential voltage line that transmits the first high potential voltage GVDD1 and the QH node. The seventh transistor T27 and the eighth transistor T28 are connected in series with each other. The seventh transistor T27 and the eighth transistor T28 supply the first high potential voltage GVDD1 to the QH node in response to the voltage of the Q node. The seventh transistor T27 is turned on when the voltage of the Q node is at the on level, and supplies the first high potential voltage GVDD1 to the common node of the seventh transistor T27 and the eighth transistor T28. The eighth transistor T28 is turned on when the voltage of the Q node is at the on level, and electrically connects the common node and the QH node. Therefore, the seventh transistor T27 and the eighth transistor T28 are simultaneously turned on when the voltage of the Q node reaches the on level, and supply the first high potential voltage GVDD1 to the QH node. When the first high potential voltage GVDD1 is supplied to the QH node, the voltage difference between the gate of the third transistor T23 and the QH node increases. Therefore, when an off-level trailing carry signal C(k + 2) is input to the gate of the third transistor T23 and the third transistor T23 is turned off, the third transistor T23 can be completely maintained in the turned-off state due to the voltage difference between the gate voltage of the third transistor T23 and the QH node. Thereby, current leakage of the third transistor T23 and the voltage drop of the Q node caused thereby are prevented, and the voltage of the Q node can be stably maintained.

[0080] The Q / QH node control unit BK1 discharges the Q node and the QH node to the third low potential voltage GVSS3 level in response to the voltage of the QB node. For this purpose, the Q / QH node control unit BK1 further includes a first additional transistor T31 and a second additional transistor T32. The first additional transistor T31 and the second additional transistor T32 are connected between the Q node and the third low potential voltage line that transmits the third low potential voltage GVSS3. The first additional transistor T31 and the second additional transistor T32 are connected in series with each other. The first additional transistor T31 and the second additional transistor T32 discharge the Q node and the QH node to the third low potential voltage GVSS3 level in response to the voltage of the QB node. The second additional transistor T32 is turned on when the voltage of the QB node reaches the on level, and supplies the third low potential voltage GVSS3 to the shared node of the first additional transistor T31 and the second additional transistor T32. The first additional transistor T31 is turned on when the voltage of the QB node reaches the on level, and electrically connects the Q node and the QH node. Therefore, when the first additional transistor T31 and the second additional transistor T32 are simultaneously turned on in response to the voltage of the QB node, the Q node and the QH node are each discharged to the third low potential voltage GVSS3 level.

[0081] The QB node control unit BK2 changes the voltage level of the QB node according to the voltage level of the Q node. For this purpose, the QB node control unit BK2 includes first to fifth transistors T41 to T45.

[0082] The second transistor T42 and the third transistor T43 are connected between a second high potential voltage line that transmits a second high potential voltage GVDD2 and a third connection node NC3. The second transistor T42 and the third transistor T43 are connected in series with each other. The second transistor T42 and the third transistor T43 supply the second high potential voltage GVDD1 to the connection node NC3 in response to the second high potential voltage GVDD1. The second transistor T42 is turned on by the second high potential voltage GVDD2 and supplies the second high potential voltage GVDD2 to a shared node of the second transistor T42 and the third transistor T43. The third transistor T43 is turned on by the second high potential voltage GVDD2 and electrically connects the shared node of the second transistor T42 and the third transistor T43 and the connection node NC3. Therefore, when the second transistor T42 and the third transistor T43 are simultaneously turned on by the second high potential voltage GVDD2, the connection node NC3 is charged up to the second high potential voltage GVDD2 level. The fourth transistor T44 is connected between the connection node NC3 and a second low potential voltage line that transmits a second low potential voltage GVSS2. The fourth transistor T44 supplies the second low potential voltage GVSS2 to the connection node NC3 in response to the voltage of the Q node. The fourth transistor T44 is turned on when the voltage of the Q node is at the on level and discharges or resets the connection node NC3 to the second low potential voltage GVSS2.

[0083] The first transistor T41 is connected between the second high potential voltage line transmitting the second high potential voltage GVDD2 and the QB node. The first transistor T41 supplies the second high potential voltage GVDD1 to the QB node in response to the voltage of the connection node NC3. The first transistor T41 is turned on when the voltage of the connection node NC3 is at the on level, and charges the QB node to the second high potential voltage GVDD2 level. The fifth transistor T45 is connected between the QB node and the third low potential voltage line transmitting the third low potential voltage GVSS3. The fifth transistor T45 supplies the third low potential voltage GVSS3 to the QB node in response to the voltage of the Q node. The fifth transistor T45 is turned on when the voltage of the Q node is at the on level, and discharges the QB node to the third low potential voltage GVSS3 level.

[0084] The QB node control unit BK2 discharges the QB node to the third low potential voltage GVSS3 level in response to the input of the backend carry signal C(k - 2). For this purpose, the QB node control unit BK2 further includes a first additional transistor T51.

[0085] The first additional transistor T51 is connected between the QB node and the third low potential voltage line transmitting the third low potential voltage GVSS3. The first additional transistor T51 supplies the third low potential voltage GVSS3 to the QB node in response to the input of the backend carry signal C(k - 2).

[0086] The carry output unit BK3 outputs the carry clock CRCLK(k) of the gate on voltage to the carry signal C(k) of the on voltage while the Q node is charged to the on voltage level, and outputs the third low potential voltage GVSS3 to the carry signal C(k) of the off voltage while the QB node is charged to the on voltage level.

[0087] The carry output section BK3 includes a first transistor T81, a second transistor T82, and a boosting capacitor CC. The first transistor T81 is connected between the clock signal line of the carry clock CRCLK(k) and the output node NO. A boosting capacitor CC is connected between the gate and the source of the first transistor T81. When the carry clock CRCLK(k) with a gate-on voltage is output to the output node NO, the boosting capacitor CC bootstraps the voltage of the Q node to a boosting voltage level higher than the first high potential voltage GVDD1 level in synchronization with the carry clock CRCLK(k) with the gate-on voltage. When the voltage of the Q node is bootstrapped, the carry signal C(k) with the on-voltage can be quickly and distortionlessly charged to the output node NO. Thereby, the carry signal C(k) with the on-voltage is output from the output node NO. The second transistor T82 supplies the third low potential voltage GVSS3 to the output node NO in response to the voltage of the QB node. Thereby, the carry signal C(k) with the off-voltage is output from the output node NO.

[0088] The scan output section BK4 outputs the first to fourth scan clocks SCLK(n - 3) to SCLK(n) with the gate-on voltage as the first to fourth scan signals SCOUT(n - 3) to SCOUT(n) while the Q node is charged to the on-voltage level, and outputs the first low potential voltage GVSS1 as the first to fourth scan signals SCOUT(n - 3) to SCOUT(n) with the off-voltage while the QB node is charged to the on-voltage level. For this purpose, the scan output section BK4 includes first to eighth transistors T71 to T78 and first to fourth boosting capacitors CS1 to CS4.

[0089] The first transistor T71 is connected between the clock signal line of the first scan clock SCCLK(n - 3) and the first output node NO1. A first boosting capacitor CS1 is connected between the gate and the source of the first transistor T71. When the gate-on voltage of the first scan clock SCCLK(n - 3) is output to the first output node NO1, the first boosting capacitor CS1 bootstraps the voltage of the Q node to a boosting voltage level higher than the first high potential voltage GVDD1 level in synchronization with the gate-on voltage of the first scan clock SCCLK(n - 3). When the voltage of the Q node is bootstrapped, the on-voltage first scan signal SCOUT(n - 3) can quickly and without distortion charge the first output node NO1. As a result, the on-voltage first scan signal SCOUT(n - 3) can be output from the first output node (NO1). The second transistor T72 supplies the first low potential voltage GVSS1 to the first output node NO1 in response to the voltage of the QB node. As a result, the off-voltage first scan signal SCOUT(n - 3) is output from the first output node NO1.

[0090] The third transistor T73 is connected between the clock signal line of the second scan clock SCCLK(n - 2) and the second output node NO2. A second boosting capacitor CS2 is connected between the gate and the source of the third transistor T73. When the gate-on voltage of the second scan clock SCCLK(n - 2) is output to the second output node NO2, the second boosting capacitor CS2 bootstraps the voltage of the Q node to a boosting voltage level higher than the first high potential voltage GVDD1 level in synchronization with the gate-on voltage of the second scan clock SCCLK(n - 2). When the voltage of the Q node is bootstrapped, the on-voltage second scan signal SCOUT(n - 2) can be quickly and distortionlessly charged to the second output node NO2. As a result, the on-voltage second scan signal SCOUT(n - 2) can be output from the second output node NO2. The fourth transistor T74 supplies the first low potential voltage GVSS1 to the second output node NO2 in response to the voltage of the QB node. As a result, the off-voltage second scan signal SCOUT(n - 2) is output from the second output node NO2.

[0091] The fifth transistor T75 is connected between the clock signal line of the third scan clock SCCLK(n - 1) and the third output node NO3. A third boosting capacitor CS3 is connected between the gate and the source of the fifth transistor T75. When the gate-on voltage of the third scan clock SCCLK(n - 1) is output to the third output node NO3, the third boosting capacitor CS3 bootstraps the voltage of the Q node to a boosting voltage level higher than the first high potential voltage GVDD1 level in synchronization with the gate-on voltage of the third scan clock SCCLK(n - 1). Once the voltage of the Q node is bootstrapped, the on-voltage third scan signal SCOUT(n - 1) can quickly and without distortion charge the third output node NO3. As a result, the on-voltage third scan signal SCOUT(n - 1) can be output from the third output node NO3. The sixth transistor T76 supplies the first low potential voltage GVSS1 to the third output node NO3 in response to the voltage of the QB node. As a result, the off-voltage third scan signal SCOUT(n - 1) is output from the third output node NO3.

[0092] The seventh transistor T77 is connected between the clock signal line of the fourth scan clock SCCLK(n) and the fourth output node NO4. A fourth boosting capacitor (CS4) is connected between the gate and the source of the seventh transistor T77. When the gate-on voltage of the fourth scan clock (SCCLK(n)) is output to the fourth output node NO4, the fourth boosting capacitor (CS4) synchronizes with the gate-on voltage of the fourth scan clock (SCCLK(n)) to bootstrap the voltage of the Q node to a boosting voltage level higher than the first high potential voltage GVDD1 level. Once the voltage of the Q node is bootstrapped, the on-voltage fourth scan signal SCOUT(n) can quickly and without distortion charge the fourth output node NO4. As a result, the on-voltage fourth scan signal SCOUT(n) can be output from the fourth output node NO4. The eighth transistor (T78) supplies the first low potential voltage GVSS1 to the fourth output node NO4 in response to the voltage of the QB node. As a result, the off-voltage fourth scan signal SCOUT(n) is output from the fourth output node NO4.

[0093] In this embodiment, in order to minimize the off-current flowing through the off-state transistor and stabilize the voltages of the Q node, the QB node, and the QH node, the high potential voltage and the low potential voltage can be set to three (or two) different voltage levels respectively.

[0094] For example, the first high potential voltage GVDD1 can be set to 20V, the second high potential voltage GVDD2 can be set to 16V, the third high potential voltage GVDD3 can be set to 14V, the first low potential voltage GVSS1 can be set to -6V, the second low potential voltage GVSS2 can be set to -10V, and the third low potential voltage GVSS3 can be set to -12V. As another example, the first low potential voltage GVSS1 and the second low potential voltage GVSS2 can be set to the same voltage (for example, -6V) with respect to each other. Such numerical values are just examples. They are only one example, and the levels of the high potential voltage and the low potential voltage can be set differently according to the embodiment.

[0095] FIG. 13 is a diagram showing a concept of reducing the time required for the transmission of a carry signal in order to sufficiently secure the output time of a touch scan signal in a touch frame. FIG. 14 is a diagram showing drive waveforms of a display carry clock and a display scan clock for generating a display scan signal. FIG. 15 is a diagram showing drive waveforms of a touch carry clock and a touch scan clock for generating a touch scan signal. FIG. 16 is a diagram showing that in each of the touch screen blocks, a touch scan signal having an on period by a touch scan clock is applied only to some gate lines.

[0096] Referring to FIGS. 13 to 16, the gate drive circuit 13 of this embodiment can output a display scan signal D-SCAN or a touch scan signal T-SCAN to the display panel using the stages of FIGS. 9 to 12 described above.

[0097] The plurality of stages are sequentially activated based on a display carry clock (FIGS. 14, CRCLK1 to CRCLK3) that swings between a gate on voltage Vgh and a gate off voltage Vgl in a display frame D-Frame, and output a display scan signal D-SCAN to the display panel.

[0098] The plurality of stages are sequentially activated based on a touch carry clock (FIGS. 15, CRCLK1 to CRCLK3) that swings between a gate on voltage Vgh and a gate off voltage Vgl in a touch frame T-Frame, and output a touch scan signal T-SCAN to the display panel.

[0099] When the frame frequency is 120 Hz, the time for one frame is approximately 8 ms. That is, the display frame D-Frame and the touch frame T-Frame each have a temporal length of approximately 8 ms. In order to ensure sufficient output time of the touch scan signal T-SCAN from the touch frame T-Frame, it is necessary to relatively further reduce the time required to transmit the carry signal between stages in the touch frame T-Frame compared to the display frame D-Frame.

[0100] For this purpose, this embodiment includes the feature that the on-pulse widths of the touch carry clocks CRCLK1 to CRCLK3 are narrower than those of the display carry clocks CRCLK1 to CRCLK3 as shown in FIGS. 14 and 15. For example, the on-pulse widths of the display carry clocks CRCLK1 to CRCLK3 are 2 horizontal periods 2H, while the on-pulse widths of the touch carry clocks CRCLK1 to CRCLK3 can be 1 horizontal period 1H. Also, while one cycle period of the display carry clocks CRCLK1 to CRCLK3 is 12 horizontal periods 12H, one cycle period of the touch carry clocks CRCLK1 to CRCLK3 can be 3 horizontal periods 3H.

[0101] Referring to FIG. 14, in the display frame, since video data must be written to all pixels of the display panel, the number of on-intervals of the display scan signal D-SCAN must be the same as the number of gate lines, and the on-pulses of the display scan clocks SCLK1 to SCLK12 must be designed for the number of on-intervals of the display scan signal D-SCAN. The on-pulse widths of the display scan clocks SCLK1 to SCLK12 may be the same as the on-pulse widths of the display carry clocks CRCLK1 to CRCLK3.

[0102] In contrast, referring to FIGS. 15 and 16, in the touch frame, only the representative pixels of the display panel are touch-sensing driven in the touch frame, so the number of touch scan signals T-SCAN having an on interval is smaller than the number of gate lines. Then, the on pulses of the touch scan clocks SCLK1 to SCLK12 are designed to be synchronized with the on interval positions of the touch scan signal T-SCAN. Thereby, the on interval of the touch scan signal T-SCAN and the on pulse widths of the corresponding touch scan clocks SCLK1 to SCLK12 can be widely designed to be 100 horizontal periods 100H.

[0103] Specifically, referring to FIGS. 15 and 16, in the touch frame, in the first stage (FIG. 10, STG1), the first touch scan signal T-SCAN1 having a first on interval 100H is output to the first touch screen block TBLK1 of the display panel in response to the first touch scan clock SCLK1 of the gate on voltage Vgh, and in the second stage (FIG. 10, STG53), the second touch scan signal T-SCAN53 having SCAN-53 having a second on interval 100H is output to the second touch screen block TBLK2 of the display panel in response to the second touch scan clock SCLK5 of the gate on voltage Vgh, and in the third stage (FIG. 10, STG105), the third touch scan signal T-SCAN105 having a third on interval 100H can be output to the third touch screen block TBLK3 of the display panel in response to the third touch scan clock SCLK9 of the gate on voltage Vgh.

[0104] At this time, the phase of the first touch scan clock SCLK1 is earlier than the phase of the second touch scan clock SCLK5, and the phase of the second touch scan clock SCLK5 precedes the phase of the third touch scan clock SCL9. And each of the first to third on intervals is 100 horizontal periods 100H.

[0105] In the touch frame T-Frame, the first stage (FIG. 10, STG1) supplies the first touch scan signal T-SCAN1 to any one of the first gate lines included in the first touch screen block TBLK1, and the second stage (FIG. 10, STG53) supplies the second touch scan signal T-SCAN53 to any one of the second gate lines included in the second touch screen block TBLK2. The third stage (FIG. 10, STG105) supplies the third touch scan signal T-SCAN105 to any one of the third gate lines included in the third touch screen block TBLK3.

[0106] In the touch frame T-Frame, at least one or more stages (FIG. 10, STG2 to STG52) located between the first stage (FIG. 10, STG1) and the second stage (FIG. 10, STG53) supply at least one or more touch scan signals T-SCAN2 to T-SCAN52 that have no on-interval by the touch scan clock of the gate-off voltage Vgl to at least one or more gate lines located between the first and second gate lines.

[0107] In the touch frame T-Frame, at least one or more stages (FIG. 10, STG54 to STG104) located between the second stage (FIG. 10, STG53) and the third stage (FIG. 10, STG105) supply at least one or more touch scan signals T-SCAN54 to T-SCAN104 that have no on-interval by the touch scan clock of the gate-off voltage Vgl to at least one or more gate lines located between the second and third gate lines.

[0108] Those skilled in the art will understand through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the scope of the claims.

Description of Reference Numerals

[0109] 10 Display panel 11 Timing controller 12 Data driving circuit 13 Gate driving circuit 14A Data line 14B Sensing line 15 Gate line

Claims

1. A touch sensing display device, comprising: a display panel in which display driving for displaying an image and touch sensing driving for sensing a touch on the display panel are alternately implemented at a predetermined period; and a gate driving circuit that drives a gate line of the display panel by using a plurality of sequentially activated stages. Including Each of the plurality of stages is activated in sequence based on a display carrier signal whose voltage level swings between a gate-on voltage and a gate-off voltage in a display frame, and outputs a display scan signal to the display panel during the display driving. Each of the plurality of stages is activated in sequence based on a touch carrier signal that changes between the gate-on voltage and the gate-off voltage in a touch frame, and outputs a touch scan signal to the display panel during the touch sensing driving. The display carrier signal corresponds to a display carrier clock corresponding to one phase among a plurality of display carrier clocks having different phases from each other. The touch carrier signal corresponds to a touch carrier clock corresponding to one phase among a plurality of touch carrier clocks having different phases from each other. When each of the plurality of touch carrier clocks is the gate-on voltage, the on-pulse width of each of the plurality of touch carrier clocks is narrower than the on-pulse width of each of the plurality of display carrier clocks when each of the plurality of display carrier clocks is the gate-on voltage. One cycle period of the plurality of touch carrier clocks is shorter than one cycle period of the plurality of display carrier clocks. A touch sensing display device, wherein an on-pulse width of the touch scan signal for turning on pixels of the display panel during the touch frame is wider than an on-pulse width of the display scan signal for turning on pixels of the display panel during the display frame.

2. In the touch frame, The first stage among the plurality of stages is configured to output a first touch scan signal having a first on-section to a first touch screen block of the display panel in response to a first touch scan clock of a gate-on voltage, and the first touch screen block includes a first plurality of pixel columns. Among the plurality of stages, the second stage is configured to output a second touch scan signal having a second on interval in response to a second touch scan clock of a gate-on voltage to a second touch screen block of the display panel. The second touch screen block includes a second plurality of pixel columns. The touch sensing display device according to claim 1, wherein a phase of the first touch scan clock and a phase of the second touch scan clock are different from each other, and a length of a first on interval of the first touch scan signal is equal to a length of a second on interval of the second touch scan signal.

3. The first stage supplies the first touch scan signal to any one of the first gate lines included in the first touch screen block. The second stage supplies the second touch scan signal to any one of the second gate lines included in the second touch screen block. The first touch scan signal is not supplied to the remaining first gate lines included in the first touch screen block. The touch sensing display device according to claim 2, wherein the second touch scan signal is not supplied to the remaining second gate lines included in the second touch screen block.

4. The plurality of stages further includes at least one third stage positioned between the first stage and the second stage. The at least one third stage supplies, in the touch frame, a third touch scan signal including only an off interval without an on interval in response to a touch scan clock of a gate-off voltage to at least one or more third gate lines positioned between any one of the first gate lines and any one of the second gate lines. The touch sensing display device according to claim 3.

5. The touch sensing display device according to claim 1, further comprising a sensing circuit that senses a voltage of a source node of a representative pixel formed on a substrate of the display panel by the touch scan signal. The sensed voltage indicates whether a touch input is applied to the display panel during the touch frame.

6. The representative pixel includes a driving transistor including a source electrode connected to the source node and a gate electrode connected to a gate node, and a storage capacitor. The gate node has a first conductive pattern that faces the source node with at least one or more insulating layers therebetween and serves as a first electrode of the storage capacitor, and a second conductive pattern that is connected to the first conductive pattern through a contact hole penetrating the at least one or more insulating layers. The source node has a third conductive pattern that is located on the at least one or more insulating layers and serves as a second electrode of the storage capacitor. The touch sensing display device according to claim 5, wherein among the first conductive pattern, the second conductive pattern, and the third conductive pattern, the first conductive pattern is located closest to the substrate.

7. The touch sensing display device according to claim 6, wherein the second conductive pattern is located on the at least one or more insulating layers and is formed of the same material as the third conductive pattern.

8. The touch sensing display device according to claim 5, wherein in the touch frame, the drive current of the representative pixel and the voltage of the source node change according to the touch input.

9. The touch sensing display device according to claim 8, wherein a first drive current of the representative pixel when there is a touch input at the position of the representative pixel is smaller than a second drive current of the representative pixel when there is no touch input at the position of the representative pixel.

10. The touch sensing display device according to claim 8, wherein a voltage of the source node of the representative pixel when there is a touch input at the position of the representative pixel is smaller than a voltage of the source node of the representative pixel when there is no touch input at the position of the representative pixel.

11. The touch sensing display device according to claim 1, wherein the gate driving circuit further includes a dummy stage disposed in front of a first stage among the plurality of stages.

12. The gate driving circuit further includes a gate driving voltage line configured to supply a high potential voltage and a low potential voltage supplied from a power supply circuit to the plurality of stages and the dummy stage. The touch sensing display device according to claim 11, wherein the high potential voltage and the low potential voltage are set to different voltage levels, respectively.

13. The representative pixel has a driving transistor including a source electrode connected to the source node and a gate electrode connected to the gate node. The touch sensing display device according to claim 5, wherein the gate node is disposed closer to the substrate than the source node.

14. The touch sensing display device according to claim 5, wherein the representative pixel includes a gate node electrically disconnected from the source node.

15. The touch sensing display device according to claim 1, wherein the number of the plurality of stages is 1 / 4 of the number of the gate lines.

Images